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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 17:48:33 -04:00
Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.
This commit is contained in:
Gaurav Aggarwal
parent
079d081346
commit
ae448fc952
227 changed files with 133624 additions and 123 deletions
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@ -369,6 +369,8 @@ volatile uint32_t ulDummy = 0UL;
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extern uint32_t * __privileged_functions_start__;
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extern uint32_t * __privileged_functions_end__;
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extern uint32_t * __syscalls_flash_start__;
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extern uint32_t * __syscalls_flash_end__;
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extern uint32_t * __unprivileged_flash_start__;
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extern uint32_t * __unprivileged_flash_end__;
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extern uint32_t * __privileged_sram_start__;
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extern uint32_t * __privileged_sram_end__;
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@ -377,6 +379,8 @@ volatile uint32_t ulDummy = 0UL;
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extern uint32_t __privileged_functions_start__[];
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extern uint32_t __privileged_functions_end__[];
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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extern uint32_t __unprivileged_flash_start__[];
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extern uint32_t __unprivileged_flash_end__[];
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extern uint32_t __privileged_sram_start__[];
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extern uint32_t __privileged_sram_end__[];
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@ -400,17 +404,26 @@ volatile uint32_t ulDummy = 0UL;
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup unprivileged flash and system calls flash as Read Only by
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* both privileged and unprivileged tasks. All tasks can read it but
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* no-one can modify. */
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/* Setup unprivileged flash as Read Only by both privileged and
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* unprivileged tasks. All tasks can read it but no-one can modify. */
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portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup unprivileged syscalls flash as Read Only by both privileged
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* and unprivileged tasks. All tasks can read it but no-one can modify. */
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portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup RAM containing kernel data for privileged access only. */
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portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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@ -421,17 +434,6 @@ volatile uint32_t ulDummy = 0UL;
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* By default allow everything to access the general peripherals.
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* The system peripherals and registers are protected. */
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portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_WRITE ) |
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( portMPU_REGION_EXECUTE_NEVER );
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portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX1 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Enable mem fault. */
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portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
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@ -28,9 +28,17 @@
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/* Standard includes. */
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#include <stdint.h>
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
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* is defined correctly and privileged functions are placed in correct sections. */
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#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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/* Portasm includes. */
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#include "portasm.h"
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/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
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* header files. */
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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@ -42,6 +50,12 @@ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_
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" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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#if( configENABLE_MPU == 1 )
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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" bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n" /* Disable MPU. */
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" \n"
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" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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@ -53,6 +67,12 @@ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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" ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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" orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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" \n"
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#if( configENABLE_MPU == 1 )
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@ -82,6 +102,7 @@ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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"xSecureContextConst2: .word xSecureContext \n"
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#if( configENABLE_MPU == 1 )
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"xMPUCTRLConst2: .word 0xe000ed94 \n"
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"xMAIR0Const2: .word 0xe000edc0 \n"
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"xRNRConst2: .word 0xe000ed98 \n"
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"xRBARConst2: .word 0xe000ed9c \n"
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@ -269,6 +290,12 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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" \n"
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#if( configENABLE_MPU == 1 )
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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" bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n" /* Disable MPU. */
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" \n"
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" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
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" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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@ -280,6 +307,12 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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" ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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" orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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" \n"
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#if( configENABLE_MPU == 1 )
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@ -329,6 +362,7 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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"pxCurrentTCBConst: .word pxCurrentTCB \n"
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"xSecureContextConst: .word xSecureContext \n"
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#if( configENABLE_MPU == 1 )
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"xMPUCTRLConst: .word 0xe000ed94 \n"
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"xMAIR0Const: .word 0xe000edc0 \n"
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"xRNRConst: .word 0xe000ed98 \n"
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"xRBARConst: .word 0xe000ed9c \n"
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@ -135,18 +135,14 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( nak
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/* MPU regions. */
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#define portPRIVILEGED_FLASH_REGION ( 0UL )
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#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
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#define portPRIVILEGED_RAM_REGION ( 2UL )
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#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )
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#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
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#define portPRIVILEGED_RAM_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portLAST_CONFIGURABLE_REGION ( 7UL )
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#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
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/* Devices Region. */
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#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )
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#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )
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/* Device memory attributes used in MPU_MAIR registers.
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*
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* 8-bit values encoded as follows:
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@ -289,7 +285,11 @@ typedef struct MPU_SETTINGS
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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/**
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* @brief Barriers.
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*/
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#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
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/*-----------------------------------------------------------*/
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#ifdef __cplusplus
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}
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