mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-12-07 05:34:59 -05:00
Merge branch 'main' into fix-vTaskSuspend-vTaskDelete-self-add-back
This commit is contained in:
commit
ad1a17873b
21 changed files with 44 additions and 44 deletions
|
|
@ -53,10 +53,10 @@
|
|||
* The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
|
||||
* values will reflect the last released version number.
|
||||
*/
|
||||
#define tskKERNEL_VERSION_NUMBER "V10.4.4+"
|
||||
#define tskKERNEL_VERSION_MAJOR 10
|
||||
#define tskKERNEL_VERSION_MINOR 4
|
||||
#define tskKERNEL_VERSION_BUILD 4
|
||||
#define tskKERNEL_VERSION_NUMBER "V11.0.1+"
|
||||
#define tskKERNEL_VERSION_MAJOR 11
|
||||
#define tskKERNEL_VERSION_MINOR 0
|
||||
#define tskKERNEL_VERSION_BUILD 1
|
||||
|
||||
/* MPU region parameters passed in ulParameters
|
||||
* of MemoryRegion_t struct. */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
name : "FreeRTOS-Kernel"
|
||||
version: "v10.5.1"
|
||||
version: "v11.0.1+"
|
||||
description: "FreeRTOS Kernel."
|
||||
license: "MIT"
|
||||
|
|
|
|||
|
|
@ -68,12 +68,12 @@ add_library(freertos_kernel_port OBJECT
|
|||
|
||||
# ARMv8-A ports for GCC
|
||||
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:
|
||||
GCC/Arm_AARCH64/port.c
|
||||
GCC/Arm_AARCH64/portASM.S>
|
||||
GCC/ARM_AARCH64/port.c
|
||||
GCC/ARM_AARCH64/portASM.S>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:
|
||||
GCC/Arm_AARCH64_SRE/port.c
|
||||
GCC/Arm_AARCH64_SRE/portASM.S>
|
||||
GCC/ARM_AARCH64_SRE/port.c
|
||||
GCC/ARM_AARCH64_SRE/portASM.S>
|
||||
|
||||
# ARMv6-M port for GCC
|
||||
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
|
||||
|
|
|
|||
|
|
@ -92,16 +92,16 @@
|
|||
/**
|
||||
* @brief Checks whether an external index is valid or not.
|
||||
*/
|
||||
#define IS_EXTERNAL_INDEX_VALID( lIndex ) \
|
||||
( ( ( lIndex ) >= INDEX_OFFSET ) && \
|
||||
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) )
|
||||
#define IS_EXTERNAL_INDEX_VALID( lIndex ) \
|
||||
( ( ( ( lIndex ) >= INDEX_OFFSET ) && \
|
||||
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) ) ? pdTRUE : pdFALSE )
|
||||
|
||||
/**
|
||||
* @brief Checks whether an internal index is valid or not.
|
||||
*/
|
||||
#define IS_INTERNAL_INDEX_VALID( lIndex ) \
|
||||
( ( ( lIndex ) >= 0 ) && \
|
||||
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) )
|
||||
#define IS_INTERNAL_INDEX_VALID( lIndex ) \
|
||||
( ( ( ( lIndex ) >= 0 ) && \
|
||||
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) ) ? pdTRUE : pdFALSE )
|
||||
|
||||
/**
|
||||
* @brief Converts an internal index into external.
|
||||
|
|
@ -2197,7 +2197,7 @@
|
|||
if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
|
||||
( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -2312,7 +2312,7 @@
|
|||
|
||||
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -2364,7 +2364,7 @@
|
|||
|
||||
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -2411,9 +2411,9 @@
|
|||
{
|
||||
uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
|
||||
|
||||
if( ( uxQueueItemSize == 0 )
|
||||
if( ( uxQueueItemSize == 0U )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -3906,10 +3906,10 @@
|
|||
|
||||
if( xAreParamsReadable == pdTRUE )
|
||||
{
|
||||
if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
|
||||
( pxParams->uxBitsToWaitFor != 0 )
|
||||
if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
|
||||
( pxParams->uxBitsToWaitFor != 0U )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
@ -3951,7 +3951,7 @@
|
|||
int32_t lIndex;
|
||||
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
|
||||
|
||||
if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
|
||||
if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
|
||||
{
|
||||
lIndex = ( int32_t ) xEventGroup;
|
||||
|
||||
|
|
@ -3986,7 +3986,7 @@
|
|||
int32_t lIndex;
|
||||
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
|
||||
|
||||
if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
|
||||
if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
|
||||
{
|
||||
lIndex = ( int32_t ) xEventGroup;
|
||||
|
||||
|
|
@ -4025,10 +4025,10 @@
|
|||
int32_t lIndex;
|
||||
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
|
||||
|
||||
if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
|
||||
( uxBitsToWaitFor != 0 )
|
||||
if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
|
||||
( uxBitsToWaitFor != 0U )
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
|
||||
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
|
|||
[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
|
||||
for more information.
|
||||
|
||||
## Arm_AARCH64 port
|
||||
## ARM_AARCH64 port
|
||||
|
||||
This port adds support for Armv8-A architecture AArch64 execution state.
|
||||
This port is generic and can be used as a starting point for Armv8-A
|
||||
application processors.
|
||||
|
||||
* Arm_AARCH64
|
||||
* ARM_AARCH64
|
||||
* Memory mapped interace to access Arm GIC registers
|
||||
|
|
@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
|
|||
[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
|
||||
for more information.
|
||||
|
||||
## Arm_AARCH64_SRE port
|
||||
## ARM_AARCH64_SRE port
|
||||
|
||||
This port adds support for Armv8-A architecture AArch64 execution state.
|
||||
This port is generic and can be used as a starting point for Armv8-A
|
||||
application processors.
|
||||
|
||||
* Arm_AARCH64_SRE
|
||||
* ARM_AARCH64_SRE
|
||||
* System Register interace to access Arm GIC registers
|
||||
|
|
@ -8,8 +8,8 @@ Arm Cortex-A53 processor.
|
|||
|
||||
This port is generic and can be used as a starting point for other Armv8-A
|
||||
application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
|
||||
`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
|
||||
should migrate to renamed port `Arm_AARCH64`.
|
||||
`ARM_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
|
||||
should migrate to renamed port `ARM_AARCH64`.
|
||||
|
||||
**NOTE**
|
||||
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ Arm Cortex-A53 processor.
|
|||
* System Register interace to access Arm GIC registers
|
||||
|
||||
This port is generic and can be used as a starting point for other Armv8-A
|
||||
application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
|
||||
`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
|
||||
should migrate to renamed port `Arm_AARCH64_SRE`.
|
||||
application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
|
||||
`ARM_AARCH64_SRE`. The existing projects that use old port `ARM_AARCH64_SRE`,
|
||||
should migrate to renamed port `ARM_AARCH64_SRE`.
|
||||
|
||||
**NOTE**
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
|
|
|
|||
2
portable/ThirdParty/GCC/RP2040/port.c
vendored
2
portable/ThirdParty/GCC/RP2040/port.c
vendored
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
|
|
|
|||
2
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
vendored
2
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
vendored
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue