mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Add IAR RISC-V port to SVN - a work in progress.
This commit is contained in:
Richard Barry
parent
2b546b1984
commit
ab41d89285
5
FreeRTOS/Source/portable/IAR/RISC-V/Documentation.url
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5
FreeRTOS/Source/portable/IAR/RISC-V/Documentation.url
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[{000214A0-0000-0000-C000-000000000046}]
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Prop3=19,11
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[InternetShortcut]
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IDList=
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URL=https://freertos.org/Using-FreeRTOS-on-RISC-V.html
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@ -0,0 +1,109 @@
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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|
* the Software, and t
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|
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o permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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||||||
|
*
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||||||
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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/*
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* This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
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* devices, developed and tested using the Vega board RV32M1RM.
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 0
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/* Constants to define the additional registers found on the Pulpino RI5KY. */
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#define lpstart0 0x7b0
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#define lpend0 0x7b1
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#define lpcount0 0x7b2
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#define lpstart1 0x7b4
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#define lpend1 0x7b5
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#define lpcount1 0x7b6
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/* Six additional registers to save and restore, as per the #defines above. */
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#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
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/* Save additional registers found on the Pulpino. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
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csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
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csrr t1, lpend0
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csrr t2, lpcount0
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csrr t3, lpstart1
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csrr t4, lpend1
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csrr t5, lpcount1
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sw t0, 1 * portWORD_SIZE( sp )
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sw t1, 2 * portWORD_SIZE( sp )
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sw t2, 3 * portWORD_SIZE( sp )
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sw t3, 4 * portWORD_SIZE( sp )
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sw t4, 5 * portWORD_SIZE( sp )
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sw t5, 6 * portWORD_SIZE( sp )
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.endm
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/* Restore the additional registers found on the Pulpino. */
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
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lw t1, 2 * portWORD_SIZE( sp )
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lw t2, 3 * portWORD_SIZE( sp )
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lw t3, 4 * portWORD_SIZE( sp )
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lw t4, 5 * portWORD_SIZE( sp )
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lw t5, 6 * portWORD_SIZE( sp )
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csrw lpstart0, t0
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csrw lpend0, t1
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csrw lpcount0, t2
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csrw lpstart1, t3
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csrw lpend1, t4
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csrw lpcount1, t5
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addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -0,0 +1,68 @@
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/*
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* FreeRTOS Kernel V10.2.1
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|
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
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* http://www.FreeRTOS.org
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||||||
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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|
*
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|
* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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||||||
|
* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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||||||
|
* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
||||||
|
* compiler's!) include path. For example, if the chip in use includes a core
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||||||
|
* local interrupter (CLINT) and does not include any chip specific register
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||||||
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 1
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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portasmSAVE_ADDITIONAL_REGISTERS MACRO
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/* No additional registers to save, so this macro does nothing. */
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ENDM
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/* Restore the additional registers found on the Pulpino. */
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portasmRESTORE_ADDITIONAL_REGISTERS MACRO
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/* No additional registers to restore, so this macro does nothing. */
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ENDM
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -0,0 +1,23 @@
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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||||||
|
*
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||||||
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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193
FreeRTOS/Source/portable/IAR/RISC-V/port.c
Normal file
193
FreeRTOS/Source/portable/IAR/RISC-V/port.c
Normal file
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@ -0,0 +1,193 @@
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/*
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|
* FreeRTOS Kernel V10.2.1
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|
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* http://www.FreeRTOS.org
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||||||
|
* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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||||||
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the RISC-V RV32 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "portmacro.h"
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#ifndef configCLINT_BASE_ADDRESS
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#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address. Otherwise set configCLINT_BASE_ADDRESS to 0.
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#endif
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
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to use a statically allocated array as the interrupt stack. Alternative leave
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configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
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|
linker variable names __freertos_irq_stack_top has the same value as the top
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of the stack used by main. Using the linker script method will repurpose the
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stack that was used by main before the scheduler was started for use as the
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|
interrupt stack after the scheduler has started. */
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|
#ifdef configISR_STACK_SIZE_WORDS
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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StackType_t xISRStackTop = ( StackType_t ) 0;
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#else
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extern const uint32_t __freertos_irq_stack_top[];
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const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
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#endif
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||||||
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/*
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||||||
|
* Setup the timer to generate the tick interrupts. The implementation in this
|
||||||
|
* file is weak to allow application writers to change the timer used to
|
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* generate the tick interrupt.
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|
*/
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void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
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||||||
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|
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|
/*-----------------------------------------------------------*/
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||||||
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/* Used to program the machine timer compare register. */
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uint64_t ullNextTime = 0ULL;
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const uint64_t *pullNextTime = &ullNextTime;
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const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
|
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volatile uint64_t * const pullMachineTimerCompareRegister = ( uint64_t * ) ( configCLINT_BASE_ADDRESS + 0x4000 );
|
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|
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/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||||
|
stack checking. A problem in the ISR stack will trigger an assert, not call the
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stack overflow hook function (because the stack overflow hook is specific to a
|
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task stack, not the ISR stack). */
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#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#warning This path not tested, or even compiled yet.
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||||
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the task stacks, and so will legitimately appear in many positions within
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the ISR stack. */
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#define portISR_STACK_FILL_BYTE 0xee
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static const uint8_t ucExpectedStackBytes[] = {
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
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||||||
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||||
|
#else
|
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|
/* Define the function away. */
|
||||||
|
#define portCHECK_ISR_STACK()
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||||
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||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if( configCLINT_BASE_ADDRESS != 0 )
|
||||||
|
|
||||||
|
void vPortSetupTimerInterrupt( void )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
|
||||||
|
volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
|
||||||
|
volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ulCurrentTimeHigh = *pulTimeHigh;
|
||||||
|
ulCurrentTimeLow = *pulTimeLow;
|
||||||
|
} while( ulCurrentTimeHigh != *pulTimeHigh );
|
||||||
|
|
||||||
|
ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
|
||||||
|
ullNextTime <<= 32ULL;
|
||||||
|
ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
|
||||||
|
ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
|
||||||
|
*pullMachineTimerCompareRegister = ullNextTime;
|
||||||
|
|
||||||
|
/* Prepare the time to use after the next tick interrupt. */
|
||||||
|
ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
BaseType_t xPortStartScheduler( void )
|
||||||
|
{
|
||||||
|
extern void xPortStartFirstTask( void );
|
||||||
|
#warning Replicate this change in the GCC version.
|
||||||
|
#ifdef configISR_STACK_SIZE_WORDS
|
||||||
|
xISRStackTop = ( ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS - 1 ] ) & ~portBYTE_ALIGNMENT_MASK );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if( configASSERT_DEFINED == 1 )
|
||||||
|
{
|
||||||
|
volatile uint32_t mtvec = 0;
|
||||||
|
|
||||||
|
/* Check the least significant two bits of mtvec are 00 - indicating
|
||||||
|
single vector mode. */
|
||||||
|
__asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */
|
||||||
|
configASSERT( ( mtvec & 0x03UL ) == 0 );
|
||||||
|
|
||||||
|
/* Check alignment of the interrupt stack - which is the same as the
|
||||||
|
stack that was being used by main() prior to the scheduler being
|
||||||
|
started. */
|
||||||
|
configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
|
||||||
|
}
|
||||||
|
#endif /* configASSERT_DEFINED */
|
||||||
|
|
||||||
|
/* If there is a CLINT then it is ok to use the default implementation
|
||||||
|
in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
|
||||||
|
configure whichever clock is to be used to generate the tick interrupt. */
|
||||||
|
vPortSetupTimerInterrupt();
|
||||||
|
|
||||||
|
#if( configCLINT_BASE_ADDRESS != 0 )
|
||||||
|
{
|
||||||
|
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
|
||||||
|
for external interrupt. _RB_ What happens here when mtime is not present as
|
||||||
|
with pulpino? */
|
||||||
|
__asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
{
|
||||||
|
/* Enable external interrupts. */
|
||||||
|
__asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */
|
||||||
|
}
|
||||||
|
#endif /* configCLINT_BASE_ADDRESS */
|
||||||
|
|
||||||
|
xPortStartFirstTask();
|
||||||
|
|
||||||
|
/* Should not get here as after calling xPortStartFirstTask() only tasks
|
||||||
|
should be executing. */
|
||||||
|
return pdFAIL;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vPortEndScheduler( void )
|
||||||
|
{
|
||||||
|
/* Not implemented. */
|
||||||
|
for( ;; );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
426
FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
Normal file
426
FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
Normal file
|
|
@ -0,0 +1,426 @@
|
||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.2.1
|
||||||
|
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* http://www.FreeRTOS.org
|
||||||
|
* http://aws.amazon.com/freertos
|
||||||
|
*
|
||||||
|
* 1 tab == 4 spaces!
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + The code that is common to all RISC-V chips is implemented in
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
|
||||||
|
* portASM.S file because the same file is used no matter which RISC-V chip is
|
||||||
|
* in use.
|
||||||
|
*
|
||||||
|
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
|
||||||
|
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
|
||||||
|
* RISC-V chip that both includes a standard CLINT and does not add to the
|
||||||
|
* base set of RISC-V registers. There are additional
|
||||||
|
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
|
||||||
|
* that do not include a standard CLINT or do add to the base set of RISC-V
|
||||||
|
* registers.
|
||||||
|
*
|
||||||
|
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
|
||||||
|
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
|
||||||
|
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* header file ensure the path to the correct header file is in the assembler's
|
||||||
|
* include path.
|
||||||
|
*
|
||||||
|
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
|
||||||
|
* that include a standard CLINT and do not add to the base set of RISC-V
|
||||||
|
* registers.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#if __riscv_xlen == 64
|
||||||
|
#define portWORD_SIZE 8
|
||||||
|
#define store_x sd
|
||||||
|
#define load_x ld
|
||||||
|
#elif __riscv_xlen == 32
|
||||||
|
#define store_x sw
|
||||||
|
#define load_x lw
|
||||||
|
#define portWORD_SIZE 4
|
||||||
|
#else
|
||||||
|
#error Assembler did not define __riscv_xlen
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "freertos_risc_v_chip_specific_extensions.h"
|
||||||
|
|
||||||
|
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
|
||||||
|
definitions. */
|
||||||
|
#ifndef portasmHAS_CLINT
|
||||||
|
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portasmHANDLE_INTERRUPT
|
||||||
|
#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CSR definitions. */
|
||||||
|
#define CSR_MSTATUS 0x300
|
||||||
|
#define CSR_MTVEC 0x305
|
||||||
|
#define CSR_MEPC 0x341
|
||||||
|
#define CSR_MCAUSE 0x342
|
||||||
|
|
||||||
|
|
||||||
|
/* Only the standard core registers are stored by default. Any additional
|
||||||
|
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
|
||||||
|
specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
|
||||||
|
at the top of this file. */
|
||||||
|
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
|
||||||
|
|
||||||
|
PUBLIC xPortStartFirstTask
|
||||||
|
PUBLIC freertos_risc_v_trap_handler
|
||||||
|
PUBLIC pxPortInitialiseStack
|
||||||
|
EXTERN pxCurrentTCB
|
||||||
|
EXTERN ulPortTrapHandler
|
||||||
|
EXTERN vTaskSwitchContext
|
||||||
|
EXTERN Timer_IRQHandler
|
||||||
|
EXTERN pullMachineTimerCompareRegister
|
||||||
|
EXTERN pullNextTime
|
||||||
|
EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
|
||||||
|
EXTERN xISRStackTop
|
||||||
|
EXTERN xTaskIncrementTick
|
||||||
|
EXTERN portasmHANDLE_INTERRUPT
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
SECTION `.text`:CODE:NOROOT(2)
|
||||||
|
CODE
|
||||||
|
|
||||||
|
freertos_risc_v_trap_handler:
|
||||||
|
addi sp, sp, -portCONTEXT_SIZE
|
||||||
|
store_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
store_x x5, 2 * portWORD_SIZE( sp )
|
||||||
|
store_x x6, 3 * portWORD_SIZE( sp )
|
||||||
|
store_x x7, 4 * portWORD_SIZE( sp )
|
||||||
|
store_x x8, 5 * portWORD_SIZE( sp )
|
||||||
|
store_x x9, 6 * portWORD_SIZE( sp )
|
||||||
|
store_x x10, 7 * portWORD_SIZE( sp )
|
||||||
|
store_x x11, 8 * portWORD_SIZE( sp )
|
||||||
|
store_x x12, 9 * portWORD_SIZE( sp )
|
||||||
|
store_x x13, 10 * portWORD_SIZE( sp )
|
||||||
|
store_x x14, 11 * portWORD_SIZE( sp )
|
||||||
|
store_x x15, 12 * portWORD_SIZE( sp )
|
||||||
|
store_x x16, 13 * portWORD_SIZE( sp )
|
||||||
|
store_x x17, 14 * portWORD_SIZE( sp )
|
||||||
|
store_x x18, 15 * portWORD_SIZE( sp )
|
||||||
|
store_x x19, 16 * portWORD_SIZE( sp )
|
||||||
|
store_x x20, 17 * portWORD_SIZE( sp )
|
||||||
|
store_x x21, 18 * portWORD_SIZE( sp )
|
||||||
|
store_x x22, 19 * portWORD_SIZE( sp )
|
||||||
|
store_x x23, 20 * portWORD_SIZE( sp )
|
||||||
|
store_x x24, 21 * portWORD_SIZE( sp )
|
||||||
|
store_x x25, 22 * portWORD_SIZE( sp )
|
||||||
|
store_x x26, 23 * portWORD_SIZE( sp )
|
||||||
|
store_x x27, 24 * portWORD_SIZE( sp )
|
||||||
|
store_x x28, 25 * portWORD_SIZE( sp )
|
||||||
|
store_x x29, 26 * portWORD_SIZE( sp )
|
||||||
|
store_x x30, 27 * portWORD_SIZE( sp )
|
||||||
|
store_x x31, 28 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
csrr t0, CSR_MSTATUS /* Required for MPIE bit. */
|
||||||
|
store_x t0, 29 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
store_x sp, 0( t0 ) /* Write sp to first TCB member. */
|
||||||
|
|
||||||
|
csrr a0, CSR_MCAUSE
|
||||||
|
csrr a1, CSR_MEPC
|
||||||
|
|
||||||
|
test_if_asynchronous:
|
||||||
|
srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
|
||||||
|
beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
|
||||||
|
store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
|
||||||
|
|
||||||
|
handle_asynchronous:
|
||||||
|
|
||||||
|
#if( portasmHAS_CLINT != 0 )
|
||||||
|
|
||||||
|
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
|
||||||
|
|
||||||
|
addi t0, x0, 1
|
||||||
|
|
||||||
|
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
|
||||||
|
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
|
||||||
|
bne a0, t1, test_if_external_interrupt
|
||||||
|
|
||||||
|
load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
|
||||||
|
load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
|
||||||
|
|
||||||
|
#if( __riscv_xlen == 32 )
|
||||||
|
|
||||||
|
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
|
||||||
|
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
|
||||||
|
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
|
||||||
|
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
|
||||||
|
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */
|
||||||
|
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
||||||
|
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
|
||||||
|
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
|
||||||
|
add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
|
||||||
|
sw t4, 0(t1) /* Store new low word of ullNextTime. */
|
||||||
|
sw t6, 4(t1) /* Store new high word of ullNextTime. */
|
||||||
|
|
||||||
|
#endif /* __riscv_xlen == 32 */
|
||||||
|
|
||||||
|
#if( __riscv_xlen == 64 )
|
||||||
|
|
||||||
|
/* Update the 64-bit mtimer compare match value. */
|
||||||
|
ld t2, 0(t1) /* Load ullNextTime into t2. */
|
||||||
|
sd t2, 0(t0) /* Store ullNextTime into compare register. */
|
||||||
|
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
||||||
|
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
|
||||||
|
sd t4, 0(t1) /* Store ullNextTime. */
|
||||||
|
|
||||||
|
#endif /* __riscv_xlen == 64 */
|
||||||
|
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
||||||
|
jal xTaskIncrementTick
|
||||||
|
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
|
||||||
|
jal vTaskSwitchContext
|
||||||
|
j processed_source
|
||||||
|
|
||||||
|
test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
|
||||||
|
addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
|
||||||
|
bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
|
||||||
|
|
||||||
|
#endif /* portasmHAS_CLINT */
|
||||||
|
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
||||||
|
jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
|
||||||
|
j processed_source
|
||||||
|
|
||||||
|
handle_synchronous:
|
||||||
|
addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
|
||||||
|
store_x a1, 0( sp ) /* Save updated exception return address. */
|
||||||
|
|
||||||
|
test_if_environment_call:
|
||||||
|
li t0, 11 /* 11 == environment call. */
|
||||||
|
bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
||||||
|
jal vTaskSwitchContext
|
||||||
|
j processed_source
|
||||||
|
|
||||||
|
is_exception:
|
||||||
|
ebreak
|
||||||
|
j is_exception
|
||||||
|
|
||||||
|
as_yet_unhandled:
|
||||||
|
ebreak
|
||||||
|
j as_yet_unhandled
|
||||||
|
|
||||||
|
processed_source:
|
||||||
|
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
|
||||||
|
|
||||||
|
/* Load mret with the address of the next instruction in the task to run next. */
|
||||||
|
load_x t0, 0( sp )
|
||||||
|
csrw CSR_MEPC, t0
|
||||||
|
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
/* Load mstatus with the interrupt enable bits used by the task. */
|
||||||
|
load_x t0, 29 * portWORD_SIZE( sp )
|
||||||
|
csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */
|
||||||
|
|
||||||
|
load_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
||||||
|
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||||
|
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||||
|
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||||
|
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||||
|
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||||
|
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||||
|
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||||
|
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||||
|
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||||
|
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||||
|
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||||
|
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||||
|
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||||
|
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||||
|
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||||
|
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||||
|
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||||
|
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||||
|
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||||
|
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||||
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
|
|
||||||
|
mret
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
xPortStartFirstTask:
|
||||||
|
|
||||||
|
#if( portasmHAS_CLINT != 0 )
|
||||||
|
/* If there is a clint then interrupts can branch directly to the FreeRTOS
|
||||||
|
trap handler. Otherwise the interrupt controller will need to be configured
|
||||||
|
outside of this file. */
|
||||||
|
la t0, freertos_risc_v_trap_handler
|
||||||
|
csrw CSR_MTVEC, t0
|
||||||
|
#endif /* portasmHAS_CLILNT */
|
||||||
|
|
||||||
|
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
load_x sp, 0( sp ) /* Read sp from first TCB member. */
|
||||||
|
|
||||||
|
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
||||||
|
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */
|
||||||
|
csrrw x0, CSR_MSTATUS, t0 /* Interrupts enabled from here! */
|
||||||
|
|
||||||
|
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
||||||
|
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||||
|
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||||
|
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||||
|
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||||
|
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||||
|
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||||
|
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||||
|
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||||
|
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||||
|
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||||
|
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||||
|
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||||
|
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||||
|
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||||
|
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||||
|
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||||
|
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||||
|
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||||
|
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||||
|
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||||
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
|
ret
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
|
||||||
|
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
|
||||||
|
* for the function is as per the other ports:
|
||||||
|
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
||||||
|
*
|
||||||
|
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
||||||
|
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
||||||
|
*
|
||||||
|
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
||||||
|
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
||||||
|
*
|
||||||
|
* Register ABI Name Description Saver
|
||||||
|
* x0 zero Hard-wired zero -
|
||||||
|
* x1 ra Return address Caller
|
||||||
|
* x2 sp Stack pointer Callee
|
||||||
|
* x3 gp Global pointer -
|
||||||
|
* x4 tp Thread pointer -
|
||||||
|
* x5-7 t0-2 Temporaries Caller
|
||||||
|
* x8 s0/fp Saved register/Frame pointer Callee
|
||||||
|
* x9 s1 Saved register Callee
|
||||||
|
* x10-11 a0-1 Function Arguments/return values Caller
|
||||||
|
* x12-17 a2-7 Function arguments Caller
|
||||||
|
* x18-27 s2-11 Saved registers Callee
|
||||||
|
* x28-31 t3-6 Temporaries Caller
|
||||||
|
*
|
||||||
|
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
||||||
|
* where the global and thread pointers are currently assumed to be constant so
|
||||||
|
* are not saved:
|
||||||
|
*
|
||||||
|
* mstatus
|
||||||
|
* x31
|
||||||
|
* x30
|
||||||
|
* x29
|
||||||
|
* x28
|
||||||
|
* x27
|
||||||
|
* x26
|
||||||
|
* x25
|
||||||
|
* x24
|
||||||
|
* x23
|
||||||
|
* x22
|
||||||
|
* x21
|
||||||
|
* x20
|
||||||
|
* x19
|
||||||
|
* x18
|
||||||
|
* x17
|
||||||
|
* x16
|
||||||
|
* x15
|
||||||
|
* x14
|
||||||
|
* x13
|
||||||
|
* x12
|
||||||
|
* x11
|
||||||
|
* pvParameters
|
||||||
|
* x9
|
||||||
|
* x8
|
||||||
|
* x7
|
||||||
|
* x6
|
||||||
|
* x5
|
||||||
|
* portTASK_RETURN_ADDRESS
|
||||||
|
* [chip specific registers go here]
|
||||||
|
* pxCode
|
||||||
|
*/
|
||||||
|
pxPortInitialiseStack:
|
||||||
|
|
||||||
|
csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
|
||||||
|
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
||||||
|
slli t1, t1, 4
|
||||||
|
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||||
|
|
||||||
|
addi a0, a0, -portWORD_SIZE
|
||||||
|
store_x t0, 0(a0) /* mstatus onto the stack. */
|
||||||
|
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||||
|
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||||
|
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||||
|
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
||||||
|
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||||
|
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||||
|
beq t0, x0, no_more_regs /* No more chip specific registers to save. */
|
||||||
|
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||||
|
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||||
|
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||||
|
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||||
|
no_more_regs:
|
||||||
|
addi a0, a0, -portWORD_SIZE
|
||||||
|
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||||
|
ret
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
149
FreeRTOS/Source/portable/IAR/RISC-V/portmacro.h
Normal file
149
FreeRTOS/Source/portable/IAR/RISC-V/portmacro.h
Normal file
|
|
@ -0,0 +1,149 @@
|
||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.2.1
|
||||||
|
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* http://www.FreeRTOS.org
|
||||||
|
* http://aws.amazon.com/freertos
|
||||||
|
*
|
||||||
|
* 1 tab == 4 spaces!
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef PORTMACRO_H
|
||||||
|
#define PORTMACRO_H
|
||||||
|
|
||||||
|
#include "intrinsics.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------
|
||||||
|
* Port specific definitions.
|
||||||
|
*
|
||||||
|
* The settings in this file configure FreeRTOS correctly for the
|
||||||
|
* given hardware and compiler.
|
||||||
|
*
|
||||||
|
* These settings should not be altered.
|
||||||
|
*-----------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Type definitions. */
|
||||||
|
#if __riscv_xlen == 64
|
||||||
|
#define portSTACK_TYPE uint64_t
|
||||||
|
#define portBASE_TYPE int64_t
|
||||||
|
#define portUBASE_TYPE uint64_t
|
||||||
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
|
||||||
|
#define portPOINTER_SIZE_TYPE uint64_t
|
||||||
|
#elif __riscv_xlen == 32
|
||||||
|
#define portSTACK_TYPE uint32_t
|
||||||
|
#define portBASE_TYPE int32_t
|
||||||
|
#define portUBASE_TYPE uint32_t
|
||||||
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||||
|
#else
|
||||||
|
#error Assembler did not define __riscv_xlen
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
typedef portSTACK_TYPE StackType_t;
|
||||||
|
typedef portBASE_TYPE BaseType_t;
|
||||||
|
typedef portUBASE_TYPE UBaseType_t;
|
||||||
|
typedef portUBASE_TYPE TickType_t;
|
||||||
|
|
||||||
|
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||||
|
not need to be guarded with a critical section. */
|
||||||
|
#define portTICK_TYPE_IS_ATOMIC 1
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Architecture specifics. */
|
||||||
|
#define portSTACK_GROWTH ( -1 )
|
||||||
|
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||||
|
#ifdef __riscv64
|
||||||
|
#error This is the RV32 port that has not yet been adapted for 64.
|
||||||
|
#define portBYTE_ALIGNMENT 16
|
||||||
|
#else
|
||||||
|
#define portBYTE_ALIGNMENT 8
|
||||||
|
#endif
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Scheduler utilities. */
|
||||||
|
extern void vTaskSwitchContext( void );
|
||||||
|
#define portYIELD() __asm volatile( "ecall" );
|
||||||
|
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
|
||||||
|
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Critical section management. */
|
||||||
|
#define portCRITICAL_NESTING_IN_TCB 1
|
||||||
|
extern void vTaskEnterCritical( void );
|
||||||
|
extern void vTaskExitCritical( void );
|
||||||
|
|
||||||
|
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
|
||||||
|
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
|
||||||
|
#define portDISABLE_INTERRUPTS() __disable_interrupt()
|
||||||
|
#define portENABLE_INTERRUPTS() __enable_interrupt()
|
||||||
|
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||||
|
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Architecture specific optimisations. */
|
||||||
|
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||||
|
|
||||||
|
#error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
|
||||||
|
|
||||||
|
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||||
|
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||||
|
not necessary for to use this port. They are defined so the common demo files
|
||||||
|
(which build with all the ports) will build. */
|
||||||
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define portNOP() __asm volatile ( " nop " )
|
||||||
|
|
||||||
|
#define portINLINE __inline
|
||||||
|
|
||||||
|
#ifndef portFORCE_INLINE
|
||||||
|
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||||
|
|
||||||
|
|
||||||
|
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
|
||||||
|
the source code because to do so would cause other compilers to generate
|
||||||
|
warnings. */
|
||||||
|
#pragma diag_suppress=Pa082
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* PORTMACRO_H */
|
||||||
|
|
||||||
23
FreeRTOS/Source/portable/IAR/RISC-V/readme.txt
Normal file
23
FreeRTOS/Source/portable/IAR/RISC-V/readme.txt
Normal file
|
|
@ -0,0 +1,23 @@
|
||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
|
||||||
|
* is common to all currently supported RISC-V chips. There is only one
|
||||||
|
* portASM.S file because the same file is built for all RISC-V target chips.
|
||||||
|
*
|
||||||
|
* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
|
||||||
|
* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
|
||||||
|
* as there are multiple RISC-V chip implementations.
|
||||||
|
*
|
||||||
|
* !!!NOTE!!!
|
||||||
|
* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
||||||
|
* compiler's!) include path. For example, if the chip in use includes a core
|
||||||
|
* local interrupter (CLINT) and does not include any chip specific register
|
||||||
|
* extensions then add the path below to the assembler's include path:
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
||||||
|
*
|
||||||
|
*/
|
||||||
Loading…
Reference in a new issue