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Add XMC4200 and XMC4400 build configurations to the XMC4000 Dave project.

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This commit is contained in:
Richard Barry 2013-09-04 14:22:45 +00:00
parent 6acac72ff1
commit aaf2d32011
19 changed files with 50259 additions and 3344 deletions
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252
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject
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@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.ifx.xmc4000.appDebug.607051084">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.607051084" moduleId="org.eclipse.cdt.core.settings" name="XMC4500">
<cconfiguration id="com.ifx.xmc4000.appDebug.1453655874">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.1453655874" moduleId="org.eclipse.cdt.core.settings" name="XMC4200">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@ -18,89 +18,259 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="com.ifx.xmc4000.appBuildArtefactType" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.ifx.xmc4000.appBuildArtefactType" description="" id="com.ifx.xmc4000.appDebug.607051084" name="XMC4500" parent="com.ifx.xmc4000.appDebug">
<folderInfo id="com.ifx.xmc4000.appDebug.607051084." name="/" resourcePath="">
<toolChain id="com.ifx.xmc4000.appDebug.toolChain.1759539149" name="ARM-GCC Application for XMC" superClass="com.ifx.xmc4000.appDebug.toolChain">
<option id="com.ifx.xmc4000.option.debugging.level.1802412347" name="Debug level" superClass="com.ifx.xmc4000.option.debugging.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.debugging.level.max" valueType="enumerated"/>
<option id="com.ifx.xmc4000.option.targetPath.75554300" name="Target Path" superClass="com.ifx.xmc4000.option.targetPath" value="/ProcessorsInfo/XMC4000/XMC4500 Series/XMC4500-F144x1024" valueType="string"/>
<option id="com.ifx.xmc4000.option.targetName.1214792959" name="Target Name" superClass="com.ifx.xmc4000.option.targetName" value="XMC4500-F144x1024" valueType="string"/>
<option id="com.ifx.xmc4000.option.startupFilePrefrence.2100908094" name="Startup File Preference" superClass="com.ifx.xmc4000.option.startupFilePrefrence" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.ifx.xmc4000.targetPlatform.1734084429" isAbstract="false" name="Windows Platform" osList="win32" superClass="com.ifx.xmc4000.targetPlatform"/>
<builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.1543365862" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>
<tool id="com.ifx.xmc4000.appDebug.compiler.1635621846" name="ARM-GCC C Compiler" superClass="com.ifx.xmc4000.appDebug.compiler">
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level.1306428872" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.compiler.option.include.paths.2132094169" name="Include paths (-I)" superClass="com.ifx.xmc4000.compiler.option.include.paths" valueType="includePath">
<configuration artifactName="${ProjName}" buildArtefactType="com.ifx.xmc4000.appBuildArtefactType" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.ifx.xmc4000.appBuildArtefactType" description="" id="com.ifx.xmc4000.appDebug.1453655874" name="XMC4200" parent="com.ifx.xmc4000.appDebug">
<folderInfo id="com.ifx.xmc4000.appDebug.1453655874." name="/" resourcePath="">
<toolChain id="com.ifx.xmc4000.appDebug.toolChain.1886697968" name="ARM-GCC Application for XMC" superClass="com.ifx.xmc4000.appDebug.toolChain">
<option id="com.ifx.xmc4000.option.debugging.level.1879389544" name="Debug level" superClass="com.ifx.xmc4000.option.debugging.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.debugging.level.max" valueType="enumerated"/>
<option id="com.ifx.xmc4000.option.targetPath.97106059" name="Target Path" superClass="com.ifx.xmc4000.option.targetPath" value="/ProcessorsInfo/XMC4000/XMC4200_XMC4100 Series/XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.targetName.1668214183" name="Target Name" superClass="com.ifx.xmc4000.option.targetName" value="XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.startupFilePrefrence.796665719" name="Startup File Preference" superClass="com.ifx.xmc4000.option.startupFilePrefrence" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.ifx.xmc4000.targetPlatform.2046970274" isAbstract="false" name="Windows Platform" osList="win32" superClass="com.ifx.xmc4000.targetPlatform"/>
<builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.1012966589" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>
<tool id="com.ifx.xmc4000.appDebug.compiler.1907520373" name="ARM-GCC C Compiler" superClass="com.ifx.xmc4000.appDebug.compiler">
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level.780749541" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.compiler.option.include.paths.768764347" name="Include paths (-I)" superClass="com.ifx.xmc4000.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Common_Demo_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM4F}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/System}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4500_series/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def.597668784" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def.11557608" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4206"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.947657962" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input"/>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.954136299" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cppcompiler.1089177015" name="ARM-GCC C++ Compiler" superClass="com.ifx.xmc4000.appDebug.cppcompiler">
<option id="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level.478794105" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.cppcompiler.option.include.paths.1815651512" name="Include paths (-I)" superClass="com.ifx.xmc4000.cppcompiler.option.include.paths" valueType="includePath">
<tool id="com.ifx.xmc4000.appDebug.cppcompiler.657201994" name="ARM-GCC C++ Compiler" superClass="com.ifx.xmc4000.appDebug.cppcompiler">
<option id="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level.1054359607" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.cppcompiler.option.include.paths.1033005408" name="Include paths (-I)" superClass="com.ifx.xmc4000.cppcompiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include/c++/4.6.2&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4500_series/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
</tool>
<tool id="com.ifx.xmc4000.appDebug.assembler.1113299181" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">
<option id="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def.1414012373" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
<tool id="com.ifx.xmc4000.appDebug.assembler.73635964" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">
<option id="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def.1954230453" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4206"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.859825253" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input"/>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1581584502" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.linker.540417974" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">
<option id="com.ifx.xmc4000.appLinker.option.scriptfile.1274916363" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4500.ld" valueType="string"/>
<inputType id="com.ifx.xmc4000.appLinker.inputType.193148015" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">
<tool id="com.ifx.xmc4000.appDebug.linker.299859653" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">
<option id="com.ifx.xmc4000.appLinker.option.scriptfile.2042277734" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4200.ld" valueType="string"/>
<inputType id="com.ifx.xmc4000.appLinker.inputType.1850249191" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cpplinker.1425994416" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>
<tool id="com.ifx.xmc4000.libLinker.1022326266" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>
<tool id="com.ifx.xmc4000.appDebug.createflash.496475414" name="ARM-GCC Create Flash Image" superClass="com.ifx.xmc4000.appDebug.createflash"/>
<tool id="com.ifx.xmc4000.appDebug.createlisting.130181717" name="ARM-GCC Create Listing" superClass="com.ifx.xmc4000.appDebug.createlisting"/>
<tool id="com.ifx.xmc4000.printsize.1124241582" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>
<tool id="com.ifx.xmc4000.appDebug.cpplinker.285292256" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>
<tool id="com.ifx.xmc4000.libLinker.1062716079" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>
<tool id="com.ifx.xmc4000.appDebug.createflash.260401566" name="ARM-GCC Create Flash Image" superClass="com.ifx.xmc4000.appDebug.createflash"/>
<tool id="com.ifx.xmc4000.appDebug.createlisting.370765939" name="ARM-GCC Create Listing" superClass="com.ifx.xmc4000.appDebug.createlisting"/>
<tool id="com.ifx.xmc4000.printsize.341592086" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="Startup/startup_XMC4400.s|Startup/System_XMC4400.c|Startup/startup_XMC4500.s|Startup/system_XMC4500.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.ifx.xmc4000.appDebug.1453655874.134052553">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.1453655874.134052553" moduleId="org.eclipse.cdt.core.settings" name="XMC4500">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ifx.xmc4000.errorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="com.ifx.xmc4000.appBuildArtefactType" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.ifx.xmc4000.appBuildArtefactType" description="" id="com.ifx.xmc4000.appDebug.1453655874.134052553" name="XMC4500" parent="com.ifx.xmc4000.appDebug">
<folderInfo id="com.ifx.xmc4000.appDebug.1453655874.134052553." name="/" resourcePath="">
<toolChain id="com.ifx.xmc4000.appDebug.toolChain.2038296907" name="ARM-GCC Application for XMC" superClass="com.ifx.xmc4000.appDebug.toolChain">
<option id="com.ifx.xmc4000.option.debugging.level.1742298511" name="Debug level" superClass="com.ifx.xmc4000.option.debugging.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.debugging.level.max" valueType="enumerated"/>
<option id="com.ifx.xmc4000.option.targetPath.583580844" name="Target Path" superClass="com.ifx.xmc4000.option.targetPath" value="/ProcessorsInfo/XMC4000/XMC4200_XMC4100 Series/XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.targetName.1531420586" name="Target Name" superClass="com.ifx.xmc4000.option.targetName" value="XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.startupFilePrefrence.1783367097" name="Startup File Preference" superClass="com.ifx.xmc4000.option.startupFilePrefrence" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.ifx.xmc4000.targetPlatform.1318721646" isAbstract="false" name="Windows Platform" osList="win32" superClass="com.ifx.xmc4000.targetPlatform"/>
<builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.1720842399" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>
<tool id="com.ifx.xmc4000.appDebug.compiler.1798219001" name="ARM-GCC C Compiler" superClass="com.ifx.xmc4000.appDebug.compiler">
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level.688763838" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.compiler.option.include.paths.610924922" name="Include paths (-I)" superClass="com.ifx.xmc4000.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Common_Demo_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM4F}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/System}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def.2040762925" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
</option>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.datasections.1982698035" name="Function sections (-fdata-sections)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.datasections" value="true" valueType="boolean"/>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.2084291505" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cppcompiler.663408094" name="ARM-GCC C++ Compiler" superClass="com.ifx.xmc4000.appDebug.cppcompiler">
<option id="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level.500727063" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.cppcompiler.option.include.paths.1519355055" name="Include paths (-I)" superClass="com.ifx.xmc4000.cppcompiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include/c++/4.6.2&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
</tool>
<tool id="com.ifx.xmc4000.appDebug.assembler.388967637" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">
<option id="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def.118944342" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4502"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1806736785" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.linker.1227007552" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">
<option id="com.ifx.xmc4000.appLinker.option.scriptfile.932571486" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4500.ld" valueType="string"/>
<option id="com.ifx.xmc4000.appLinker.option.gcsections.1404968826" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.ifx.xmc4000.appLinker.option.gcsections" value="true" valueType="boolean"/>
<inputType id="com.ifx.xmc4000.appLinker.inputType.120773479" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cpplinker.1847163170" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>
<tool id="com.ifx.xmc4000.libLinker.2038648355" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>
<tool id="com.ifx.xmc4000.appDebug.createflash.199374187" name="ARM-GCC Create Flash Image" superClass="com.ifx.xmc4000.appDebug.createflash"/>
<tool id="com.ifx.xmc4000.appDebug.createlisting.1969313402" name="ARM-GCC Create Listing" superClass="com.ifx.xmc4000.appDebug.createlisting"/>
<tool id="com.ifx.xmc4000.printsize.1308578423" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="Startup/startup_XMC4400.s|Startup/System_XMC4400.c|Startup/startup_XMC4200.s|Startup/System_XMC4200.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.ifx.xmc4000.appDebug.1453655874.51075279">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.1453655874.51075279" moduleId="org.eclipse.cdt.core.settings" name="XMC4400">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ifx.xmc4000.errorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="com.ifx.xmc4000.appBuildArtefactType" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.ifx.xmc4000.appBuildArtefactType" description="" id="com.ifx.xmc4000.appDebug.1453655874.51075279" name="XMC4400" parent="com.ifx.xmc4000.appDebug">
<folderInfo id="com.ifx.xmc4000.appDebug.1453655874.51075279." name="/" resourcePath="">
<toolChain id="com.ifx.xmc4000.appDebug.toolChain.2108354968" name="ARM-GCC Application for XMC" superClass="com.ifx.xmc4000.appDebug.toolChain">
<option id="com.ifx.xmc4000.option.debugging.level.1441190288" name="Debug level" superClass="com.ifx.xmc4000.option.debugging.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.debugging.level.max" valueType="enumerated"/>
<option id="com.ifx.xmc4000.option.targetPath.1612570582" name="Target Path" superClass="com.ifx.xmc4000.option.targetPath" value="/ProcessorsInfo/XMC4000/XMC4200_XMC4100 Series/XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.targetName.121104047" name="Target Name" superClass="com.ifx.xmc4000.option.targetName" value="XMC4200-Q48x256" valueType="string"/>
<option id="com.ifx.xmc4000.option.startupFilePrefrence.830579589" name="Startup File Preference" superClass="com.ifx.xmc4000.option.startupFilePrefrence" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.ifx.xmc4000.targetPlatform.1581097885" isAbstract="false" name="Windows Platform" osList="win32" superClass="com.ifx.xmc4000.targetPlatform"/>
<builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.572070356" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>
<tool id="com.ifx.xmc4000.appDebug.compiler.1327409573" name="ARM-GCC C Compiler" superClass="com.ifx.xmc4000.appDebug.compiler">
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level.1028662146" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.compiler.option.include.paths.1444078301" name="Include paths (-I)" superClass="com.ifx.xmc4000.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Common_Demo_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM4F}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/System}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
<option id="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def.1646100019" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.c.compiler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4400"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.1121966342" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cppcompiler.454612406" name="ARM-GCC C++ Compiler" superClass="com.ifx.xmc4000.appDebug.cppcompiler">
<option id="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level.745240577" name="Optimization level" superClass="org.eclipse.cdt.cross.arm.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.arm.gnu.base.option.optimization.level.none" valueType="enumerated"/>
<option id="com.ifx.xmc4000.cppcompiler.option.include.paths.973886291" name="Include paths (-I)" superClass="com.ifx.xmc4000.cppcompiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/Include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../emWin/Start/GUI/inc&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ARM_GCC_HOME}/arm-none-eabi/include/c++/4.6.2&quot;"/>
<listOptionValue builtIn="false" value="&quot;${eclipse_home}/../CMSIS/Infineon/XMC4200-4100_series/Include&quot;"/>
</option>
</tool>
<tool id="com.ifx.xmc4000.appDebug.assembler.1309583224" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">
<option id="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def.503490445" name="Defined symbols (-D)" superClass="org.eclipse.cdt.cross.arm.gnu.assembler.option.preprocessor.def" valueType="definedSymbols">
<listOptionValue builtIn="false" value="UC_ID=4206"/>
</option>
<inputType id="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1048422861" superClass="org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input"/>
</tool>
<tool id="com.ifx.xmc4000.appDebug.linker.6344778" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">
<option id="com.ifx.xmc4000.appLinker.option.scriptfile.318472598" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4400.ld" valueType="string"/>
<inputType id="com.ifx.xmc4000.appLinker.inputType.2046328081" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.ifx.xmc4000.appDebug.cpplinker.96427232" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>
<tool id="com.ifx.xmc4000.libLinker.1560176163" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>
<tool id="com.ifx.xmc4000.appDebug.createflash.1728255655" name="ARM-GCC Create Flash Image" superClass="com.ifx.xmc4000.appDebug.createflash"/>
<tool id="com.ifx.xmc4000.appDebug.createlisting.702553969" name="ARM-GCC Create Listing" superClass="com.ifx.xmc4000.appDebug.createlisting"/>
<tool id="com.ifx.xmc4000.printsize.243767898" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="Startup/startup_XMC4500.s|Startup/system_XMC4500.c|Startup/System_XMC4200.c|Startup/startup_XMC4200.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="RTOSDemo.com.ifx.xmc4000.appProject.1454830415" name="ARM-GCC Application for XMC Project" projectType="com.ifx.xmc4000.appProject"/>
<project id="RTOSDemo.com.ifx.xmc4000.appProject.869320741" name="ARM-GCC Application for XMC Project" projectType="com.ifx.xmc4000.appProject"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.compiler.1453708254;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.403412067">
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.1453655874;com.ifx.xmc4000.appDebug.1453655874.;com.ifx.xmc4000.appDebug.compiler.1907520373;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.954136299">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.assembler.1016067260;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1614170329">
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.1453655874;com.ifx.xmc4000.appDebug.1453655874.;com.ifx.xmc4000.appDebug.assembler.73635964;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1581584502">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.compiler.1635621846;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.947657962">
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.936302067;com.ifx.xmc4000.appRelease.936302067.;com.ifx.xmc4000.appRelease.assembler.157732027;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.2088827819">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.assembler.1113299181;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.859825253">
<scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.936302067;com.ifx.xmc4000.appRelease.936302067.;com.ifx.xmc4000.appRelease.compiler.1262078806;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.1284762204">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
<project-mappings/>
</storageModule>
<storageModule moduleId="refreshScope"/>
<storageModule moduleId="refreshScope" versionNumber="1">
<resource resourceType="PROJECT" workspacePath="/RTOSDemo"/>
</storageModule>
</cproject>

31
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4200.jlink Normal file
View file

@ -0,0 +1,31 @@
[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

31
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4400.jlink Normal file
View file

@ -0,0 +1,31 @@
[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

4
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink
View file

@ -15,8 +15,8 @@ SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
Override = 1
Device="XMC4500-1024"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00

4
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h
View file

@ -169,7 +169,7 @@ standard names. */
#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
#elif defined( PART_XMC4400 )
#elif UC_ID == 4400
/* Hardware includes. */
#include "XMC4400.h"
#include "System_XMC4200.h"
@ -178,7 +178,7 @@ standard names. */
#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )
#elif defined( PART_XMC4200 )
#elif UC_ID == 4206
/* Hardware includes. */
#include "XMC4200.h"
#include "System_XMC4200.h"

3299
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h
View file

File diff suppressed because it is too large Load diff

174
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4200.ld Normal file
View file

@ -0,0 +1,174 @@
/* Generated Linker Script file */
/*
* Template Version 1.2 dated 19 Nov 2012
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(__Xmc4200_reset_cortex_m)
GROUP(-lxmclibcstubs)
MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x40000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x40000
PSRAM_1(!RX) : ORIGIN = 0x1FFFE000, LENGTH = 0x2000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x6000
SRAM_combined(!RX) : ORIGIN = 0x1FFFE000, LENGTH = 0x8000
}
stack_size = 2048;
SECTIONS
{
/* TEXT section */
.text : AT(ORIGIN(FLASH_1_uncached))
{
sText = .;
*(.Xmc4200.reset);
*(.Xmc4200.postreset);
*(.XmcStartup);
*(.text .text.* .gnu.linkonce.t.*);
/* ARM <->THUMB interworking */
*(.glue*)
*(.v4*)
*(.vfp11_veneer)
/* C++ Support */
KEEP(*(.init))
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP(*(.fini))
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* Exception handling support */
__extab_start = .;
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
__extab_end = ABSOLUTE(.);
} > FLASH_1_cached
/* Exception handling, exidx needs a dedicated section */
.ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
. = ALIGN(4);
__exidx_end = ABSOLUTE(.);
} > FLASH_1_cached
/* CONST data section */
.rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000)
{
*(.rodata .rodata.*)
*(.gnu.linkonce.r*)
} > FLASH_1_cached
. = ALIGN(16);
/* End of RO-DATA and start of LOAD region for DATA */
eROData = . | 0x04000000;
/* DSRAM layout (Lowest to highest)*/
/* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */
/* Dummy section for stack */
Stack (NOLOAD) :
{
. = . + stack_size;
__Xmc4200_stack = .;
} > SRAM_combined
/* BSS section */
.bss :
{
__Xmc4200_sBSS = .;
* (.bss);
* (.bss*);
* (COMMON);
*(.gnu.linkonce.b*)
__Xmc4200_eBSS = ALIGN(4);
} > SRAM_combined
/* Yes, the size must be kept outside */
__Xmc4200_BSS_Size = __Xmc4200_eBSS - __Xmc4200_sBSS;
/* Standard DATA and user defined DATA/BSS/CONST sections */
.data ABSOLUTE(ALIGN(16)): AT(eROData)
{
__Xmc4200_sData = .;
* (.data);
* (.data*);
*(*.data);
*(.gnu.linkonce.d*)
__Xmc4200_eData = ALIGN(4);
} > SRAM_combined
/* Yes, the size must be kept outside */
__Xmc4200_Data_Size = __Xmc4200_eData - __Xmc4200_sData;
/* Heap - Bank1*/
__Xmc4200_heap_start = ALIGN(8);
__Xmc4200_heap_end = ORIGIN(SRAM_combined) + LENGTH (SRAM_combined);
Heap_Bank1_Start = __Xmc4200_heap_start;
Heap_Bank1_Size = __Xmc4200_heap_end - __Xmc4200_heap_start;
Heap_Bank1_End = ABSOLUTE(__Xmc4200_heap_end);
/DISCARD/ :
{
*(.comment)
}
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Build attributes */
.build_attributes 0 : { *(.ARM.attributes) }
}

175
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4400.ld Normal file
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@ -0,0 +1,175 @@
/* Generated Linker Script file */
/*
* Template Version 1.2 dated 19 Nov 2012
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(__Xmc4400_reset_cortex_m)
GROUP(-lxmclibcstubs)
MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x80000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x80000
PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x8000
DSRAM_2_comm(!RX) : ORIGIN = 0x20008000, LENGTH = 0x8000
SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x14000
}
stack_size = 2048;
SECTIONS
{
/* TEXT section */
.text : AT(ORIGIN(FLASH_1_uncached))
{
sText = .;
*(.Xmc4400.reset);
*(.Xmc4400.postreset);
*(.XmcStartup);
*(.text .text.* .gnu.linkonce.t.*);
/* ARM <->THUMB interworking */
*(.glue*)
*(.v4*)
*(.vfp11_veneer)
/* C++ Support */
KEEP(*(.init))
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP(*(.fini))
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* Exception handling support */
__extab_start = .;
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
__extab_end = ABSOLUTE(.);
} > FLASH_1_cached
/* Exception handling, exidx needs a dedicated section */
.ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
. = ALIGN(4);
__exidx_end = ABSOLUTE(.);
} > FLASH_1_cached
/* CONST data section */
.rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000)
{
*(.rodata .rodata.*)
*(.gnu.linkonce.r*)
} > FLASH_1_cached
. = ALIGN(16);
/* End of RO-DATA and start of LOAD region for DATA */
eROData = . | 0x04000000;
/* DSRAM layout (Lowest to highest)*/
/* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */
/* Dummy section for stack */
Stack (NOLOAD) :
{
. = . + stack_size;
__Xmc4400_stack = .;
} > SRAM_combined
/* BSS section */
.bss :
{
__Xmc4400_sBSS = .;
* (.bss);
* (.bss*);
* (COMMON);
*(.gnu.linkonce.b*)
__Xmc4400_eBSS = ALIGN(4);
} > SRAM_combined
/* Yes, the size must be kept outside */
__Xmc4400_BSS_Size = __Xmc4400_eBSS - __Xmc4400_sBSS;
/* Standard DATA and user defined DATA/BSS/CONST sections */
.data ABSOLUTE(ALIGN(16)): AT(eROData)
{
__Xmc4400_sData = .;
* (.data);
* (.data*);
*(*.data);
*(.gnu.linkonce.d*)
__Xmc4400_eData = ALIGN(4);
} > SRAM_combined
/* Yes, the size must be kept outside */
__Xmc4400_Data_Size = __Xmc4400_eData - __Xmc4400_sData;
/* Heap - Bank1*/
__Xmc4400_heap_start = ALIGN(8);
__Xmc4400_heap_end = ORIGIN(SRAM_combined) + LENGTH (SRAM_combined);
Heap_Bank1_Start = __Xmc4400_heap_start;
Heap_Bank1_Size = __Xmc4400_heap_end - __Xmc4400_heap_start;
Heap_Bank1_End = ABSOLUTE(__Xmc4400_heap_end);
/DISCARD/ :
{
*(.comment)
}
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Build attributes */
.build_attributes 0 : { *(.ARM.attributes) }
}

708
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4200.c Normal file
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@ -0,0 +1,708 @@
/**************************************************************************//**
* @file system_XMC4200.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4000 Device Series
* @version V3.0.1 Alpha
* @date 26. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <system_XMC4200.h>
#include <XMC4200.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 80000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 5
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 5
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4400.c Normal file
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/**************************************************************************//**
* @file system_XMC4400.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4500 Device Series
* @version V3.0.1 Alpha
* @date 17. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <system_XMC4400.h>
#include <XMC4400.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 120000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 3
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 3
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

559
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4200.s Normal file
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@ -0,0 +1,559 @@
/*****************************************************************************/
/* Startup_XMC4200.s: Startup file for XMC4200 device series */
/*****************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V0.1 , Sep, 13, 2012 ES : initial version
V0.2 , Oct, 12, 2012 PKB: C++ support
V0.3 , Jan, 26, 2013 PKB: Workaround for prefetch bug
**************************************************************************** */
/**
* @file Startup_XMC4200.s
* XMC4000 Device Series
* @version V0.3
* @date Jan 2013
*
Copyright (C) 2013 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <uc_id.inc>
/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
/*
* STEP_AB and below have the prefetch bug. A veneer defined below will first
* be executed which in turn branches to the final exception handler.
*
* In addition to defining the veneers, the vector table must for these buggy
* devices contain the veneers.
*/
/* A macro to setup a vector table entry based on STEP ID */
.macro Entry Handler
#if (UC_STEP > STEP_AA)
.long \Handler
#else
.long \Handler\()_Veneer
#endif
.endm
/* A macro to ease definition of the various handlers based on STEP ID */
#if (UC_STEP == STEP_AA)
/* First define the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
/* And then define a veneer that will branch to the final excp handler */
.weak \Handler_Func\()_Veneer
.type \Handler_Func\()_Veneer, %function
\Handler_Func\()_Veneer:
LDR R0, =\Handler_Func
PUSH {LR}
BLX R0
POP {PC}
.size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
.endm
#else
/* No prefetch bug, hence define only the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
.endm
#endif
/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This gets programed into VTOR register by onchip BootROM */
.syntax unified
.section ".Xmc4200.reset"
.globl __Xmc4200_interrupt_vector_cortex_m
.type __Xmc4200_interrupt_vector_cortex_m, %object
__Xmc4200_interrupt_vector_cortex_m:
.long __Xmc4200_stack /* Top of Stack */
.long __Xmc4200_reset_cortex_m /* Reset Handler */
Entry NMI_Handler /* NMI Handler */
Entry HardFault_Handler /* Hard Fault Handler */
Entry MemManage_Handler /* MPU Fault Handler */
Entry BusFault_Handler /* Bus Fault Handler */
Entry UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
Entry DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */
Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.long 0 /* Not Available */
Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */
Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */
Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */
Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */
Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */
Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.long 0 /* Not Available */
Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
.long 0 /* Not Available */
Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.size __Xmc4200_interrupt_vector_cortex_m, . - __Xmc4200_interrupt_vector_cortex_m
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.thumb
/* ======================================================================== */
/* Reset Handler */
.thumb_func
.globl __Xmc4200_reset_cortex_m
.type __Xmc4200_reset_cortex_m, %function
__Xmc4200_reset_cortex_m:
.fnstart
/* C routines are likely to be called. Setup the stack now */
/* This is already setup by BootROM,hence this step is optional */
LDR SP,=__Xmc4200_stack
/* Clock tree, External memory setup etc may be done here */
LDR R0, =SystemInit
BLX R0
/*
SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
weakly defined here though for a potential override.
*/
LDR R0, =SystemInit_DAVE3
BLX R0
B __Xmc4200_Program_Loader
.pool
.cantunwind
.fnend
.size __Xmc4200_reset_cortex_m,.-__Xmc4200_reset_cortex_m
/* ======================================================================== */
/* __Xmc4200_reset must yield control to __Xmc4200_Program_Loader before control
to C land is given */
.section .Xmc4200.postreset,"x",%progbits
__Xmc4200_Program_Loader:
.fnstart
/* Memories are accessible now*/
/* DATA COPY */
/* R0 = Start address, R1 = Destination address, R2 = Size */
LDR R0, =eROData
LDR R1, =__Xmc4200_sData
LDR R2, =__Xmc4200_Data_Size
/* Is there anything to be copied? */
CMP R2,#0
BEQ SKIPCOPY
/* For bytecount less than 4, at least 1 word must be copied */
CMP R2,#4
BCS STARTCOPY
/* Byte count < 4 ; so bump it up */
MOV R2,#4
STARTCOPY:
/*
R2 contains byte count. Change it to word count. It is ensured in the
linker script that the length is always word aligned.
*/
LSR R2,R2,#2 /* Divide by 4 to obtain word count */
/* The proverbial loop from the schooldays */
COPYLOOP:
LDR R3,[R0]
STR R3,[R1]
SUBS R2,#1
BEQ SKIPCOPY
ADD R0,#4
ADD R1,#4
B COPYLOOP
SKIPCOPY:
/* BSS CLEAR */
LDR R0, =__Xmc4200_sBSS /* Start of BSS */
LDR R1, =__Xmc4200_BSS_Size /* BSS size in bytes */
/* Find out if there are items assigned to BSS */
CMP R1,#0
BEQ SKIPCLEAR
/* At least 1 word must be copied */
CMP R1,#4
BCS STARTCLEAR
/* Byte count < 4 ; so bump it up to a word*/
MOV R1,#4
STARTCLEAR:
LSR R1,R1,#2 /* BSS size in words */
MOV R2,#0
CLEARLOOP:
STR R2,[R0]
SUBS R1,#1
BEQ SKIPCLEAR
ADD R0,#4
B CLEARLOOP
SKIPCLEAR:
/* Remap vector table */
/* This is already setup by BootROM,hence this step is optional */
LDR R0, =__Xmc4200_interrupt_vector_cortex_m
LDR R1, =SCB_VTOR
STR R0,[R1]
/* Update System Clock */
LDR R0,=SystemCoreClockUpdate
BLX R0
/* C++ : Call the global constructor */
LDR R0,=__libc_init_array
BLX R0
/* Reset stack pointer before zipping off to user application, Optional */
LDR SP,=__Xmc4200_stack
MOV R0,#0
MOV R1,#0
LDR PC, =main
.pool
.cantunwind
.fnend
.size __Xmc4200_Program_Loader,.-__Xmc4200_Program_Loader
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
/* Default exception Handlers - Users may override this default functionality by
defining handlers of the same name in their C code */
.thumb
.text
Insert_ExceptionHandler NMI_Handler
/* ======================================================================== */
Insert_ExceptionHandler HardFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler MemManage_Handler
/* ======================================================================== */
Insert_ExceptionHandler BusFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler UsageFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler SVC_Handler
/* ======================================================================== */
Insert_ExceptionHandler DebugMon_Handler
/* ======================================================================== */
Insert_ExceptionHandler PendSV_Handler
/* ======================================================================== */
Insert_ExceptionHandler SysTick_Handler
/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
/* IRQ Handlers */
Insert_ExceptionHandler SCU_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler PMU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_6_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_7_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler LEDTS0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler FCE0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler GPDMA0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USB0_0_IRQHandler
/* ======================================================================== */
/* ======================================================================== */
/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
/* ========= Decision function queried by CMSIS startup for PLL setup ======== */
/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
tree setup.
This decision routine defined here will always return TRUE.
When overridden by a definition defined in DAVE code engine, this routine
returns FALSE indicating that the code engine has performed the clock setup
*/
.weak AllowPLLInitByStartup
.type AllowPLLInitByStartup, %function
AllowPLLInitByStartup:
MOV R0,#1
BX LR
.size AllowPLLInitByStartup, . - AllowPLLInitByStartup
/* ====== Definition of the default weak SystemInit_DAVE3 function =========
If DAVE3 requires an extended SystemInit it will create its own version of
SystemInit_DAVE3 which overrides this weak definition. Example includes
setting up of external memory interfaces.
*/
.section ".XmcStartup"
.weak SystemInit_DAVE3
.type SystemInit_DAVE3, %function
SystemInit_DAVE3:
NOP
BX LR
.size SystemInit_DAVE3, . - SystemInit_DAVE3
/* ======================================================================== */
/* ======================================================================== */
/* ======================== Data references =============================== */
.equ SCB_VTOR, 0xE000ED08
.equ PREF_PCON, 0x58004000
.equ SCU_GCU_PEEN, 0x5000413C
.equ SCU_GCU_PEFLAG, 0x50004150
.equ FLASH_FCON, 0x58002014
.end

621
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4400.s Normal file
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@ -0,0 +1,621 @@
/*****************************************************************************/
/* Startup_XMC4400.s: Startup file for XMC4400 device series */
/*****************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V0.1 , Aug, 13, 2012 ES: initial version
V0.2 , Oct, 12, 2012 PKB: C++ support
V0.3 , Jan, 25, 2013 PKB: Prefetch bug workaround for STEP_AA
**************************************************************************** */
/**
* @file Startup_XMC4400.s
* XMC4000 Device Series
* @version V0.3
* @date Jan 2013
*
Copyright (C) 2013 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <uc_id.inc>
/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
/*
* STEP_AB and below have the prefetch bug. A veneer defined below will first
* be executed which in turn branches to the final exception handler.
*
* In addition to defining the veneers, the vector table must for these buggy
* devices contain the veneers.
*/
/* A macro to setup a vector table entry based on STEP ID */
.macro Entry Handler
#if (UC_STEP > STEP_AA)
.long \Handler
#else
.long \Handler\()_Veneer
#endif
.endm
/* A macro to ease definition of the various handlers based on STEP ID */
#if (UC_STEP == STEP_AA)
/* First define the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
/* And then define a veneer that will branch to the final excp handler */
.weak \Handler_Func\()_Veneer
.type \Handler_Func\()_Veneer, %function
\Handler_Func\()_Veneer:
LDR R0, =\Handler_Func
PUSH {LR}
BLX R0
POP {PC}
.size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
.endm
#else
/* No prefetch bug, hence define only the final exception handler */
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.type \Handler_Func, %function
\Handler_Func:
B .
.size \Handler_Func, . - \Handler_Func
.endm
#endif
/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This gets programed into VTOR register by onchip BootROM */
.syntax unified
.section ".Xmc4400.reset"
.globl __Xmc4400_interrupt_vector_cortex_m
.type __Xmc4400_interrupt_vector_cortex_m, %object
__Xmc4400_interrupt_vector_cortex_m:
.long __Xmc4400_stack /* Top of Stack */
.long __Xmc4400_reset_cortex_m /* Reset Handler */
Entry NMI_Handler /* NMI Handler */
Entry HardFault_Handler /* Hard Fault Handler */
Entry MemManage_Handler /* MPU Fault Handler */
Entry BusFault_Handler /* Bus Fault Handler */
Entry UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
Entry DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals */
Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.long 0 /* Not Available */
Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
Entry DSD0_0_IRQHandler /* Handler name for SR DSD_SRM_0 */
Entry DSD0_1_IRQHandler /* Handler name for SR DSD_SRM_1 */
Entry DSD0_2_IRQHandler /* Handler name for SR DSD_SRM_2 */
Entry DSD0_3_IRQHandler /* Handler name for SR DSD_SRM_3 */
Entry DSD0_4_IRQHandler /* Handler name for SR DSD_SRA_0 */
Entry DSD0_5_IRQHandler /* Handler name for SR DSD_SRA_1 */
Entry DSD0_6_IRQHandler /* Handler name for SR DSD_SRA_2 */
Entry DSD0_7_IRQHandler /* Handler name for SR DSD_SRA_3 */
Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */
Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */
Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */
Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */
Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */
Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.long 0 /* Not Available */
Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
.long 0 /* Not Available */
Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.size __Xmc4400_interrupt_vector_cortex_m, . - __Xmc4400_interrupt_vector_cortex_m
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.thumb
/* ======================================================================== */
/* Reset Handler */
.thumb_func
.globl __Xmc4400_reset_cortex_m
.type __Xmc4400_reset_cortex_m, %function
__Xmc4400_reset_cortex_m:
.fnstart
/* C routines are likely to be called. Setup the stack now */
/* This is already setup by BootROM,hence this step is optional */
LDR SP,=__Xmc4400_stack
/* Clock tree, External memory setup etc may be done here */
LDR R0, =SystemInit
BLX R0
/*
SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
weakly defined here though for a potential override.
*/
LDR R0, =SystemInit_DAVE3
BLX R0
B __Xmc4400_Program_Loader
.pool
.cantunwind
.fnend
.size __Xmc4400_reset_cortex_m,.-__Xmc4400_reset_cortex_m
/* ======================================================================== */
/* __Xmc4400_reset must yield control to __Xmc4400_Program_Loader before control
to C land is given */
.section .Xmc4400.postreset,"x",%progbits
__Xmc4400_Program_Loader:
.fnstart
/* Memories are accessible now*/
/* DATA COPY */
/* R0 = Start address, R1 = Destination address, R2 = Size */
LDR R0, =eROData
LDR R1, =__Xmc4400_sData
LDR R2, =__Xmc4400_Data_Size
/* Is there anything to be copied? */
CMP R2,#0
BEQ SKIPCOPY
/* For bytecount less than 4, at least 1 word must be copied */
CMP R2,#4
BCS STARTCOPY
/* Byte count < 4 ; so bump it up */
MOV R2,#4
STARTCOPY:
/*
R2 contains byte count. Change it to word count. It is ensured in the
linker script that the length is always word aligned.
*/
LSR R2,R2,#2 /* Divide by 4 to obtain word count */
/* The proverbial loop from the schooldays */
COPYLOOP:
LDR R3,[R0]
STR R3,[R1]
SUBS R2,#1
BEQ SKIPCOPY
ADD R0,#4
ADD R1,#4
B COPYLOOP
SKIPCOPY:
/* BSS CLEAR */
LDR R0, =__Xmc4400_sBSS /* Start of BSS */
LDR R1, =__Xmc4400_BSS_Size /* BSS size in bytes */
/* Find out if there are items assigned to BSS */
CMP R1,#0
BEQ SKIPCLEAR
/* At least 1 word must be copied */
CMP R1,#4
BCS STARTCLEAR
/* Byte count < 4 ; so bump it up to a word*/
MOV R1,#4
STARTCLEAR:
LSR R1,R1,#2 /* BSS size in words */
MOV R2,#0
CLEARLOOP:
STR R2,[R0]
SUBS R1,#1
BEQ SKIPCLEAR
ADD R0,#4
B CLEARLOOP
SKIPCLEAR:
/* Remap vector table */
/* This is already setup by BootROM,hence this step is optional */
LDR R0, =__Xmc4400_interrupt_vector_cortex_m
LDR R1, =SCB_VTOR
STR R0,[R1]
/* Update System Clock */
LDR R0,=SystemCoreClockUpdate
BLX R0
/* C++ : Call the global constructor */
LDR R0,=__libc_init_array
BLX R0
/* Reset stack pointer before zipping off to user application, Optional */
LDR SP,=__Xmc4400_stack
MOV R0,#0
MOV R1,#0
LDR PC, =main
.pool
.cantunwind
.fnend
.size __Xmc4400_Program_Loader,.-__Xmc4400_Program_Loader
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
/* Default exception Handlers - Users may override this default functionality by
defining handlers of the same name in their C code */
.thumb
.text
Insert_ExceptionHandler NMI_Handler
/* ======================================================================== */
Insert_ExceptionHandler HardFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler MemManage_Handler
/* ======================================================================== */
Insert_ExceptionHandler BusFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler UsageFault_Handler
/* ======================================================================== */
Insert_ExceptionHandler SVC_Handler
/* ======================================================================== */
Insert_ExceptionHandler DebugMon_Handler
/* ======================================================================== */
Insert_ExceptionHandler PendSV_Handler
/* ======================================================================== */
Insert_ExceptionHandler SysTick_Handler
/* ======================================================================== */
/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
/* IRQ Handlers */
Insert_ExceptionHandler SCU_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ERU1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler PMU0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_C0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G2_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler VADC0_G3_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_6_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DSD0_7_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler DAC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU40_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU41_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU42_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU43_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU80_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CCU81_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler POSIF1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler HRPWM_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_6_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler CAN0_7_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC0_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_1_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_2_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_3_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_4_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USIC1_5_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler LEDTS0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler FCE0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler GPDMA0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler USB0_0_IRQHandler
/* ======================================================================== */
Insert_ExceptionHandler ETH0_0_IRQHandler
/* ======================================================================== */
/* ======================================================================== */
/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
/* ========= Decision function queried by CMSIS startup for PLL setup ======== */
/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
tree setup.
This decision routine defined here will always return TRUE.
When overridden by a definition defined in DAVE code engine, this routine
returns FALSE indicating that the code engine has performed the clock setup
*/
.weak AllowPLLInitByStartup
.type AllowPLLInitByStartup, %function
AllowPLLInitByStartup:
MOV R0,#1
BX LR
.size AllowPLLInitByStartup, . - AllowPLLInitByStartup
/* ====== Definition of the default weak SystemInit_DAVE3 function =========
If DAVE3 requires an extended SystemInit it will create its own version of
SystemInit_DAVE3 which overrides this weak definition. Example includes
setting up of external memory interfaces.
*/
.section ".XmcStartup"
.weak SystemInit_DAVE3
.type SystemInit_DAVE3, %function
SystemInit_DAVE3:
NOP
BX LR
.size SystemInit_DAVE3, . - SystemInit_DAVE3
/* ======================================================================== */
/* ======================================================================== */
/* ======================== Data references =============================== */
.equ SCB_VTOR, 0xE000ED08
.equ PREF_PCON, 0x58004000
.equ SCU_GCU_PEEN, 0x5000413C
.equ SCU_GCU_PEFLAG, 0x50004150
.equ FLASH_FCON, 0x58002014
.end

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/System_XMC4500.h Normal file
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@ -0,0 +1,114 @@
/**************************************************************************//**
* @file system_XMC4500.h
* @brief Header file for the XMC4500-Series systeminit
*
* @version V1.6
* @date 23. October 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4500_H
#define __SYSTEM_XMC4500_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
/*
* mandatory clock parameters **************************************************
*/
/* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
* mandatory for old system_xmc4500.c files - please do not remove!!!
**************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
#define CLOCK_OSC_HP 24000000
#define CLOCK_BACK_UP 24000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define SYSTEM_FREQUENCY 120000000
/* OSC_HP setup parameters */
#define OSC_HP_MODE 0
#define OSCHPWDGDIV 2
/* MAIN PLL setup parameters */
#define PLL_K1DIV 1
#define PLL_K2DIV 3
#define PLL_PDIV 1
#define PLL_NDIV 79
#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
#define USBPLL_PDIV 1
#define USBPLL_NDIV 15
#ifdef __cplusplus
}
#endif
#endif

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/**************************************************************************//**
* @file system_XMC4200.h
* @brief Header file for the XMC4200-Series systeminit
*
* @version V1.0
* @date 27. August 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4200_H
#define __SYSTEM_XMC4200_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
#ifdef __cplusplus
}
#endif
#endif

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/**************************************************************************//**
* @file system_XMC4400.h
* @brief Header file for the XMC4400-Series systeminit
*
* @version V1.0
* @date 17. August 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4400_H
#define __SYSTEM_XMC4400_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
#ifdef __cplusplus
}
#endif
#endif

7
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c
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@ -648,6 +648,13 @@ static void prvRegTest2Task( void *pvParameters )
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" \n"
" /* Yield to increase test coverage. */ \n"
" movs r0, #0x01 \n"
" ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */
" lsl r0, #28 \n" /* Shift to PendSV bit */
" str r0, [r1] \n"
" dsb \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"