mirror of
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synced 2025-04-19 21:11:57 -04:00
Interrupt priority assert improvements for CM3/4/7 (#602)
* Interrupt priority assert improvements for CM3/4/7 In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that `configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the number of priority bits implemented by the hardware. Change these ports to also use the lowest priority for PendSV and SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`. * Remove not needed configKERNEL_INTERRUPT_PRIORITY define Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> --------- Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Chris Copeland
GitHub
parent
c3e1df031e
commit
a9e1f66849
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@ -52,8 +52,9 @@
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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@ -239,6 +240,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -56,8 +56,9 @@
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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@ -258,6 +259,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -34,13 +34,6 @@
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#include "FreeRTOS.h"
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#include "task.h"
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/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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* defined. The value should also ensure backward compatibility.
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* FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 255
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#endif
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/* Constants required to manipulate the core. Registers first... */
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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@ -55,8 +48,9 @@
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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@ -265,10 +259,6 @@ static void prvPortStartFirstTask( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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@ -293,6 +283,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -83,8 +83,9 @@
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/* Constants required to access and manipulate the SysTick. */
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#define portNVIC_SYSTICK_INT ( 0x00000002UL )
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#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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/* Constants required to set up the initial stack. */
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@ -381,10 +382,6 @@ static void prvRestoreContextOfFirstTask( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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@ -409,6 +406,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -58,8 +58,9 @@
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#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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@ -295,10 +296,6 @@ static void prvPortStartFirstTask( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port can be used on all revisions of the Cortex-M7 core other than
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* the r0p1 parts. r0p1 parts should use the port from the
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* /source/portable/GCC/ARM_CM7/r0p1 directory. */
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@ -329,6 +326,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -93,8 +93,9 @@
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/* Constants required to access and manipulate the SysTick. */
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#define portNVIC_SYSTICK_INT ( 0x00000002UL )
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#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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/* Constants required to manipulate the VFP. */
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@ -412,10 +413,6 @@ static void prvRestoreContextOfFirstTask( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
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* and r0p1 cores. */
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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@ -452,6 +449,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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@ -52,8 +52,9 @@
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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@ -289,10 +290,6 @@ static void prvPortStartFirstTask( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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@ -317,6 +314,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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* defined. The value 255 should also ensure backward compatibility.
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* FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 0
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#endif
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/* Each task maintains its own interrupt status in the critical nesting
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* variable. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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* defined. The value 255 should also ensure backward compatibility.
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* FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 255
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#endif
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/* Let the user override the default SysTick clock rate. If defined by the
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* user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
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* configuration register. */
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@ -214,10 +208,6 @@ static void prvTaskExitError( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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@ -242,6 +232,14 @@ BaseType_t xPortStartScheduler( void )
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -65,8 +65,9 @@
|
|||
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
|
||||
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -239,10 +240,6 @@ static void prvTaskExitError( void )
|
|||
*/
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
|
||||
/* This port can be used on all revisions of the Cortex-M7 core other than
|
||||
* the r0p1 parts. r0p1 parts should use the port from the
|
||||
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
|
||||
|
|
@ -273,6 +270,14 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -104,8 +104,9 @@
|
|||
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
|
||||
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
|
|
@ -346,10 +347,6 @@ void vPortSVCHandler_C( uint32_t * pulParam )
|
|||
*/
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
|
||||
/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
|
||||
* and r0p1 cores. */
|
||||
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
|
||||
|
|
@ -386,6 +383,14 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -59,8 +59,9 @@
|
|||
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
|
||||
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -233,10 +234,6 @@ static void prvTaskExitError( void )
|
|||
*/
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
|
||||
#if ( configASSERT_DEFINED == 1 )
|
||||
{
|
||||
volatile uint32_t ulOriginalPriority;
|
||||
|
|
@ -261,6 +258,14 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -48,8 +48,9 @@
|
|||
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
|
||||
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -295,10 +296,6 @@ static void prvPortStartFirstTask( void )
|
|||
*/
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
|
||||
#if ( configASSERT_DEFINED == 1 )
|
||||
{
|
||||
volatile uint32_t ulOriginalPriority;
|
||||
|
|
@ -320,13 +317,17 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Read the value back to see how many bits stuck. */
|
||||
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
||||
|
||||
/* The kernel interrupt priority should be set to the lowest
|
||||
* priority. */
|
||||
configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
|
||||
|
||||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -34,10 +34,6 @@
|
|||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#ifndef configKERNEL_INTERRUPT_PRIORITY
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 255
|
||||
#endif
|
||||
|
||||
#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
#endif
|
||||
|
|
@ -65,8 +61,9 @@
|
|||
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
|
||||
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -285,13 +282,17 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Read the value back to see how many bits stuck. */
|
||||
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
||||
|
||||
/* The kernel interrupt priority should be set to the lowest
|
||||
* priority. */
|
||||
configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
|
||||
|
||||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -71,8 +71,9 @@
|
|||
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
|
||||
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -347,13 +348,17 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Read the value back to see how many bits stuck. */
|
||||
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
||||
|
||||
/* The kernel interrupt priority should be set to the lowest
|
||||
* priority. */
|
||||
configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
|
||||
|
||||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -83,8 +83,9 @@
|
|||
#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
|
||||
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
|
||||
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
|
||||
|
||||
/* Constants required to manipulate the VFP. */
|
||||
|
|
@ -442,6 +443,14 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -65,8 +65,9 @@
|
|||
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
|
||||
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Constants required to check the validity of an interrupt priority. */
|
||||
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
|
||||
|
|
@ -331,13 +332,17 @@ BaseType_t xPortStartScheduler( void )
|
|||
/* Read the value back to see how many bits stuck. */
|
||||
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
||||
|
||||
/* The kernel interrupt priority should be set to the lowest
|
||||
* priority. */
|
||||
configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
|
||||
|
||||
/* Use the same mask on the maximum system call priority. */
|
||||
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||||
|
||||
/* Check that the maximum system call priority is nonzero after
|
||||
* accounting for the number of priority bits supported by the
|
||||
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
||||
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
||||
* cannot be masked using BASEPRI.
|
||||
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
||||
configASSERT( ucMaxSysCallPriority );
|
||||
|
||||
/* Calculate the maximum acceptable priority group value for the number
|
||||
* of bits read back. */
|
||||
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||||
|
|
|
|||
|
|
@ -41,8 +41,9 @@
|
|||
#define portNVIC_SYSTICK_CLK 0x00000004
|
||||
#define portNVIC_SYSTICK_INT 0x00000002
|
||||
#define portNVIC_SYSTICK_ENABLE 0x00000001
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
|
||||
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
|
||||
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
|
||||
|
||||
/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
|
||||
#define portVECTACTIVE_MASK ( 0xFFUL )
|
||||
|
|
@ -70,7 +71,7 @@
|
|||
|
||||
/* The priority used by the kernel is assigned to a variable to make access
|
||||
* from inline assembler easier. */
|
||||
const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
|
||||
const uint32_t ulKernelPriority = portMIN_INTERRUPT_PRIORITY;
|
||||
|
||||
/* Each task maintains its own interrupt status in the critical nesting
|
||||
* variable. */
|
||||
|
|
|
|||
Loading…
Reference in a new issue