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Merge commit.
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a730a56a14
4 changed files with 6 additions and 42 deletions
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@ -38,6 +38,8 @@ Changes between FreeRTOS V10.4.0 and FreeRTOS V10.3.1 released September 1 2020
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the same way the Windows port layer enables FreeRTOS to run on Windows
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hosts.
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+ Many other minor optimisations and enhancements.
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+ Many other minor optimisations and enhancements. For full details
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see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/master
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Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020
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@ -90,12 +90,7 @@
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do { \
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if( (xSwitchRequired) != pdFALSE ) portYIELD(); \
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} while (0)
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -146,20 +146,6 @@
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/* Adding the necessary stuff in order to be able to determine from C code wheter or not the IRQs are enabled at the processor level (not interrupt controller level) */
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#define GET_CPSR() \
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( { u32 rval = 0U; \
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__asm__ __volatile__ ( \
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"mrs %0, cpsr\n"\
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: "=r" ( rval ) \
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); \
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rval; \
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} )
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#define CPSR_IRQ_ENABLE_MASK 0x80U
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#define IS_IRQ_DISABLED() ( { unsigned int val = 0; val = ( GET_CPSR() & CPSR_IRQ_ENABLE_MASK ) ? 1 : 0; val; } )
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/*-----------------------------------------------------------*/
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/*
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@ -481,12 +467,6 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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uint32_t ulPortSetInterruptMask( void )
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{
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uint32_t ulReturn;
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uint32_t wasIRQDisabled;
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/* We keep track of if the IRQ are enabled in the CPU (as opposed to interrupts masked in the interrupt controller, like the intend of this function).
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* This is very important because when the CPU is interrupted, among other things, the hardware clears the IRQ Enable bit in the CPSR of the IRQ CPU Mode in which
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* we enter. */
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wasIRQDisabled = IS_IRQ_DISABLED();
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/* Interrupt in the CPU must be turned off while the ICCPMR is being
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* updated. */
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@ -505,20 +485,7 @@ uint32_t ulPortSetInterruptMask( void )
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"isb \n"::: "memory" );
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}
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/* Just like this function returns a value of wether or not the interrupts where masked in the interrupt controller in order to avoid race condition when
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* calling its matching vPortClearInterruptMask function, we needed a 'wasIRQDisabled' variable holding the state of the IRQ Enable bit in the CPSR in order
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* to leave that bit in it's original state. Like mentioned above, hardware automatically clear the IRQEnable bit upon trapping into IRQ Mode, so the programmer
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* cannot make assumption about it's state. Very rare, but very important race condition is avoided with this when this function is called in an ISR. The race
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* condition in question was discovered when integrating tracealyzer code. Inside the function 'void vTaskSwitchContext( void )' in tasks.c, there is a macro 'traceTASK_SWITCHED_IN();'
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* which gets replaced by something when using the tracing capabilities. That macro protects some critical section with matching calls to 'ulPortSetInterruptMask'
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* and 'vPortClearInterruptMask'. At the time of calling those functions, the interrupt mask is not set in the interrupt controller, thus the only protecting barrier
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* against the CPU traping into recursive interrupt was the IRQ Enable bit in the CPSR. By not taking it into acount, the very code that protects the CPU against
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* critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a
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* switch of context while already performing a switch context. */
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if( !wasIRQDisabled )
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{
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portCPU_IRQ_ENABLE();
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}
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portCPU_IRQ_ENABLE();
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return ulReturn;
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}
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@ -28,8 +28,8 @@
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#include <Windows.h>
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#include <WinBase.h>
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#include <windows.h>
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#include <winbase.h>
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/******************************************************************************
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Defines
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