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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-03 12:53:52 -04:00
Start to configure the uIP demo for the RX RDK hardware. ping is working, but thus far the web server is not.
This commit is contained in:
Richard Barry
parent
2e0af9b6e6
commit
a4893aed60
8 changed files with 153 additions and 85 deletions
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@ -55,7 +55,6 @@
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#include "iodefine.h"
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#include "typedefine.h"
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#include "r_ether.h"
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#include "phy.h"
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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@ -95,28 +94,24 @@ become free. */
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/*-----------------------------------------------------------*/
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/* The buffers and descriptors themselves. */
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static union x_RX_Desc
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{
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unsigned long long ullAlignmentVariable;
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ethfifo xDescriptorArray[ emacNUM_RX_DESCRIPTORS ];
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} xRxDescriptors;
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/* The buffers and descriptors themselves. */
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#pragma section _RX_DESC
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volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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#pragma section _TX_DESC
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volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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#pragma section _ETHERNET_BUFFERS
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struct
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{
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unsigned long ulAlignmentVariable;
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char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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} xEthernetBuffers;
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#pragma section
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static union x_TX_Desc
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{
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unsigned long long ullAlignmentVariable;
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ethfifo xDescriptorArray[ emacNUM_TX_BUFFERS ];
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} xTxDescriptors;
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static union x_ETH_Buffers
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{
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unsigned long long ullAlignmentVariable;
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char xDataBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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} xEthernetBuffers;
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/* Used to indicate which buffers are free and which are in use. If an index
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contains 0 then the corresponding buffer in xEthernetBuffers.xDataBuffers is free, otherwise
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contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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the buffer is in use or about to be used. */
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static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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@ -128,7 +123,7 @@ static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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static void prvInitialiseDescriptors( void );
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/*
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* Return a pointer to a free buffer within xEthernetBuffers.xDataBuffers.
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* Return a pointer to a free buffer within xEthernetBuffers.
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*/
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static unsigned char *prvGetNextBuffer( void );
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@ -204,7 +199,7 @@ long x;
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/* Wait until the second transmission of the last packet has completed. */
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for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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{
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if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )
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if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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{
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/* Descriptor is still active. */
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vTaskDelay( emacTX_WAIT_DELAY_ms );
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@ -216,27 +211,27 @@ long x;
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}
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/* Is the descriptor free after waiting for it? */
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if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )
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if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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{
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/* Something has gone wrong. */
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prvResetEverything();
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}
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/* Setup both descriptors to transmit the frame. */
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xTxDescriptors.xDescriptorArray[ 0 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors.xDescriptorArray[ 0 ].bufsize = uip_len;
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xTxDescriptors.xDescriptorArray[ 1 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors.xDescriptorArray[ 1 ].bufsize = uip_len;
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xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors[ 0 ].bufsize = uip_len;
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xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors[ 1 ].bufsize = uip_len;
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/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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for use by the stack. */
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uip_buf = prvGetNextBuffer();
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/* Clear previous settings and go. */
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xTxDescriptors.xDescriptorArray[0].status &= ~( FP1 | FP0 );
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xTxDescriptors.xDescriptorArray[0].status |= ( FP1 | FP0 | ACT );
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xTxDescriptors.xDescriptorArray[1].status &= ~( FP1 | FP0 );
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xTxDescriptors.xDescriptorArray[1].status |= ( FP1 | FP0 | ACT );
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xTxDescriptors[0].status &= ~( FP1 | FP0 );
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xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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xTxDescriptors[1].status &= ~( FP1 | FP0 );
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xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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EDMAC.EDTRR.LONG = 0x00000001;
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}
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@ -282,15 +277,28 @@ long lReturn;
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{
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/* Half duplex link */
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case PHY_LINK_100H:
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case PHY_LINK_10H:
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ETHERC.ECMR.BIT.DM = 0;
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ETHERC.ECMR.BIT.RTM = 1;
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lReturn = pdPASS;
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break;
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case PHY_LINK_10H:
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ETHERC.ECMR.BIT.DM = 0;
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ETHERC.ECMR.BIT.RTM = 0;
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lReturn = pdPASS;
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break;
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/* Full duplex link */
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case PHY_LINK_100F:
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ETHERC.ECMR.BIT.DM = 1;
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ETHERC.ECMR.BIT.RTM = 1;
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lReturn = pdPASS;
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break;
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case PHY_LINK_10F:
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ETHERC.ECMR.BIT.DM = 1;
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ETHERC.ECMR.BIT.RTM = 0;
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lReturn = pdPASS;
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break;
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@ -327,13 +335,13 @@ long x;
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/* Initialise the Rx descriptors. */
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for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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{
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pxDescriptor = &( xRxDescriptors.xDescriptorArray[ x ] );
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pxDescriptor->buf_p = &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );
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pxDescriptor = &( xRxDescriptors[ x ] );
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pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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pxDescriptor->bufsize = UIP_BUFSIZE;
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pxDescriptor->size = 0;
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pxDescriptor->status = ACT;
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pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ x + 1 ];
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pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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/* Mark this buffer as in use. */
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ucBufferInUse[ x ] = pdTRUE;
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@ -341,12 +349,12 @@ long x;
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/* The last descriptor points back to the start. */
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pxDescriptor->status |= DL;
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pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ 0 ];
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pxDescriptor->next = &xRxDescriptors[ 0 ];
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/* Initialise the Tx descriptors. */
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for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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{
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pxDescriptor = &( xTxDescriptors.xDescriptorArray[ x ] );
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pxDescriptor = &( xTxDescriptors[ x ] );
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/* A buffer is not allocated to the Tx descriptor until a send is
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actually required. */
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@ -355,15 +363,15 @@ long x;
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pxDescriptor->bufsize = UIP_BUFSIZE;
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pxDescriptor->size = 0;
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pxDescriptor->status = 0;
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pxDescriptor->next = &xTxDescriptors.xDescriptorArray[ x + 1 ];
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pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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}
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/* The last descriptor points back to the start. */
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pxDescriptor->status |= DL;
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pxDescriptor->next = &( xTxDescriptors.xDescriptorArray[ 0 ] );
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pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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/* Use the first Rx descriptor to start with. */
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xCurrentRxDesc = &( xRxDescriptors.xDescriptorArray[ 0 ] );
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xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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}
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/*-----------------------------------------------------------*/
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@ -382,7 +390,7 @@ unsigned long ulAttempts = 0;
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if( ucBufferInUse[ x ] == pdFALSE )
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{
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ucBufferInUse[ x ] = pdTRUE;
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pucReturn = ( unsigned char * ) &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );
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pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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break;
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}
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}
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@ -413,7 +421,7 @@ unsigned long ul;
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/* Return a buffer to the pool of free buffers. */
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for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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{
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if( &( xEthernetBuffers.xDataBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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{
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ucBufferInUse[ ul ] = pdFALSE;
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break;
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@ -503,12 +511,18 @@ static void prvConfigureEtherCAndEDMAC( void )
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/* EDMAC */
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EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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#ifdef __LIT
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EDMAC.EDMR.BIT.DE = 1;
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#endif
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EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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EDMAC.TDLAR = &( xTxDescriptors.xDescriptorArray[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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/* Enable the interrupt... */
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_IEN( _ETHER_EINT ) = 1;
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}
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/*-----------------------------------------------------------*/
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@ -527,7 +541,7 @@ static long ulTxEndInts = 0;
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if( ulTxEndInts >= 2 )
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{
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/* Only return the buffer to the pool once both Txes have completed. */
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prvReturnBuffer( ( void * ) xTxDescriptors.xDescriptorArray[ 0 ].buf_p );
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prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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ulTxEndInts = 0;
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}
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EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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@ -542,3 +556,4 @@ static long ulTxEndInts = 0;
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EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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}
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}
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@ -114,7 +114,7 @@ typedef unsigned short uip_stats_t;
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*
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* \hideinitializer
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*/
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#define UIP_CONF_BYTE_ORDER UIP_BIG_ENDIAN
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#define UIP_CONF_BYTE_ORDER UIP_LITTLE_ENDIAN
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/**
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* Logging on or off
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