mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add PIC32MEC14xx port and demo application.
This commit is contained in:
Richard Barry
parent
f19497c3d6
commit
a29dc8d6c6
103 changed files with 49682 additions and 6 deletions
642
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx.h
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642
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx.h
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/*****************************************************************************
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* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
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* You may use this software and any derivatives exclusively with
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* Microchip products.
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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* OF THESE TERMS.
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*****************************************************************************/
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/** @file mec14xx.h
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*MEC14xx master header
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*/
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/** @defgroup MEC14xx
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*/
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/**
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* MEC14xx initial version
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*/
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#ifndef MEC14XX_DEFS_H
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#define MEC14XX_DEFS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup MEC14xx_Definitions
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This file defines all structures and symbols for MEC14xx:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- Peripheral definitions
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@{
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*/
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/** MEC14xx Hardware memory maps.
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* @note
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* Common
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*
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* MEC1404
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* 96KB CODE SRAM
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* 32KB DATA SRAM
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*
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* Physical Virtual Length
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* CODE SRAM 0x1FD0_0000 - 0x1FD1_7FFF 0xBFD0_0000 - 0xBFD1_7FFF 96KB (0x18000)
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* DATA SRAM 0x1FD1_8000 - 0x1FD1_FFFF 0xBFD1_8000 - 0xBFD1_FFFF 32KB
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* CPP Regs 0x1FFF_C000 - 0x1FFF_FFFF 0xBFFF_C000 - 0xBFFF_FFFF 16KB
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*
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* MEC1418
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* 160KB CODE SRAM
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* 32KB DATA SRAM
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*
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* Physical Virtual Length
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* CODE SRAM 0x1FCF_0000 - 0x1FD1_7FFF 0xBFCF_0000 - 0xBFD1_7FFF 128KB (0x20000)
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* DATA SRAM 0x1FD1_8000 - 0x1FD1_FFFF 0xBFD1_8000 - 0xBFD1_FFFF 32KB
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* CPP Regs 0x1FFF_C000 - 0x1FFF_FFFF 0xBFFF_C000 - 0xBFFF_FFFF 16KB
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*
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*/
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#define MEC14XX_TRUE (1ul)
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#define MEC14XX_FALSE (0ul)
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#define MEC14XX_ON (1ul)
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#define MEC14XX_OFF (0ul)
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#define MEC14XX_ENABLE (1ul)
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#define MEC14XX_DISABLE (0ul)
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#define MEC14XX_ROM_PBASE (0x1FC00000ul)
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#define MEC14XX_ROM_PBLEN (1024ul * 64ul)
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#define MEC14XX_ROM_PLIMIT ((MEC14XX_ROM_PBASE) + (MEC14XX_ROM_PBLEN))
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#define MEC14XX_ROM_VBASE (0xBFC00000ul)
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#define MEC14XX_ROM_VBLEN (1024ul * 64ul)
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#define MEC14XX_ROM_VLIMIT ((MEC14XX_ROM_VBASE) + (MEC14XX_ROM_VBLEN))
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/* MEC1404 */
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#define MEC1404_ICODE_PSRAM_BASE (0x1FD00000ul)
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#define MEC1404_ICODE_PSRAM_BLEN (1024ul * 96ul)
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#define MEC1404_ICODE_PSRAM_LIMIT ((MEC1404_ICODE_PSRAM_SM_BASE)+(MEC1404_ICODE_PSRAM_SM_BLEN))
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// Virtual
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#define MEC1404_ICODE_VSRAM_BASE ((MEC1404_ICODE_PSRAM_BASE) | (0xA0000000ul))
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#define MEC1404_ICODE_VSRAM_BLEN (MEC1404_ICODE_PSRAM_BLEN)
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#define MEC1404_ICODE_VSRAM_LIMIT ((MEC1404_ICODE_PSRAM_LIMIT) | (0xA0000000ul))
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/* MEC1418 */
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#define MEC1418_ICODE_PSRAM_BASE (0x1FCF0000ul)
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#define MEC1418_ICODE_PSRAM_BLEN (1024ul * 160ul)
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#define MEC1418_ICODE_PSRAM_LIMIT ((MEC1418_ICODE_PSRAM_SM_BASE)+(MEC1418_ICODE_PSRAM_SM_BLEN))
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// Virtual
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#define MEC1418_ICODE_VSRAM_BASE ((MEC1418_ICODE_PSRAM_BASE) | (0xA0000000ul))
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#define MEC1418_ICODE_VSRAM_BLEN (MEC1418_ICODE_PSRAM_BLEN)
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#define MEC1418_ICODE_VSRAM_LIMIT ((MEC1418_ICODE_PSRAM_LIMIT) | (0xA0000000ul))
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/* 32KB Data SRAM */
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#define MEC14XX_DCODE_PSRAM_BASE (0x1FD18000ul)
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#define MEC14XX_DCODE_PSRAM_BLEN (1024ul * 32ul)
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#define MEC14XX_DCODE_PSRAM_LIMIT ((MEC14XX_DCODE_PSRAM_BASE)+(MEC14XX_DCODE_PSRAM_BLEN))
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#define MEC14XX_DCODE_PSRAM_MASK ((MEC14XX_DCODE_PSRAM_BLEN) - 1ul)
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#define MEC14XX_DCODE_VSRAM_BASE (0xBFD18000ul)
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#define MEC14XX_DCODE_VSRAM_BLEN (1024ul * 32ul)
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#define MEC14XX_DCODE_VSRAM_LIMIT ((MEC14XX_DCODE_VSRAM_BASE)+(MEC14XX_DCODE_VSRAM_BLEN))
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#define MEC14XX_DCODE_VSRAM_MASK ((MEC14XX_DCODE_VSRAM_BLEN) - 1ul)
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/* Closely Coupled Peripheral Region */
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#define MEC14XX_CCP_PHYS_BASE (0x1FFFC000ul)
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#define MEC14XX_CCP_BLEN (16ul * 1024ul)
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#define MEC14XX_CCP_PHYS_LIMIT ((MEC14XX_CCP_PHYS_BASE) + (MEC14XX_CCP_BLEN))
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#define MEC14XX_CCP_VIRT_BASE (0xBFFFC000ul)
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#define MEC14XX_CCP_VIRT_LIMIT ((MEC14XX_CCP_VIRT_BASE) + (MEC14XX_CCP_BLEN))
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/******************************************************************************/
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/* Processor and Core Peripherals */
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/******************************************************************************/
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/** @addtogroup MEC14xx_DEFS Device Definitions
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Configuration of the MIPS microAptiv M14K Processor and Core Peripherals
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@{
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*/
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// Memory Mapped Control Register on AHB (system bus)
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#define MMCR_BASE (0xA0000000UL)
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#define MMCR_MASK (0x000FFFFFUL)
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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#define MEC14xx_GIRQ08_ID (0)
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#define MEC14xx_GIRQ09_ID (1)
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#define MEC14xx_GIRQ10_ID (2)
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#define MEC14xx_GIRQ11_ID (3)
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#define MEC14xx_GIRQ12_ID (4)
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#define MEC14xx_GIRQ13_ID (5)
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#define MEC14xx_GIRQ14_ID (6)
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#define MEC14xx_GIRQ15_ID (7)
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#define MEC14xx_GIRQ16_ID (8)
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#define MEC14xx_GIRQ17_ID (9)
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#define MEC14xx_GIRQ18_ID (10)
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#define MEC14xx_GIRQ19_ID (11)
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#define MEC14xx_GIRQ20_ID (12)
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#define MEC14xx_GIRQ21_ID (13)
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#define MEC14xx_GIRQ22_ID (14)
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#define MEC14xx_GIRQ23_ID (15)
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#define MEC14xx_GIRQ24_ID (16)
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#define MEC14xx_GIRQ25_ID (17)
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#define MEC14xx_GIRQ26_ID (18)
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#define MEC14xx_NUM_JTVIC_INTS (18+1)
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// 4-bits per GIRQ source bit (only lower 2-bits used)
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// 4 * 32 * 19 = 2432 bits -> 76 32-bit registers
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#define MEC14xx_NUM_GIRQ_PRI_REGS ((MEC14xx_NUM_JTVIC_INTS) << 2)
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/*@}*/ /* end of group MEC14xx_DEFS */
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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/** @addtogroup MEC14xx_Peripherals MEC14xx Peripherals
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MEC14xx Device Specific Peripheral registers structures
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@{
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*/
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/* Register Union */
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typedef union
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{
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volatile uint32_t w;
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volatile uint16_t h[2];
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volatile uint8_t b[4];
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} REG32_U;
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typedef union
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{
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uint32_t w;
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uint16_t hw[2];
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uint8_t b[4];
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} DATA32_U;
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typedef struct buff8_s
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{
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uint32_t len;
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uint8_t *pd;
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} BUFF8_T;
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typedef struct buff16_s
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{
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uint32_t len;
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uint16_t *pd;
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} BUFF16_T;
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typedef struct buff32_s
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{
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uint32_t len;
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uint32_t *pd;
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} BUFF32_T;
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#ifndef __IO
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#define __IO volatile
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#ifdef __cplusplus
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#define __I volatile
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#else
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#define __I volatile const
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#endif
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#define __O volatile
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#endif
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/*---------!!!! M14K Closely Coupled Peripherals !!!!-----------------------*/
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/*------------- Jump Table Interrupt Controller (JTVIC)------------------*/
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/** @addtogroup JTVIC MEC14xx External Interrupt Controller (JTVIC)
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@{
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*/
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typedef struct
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{
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__IO uint32_t SOURCE; /*!< Offset: 0x0000 Source RW1C */
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__IO uint32_t EN_SET; /*!< Offset: 0x0004 Enable Set RW */
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__IO uint32_t EN_CLR; /*!< Offset: 0x0008 Enable Clear RW */
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__IO uint32_t RESULT; /*!< Offset: 0x000C Result RO */
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} GIRQ_TypeDef;
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typedef struct
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{
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__IO uint32_t REG32[MEC14xx_NUM_GIRQ_PRI_REGS];
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uint8_t PAD[0x200ul - ((MEC14xx_NUM_GIRQ_PRI_REGS)<<2)];
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} GIRQ_PRIORITY_TypeDef;
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/*
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* JTVIC GIRQ Sub-block size = 512 bytes (0x200)
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* Pad structure to 512 bytes
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*/
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typedef struct
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{
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GIRQ_TypeDef REGS[MEC14xx_NUM_JTVIC_INTS];
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uint8_t PAD[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)];
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} JTVIC_GIRQ_REGS_TypeDef; // at CPP_BASE
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/*
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* JTVIC Aggregator Control Sub-block size = 256 bytes (0x100)
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* Pad structure to 256 bytes
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*/
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typedef struct
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{
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__IO uint32_t REG32[MEC14xx_NUM_JTVIC_INTS];
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uint8_t PAD[0x100ul-((MEC14xx_NUM_JTVIC_INTS)<<2)];
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} JTVIC_AGG_CTRL_TypeDef; // at CCP_BASE+0x200
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/*
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* JTVIC Priority Sub-block size = 512 bytes (0x200)
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* Pad structure to 512 bytes
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*/
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typedef struct
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{
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__IO uint32_t REG32[(MEC14xx_NUM_JTVIC_INTS)<<4];
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uint8_t PAD[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)];
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} JTVIC_PRIORITY_TypeDef; // at CPP_Base+0x300
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typedef struct
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{
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GIRQ_TypeDef GIRQ[MEC14xx_NUM_JTVIC_INTS]; // CPP_BASE
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uint8_t PADA[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)]; // 16 bytes/girq
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__IO uint32_t AGG_CTRL[MEC14xx_NUM_JTVIC_INTS]; // CPP_BASE + 0x200
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uint8_t PADB[0x100ul-((MEC14xx_NUM_JTVIC_INTS)<<2)]; // 4 bytes/girq
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GIRQ_PRIORITY_TypeDef GIRQPRI[MEC14xx_NUM_GIRQ_PRI_REGS]; // CPP_BASE + 0x300
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uint8_t PADC[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)]; // 16 bytes/girq
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__IO uint32_t CONTROL; // CPP_BASE + 0x500
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__IO uint32_t PENDING; // CPP_BASE + 0x504
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__IO uint32_t GROUP_ENABLE_SET; // CPP_BASE + 0x508
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__IO uint32_t GROUP_ENABLE_CLR; // CPP_BASE + 0x50c
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__IO uint32_t GIRQ_ACTIVE; // CPP_BASE + 0x510
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} JTVIC_TypeDef;
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#define JTVIC_BASE (MEC14XX_CCP_VIRT_BASE)
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#define JTVIC ((JTVIC_TypeDef *) JTVIC_BASE)
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#define JTVIC_GIRQ ((JTVIC_GIRQ_REGS_TypeDef *)(JTVIC_BASE))
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#define JTVIC_ACTRL ((JTVIC_AGG_CTRL_TypeDef *)(JTVIC_BASE + 0x200ul))
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#define JTVIC_PRI ((GIRQ_PRIORITY_TypeDef *)(JTVIC_BASE + 0x300ul))
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#define JTVIC_CTRL ((REG32_U *)(JTVIC_BASE + 0x500ul))
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#define JTVIC_PEND ((REG32_U *)(JTVIC_BASE + 0x504ul))
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#define JTVIC_GROUP_EN_SET ((REG32_U *)(JTVIC_BASE + 0x508ul))
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#define JTVIC_GROUP_EN_CLR ((REG32_U *)(JTVIC_BASE + 0x50Cul))
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#define JTVIC_GIRQ_ACTIVE ((REG32_U *)(JTVIC_BASE + 0x510ul))
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/*@}*/ /* end of group JTVIC */
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/*---------!!!! EC AHB Bus Segment !!!!---------------------------*/
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/*------------- Watch Dog Timer (WDT) --------------------------*/
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/** @addtogroup WDT MEC14xx Watch Dog Timer (WDT)
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@{
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*/
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typedef struct
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{
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__IO uint16_t LOAD;
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uint16_t RESERVEDA[1];
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__IO uint8_t CONTROL;
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uint8_t RESERVEDB[3];
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__O uint8_t KICK;
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uint8_t RESERVEDC[3];
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__I uint16_t COUNT;
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uint16_t RESERVEDD[1];
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} WDT_TypeDef;
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/*@}*/ /* end of group WDT */
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/*------------- Basic Timer (TMR) -----------------------------*/
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/** @addtogroup BTMR MEC14xx Basic Timer (TMR)
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@{
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*/
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#define MEC14xx_NUM_BASIC_TIMERS (4)
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typedef struct
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{
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__IO uint32_t COUNT; /*!< Offset: 0x0000 Timer Count Register */
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__IO uint32_t PRELOAD; /*!< Offset: 0x0004 Timer Preload Register */
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__IO uint8_t STATUS; /*!< Offset: 0x0008 Timer Status Register */
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uint8_t RESERVEDC[3];
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__IO uint8_t INTEN; /*!< Offset: 0x000C Timer Interrupt Enable Register */
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uint8_t RESERVEDD[3];
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__IO uint32_t CONTROL; /*!< Offset: 0x0010 Timer Control Register */
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uint32_t RESERVEDE[3];
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} BTMR_TypeDef;
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typedef struct
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{
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BTMR_TypeDef BTimer[MEC14xx_NUM_BASIC_TIMERS];
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} BTMRS_TypeDef;
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/*@}*/ /* end of group BTMR */
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/*------------- RTOS Timer (RTMR) -----------------------------*/
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/** @addtogroup RTOS Timer (RTMR)
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@{
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*/
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typedef struct
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{
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__IO uint32_t COUNT; /*!< Offset: 0x0000 Counter RO */
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__IO uint32_t PRELOAD; /*!< Offset: 0x0004 Pre-Load */
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__IO uint8_t CONTROL; /*!< Offset: 0x0008 Control */
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uint8_t RESERVEDA[3];
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} RTMR_TypeDef;
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/*@}*/ /* end of group RTMR */
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/*------------- Trace FIFO Data Port (TFDP) -----------------------------*/
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/** @addtogroup TFDP Trace FIFO Data Port (TFDP)
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@{
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*/
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typedef struct
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{
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__IO uint8_t DATA;
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uint8_t RESERVEDA[3];
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__IO uint8_t CONTROL;
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uint8_t RESERVEDB[3];
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} TFDP_TypeDef;
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/*@}*/ /* end of group MEC14xx_TFDP */
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/*------------- Breathing/Blinking LED (BBLED) -----------------------------*/
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/** @addtogroup BBLED Breathing-Blinking LED (BBLED)
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@{
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*/
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typedef struct
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{
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__IO uint32_t CONFIG;
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__IO uint32_t LIMIT;
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__IO uint32_t DELAY;
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__IO uint32_t STEP;
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__IO uint32_t INTERVAL;
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} BBLED_TypeDef;
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/*@}*/ /* end of group BBLED */
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/*------------- VBAT Registers (VBATREGS) ---------------------------*/
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/** @addtogroup PCR MEC14xx VBAT Register Block (VBATREGS)
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@{
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*/
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typedef struct
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{
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__IO uint32_t POWER_FAIL_RESET; /*!< Offset: 0x0000 Power-Fail and Reset Status */
|
||||
__IO uint32_t ATE_REG_CTRL; /*!< Offset: 0x0004 ATE Regulator Control Register */
|
||||
__IO uint32_t CLOCK_ENABLE; /*!< Offset: 0x0008 Clock Enable */
|
||||
uint32_t RESERVEDA[1];
|
||||
__IO uint32_t ATE_TEST; /*!< Offset: 0x0010 ATE Test Register */
|
||||
__IO uint32_t OSC_32K_TRIM; /*!< Offset: 0x0014 32KHz OSC trim */
|
||||
__IO uint32_t VTR_ALT_CTRL; /*!< Offset: 0x0018 Alternate Function VTR Control */
|
||||
__IO uint32_t OSC_TRIM_CTRL; /*!< Offset: 0x001C 32KHz Trim Control */
|
||||
} VBATREGS_TypeDef;
|
||||
|
||||
/*@}*/ /* end of group VBATREGS */
|
||||
|
||||
/*------------- EC Subsystem (ECS) -----------------------------*/
|
||||
/** @addtogroup ECS EC Subsystem (ECS)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t JTAG_ENABLE; /*!< JTAG Enable */
|
||||
} ECS_TypeDef;
|
||||
/*@}*/ /* end of group MEC14xx_ECS */
|
||||
|
||||
|
||||
/*----------!!!! Chip AHB Bus Segment !!!!-----------------------------*/
|
||||
|
||||
/*------------- Chip Power Control Reset (PCR) ------------------------*/
|
||||
/** @addtogroup PCR MEC14xx Power Control Reset Block (PCR)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CHIP_SLEEP_EN; /*!< Offset: 0x0000 Chip sleep enable */
|
||||
__IO uint32_t CHIP_CLOCK_REQ_STS; /*!< Offset: 0x0004 Chip Clocks required status */
|
||||
__IO uint32_t EC_SLEEP_EN; /*!< Offset: 0x0008 EC Sleep enable */
|
||||
__IO uint32_t EC_CLOCK_REQ_STS; /*!< Offset: 0x000C EC Clocks required status */
|
||||
__IO uint32_t HOST_SLEEP_EN; /*!< Offset: 0x0010 Host Sleep enable */
|
||||
__IO uint32_t HOST_CLOCK_REQ_STS; /*!< Offset: 0x0014 Host clocks required status */
|
||||
__IO uint32_t SYSTEM_SLEEP_CNTRL; /*!< Offset: 0x0018 System Sleep control */
|
||||
uint32_t RESERVEDA[1];
|
||||
__IO uint32_t PROC_CLOCK_CNTRL; /*!< Offset: 0x0020 Processor clock control */
|
||||
__IO uint32_t EC_SLEEP_EN2; /*!< Offset: 0x0024 EC Sleep Enable 2 */
|
||||
__IO uint32_t EC_CLOCK_REQ_STS2; /*!< Offset: 0x0028 EC Clock Required 2 */
|
||||
__IO uint32_t SLOW_CLOCK_CNTRL; /*!< Offset: 0x002C Slow clock control */
|
||||
__IO uint32_t OSC_ID; /*!< Offset: 0x0030 Chip Oscillator ID, Read-Only */
|
||||
__IO uint32_t CHIP_PWR_RST_STS; /*!< Offset: 0x0034 Chip Sub-system Power Reset Status */
|
||||
__IO uint32_t CHIP_RESET_EN; /*!< Offset: 0x0038 Chip block resets */
|
||||
__IO uint32_t HOST_RESET_EN; /*!< Offset: 0x003C Host block resets */
|
||||
__IO uint32_t EC_RESET_EN; /*!< Offset: 0x0040 EC Block resets */
|
||||
__IO uint32_t EC_RESET_EN2; /*!< Offset: 0x0044 EC Block resets 2 */
|
||||
__IO uint32_t PWR_RST_CTRL; /*!< Offset: 0x0048 Power Reset Control */
|
||||
} PCR_TypeDef;
|
||||
/*@}*/ /* end of group PCR */
|
||||
|
||||
|
||||
/*------------- General Purpose IO Pin Config (GPIO_CFG) -----------------------------*/
|
||||
/** @addtogroup GPIO MEC14xx GPIO Pin Config (GPIO_CFG)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t CONFIG;
|
||||
__IO uint8_t ALT_OUT;
|
||||
__I uint8_t PAD_IN;
|
||||
} GPIO_CFG_TypeDef;
|
||||
/*@}*/ /* end of group GPIO_CFG */
|
||||
|
||||
/*------------- General Purpose IO (GPIO) -----------------------------*/
|
||||
/** @addtogroup GPIO MEC14xx GPIO (GPIO)
|
||||
@{
|
||||
*/
|
||||
#define MEC14xx_NUM_GPIO_BANKS (4)
|
||||
#define MEC14xx_NUM_GPIO_PINS ((MEC14xx_NUM_GPIO_BANKS) * 32)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
GPIO_CFG_TypeDef PIN_CFG[MEC14xx_NUM_GPIO_PINS];
|
||||
} GPIO_TypeDef;
|
||||
|
||||
typedef union
|
||||
{
|
||||
__IO uint32_t w;
|
||||
GPIO_CFG_TypeDef s;
|
||||
} GPIO_CTRL_REG_TypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
GPIO_CTRL_REG_TypeDef REG[MEC14xx_NUM_GPIO_PINS];
|
||||
} GPIO_CTRL_TypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
|
||||
} GPIO_PAROUT_TypeDef; /*!< Offset: 0x0280 GPIO Pins Parallel Output */
|
||||
|
||||
#define GPIO_PAR_000_037_IDX (0u)
|
||||
#define GPIO_PAR_040_077_IDX (1u)
|
||||
#define GPIO_PAR_100_137_IDX (2u)
|
||||
#define GPIO_PAR_140_177_IDX (3u)
|
||||
|
||||
#define GPIO_LOCK_140_177_IDX (0u)
|
||||
#define GPIO_LOCK_100_137_IDX (1u)
|
||||
#define GPIO_LOCK_040_077_IDX (2u)
|
||||
#define GPIO_LOCK_000_037_IDX (3u)
|
||||
|
||||
#define GPIO_LOCK_140_177_OFS ((GPIO_LOCK_140_177_IDX) << 2)
|
||||
#define GPIO_LOCK_100_137_OFS ((GPIO_LOCK_100_137_IDX) << 2)
|
||||
#define GPIO_LOCK_040_077_OFS ((GPIO_LOCK_040_077_IDX) << 2)
|
||||
#define GPIO_LOCK_000_037_OFS ((GPIO_LOCK_000_037_IDX) << 2)
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
|
||||
} GPIO_PARIN_TypeDef; /*!< Offset: 0x0300 GPIO Pins Parallel Input */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
|
||||
} GPIO_LOCK_Typedef; /*!< Offset: 0x03EC GPIO Pins Lock */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PINS[MEC14xx_NUM_GPIO_PINS];
|
||||
} GPIO_DRVSTR_Typedef; /*!< Offset: 0x0500 GPIO Pins Lock */
|
||||
/*@}*/ /* end of group GPIO */
|
||||
|
||||
/*@}*/ /* end of group MEC14xx_Peripherals */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
|
||||
/** @addtogroup MEC14xx_MemoryMap MEC14xx Memory Mapping
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Peripheral and SRAM base address */
|
||||
|
||||
#define MEC14xx_PERIPH_BASE (0xA0000000UL) /*!< (Peripheral) Base Address */
|
||||
#define MEC14xx_SPB_PERIPH_BASE (0xA0080000UL) /*!< (Chip Subsystem SPB Peripheral) Base Address */
|
||||
#define MEC14xx_HOST_PERIPH_BASE (0xA00F0000UL) /*!< (Host Peripheral) Base Address */
|
||||
|
||||
/* Peripheral memory map */
|
||||
#define WDT_BASE ((MEC14xx_PERIPH_BASE) + 0x0400) /*!< (WDT ) Base */
|
||||
#define BTMRS_BASE ((MEC14xx_PERIPH_BASE) + 0x0C00) /*!< (Basic Timers ) Base Address */
|
||||
#define BTMR0_BASE ((MEC14xx_PERIPH_BASE) + 0x0C00) /*!< (Basic 16-bit timer 0 ) Base Address */
|
||||
#define BTMR1_BASE ((MEC14xx_PERIPH_BASE) + 0x0C20) /*!< (Basic 16-bit timer 1 ) Base Address */
|
||||
#define BTMR2_BASE ((MEC14xx_PERIPH_BASE) + 0x0C40) /*!< (Basic 16-bit timer 2 ) Base Address */
|
||||
#define BTMR3_BASE ((MEC14xx_PERIPH_BASE) + 0x0C60) /*!< (Basic 16-bit timer 3 ) Base Address */
|
||||
#define RTOS_TIMER_BASE ((MEC14xx_PERIPH_BASE) + 0x7400) /*!< (RTOS Timer) Base Address */
|
||||
#define TFDP_BASE ((MEC14xx_PERIPH_BASE) + 0x8C00) /*!< (TFDP ) Base Address */
|
||||
#define VBAT_REGS_BASE ((MEC14xx_PERIPH_BASE) + 0xA400) /*!< (PCR VBAT Regs ) Base Address */
|
||||
#define VBAT_MEM_BASE ((MEC14xx_PERIPH_BASE) + 0xA800) /*!< (VBAT MEM ) Base Address */
|
||||
#define LED0_BASE ((MEC14xx_PERIPH_BASE) + 0xB800) /*!< (LED0 ) Base Address */
|
||||
#define LED1_BASE ((MEC14xx_PERIPH_BASE) + 0xB900) /*!< (LED1 ) Base Address */
|
||||
#define LED2_BASE ((MEC14xx_PERIPH_BASE) + 0xBA00) /*!< (LED2 ) Base Address */
|
||||
#define ECS_BASE ((MEC14xx_PERIPH_BASE) + 0xFC00) /*!< (ECS ) Base Address */
|
||||
|
||||
/* SPB Peripheral memory map */
|
||||
#define PCR_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x0100) /*!< (PCR ) Base Address */
|
||||
#define GPIO_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1000) /*!< (GPIO ) Base Address */
|
||||
#define GPIO_CTRL_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1000)
|
||||
#define GPIO_POUT_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1280)
|
||||
#define GPIO_PIN_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1300)
|
||||
#define GPIO_LOCK_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x13F0) /*!< (GPIO Lock Regis) Base Address */
|
||||
#define GPIO_PCTRL2_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1500) /*!< (GPIO Pin Ctrl 2) Base Address */
|
||||
|
||||
/*@}*/ /* end of group MEC14xx_MemoryMap */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
/** @addtogroup MEC14xx_PeripheralDecl MEC14xx Peripheral Declaration
|
||||
@{
|
||||
*/
|
||||
|
||||
/* EC Bus Segment Devices */
|
||||
#define WDT ((WDT_TypeDef *)(WDT_BASE))
|
||||
#define RTOS_TIMER ((RTMR_TypeDef *)(RTOS_TIMER_BASE))
|
||||
#define TFDP ((TFDP_TypeDef *)(TFDP_BASE))
|
||||
#define VBAT_REGS ((VBATREGS_TypeDef *)(VBAT_REGS_BASE))
|
||||
#define BBLED0 ((BBLED_TypeDef *)(LED0_BASE))
|
||||
#define BBLED1 ((BBLED_TypeDef *)(LED1_BASE))
|
||||
#define BBLED2 ((BBLED_TypeDef *)(LED2_BASE))
|
||||
#define ECS ((ECS_TypeDef *)(ECS_BASE))
|
||||
#define ECS_REG ((ECS_TypeDef *)(ECS_BASE + 0x20))
|
||||
|
||||
/* Chip Bus Segment Devices */
|
||||
#define PCR ((PCR_TypeDef *)(PCR_BASE))
|
||||
#define GPIO ((GPIO_TypeDef *)(GPIO_BASE))
|
||||
#define GPIO_CTRL ((GPIO_CTRL_TypeDef *) (GPIO_BASE))
|
||||
#define GPIO_PAROUT ((GPIO_PAROUT_TypeDef *)(GPIO_POUT_BASE))
|
||||
#define GPIO_PARIN ((GPIO_PARIN_TypeDef *)(GPIO_PIN_BASE))
|
||||
#define GPIO_LOCK ((GPIO_LOCK_Typedef *)(GPIO_LOCK_BASE))
|
||||
#define GPIO_DRVSTR ((GPIO_DRVSTR_Typedef *)(GPIO_PCTRL2_BASE))
|
||||
|
||||
|
||||
/*@}*/ /* end of group MEC14xx_PeripheralDecl */
|
||||
|
||||
/*@}*/ /* end of group MEC14xx_Definitions */
|
||||
|
||||
/*
|
||||
* Convert MEC14xx MIPS M14K virtual address to physical
|
||||
* Physical address is bits [31:29] = 000b
|
||||
* [28:0] = virtual [28:0]
|
||||
*/
|
||||
#define sys_virt_to_phys(v) ( (uint32_t)(v) & 0x1FFFFFFFul )
|
||||
|
||||
|
||||
/*
|
||||
* Convert MEC14xx MIPS M14K physical address to virtual.
|
||||
* Bit-wise OR bits[31:29] of physical with 101b
|
||||
*/
|
||||
#define sys_phys_to_virt(p) ( (uint32_t)(p) | 0xA0000000ul )
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* MEC14XX_H */
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/** @file mec14xx_bbled.h
|
||||
*MEC14xx Blinking Breathing LED definitions
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals LED
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_BBLED_H
|
||||
#define _MEC14XX_BBLED_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED_NUM_BLOCKS (3)
|
||||
|
||||
|
||||
#define LED_INSTANCE_OFFSET (0x100UL)
|
||||
|
||||
//
|
||||
// LED Configuration Register
|
||||
//
|
||||
#define LED_CFG_CNTL_MASK (0x0003u)
|
||||
#define LED_CFG_CNTL_LO (0x0000u)
|
||||
#define LED_CFG_CNTL_BREATH (0x0001u)
|
||||
#define LED_CFG_CNTL_BLINK (0x0002u)
|
||||
#define LED_CFG_CNTL_HI (0x0003u)
|
||||
#define LED_CFG_CLK_SRC_MCLK (0x0002u)
|
||||
#define LED_CFG_CLK_SRC_32K (0x0000u)
|
||||
#define LED_CFG_SYNC (0x0008u)
|
||||
#define LED_CFG_PWM_COUNT_WIDTH_MASK (0x0030u)
|
||||
#define LED_CFG_COUNT_WIDTH_8 (0x0000u)
|
||||
#define LED_CFG_COUNT_WIDTH_7 (0x0010u)
|
||||
#define LED_CFG_COUNT_WIDTH_6 (0x0020u)
|
||||
#define LED_CFG_EN_UPDATE (0x0040u)
|
||||
#define LED_CFG_RESET (0x0080u)
|
||||
#define LED_CFG_WDT_PRELOAD_MASK (0xFF00u)
|
||||
#define LED_CFG_WDT_PRELOAD_POR (0x1400u)
|
||||
#define LED_CFG_SYMMETRY_EN (0x10000u)
|
||||
|
||||
//
|
||||
// LED Limit Register
|
||||
//
|
||||
#define LED_LIMIT_MIN_BITPOS (0u)
|
||||
#define LED_LIMIT_MIN_MASK (0xFFu)
|
||||
#define LED_LIMIT_MAX_BITPOS (8u)
|
||||
#define LED_LIMIT_MAX_MASK (0xFF00u)
|
||||
|
||||
//
|
||||
// LED Delay Register
|
||||
//
|
||||
#define LED_DELAY_LOW_MASK (0x0000FFFu)
|
||||
#define LED_DELAY_HIGH_MASK (0x0FFF000u)
|
||||
#define LED_DELAY_HIGH_BITPOS (12u)
|
||||
|
||||
//
|
||||
// LED Step Size Register
|
||||
//
|
||||
#define LED_STEP_FIELD_WIDTH (4u)
|
||||
#define LED_STEP0_MASK (0x0000000Fu)
|
||||
#define LED_STEP1_MASK (0x000000F0u)
|
||||
#define LED_STEP2_MASK (0x00000F00u)
|
||||
#define LED_STEP3_MASK (0x0000F000u)
|
||||
#define LED_STEP4_MASK (0x000F0000u)
|
||||
#define LED_STEP5_MASK (0x00F00000u)
|
||||
#define LED_STEP6_MASK (0x0F000000u)
|
||||
#define LED_STEP7_MASK (0xF0000000u)
|
||||
|
||||
//
|
||||
// LED Update Register
|
||||
//
|
||||
#define LED_UPDATE_FIELD_WIDTH (4u)
|
||||
#define LED_UPDATE0_MASK (0x0000000Fu)
|
||||
#define LED_UPDATE1_MASK (0x000000F0u)
|
||||
#define LED_UPDATE2_MASK (0x00000F00u)
|
||||
#define LED_UPDATE3_MASK (0x0000F000u)
|
||||
#define LED_UPDATE4_MASK (0x000F0000u)
|
||||
#define LED_UPDATE5_MASK (0x00F00000u)
|
||||
#define LED_UPDATE6_MASK (0x0F000000u)
|
||||
#define LED_UPDATE7_MASK (0xF0000000u)
|
||||
|
||||
|
||||
#define BLINK_0P5_HZ_DUTY_CYCLE (0x010ul)
|
||||
#define BLINK_0P5_HZ_PRESCALE (0x0FFul)
|
||||
#define BLINK_1_HZ_DUTY_CYCLE (0x020ul)
|
||||
#define BLINK_1_HZ_PRESCALE (0x07Ful)
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* BBLED API
|
||||
*****************************************************************************/
|
||||
#define LED0_ID (0x00u)
|
||||
#define LED1_ID (0x01u)
|
||||
#define LED2_ID (0x02u)
|
||||
#define LED_ID_MAX (0x03u)
|
||||
|
||||
|
||||
#define BLINK_0P5_HZ_DUTY_CYCLE (0x010ul)
|
||||
#define BLINK_0P5_HZ_PRESCALE (0x0FFul)
|
||||
#define BLINK_1_HZ_DUTY_CYCLE (0x020ul)
|
||||
#define BLINK_1_HZ_PRESCALE (0x07Ful)
|
||||
|
||||
|
||||
uint8_t led_get_gpio_num(uint8_t led_id);
|
||||
void led_init(uint8_t led_id);
|
||||
|
||||
void led_sleep_en(uint8_t led_id, uint8_t sleep_en);
|
||||
void led_reset(uint8_t led_id);
|
||||
|
||||
void led_mode_blink(uint8_t led_id,
|
||||
uint8_t duty_cycle,
|
||||
uint16_t prescale);
|
||||
|
||||
void led_out_high(uint8_t led_id);
|
||||
void led_out_low(uint8_t led_id);
|
||||
void led_out_toggle(uint8_t led_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_BBLED_H
|
||||
/* end hw_led.h */
|
||||
/** @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file mec14xx_girqm.h
|
||||
*MEC14xx JTVIC Disaggregation Control Flags
|
||||
*/
|
||||
/** @defgroup MEC14xx interrupt
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is intended to be included in both C source and assembly language
|
||||
* files. The assembly language C pre-processor cannot handle complex macros.
|
||||
* Keep it simple!
|
||||
*/
|
||||
|
||||
/* Include FreeRTOS configuration settings.
|
||||
* These include porting layer switches affecting interrupt aggregation
|
||||
* of GIRQ23 & GIRQ24
|
||||
*/
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
/*
|
||||
* Set to 0 for Aggregated GIRQ
|
||||
* Set to 1 for Dis-aggregated(Jump Table) GIRQ
|
||||
*/
|
||||
|
||||
#define GIRQ08_DISAGG (0)
|
||||
#define GIRQ09_DISAGG (0)
|
||||
#define GIRQ10_DISAGG (0)
|
||||
#define GIRQ11_DISAGG (0)
|
||||
#define GIRQ12_DISAGG (0)
|
||||
#define GIRQ13_DISAGG (0)
|
||||
#define GIRQ14_DISAGG (0)
|
||||
#define GIRQ15_DISAGG (0)
|
||||
#define GIRQ16_DISAGG (0)
|
||||
#define GIRQ17_DISAGG (0)
|
||||
#define GIRQ18_DISAGG (0)
|
||||
#define GIRQ19_DISAGG (0)
|
||||
#define GIRQ20_DISAGG (0)
|
||||
#define GIRQ21_DISAGG (0)
|
||||
#define GIRQ22_DISAGG (0)
|
||||
|
||||
#if configTIMERS_DISAGGREGATED_ISRS == 0
|
||||
#define GIRQ23_DISAGG (0)
|
||||
#else
|
||||
#define GIRQ23_DISAGG (1)
|
||||
#endif
|
||||
|
||||
#if configCPU_DISAGGREGATED_ISRS == 0
|
||||
#define GIRQ24_DISAGG (0)
|
||||
#else
|
||||
#define GIRQ24_DISAGG (1)
|
||||
#endif
|
||||
|
||||
#define GIRQ25_DISAGG (0)
|
||||
#define GIRQ26_DISAGG (0)
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Aggregated/Dis-aggrated bit-map
|
||||
*/
|
||||
#define JTVIC_DISAGR_BITMAP ( ((GIRQ08_DISAGG)<<0) + \
|
||||
((GIRQ09_DISAGG)<<1) + ((GIRQ10_DISAGG)<<2) + \
|
||||
((GIRQ11_DISAGG)<<3) + ((GIRQ12_DISAGG)<<4) + \
|
||||
((GIRQ13_DISAGG)<<5) + ((GIRQ14_DISAGG)<<6) + \
|
||||
((GIRQ15_DISAGG)<<7) + ((GIRQ16_DISAGG)<<8) + \
|
||||
((GIRQ17_DISAGG)<<9) + ((GIRQ18_DISAGG)<<10) + \
|
||||
((GIRQ19_DISAGG)<<11) + ((GIRQ20_DISAGG)<<12) + \
|
||||
((GIRQ21_DISAGG)<<13) + ((GIRQ22_DISAGG)<<14) + \
|
||||
((GIRQ23_DISAGG)<<15) + ((GIRQ24_DISAGG)<<16) + \
|
||||
((GIRQ25_DISAGG)<<17) + ((GIRQ26_DISAGG)<<18) )
|
||||
|
||||
|
||||
#define GIRQ08_NUM_SOURCES (23)
|
||||
#define GIRQ08_SRC_MASK (0x007FFFFFul)
|
||||
|
||||
#define GIRQ09_NUM_SOURCES (31)
|
||||
#define GIRQ09_SRC_MASK (0x7FFFFFFFul)
|
||||
|
||||
#define GIRQ10_NUM_SOURCES (24)
|
||||
#define GIRQ10_SRC_MASK (0x00FFFFFFul)
|
||||
|
||||
#define GIRQ11_NUM_SOURCES (30)
|
||||
#define GIRQ11_SRC_MASK (0x7FFFFFFEul)
|
||||
|
||||
#define GIRQ12_NUM_SOURCES (3)
|
||||
#define GIRQ12_SRC_MASK (0x00000007ul)
|
||||
|
||||
#define GIRQ13_NUM_SOURCES (7)
|
||||
#define GIRQ13_SRC_MASK (0x0000007Ful)
|
||||
|
||||
#define GIRQ14_NUM_SOURCES (6)
|
||||
#define GIRQ14_SRC_MASK (0x0000003Ful)
|
||||
|
||||
#define GIRQ15_NUM_SOURCES (19)
|
||||
#define GIRQ15_SRC_MASK (0x0007FFFFul)
|
||||
|
||||
#define GIRQ16_NUM_SOURCES (10)
|
||||
#define GIRQ16_SRC_MASK (0x000003FFul)
|
||||
|
||||
#define GIRQ17_NUM_SOURCES (11)
|
||||
#define GIRQ17_SRC_MASK (0x000007FFul)
|
||||
|
||||
#define GIRQ18_NUM_SOURCES (1)
|
||||
#define GIRQ18_SRC_MASK (0x00000001ul)
|
||||
|
||||
#define GIRQ19_NUM_SOURCES (9)
|
||||
#define GIRQ19_SRC_MASK (0x000001FFul)
|
||||
|
||||
#define GIRQ20_NUM_SOURCES (6)
|
||||
#define GIRQ20_SRC_MASK (0x0000003Ful)
|
||||
|
||||
#define GIRQ21_NUM_SOURCES (3)
|
||||
#define GIRQ21_SRC_MASK (0x00000007ul)
|
||||
|
||||
#define GIRQ22_NUM_SOURCES (10)
|
||||
#define GIRQ22_SRC_MASK (0x000003FFul)
|
||||
|
||||
#define GIRQ23_NUM_SOURCES (14)
|
||||
#define GIRQ23_SRC_MASK (0x00003FFFul)
|
||||
|
||||
#define GIRQ24_NUM_SOURCES (3)
|
||||
#define GIRQ24_SRC_MASK (0x00000007ul)
|
||||
|
||||
#define GIRQ25_NUM_SOURCES (28)
|
||||
#define GIRQ25_SRC_MASK (0x0FFFFFFFul)
|
||||
|
||||
#define GIRQ26_NUM_SOURCES (12)
|
||||
#define GIRQ26_SRC_MASK (0x00000FFFul)
|
||||
|
||||
/** @}
|
||||
*/
|
||||
1053
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx_girqs.h
Normal file
1053
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx_girqs.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,446 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/** @file mec14xx_gpio.h
|
||||
*MEC14xx GPIO definitions
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals GPIO
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_GPIO_H
|
||||
#define _MEC14XX_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "mec14xx.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NUM_GPIO_PORTS (MEC14xx_NUM_GPIO_BANKS)
|
||||
#define MAX_NUM_GPIO (NUM_GPIO_PORTS * 32)
|
||||
|
||||
#define GPIO_PORT_A_BITMAP (0x7FFFFFFFul) // GPIO_0000 to GPIO_0037
|
||||
#define GPIO_PORT_B_BITMAP (0x00FFFFFFul) // GPIO_0040 to GPIO_0077
|
||||
#define GPIO_PORT_C_BITMAP (0x7FFFFFFFul) // GPIO_0100 to GPIO_0137
|
||||
#define GPIO_PORT_D_BITMAP (0x7FFFFFFFul) // GPIO_0140 to GPIO_0177
|
||||
|
||||
|
||||
#define GPIO_PORT_A_DRVSTR_BITMAP (0x7FFFFFFEul)
|
||||
#define GPIO_PORT_B_DRVSTR_BITMAP (0x006FFFFFul)
|
||||
#define GPIO_PORT_C_DRVSTR_BITMAP (0x7FFFFFFFul)
|
||||
#define GPIO_PORT_D_DRVSTR_BITMAP (0x007FFFFFul)
|
||||
|
||||
|
||||
//
|
||||
// Control
|
||||
//
|
||||
#define GPIO_CTRL_RSVD_MASK (0xFEFEC000UL)
|
||||
//
|
||||
#define GPIO_PUD_BITPOS (0)
|
||||
#define GPIO_PUD_BLEN (2)
|
||||
#define GPIO_PUD_MASK (0x03UL << (GPIO_PUD_BITPOS))
|
||||
#define GPIO_PUD_NONE (0x00)
|
||||
#define GPIO_PUD_PU (0x01)
|
||||
#define GPIO_PUD_PD (0x02)
|
||||
#define GPIO_PUD_NONE2 (0x03)
|
||||
//
|
||||
#define GPIO_PWRG_BITPOS (2)
|
||||
#define GPIO_PWRG_BLEN (2)
|
||||
#define GPIO_PWRG_MASK (0x03UL << (GPIO_PWRG_BITPOS))
|
||||
#define GPIO_PWRG_V3_S5 (0x00UL << (GPIO_PWRG_BITPOS))
|
||||
#define GPIO_PWRG_VCC_MAIN (0x01UL << (GPIO_PWRG_BITPOS))
|
||||
#define GPIO_PWRG_V3_DUAL (0x02UL << (GPIO_PWRG_BITPOS))
|
||||
#define GPIO_PWRG_UNPWRD (0x03UL << (GPIO_PWRG_BITPOS))
|
||||
//
|
||||
#define GPIO_INTDET_BITPOS (4)
|
||||
#define GPIO_INTDET_BLEN (4)
|
||||
#define GPIO_INTDET_MASK (0x0FUL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_LVL_LOW (0x00UL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_LVL_HI (0x01UL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_DISABLE (0x04UL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_RISE_EDG (0x0DUL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_FALL_EDG (0x0EUL << (GPIO_INTDET_BITPOS))
|
||||
#define GPIO_INTDET_BOTH_EDG (0x0FUL << (GPIO_INTDET_BITPOS))
|
||||
//
|
||||
#define GPIO_BUFFTYPE_BITPOS (8)
|
||||
#define GPIO_BUFFTYPE_BLEN (1)
|
||||
#define GPIO_BUFFTYPE_PUSHPULL (0x00UL << (GPIO_BUFFTYPE_BITPOS))
|
||||
#define GPIO_BUFFTYPE_OPENDRAIN (0x01UL << (GPIO_BUFFTYPE_BITPOS))
|
||||
//
|
||||
#define GPIO_DIR_BITPOS (9)
|
||||
#define GPIO_DIR_BLEN (1)
|
||||
#define GPIO_DIR_MASK (0x01UL << (GPIO_DIR_BITPOS))
|
||||
#define GPIO_DIR_INPUT (0x00UL << (GPIO_DIR_BITPOS))
|
||||
#define GPIO_DIR_OUTPUT (0x01UL << (GPIO_DIR_BITPOS))
|
||||
//
|
||||
#define GPIO_PARWEN_BITPOS (10)
|
||||
#define GPIO_PARWEN_BLEN (1)
|
||||
#define GPIO_PARWEN_DIS (0x00UL << (GPIO_PARWEN_BITPOS))
|
||||
#define GPIO_PARWEN_EN (0x01UL << (GPIO_PARWEN_BITPOS))
|
||||
//
|
||||
#define GPIO_POLARITY_BITPOS (11)
|
||||
#define GPIO_POLARITY_BLEN (1)
|
||||
#define GPIO_POLARITY_NON_INV (0x00UL << (GPIO_POLARITY_BITPOS))
|
||||
#define GPIO_POLARITY_INV (0x01UL << (GPIO_POLARITY_BITPOS))
|
||||
//
|
||||
#define GPIO_MUX_BITPOS (12)
|
||||
#define GPIO_MUX_BLEN (2)
|
||||
#define GPIO_MUX_MASK (0x0FUL << (GPIO_MUX_BITPOS))
|
||||
#define GPIO_MUX_GPIO (0x00UL << (GPIO_MUX_BITPOS))
|
||||
#define GPIO_MUX_FUNC1 (0x01UL << (GPIO_MUX_BITPOS))
|
||||
#define GPIO_MUX_FUNC2 (0x02UL << (GPIO_MUX_BITPOS))
|
||||
#define GPIO_MUX_FUNC3 (0x03UL << (GPIO_MUX_BITPOS))
|
||||
//
|
||||
#define GPIO_OUTPUT_BITPOS (16)
|
||||
#define GPIO_OUTPUT_BLEN (1)
|
||||
#define GPIO_OUTPUT_0 (0x00UL << (GPIO_OUTPUT_BITPOS))
|
||||
#define GPIO_OUTPUT_1 (0x01UL << (GPIO_OUTPUT_BITPOS))
|
||||
#define GP_OUTPUT_0 (0x00UL) // Byte or Bit-banding usage
|
||||
#define GP_OUTPUT_1 (0x01UL)
|
||||
//
|
||||
#define GPIO_PADIN_BITPOS (24)
|
||||
#define GPIO_PADIN_BLEN (1)
|
||||
#define GPIO_PADIN_LOW (0x00UL << (GPIO_PADIN_BITPOS))
|
||||
#define GPIO_PADIN_HI (0x01UL << (GPIO_PADIN_BITPOS))
|
||||
#define GP_PADIN_LO (0x00UL) // Byte or Bit-banding usage
|
||||
#define GP_PADIN_HI (0x01UL)
|
||||
|
||||
#define GPIO_PIN_LOW (0UL)
|
||||
#define GPIO_PIN_HIGH (1UL)
|
||||
|
||||
//
|
||||
// Drive Strength
|
||||
// For GPIO pins that implement drive strength each pin
|
||||
// has a 32-bit register containing bit fields for
|
||||
// slew rate and buffer current strength
|
||||
//
|
||||
#define GPIO_DRV_STR_OFFSET (0x0500ul)
|
||||
#define GPIO_DRV_SLEW_BITPOS (0ul)
|
||||
#define GPIO_DRV_SLEW_MASK (1ul << GPIO_DRV_SLEW_BITPOS)
|
||||
#define GPIO_DRV_SLEW_SLOW (0ul << GPIO_DRV_SLEW_BITPOS)
|
||||
#define GPIO_DRV_SLEW_FAST (1ul << GPIO_DRV_SLEW_BITPOS)
|
||||
#define GPIO_DRV_STR_BITPOS (4ul)
|
||||
#define GPIO_DRV_STR_LEN (2ul)
|
||||
#define GPIO_DRV_STR_MASK (0x03ul << GPIO_DRV_STR_BITPOS)
|
||||
#define GPIO_DRV_STR_2MA (0ul << GPIO_DRV_STR_BITPOS)
|
||||
#define GPIO_DRV_STR_4MA (1ul << GPIO_DRV_STR_BITPOS)
|
||||
#define GPIO_DRV_STR_8MA (2ul << GPIO_DRV_STR_BITPOS)
|
||||
#define GPIO_DRV_STR_12MA (3ul << GPIO_DRV_STR_BITPOS)
|
||||
|
||||
/*****************************************************************************
|
||||
* GPIO API
|
||||
****************************************************************************/
|
||||
#define GPIO_PORTA (0u)
|
||||
#define GPIO_PORTB (1u)
|
||||
#define GPIO_PORTC (2u)
|
||||
#define GPIO_PORTD (3u)
|
||||
#define GPIO_PORTE (4u)
|
||||
#define GPIO_MAX_PORT (5u)
|
||||
|
||||
|
||||
/*
|
||||
* GPIO Functionality
|
||||
*/
|
||||
|
||||
typedef enum gpio_id_t
|
||||
{
|
||||
GPIO_0000_ID, // 00h: Begin Port A
|
||||
GPIO_0001_ID,
|
||||
GPIO_0002_ID,
|
||||
GPIO_0003_ID,
|
||||
GPIO_0004_ID,
|
||||
GPIO_0005_ID,
|
||||
GPIO_0006_ID,
|
||||
GPIO_0007_ID,
|
||||
//
|
||||
GPIO_0010_ID, // 08h
|
||||
GPIO_0011_ID,
|
||||
GPIO_0012_ID,
|
||||
GPIO_0013_ID,
|
||||
GPIO_0014_ID,
|
||||
GPIO_0015_ID,
|
||||
GPIO_0016_ID,
|
||||
GPIO_0017_ID,
|
||||
//
|
||||
GPIO_0020_ID, // 10h
|
||||
GPIO_0021_ID,
|
||||
GPIO_0022_ID,
|
||||
GPIO_0023_ID,
|
||||
GPIO_0024_ID,
|
||||
GPIO_0025_ID,
|
||||
GPIO_0026_ID,
|
||||
GPIO_0027_ID,
|
||||
//
|
||||
GPIO_0030_ID, // 18h
|
||||
GPIO_0031_ID,
|
||||
GPIO_0032_ID,
|
||||
GPIO_0033_ID,
|
||||
GPIO_0034_ID,
|
||||
GPIO_0035_ID,
|
||||
GPIO_0036_ID,
|
||||
GPIO_0037_ID, // End Port A
|
||||
//
|
||||
GPIO_0040_ID, // 20h: Begin Port B
|
||||
GPIO_0041_ID,
|
||||
GPIO_0042_ID,
|
||||
GPIO_0043_ID,
|
||||
GPIO_0044_ID,
|
||||
GPIO_0045_ID,
|
||||
GPIO_0046_ID,
|
||||
GPIO_0047_ID,
|
||||
//
|
||||
GPIO_0050_ID, // 28h
|
||||
GPIO_0051_ID,
|
||||
GPIO_0052_ID,
|
||||
GPIO_0053_ID,
|
||||
GPIO_0054_ID,
|
||||
GPIO_0055_ID,
|
||||
GPIO_0056_ID,
|
||||
GPIO_0057_ID,
|
||||
//
|
||||
GPIO_0060_ID, // 30h
|
||||
GPIO_0061_ID,
|
||||
GPIO_0062_ID,
|
||||
GPIO_0063_ID,
|
||||
GPIO_0064_ID,
|
||||
GPIO_0065_ID,
|
||||
GPIO_0066_ID,
|
||||
GPIO_0067_ID,
|
||||
//
|
||||
GPIO_0070_ID, // 38h
|
||||
GPIO_0071_ID,
|
||||
GPIO_0072_ID,
|
||||
GPIO_0073_ID,
|
||||
GPIO_0074_ID,
|
||||
GPIO_0075_ID,
|
||||
GPIO_0076_ID,
|
||||
GPIO_0077_ID, // End Port B
|
||||
//
|
||||
GPIO_0100_ID, // 40h: Begin Port C
|
||||
GPIO_0101_ID,
|
||||
GPIO_0102_ID,
|
||||
GPIO_0103_ID,
|
||||
GPIO_0104_ID,
|
||||
GPIO_0105_ID,
|
||||
GPIO_0106_ID,
|
||||
GPIO_0107_ID,
|
||||
//
|
||||
GPIO_0110_ID, // 48h
|
||||
GPIO_0111_ID,
|
||||
GPIO_0112_ID,
|
||||
GPIO_0113_ID,
|
||||
GPIO_0114_ID,
|
||||
GPIO_0115_ID,
|
||||
GPIO_0116_ID,
|
||||
GPIO_0117_ID,
|
||||
//
|
||||
GPIO_0120_ID, // 50h
|
||||
GPIO_0121_ID,
|
||||
GPIO_0122_ID,
|
||||
GPIO_0123_ID,
|
||||
GPIO_0124_ID,
|
||||
GPIO_0125_ID,
|
||||
GPIO_0126_ID,
|
||||
GPIO_0127_ID,
|
||||
//
|
||||
GPIO_0130_ID, // 58h
|
||||
GPIO_0131_ID,
|
||||
GPIO_0132_ID,
|
||||
GPIO_0133_ID,
|
||||
GPIO_0134_ID,
|
||||
GPIO_0135_ID,
|
||||
GPIO_0136_ID,
|
||||
GPIO_0137_ID, // End Port C
|
||||
//
|
||||
GPIO_0140_ID, // 60h: Begin Port D
|
||||
GPIO_0141_ID,
|
||||
GPIO_0142_ID,
|
||||
GPIO_0143_ID,
|
||||
GPIO_0144_ID,
|
||||
GPIO_0145_ID,
|
||||
GPIO_0146_ID,
|
||||
GPIO_0147_ID,
|
||||
//
|
||||
GPIO_0150_ID, // 68h
|
||||
GPIO_0151_ID,
|
||||
GPIO_0152_ID,
|
||||
GPIO_0153_ID,
|
||||
GPIO_0154_ID,
|
||||
GPIO_0155_ID,
|
||||
GPIO_0156_ID,
|
||||
GPIO_0157_ID,
|
||||
//
|
||||
GPIO_0160_ID, // 70h
|
||||
GPIO_0161_ID,
|
||||
GPIO_0162_ID,
|
||||
GPIO_0163_ID,
|
||||
GPIO_0164_ID,
|
||||
GPIO_0165_ID,
|
||||
GPIO_0166_ID,
|
||||
GPIO_0167_ID,
|
||||
//
|
||||
MAX_GPIO_ID
|
||||
|
||||
} GPIO_ID;
|
||||
|
||||
|
||||
enum gpio_prop_t
|
||||
{
|
||||
GPIO_PROP_PU_PD,
|
||||
GPIO_PROP_PWR_GATE,
|
||||
GPIO_PROP_INT_DET,
|
||||
GPIO_PROP_OBUFF_TYPE,
|
||||
GPIO_PROP_DIR,
|
||||
GPIO_PROP_ALT_OUT_EN,
|
||||
GPIO_PROP_POLARITY,
|
||||
GPIO_PROP_MUX_SEL,
|
||||
GPIO_PROP_ALL,
|
||||
GPIO_PROP_MAX
|
||||
};
|
||||
|
||||
|
||||
enum gpio_pupd_t
|
||||
{
|
||||
GPIO_PUPD_NONE,
|
||||
GPIO_PULLUP_EN,
|
||||
GPIO_PULLDN_EN,
|
||||
GPIO_PUPD_NONE2
|
||||
};
|
||||
|
||||
|
||||
enum gpio_idetect_t
|
||||
{
|
||||
GPIO_DET_LEVEL_LOW,
|
||||
GPIO_DET_LEVEL_HIGH,
|
||||
GPIO_DET_RSVD2,
|
||||
GPIO_DET_RSVD3,
|
||||
GPIO_DET_DISABLE,
|
||||
GPIO_DET_RSVD5,
|
||||
GPIO_DET_RSVD6,
|
||||
GPIO_DET_RSVD7,
|
||||
GPIO_DET_RSVD8,
|
||||
GPIO_DET_RSVD9,
|
||||
GPIO_DET_RSVDA,
|
||||
GPIO_DET_RSVDB,
|
||||
GPIO_DET_RSVDC,
|
||||
GPIO_DET_RISING_EDGE,
|
||||
GPIO_DET_FALLING_EDGE,
|
||||
GPIO_DET_BOTH_EDGES
|
||||
};
|
||||
|
||||
|
||||
enum gpio_buff_type_t
|
||||
{
|
||||
GPIO_OUT_BUFF_PUSH_PULL,
|
||||
GPIO_OUT_BUFF_OPEN_DRAIN
|
||||
};
|
||||
|
||||
|
||||
enum gpio_dir_t
|
||||
{
|
||||
GPIO_DIR_IN,
|
||||
GPIO_DIR_OUT
|
||||
};
|
||||
|
||||
|
||||
enum gpio_polarity_t
|
||||
{
|
||||
GPIO_NON_INVERT,
|
||||
GPIO_INVERT
|
||||
};
|
||||
|
||||
|
||||
enum gpio_mux_t
|
||||
{
|
||||
GPIO_FUNC_GPIO,
|
||||
GPIO_FUNC_1,
|
||||
GPIO_FUNC_2,
|
||||
GPIO_FUNC_3
|
||||
};
|
||||
|
||||
// Slew Rate & Drive Strength
|
||||
enum gpio_slew_rate_t
|
||||
{
|
||||
GPIO_SLEW_SLOW,
|
||||
GPIO_SLEW_FAST
|
||||
};
|
||||
|
||||
enum gpio_drv_str_t
|
||||
{
|
||||
GPIO_DRV_2MA = 0,
|
||||
GPIO_DRV_4MA,
|
||||
GPIO_DRV_8MA,
|
||||
GPIO_DRV_12MA
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
uint16_t GPIOGetConfig(enum gpio_id_t gpio_id);
|
||||
void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config);
|
||||
void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask);
|
||||
|
||||
uint32_t GPIOGetControl(enum gpio_id_t gpio_id);
|
||||
|
||||
void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val);
|
||||
|
||||
void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask);
|
||||
|
||||
void GPIOPropertySet ( enum gpio_id_t gpio_id,
|
||||
enum gpio_prop_t gpio_prop,
|
||||
uint16_t prop_val
|
||||
);
|
||||
|
||||
uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id );
|
||||
void GPIOSetSlewRate ( enum gpio_id_t gpio_id,
|
||||
enum gpio_slew_rate_t slew_rate );
|
||||
uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id );
|
||||
void GPIOSetDriveStr ( enum gpio_id_t gpio_id,
|
||||
enum gpio_drv_str_t drv_str );
|
||||
uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id );
|
||||
void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,
|
||||
uint8_t drv_and_slew );
|
||||
|
||||
void GPIOSetOutput ( enum gpio_id_t gpio_id,
|
||||
uint8_t gpio_state
|
||||
);
|
||||
|
||||
void GPIOToggleOutput ( enum gpio_id_t gpio_id );
|
||||
|
||||
uint8_t GPIOReadPin( enum gpio_id_t gpio_id );
|
||||
|
||||
void GPIOPinLock(enum gpio_id_t gpio_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_GPIO_H
|
||||
/* end mec14XX_gpio.h */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file mec14xx_jtvic.h
|
||||
*MEC14xx JTVIC HW defines
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals JTVIC
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_JTVIC_H
|
||||
#define _MEC14XX_JTVIC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define JTVIC_PRI1 0
|
||||
#define JTVIC_PRI3 1
|
||||
#define JTVIC_PRI5 2
|
||||
#define JTVIC_PRI7 3
|
||||
|
||||
/* Each JTVIC GIRQx has 4 32-bit priority registers where each nibble
|
||||
* encodes one of four priorities.
|
||||
* Generate JTVIC GIRQx Priority Register value for field number b with
|
||||
* priority p
|
||||
* b is the field [0,7]
|
||||
* p is the priority 0=IPL1, 1=IPL3, 2=IPL5, 3=IPL7
|
||||
*/
|
||||
#define JTVIC_PRI_VAL(b,p) ((uint32_t)((p) & 0x03) << (((b) & 0x07) << 2))
|
||||
|
||||
#define JTVIC_GIRQ_NPRI_REGS (4)
|
||||
typedef struct {
|
||||
uint32_t isr_addr;
|
||||
uint32_t pri[JTVIC_GIRQ_NPRI_REGS];
|
||||
} JTVIC_CFG;
|
||||
|
||||
#define JTVIC_FLAG_DISAGR_SPACING_8 (0)
|
||||
#define JTVIC_FLAG_DISAGR_SPACING_512 (1ul << 0)
|
||||
|
||||
#define JTVIC_NO_CLR_SRC (0)
|
||||
#define JTVIC_CLR_SRC (1)
|
||||
|
||||
void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags);
|
||||
void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num);
|
||||
void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);
|
||||
void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_JTVIC_H
|
||||
/* end mec14XX_jtvic.h */
|
||||
/** @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,477 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file mec14xx_pcr.h
|
||||
*MEC14xx Power Control Reset definitions
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals PCR
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_PCR_H
|
||||
#define _MEC14XX_PCR_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PCR_SLEEP_EN (1u)
|
||||
#define PCR_SLEEP_DIS (0u)
|
||||
|
||||
//
|
||||
// VTR Powered PCR registers
|
||||
//
|
||||
|
||||
//
|
||||
// Chip Sleep Enable Reg (Offset +00h)
|
||||
// Chip Clock Required Status Reg (Offset +04h)
|
||||
//
|
||||
#define PCR_CHIP_SLP_EN_OFFSET (0ul)
|
||||
#define PCR_CHIP_SLP_EN_MASK (0x03ul)
|
||||
#define PCR_CHIP_STAP_BITPOS (0)
|
||||
#define PCR_CHIP_EFUSE_BITPOS (1)
|
||||
#define PCR_CHIP_CLK_REQ_OFFSET (0x04ul)
|
||||
#define PCR_CHIP_CLK_REQ_MASK (0x03ul)
|
||||
//
|
||||
#define PCR_CHIP_STAP_SLP_CLK (1ul << (PCR_CHIP_STAP_BITPOS))
|
||||
#define PCR_CHIP_EFUSE_SLP_CLK (1ul << (PCR_CHIP_EFUSE_BITPOS))
|
||||
//
|
||||
#define PCR_CHIP_STAP_NOSLP_CLK (0ul)
|
||||
#define PCR_CHIP_EFUSE_NOSLP_CLK (0ul)
|
||||
|
||||
|
||||
//
|
||||
// EC Sleep Enable Reg (Offset +08h)
|
||||
// EC Clock Required Status Reg (Offset +0Ch)
|
||||
//
|
||||
#define PCR_EC_SLP_EN_OFFSET (0x08ul)
|
||||
#define PCR_EC_SLP_EN_MASK (0xE7F00FF7ul)
|
||||
#define PCR_EC_CLK_REQ_OFFSET (0x0Cul)
|
||||
#define PCR_EC_CLK_REQ_MASK (0xE7F00FF7ul)
|
||||
//
|
||||
#define PCR_EC_INT_SLP_BITPOS (0)
|
||||
#define PCR_EC_PECI_SLP_BITPOS (1)
|
||||
#define PCR_EC_TACH0_SLP_BITPOS (2)
|
||||
// bit[3] Reserved
|
||||
#define PCR_EC_PWM0_SLP_BITPOS (4)
|
||||
#define PCR_EC_PMC_SLP_BITPOS (5)
|
||||
#define PCR_EC_DMA_SLP_BITPOS (6)
|
||||
#define PCR_EC_TFDP_SLP_BITPOS (7)
|
||||
#define PCR_EC_CPU_SLP_BITPOS (8)
|
||||
#define PCR_EC_WDT_SLP_BITPOS (9)
|
||||
#define PCR_EC_SMB0_SLP_BITPOS (10)
|
||||
#define PCR_EC_TACH1_SLP_BITPOS (11)
|
||||
// bits[19:12] Rerserved
|
||||
#define PCR_EC_PWM1_SLP_BITPOS (20)
|
||||
#define PCR_EC_PWM2_SLP_BITPOS (21)
|
||||
#define PCR_EC_PWM3_SLP_BITPOS (22)
|
||||
#define PCR_EC_PWM4_SLP_BITPOS (23)
|
||||
#define PCR_EC_PWM5_SLP_BITPOS (24)
|
||||
#define PCR_EC_PWM6_SLP_BITPOS (25)
|
||||
#define PCR_EC_PWM7_SLP_BITPOS (26)
|
||||
// bits[28:17] Reserved
|
||||
#define PCR_EC_REG_SLP_BITPOS (29)
|
||||
#define PCR_EC_TIMER0_SLP_BITPOS (30)
|
||||
#define PCR_EC_TIMER1_SLP_BITPOS (31)
|
||||
//
|
||||
|
||||
#define PCR_EC_INT_SLP_CLK (1ul << (PCR_EC_INT_SLP_BITPOS))
|
||||
#define PCR_EC_PECI_SLP_CLK (1ul << (PCR_EC_PECI_SLP_BITPOS))
|
||||
#define PCR_EC_TACH0_SLP_CLK (1ul << PCR_EC_TACH0_SLP_BITPOS))
|
||||
// bit[3] Reserved
|
||||
#define PCR_EC_PWM0_SLP_CLK (1ul << (PCR_EC_PWM0_SLP_BITPOS))
|
||||
#define PCR_EC_PMC_SLP_CLK (1ul << (PCR_EC_PMC_SLP_BITPOS))
|
||||
#define PCR_EC_DMA_SLP_CLK (1ul << (PCR_EC_DMA_SLP_BITPOS))
|
||||
#define PCR_EC_TFDP_SLP_CLK (1ul << (PCR_EC_TFDP_SLP_BITPOS))
|
||||
#define PCR_EC_CPU_SLP_CLK (1ul << (PCR_EC_CPU_SLP_BITPOS))
|
||||
#define PCR_EC_WDT_SLP_CLK (1ul << (PCR_EC_WDT_SLP_BITPOS))
|
||||
#define PCR_EC_SMB0_SLP_CLK (1ul << (PCR_EC_SMB0_SLP_BITPOS))
|
||||
#define PCR_EC_TACH1_SLP_CLK (1ul << (PCR_EC_TACH1_SLP_BITPOS))
|
||||
// bits[19:12] Rerserved
|
||||
#define PCR_EC_PWM1_SLP_CLK (1ul << (PCR_EC_PWM1_SLP_BITPOS))
|
||||
#define PCR_EC_PWM2_SLP_CLK (1ul << (PCR_EC_PWM2_SLP_BITPOS))
|
||||
#define PCR_EC_PWM3_SLP_CLK (1ul << (PCR_EC_PWM3_SLP_BITPOS))
|
||||
#define PCR_EC_PWM4_SLP_CLK (1ul << (PCR_EC_PWM4_SLP_BITPOS))
|
||||
#define PCR_EC_PWM5_SLP_CLK (1ul << (PCR_EC_PWM5_SLP_BITPOS))
|
||||
#define PCR_EC_PWM6_SLP_CLK (1ul << (PCR_EC_PWM6_SLP_BITPOS))
|
||||
#define PCR_EC_PWM7_SLP_CLK (1ul << (PCR_EC_PWM7_SLP_BITPOS))
|
||||
// bits[28:17] Reserved
|
||||
#define PCR_EC_REG_SLP_CLK (1ul << (PCR_EC_REG_SLP_BITPOS))
|
||||
#define PCR_EC_TIMER0_SLP_CLK (1ul << (PCR_EC_TIMER0_SLP_BITPOS))
|
||||
#define PCR_EC_TIMER1_SLP_CLK (1ul << (PCR_EC_TIMER1_SLP_BITPOS))
|
||||
|
||||
|
||||
//
|
||||
// Host Sleep Enable Reg (Offset +10h)
|
||||
// Host Clock Required Status Reg (Offset +14h)
|
||||
//
|
||||
#define PCR_HOST_SLP_EN_OFFSET (0x10UL)
|
||||
#define PCR_HOST_SLP_EN_MASK (0x001BFC0Ful)
|
||||
#define PCR_HOST_CLK_REQ_OFFSET (0x14UL)
|
||||
#define PCR_HOST_CLK_REQ_MASK (0x001BFC0Ful)
|
||||
//
|
||||
#define PCR_HOST_LPC_SLP_BITPOS (0)
|
||||
#define PCR_HOST_UART0_SLP_BITPOS (1)
|
||||
#define PCR_HOST_P80A_SLP_BITPOS (2)
|
||||
#define PCR_HOST_P80B_SLP_BITPOS (3)
|
||||
// b[9:4] Reserved
|
||||
#define PCR_HOST_ACPI_EC2_SLP_BITPOS (10)
|
||||
#define PCR_HOST_ACPI_EC3_SLP_BITPOS (11)
|
||||
#define PCR_HOST_GLBL_CFG_SLP_BITPOS (12)
|
||||
#define PCR_HOST_APCI_EC0_SLP_BITPOS (13)
|
||||
#define PCR_HOST_APCI_EC1_SLP_BITPOS (14)
|
||||
#define PCR_HOST_APCI_PM1_SLP_BITPOS (15)
|
||||
#define PCR_HOST_MIF8042_SLP_BITPOS (16)
|
||||
#define PCR_HOST_MBOX_SLP_BITPOS (17)
|
||||
// b[18] Reserved
|
||||
#define PCR_HOST_ESPI_SLP_BITPOS (19)
|
||||
#define PCR_HOST_TSCR_SLP_BITPOS (20)
|
||||
// b[31:12] Reserved
|
||||
|
||||
//
|
||||
#define PCR_HOST_LPC_SLP_CLK (1UL<<(PCR_HOST_LPC_SLP_BITPOS))
|
||||
#define PCR_HOST_UART0_SLP_CLK (1UL<<(PCR_HOST_UART0_SLP_BITPOS))
|
||||
#define PCR_HOST_P80A_SLP_CLK (1UL<<(PCR_HOST_P80A_SLP_BITPOS))
|
||||
#define PCR_HOST_P80B_SLP_CLK (1UL<<(PCR_HOST_P80B_SLP_BITPOS))
|
||||
#define PCR_HOST_ACPI_EC2_SLP_CLK (1UL<<(PCR_HOST_ACPI_EC2_SLP_BITPOS))
|
||||
#define PCR_HOST_ACPI_EC3_SLP_CLK (1UL<<(PCR_HOST_ACPI_EC3_SLP_BITPOS))
|
||||
#define PCR_HOST_GLBL_CFG_SLP_CLK (1UL<<(PCR_HOST_GLBL_CFG_SLP_BITPOS))
|
||||
#define PCR_HOST_APCI_EC0_SLP_CLK (1UL<<(PCR_HOST_APCI_EC0_SLP_BITPOS))
|
||||
#define PCR_HOST_APCI_EC1_SLP_CLK (1UL<<(PCR_HOST_APCI_EC1_SLP_BITPOS))
|
||||
#define PCR_HOST_APCI_PM1_SLP_CLK (1UL<<(PCR_HOST_APCI_PM1_SLP_BITPOS))
|
||||
#define PCR_HOST_MIF8042_SLP_CLK (1UL<<(PCR_HOST_MIF8042_SLP_BITPOS))
|
||||
#define PCR_HOST_MBOX_SLP_CLK (1UL<<(PCR_HOST_MBOX_SLP_BITPOS))
|
||||
#define PCR_HOST_ESPI_SLP_CLK (1UL<<(PCR_HOST_ESPI_SLP_BITPOS))
|
||||
#define PCR_HOST_TSCR_SLP_CLK (1UL<<(PCR_HOST_TSCR_SLP_BITPOS))
|
||||
|
||||
//
|
||||
#define PCR_HOST_LPC_NOSLP_CLK (0)
|
||||
#define PCR_HOST_UART0_NOSLP_CLK (0)
|
||||
#define PCR_HOST_P80A_NOSLP_CLK (0)
|
||||
#define PCR_HOST_P80B_NOSLP_CLK (0)
|
||||
#define PCR_HOST_ACPI_EC2_NOSLP_CLK (0)
|
||||
#define PCR_HOST_ACPI_EC3_NOSLP_CLK (0)
|
||||
#define PCR_HOST_GLBL_CFG_NOSLP_CLK (0)
|
||||
#define PCR_HOST_APIC_EC0_NOSLP_CLK (0)
|
||||
#define PCR_HOST_APIC_EC1_NOSLP_CLK (0)
|
||||
#define PCR_HOST_APIC_PM1_NOSLP_CLK (0)
|
||||
#define PCR_HOST_MIF8042_NOSLP_CLK (0)
|
||||
#define PCR_HOST_MBOX_NOSLP_CLK (0)
|
||||
#define PCR_HOST_ESPI_NOSLP_CLK (0)
|
||||
#define PCR_HOST_TSCR_NOSLP_CLK (0)
|
||||
|
||||
|
||||
|
||||
//
|
||||
// System Sleep Control Reg (Offset +18h)
|
||||
//
|
||||
#define PCR_SYS_SLP_CTRL_OFFSET (0x18ul)
|
||||
#define PCR_SYS_SLP_CTRL_MASK (0x77ul)
|
||||
#define PCR_SYS_SLP_ROSC_PD_BITPOS (0u)
|
||||
#define PCR_SYS_SLP_ROSC_GATE_BITPOS (1u)
|
||||
#define PCR_SYS_SLP_CORE_VREG_STDBY_BITPOS (2u)
|
||||
#define PCR_SYS_SLP_ALL_BITPOS (4u)
|
||||
#define PCR_SYS_SLP_DBG_BITPOS (5u)
|
||||
#define PCR_SYS_SLP_AUTO_CLR_BITPOS (6u)
|
||||
|
||||
#define PCR_SYS_SLP_ROSC_PD (1ul<<(PCR_SYS_SLP_ROSC_PD_BITPOS))
|
||||
#define PCR_SYS_SLP_ROSC_GATE (1ul<<(PCR_SYS_SLP_ROSC_GATE_BITPOS))
|
||||
#define PCR_SYS_SLP_CORE_VREG_STDBY (1ul<<(PCR_SYS_SLP_CORE_VREG_STDBY_BITPOS))
|
||||
#define PCR_SYS_SLP_ALL (1ul<<(PCR_SYS_SLP_ALL_BITPOS))
|
||||
#define PCR_SYS_SLP_DBG (1ul<<(PCR_SYS_SLP_DBG_BITPOS))
|
||||
#define PCR_SYS_SLP_AUTO_CLR (1ul<<(PCR_SYS_SLP_AUTO_CLR_BITPOS))
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Reserved (Offset +1Ch)
|
||||
//
|
||||
|
||||
//
|
||||
// Processor Clock Control Reg (Offset +20h)
|
||||
//
|
||||
#define PCR_CLK_CTRL_OFFSET (0x20UL)
|
||||
#define PCR_CLK_CTRL_MASK (0xFFUL)
|
||||
#define PCR_CLK_CTRL_48M (0x01UL)
|
||||
#define PCR_CLK_CTRL_24M (0x02UL)
|
||||
#define PCR_CLK_CTRL_16M (0x03UL)
|
||||
#define PCR_CLK_CTRL_12M (0x04UL)
|
||||
#define PCR_CLK_CTRL_9P6M (0x05UL)
|
||||
#define PCR_CLK_CTRL_8M (0x06UL)
|
||||
#define PCR_CLK_CTRL_6P9M (0x07UL)
|
||||
#define PCR_CLK_CTRL_6M (0x08UL)
|
||||
#define PCR_CLK_CTRL_4M (0x0CUL)
|
||||
#define PCR_CLK_CTRL_1M (0x30UL)
|
||||
|
||||
//
|
||||
// EC Sleep Enable 2 Reg (Offset +24h)
|
||||
// EC Clock Required 2 Reg (Offset +28h)
|
||||
//
|
||||
#define PCR_SLP_EN2_OFFSET (0x24UL)
|
||||
#define PCR_SLP_EN2_MASK (0x00FF7E6Eul)
|
||||
#define PCR_CLK_REQ2_OFFSET (0x28UL)
|
||||
#define PCR_CLK_REQ2_MASK (0x00FF7E6EUL)
|
||||
//
|
||||
#define PCR_EC2_DAC0_SLP_BITPOS (1)
|
||||
#define PCR_EC2_DAC1_SLP_BITPOS (2)
|
||||
#define PCR_EC2_ADC_SLP_BITPOS (3)
|
||||
// bit[4] Reserved
|
||||
#define PCR_EC2_PS2_0_SLP_BITPOS (5)
|
||||
#define PCR_EC2_PS2_1_SLP_BITPOS (6)
|
||||
// bits[8:7] Reserved
|
||||
#define PCR_EC2_SPI0_SLP_BITPOS (9)
|
||||
#define PCR_EC2_HIB_SLP_BITPOS (10)
|
||||
#define PCR_EC2_KEY_SLP_BITPOS (11)
|
||||
#define PCR_EC2_RTOS_TMR_SLP_BITPOS (12)
|
||||
#define PCR_EC2_SMB1_SLP_BITPOS (13)
|
||||
#define PCR_EC2_SMB2_SLP_BITPOS (14)
|
||||
// bit[15] Reserved
|
||||
#define PCR_EC2_LED0_SLP_BITPOS (16)
|
||||
#define PCR_EC2_LED1_SLP_BITPOS (17)
|
||||
#define PCR_EC2_LED2_SLP_BITPOS (18)
|
||||
#define PCR_EC2_BCM0_SLP_BITPOS (19)
|
||||
#define PCR_EC2_BCM1_SLP_BITPOS (20)
|
||||
#define PCR_EC2_TIMER2_SLP_BITPOS (21)
|
||||
#define PCR_EC2_TIMER3_SLP_BITPOS (22)
|
||||
#define PCR_EC2_SUBDEC_SLP_BITPOS (23)
|
||||
|
||||
//
|
||||
#define PCR_EC2_DAC0_SLP_CLK (1ul << (PCR_EC2_DAC0_SLP_BITPOS))
|
||||
#define PCR_EC2_DAC1_SLP_CLK (1ul << (PCR_EC2_DAC1_SLP_BITPOS))
|
||||
#define PCR_EC2_ADC_SLP_CLK (1ul << (PCR_EC2_ADC_SLP_BITPOS))
|
||||
#define PCR_EC2_PS2_0_SLP_CLK (1ul << (PCR_EC2_PS2_0_SLP_BITPOS))
|
||||
#define PCR_EC2_PS2_1_SLP_CLK (1ul << (PCR_EC2_PS2_1_SLP_BITPOS))
|
||||
#define PCR_EC2_SPI0_SLP_CLK (1ul << (PCR_EC2_SPI0_SLP_BITPOS))
|
||||
#define PCR_EC2_HIB_SLP_CLK (1ul << (PCR_EC2_SPI0_SLP_BITPOS))
|
||||
#define PCR_EC2_KEY_SLP_CLK (1ul << (PCR_EC2_KEY_SLP_BITPOS))
|
||||
#define PCR_EC2_RTOS_TMR_SLP_CLK (1ul << (PCR_EC2_RTOS_TMR_SLP_BITPOS))
|
||||
#define PCR_EC2_SMB1_SLP_CLK (1ul << (PCR_EC2_SMB1_SLP_BITPOS))
|
||||
#define PCR_EC2_SMB2_SLP_CLK (1ul << (PCR_EC2_SMB2_SLP_BITPOS))
|
||||
#define PCR_EC2_LED0_SLP_CLK (1ul << (PCR_EC2_LED0_SLP_BITPOS))
|
||||
#define PCR_EC2_LED1_SLP_CLK (1ul << (PCR_EC2_LED1_SLP_BITPOS))
|
||||
#define PCR_EC2_LED2_SLP_CLK (1ul << (PCR_EC2_LED2_SLP_BITPOS))
|
||||
#define PCR_EC2_BCM0_SLP_CLK (1ul << (PCR_EC2_BCM0_SLP_BITPOS))
|
||||
#define PCR_EC2_BCM1_SLP_CLK (1ul << (PCR_EC2_BCM1_SLP_BITPOS))
|
||||
#define PCR_EC2_TIMER2_SLP_CLK (1ul << (PCR_EC2_TIMER2_SLP_BITPOS))
|
||||
#define PCR_EC2_TIMER3_SLP_CLK (1ul << (PCR_EC2_TIMER3_SLP_BITPOS))
|
||||
#define PCR_EC2_SUBDEC_SLP_CLK (1ul << (PCR_EC2_SUBDEC_SLP_BITPOS))
|
||||
|
||||
//
|
||||
#define PCR_EC2_DAC0_NOSLP_CLK (0)
|
||||
#define PCR_EC2_DAC1_NOSLP_CLK (0)
|
||||
#define PCR_EC2_ADC_NOSLP_CLK (0)
|
||||
#define PCR_EC2_PS2_0_NOSLP_CLK (0)
|
||||
#define PCR_EC2_PS2_1_NOSLP_CLK (0)
|
||||
#define PCR_EC2_SPI0_NOSLP_CLK (0)
|
||||
#define PCR_EC2_HIB_NOSLP_CLK (0)
|
||||
#define PCR_EC2_KEY_NOSLP_CLK (0)
|
||||
#define PCR_EC2_RTOS_TMR_NOSLP_CLK (0)
|
||||
#define PCR_EC2_SMB1_NOSLP_CLK (0)
|
||||
#define PCR_EC2_SMB2_NOSLP_CLK (0)
|
||||
#define PCR_EC2_LED0_NOSLP_CLK (0)
|
||||
#define PCR_EC2_LED1_NOSLP_CLK (0)
|
||||
#define PCR_EC2_LED2_NOSLP_CLK (0)
|
||||
#define PCR_EC2_BCM0_NOSLP_CLK (0)
|
||||
#define PCR_EC2_BCM1_NOSLP_CLK (0)
|
||||
#define PCR_EC2_TIMER2_NOSLP_CLK (0)
|
||||
#define PCR_EC2_TIMER3_NOSLP_CLK (0)
|
||||
#define PCR_EC2_SUBDEC_NOSLP_CLK (0)
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Slow Clock Control Reg (Offset +2Ch)
|
||||
//
|
||||
#define PCR_SLOW_CLK_CTRL_OFFSET (0x2Cul)
|
||||
#define PCR_SLOW_CLK_CTRL_MASK (0x03FFul)
|
||||
#define PCR_SLOW_CLK_OFF (0ul)
|
||||
#define PCR_SLOW_CLK_48M (1ul)
|
||||
#define PCR_SLOW_CLK_24M (2ul)
|
||||
#define PCR_SLOW_CLK_16M (3ul)
|
||||
#define PCR_SLOW_CLK_12M (4ul)
|
||||
#define PCR_SLOW_CLK_9P6M (5ul)
|
||||
#define PCR_SLOW_CLK_8M (6ul)
|
||||
#define PCR_SLOW_CLK_6M (8ul)
|
||||
#define PCR_SLOW_CLK_4M (12ul)
|
||||
#define PCR_SLOW_CLK_3M (16ul)
|
||||
#define PCR_SLOW_CLK_2M (24ul)
|
||||
#define PCR_SLOW_CLK_1M (48ul)
|
||||
|
||||
//
|
||||
// Oscillator ID Reg (Offset +30h)
|
||||
//
|
||||
#define PCR_OSC_ID_OFFSET (0x30ul)
|
||||
#define PCR_OSC_LOCK (1ul<<8)
|
||||
|
||||
//
|
||||
// Chip Sub-system Power Reset Status (Offset +34h)
|
||||
//
|
||||
#define PCR_CHIP_PRS_OFFSET (0x34ul)
|
||||
#define PCR_CHIP_PRS_MASK (0x0E6Cul)
|
||||
#define PCR_CHIP_PRS_VCC_PWRGD_RO (1ul << 2)
|
||||
#define PCR_CHIP_PRS_SIO_RSTN_RO (1ul << 3)
|
||||
#define PCR_CHIP_PRS_VBAT_RST_RW1C (1ul << 5)
|
||||
#define PCR_CHIP_PRS_VTR_RST_RW1C (1ul << 6)
|
||||
#define PCR_CHIP_PRS_VBAT_LOW_RO (1ul << 9)
|
||||
#define PCR_CHIP_PRS_32K_ACT_RO (1ul << 10)
|
||||
#define PCR_CHIP_PRS_PCICLK_ACT_RO (1ul << 11)
|
||||
|
||||
//
|
||||
// Chip Reset Enable Reg (Offset +38h)
|
||||
//
|
||||
#define PCR_CHIP_RST_EN_OFFSET (0x38ul)
|
||||
#define PCR_CHIP_RST_EN_STAP (1ul << 0)
|
||||
#define PCR_CHIP_RST_EN_EFUSE (1ul << 1)
|
||||
|
||||
//
|
||||
// Host Reset Enable Reg (Offset +3Ch)
|
||||
//
|
||||
#define PCR_HOST_RST_EN_OFFSET (0x3Cul)
|
||||
#define PCR_HOST_RST_EN_MASK (0x0001F003ul)
|
||||
#define PCR_HOST_RST_EN_LPC (1ul << 0)
|
||||
#define PCR_HOST_RST_EN_UART0 (1ul << 1)
|
||||
#define PCR_HOST_RST_EN_GLBL_CFG (1ul << 12)
|
||||
#define PCR_HOST_RST_EN_ACPI_EC0 (1ul << 13)
|
||||
#define PCR_HOST_RST_EN_ACPI_EC1 (1ul << 14)
|
||||
#define PCR_HOST_RST_EN_ACPI_PM1 (1ul << 15)
|
||||
#define PCR_HOST_RST_EN_MIF8042 (1ul << 16)
|
||||
|
||||
|
||||
//
|
||||
// EC Reset Enable Register (Offset +40h)
|
||||
//
|
||||
#define PCR_EC_RST_EN_OFFSET (0x40ul)
|
||||
#define PCR_EC_RST_EN_MASK (0xE7F00FF7ul)
|
||||
#define PCR_EC_RST_EN_INT (1ul << 0)
|
||||
#define PCR_EC_RST_EN_PECI (1ul << 1)
|
||||
#define PCR_EC_RST_EN_TACH0 (1ul << 2)
|
||||
// bit[3] Reserved
|
||||
#define PCR_EC_RST_EN_PWM0 (1ul << 4)
|
||||
#define PCR_EC_RST_EN_PMC (1ul << 5)
|
||||
#define PCR_EC_RST_EN_DMA (1ul << 6)
|
||||
#define PCR_EC_RST_EN_TFDP (1ul << 7)
|
||||
#define PCR_EC_RST_EN_CPU (1ul << 8)
|
||||
#define PCR_EC_RST_EN_WDT (1ul << 9)
|
||||
#define PCR_EC_RST_EN_SMB0 (1ul << 10)
|
||||
#define PCR_EC_RST_EN_TACH1 (1ul << 11)
|
||||
// bits[19:12] Reserved
|
||||
#define PCR_EC_RST_EN_PWM1 (1ul << 20)
|
||||
#define PCR_EC_RST_EN_PWM2 (1ul << 21)
|
||||
#define PCR_EC_RST_EN_PWM3 (1ul << 22)
|
||||
#define PCR_EC_RST_EN_PWM4 (1ul << 23)
|
||||
#define PCR_EC_RST_EN_PWM5 (1ul << 24)
|
||||
#define PCR_EC_RST_EN_PWM6 (1ul << 25)
|
||||
#define PCR_EC_RST_EN_PWM7 (1ul << 26)
|
||||
// bits[28:27] Reserved
|
||||
#define PCR_EC_RST_EN_REG (1ul << 29)
|
||||
#define PCR_EC_RST_EN_TIMER0 (1ul << 30)
|
||||
#define PCR_EC_RST_EN_TIMER1 (1ul << 31)
|
||||
|
||||
//
|
||||
// EC Reset Enable 2 Register (Offset +44h)
|
||||
//
|
||||
#define PCR_EC_RST_EN2_OFFSET (0x44ul)
|
||||
#define PCR_EC_RST_EN2_MASK (0x007FEE68ul)
|
||||
#define PCR_EC2_RST_EN_ADC (1ul << 3)
|
||||
#define PCR_EC2_RST_EN_PS2_0 (1ul << 5)
|
||||
#define PCR_EC2_RST_EN_PS2_1 (1ul << 6)
|
||||
#define PCR_EC2_RST_EN_SPI0 (1ul << 9)
|
||||
#define PCR_EC2_RST_EN_HIB (1ul << 10)
|
||||
#define PCR_EC2_RST_EN_KEY (1ul << 11)
|
||||
#define PCR_EC2_RST_EN_SMB1 (1ul << 13)
|
||||
#define PCR_EC2_RST_EN_SMB2 (1ul << 14)
|
||||
#define PCR_EC2_RST_EN_SMB3 (1ul << 15)
|
||||
#define PCR_EC2_RST_EN_LED0 (1ul << 16)
|
||||
#define PCR_EC2_RST_EN_LED1 (1ul << 17)
|
||||
#define PCR_EC2_RST_EN_LED2 (1ul << 18)
|
||||
#define PCR_EC2_RST_EN_BCM0 (1ul << 19)
|
||||
#define PCR_EC2_RST_EN_BCM1 (1ul << 20)
|
||||
#define PCR_EC2_RST_EN_TIMER2 (1ul << 21)
|
||||
#define PCR_EC2_RST_EN_TIMER3 (1ul << 22)
|
||||
|
||||
//
|
||||
// Host Reset
|
||||
//
|
||||
// Power Reset Control Reg (Offset +48h)
|
||||
//
|
||||
#define PCR_HOST_OFFSET (0x48ul)
|
||||
#define PCR_HOST_MASK (0x03ul)
|
||||
#define PCR_HOST_IRESET_OUT_BITPOS (0)
|
||||
#define PCR_HOST_IRESET_OUT_ASSERT (1ul << (PCR_HOST_IRESET_OUT_BITPOS))
|
||||
#define PCR_HOST_RESET_SEL_BITPOS (1)
|
||||
#define PCR_HOST_RESET_SEL_LPC (0ul << (PCR_HOST_RESET_SEL_BITPOS))
|
||||
#define PCR_HOST_RESET_SEL_ESPI (1ul << (PCR_HOST_RESET_SEL_BITPOS))
|
||||
|
||||
//
|
||||
// ------------------------------------------------------------------
|
||||
//
|
||||
|
||||
//
|
||||
// VBAT Powered Register Bank
|
||||
//
|
||||
#define VBATR_PWR_FAIL_RESET_OFS (0)
|
||||
#define VBATR_ATE_REG_CTRL_OFS (4)
|
||||
#define VBATR_CLOCK_ENABLE_OFS (8)
|
||||
#define VBATR_ATE_TEST_OFS (0x10)
|
||||
#define VBATR_OSC_32K_TRIM_OFS (0x14)
|
||||
#define VBATR_VTR_ALT_CTRL_OFS (0x18)
|
||||
#define VBATR_OSC_TRIM_CTRL_OFS (0x1C)
|
||||
|
||||
|
||||
//
|
||||
// Power Fail Reset Status Reg
|
||||
//
|
||||
#define VBATR_PFR_MASK (0xA1)
|
||||
#define VBATR_PFR_RESERVED_MASK ~(VBATR_PFR_MASK)
|
||||
#define VBATR_PFR_DET32K_BITPOS (0)
|
||||
#define VBATR_PFR_DET32K (1U << (VBATR_PFR_DET32K_BITPOS))
|
||||
#define VBATR_PFR_WDT_STS_BITPOS (5)
|
||||
#define VBATR_PFR_WDT_STS (1U << (VBATR_PFR_WDT_STS_BITPOS))
|
||||
#define VBATR_PFR_VBAT_RST_STS_BITPOS (7)
|
||||
#define VBATR_PFR_VBAT_RST_STS (1U << (VBATR_PFR_VBAT_RST_STS_BITPOS))
|
||||
|
||||
//
|
||||
// ATE Regulator Control, offset 0x04
|
||||
|
||||
//
|
||||
// Clock Enable Reg, offset 0x08
|
||||
//
|
||||
#define PCRVB_CLKEN_XOSEL_BITPOS (0)
|
||||
#define PCRVB_CLKEN_XOSEL (1U<<0)
|
||||
#define PCRVB_CLKEN_EN_32K_BITPOS (1)
|
||||
#define PCRVB_CLKEN_EN_32K (1U<<1)
|
||||
|
||||
//
|
||||
// 32KHz Oscillator Trim, offset 0x14
|
||||
//
|
||||
#define PCRVB_OSC_32K_TRIM_MASK (0x1Ful)
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_PCR_H
|
||||
/* end mec14xx_pcr.h */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file mec14xx_system.h
|
||||
*MEC14xx System header
|
||||
*/
|
||||
/** @defgroup MEC14xx system
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_MEC14xx_H
|
||||
#define __SYSTEM_MEC14xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
uint32_t sys_code_sram_base(void);
|
||||
uint8_t sys_valid_sram_addr(void * const p);
|
||||
uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len);
|
||||
void sys_cpu_en_timer(uint32_t counts, uint8_t ien);
|
||||
|
||||
uint32_t cpu_microsecond_interval(uint32_t start_count);
|
||||
uint32_t cpu_microsecond_count(void);
|
||||
#define CPU_US_DELTA(x) cpu_microsecond_interval(x)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_MEC14xx_H */
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/** @file mec14xx_tfdp.h
|
||||
*MEC14xx TRACE FIFO Data Port definitions
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals TFDP
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_TFDP_H
|
||||
#define _MEC14XX_TFDP_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TFDP_NUM_INSTANCES (1u)
|
||||
|
||||
#define TFDP_FRAME_START (0xFD)
|
||||
|
||||
|
||||
//
|
||||
// Offset +00h TFDP Data Register: 8-bit R/W
|
||||
//
|
||||
#define TFDP_DATA_REG_OFS (0ul)
|
||||
#define TFDP_DATA_REG_MASK (0xFFul)
|
||||
|
||||
//
|
||||
// Offset +04h TFDP Control Register 8-bit R/W
|
||||
//
|
||||
#define TFDP_CTRL_REG_OFS (0x04ul)
|
||||
#define TFDP_CTRL_REG_MASK (0x7Ful)
|
||||
//
|
||||
#define TFDP_CTRL_ENABLE_BITPOS (0u)
|
||||
#define TFDP_CTRL_EDGE_SEL_BITPOS (1u)
|
||||
#define TFDP_CTRL_DIVSEL_BITPOS (2ul)
|
||||
#define TFDP_CTRL_IP_DELAY_BITPOS (4ul)
|
||||
// Enable/disable
|
||||
#define TFDP_CTRL_ENABLE (1u << (TFDP_CTRL_ENABLE_BITPOS))
|
||||
// Select clock edge data on which data is shifted out
|
||||
#define TFDP_CTRL_RISING_EDGE (0u << (TFDP_CTRL_EDGE_SEL_BITPOS))
|
||||
#define TFDP_CTRL_FALLING_EDGE (1u << (TFDP_CTRL_EDGE_SEL_BITPOS))
|
||||
// TFDP Clock divisor
|
||||
#define TFDP_CTRL_CLK_DIV2 (0u << (TFDP_CTRL_DIVSEL_BITPOS))
|
||||
#define TFDP_CTRL_CLK_DIV4 (1u << (TFDP_CTRL_DIVSEL_BITPOS))
|
||||
#define TFDP_CTRL_CLK_DIV8 (2u << (TFDP_CTRL_DIVSEL_BITPOS))
|
||||
#define TFDP_CTRL_CLK_DIV2_RSVD (3u << (TFDP_CTRL_DIVSEL_BITPOS))
|
||||
// Number of clocks to delay between each byte
|
||||
// Note: this will affect time TFDP block holds off CPU on next
|
||||
// write to TFDP data register.
|
||||
#define TFDP_CTRL_IP_1CLKS (0u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_2CLKS (1u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_3CLKS (2u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_4CLKS (3u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_5CLKS (4u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_6CLKS (5u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_7CLKS (6u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
#define TFDP_CTRL_IP_8CLKS (7u << (TFDP_CTRL_IP_DELAY_BITPOS))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_TFDP_H
|
||||
/* end mec14xx_tfdp.h */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/** @file mec14xx_timers.h
|
||||
*MEC14xx Timer definitions
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals Timers
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_TIMERS_H
|
||||
#define _MEC14XX_TIMERS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Basic 16-bit Timer
|
||||
******************************************************************************/
|
||||
|
||||
//
|
||||
// Basic 16-bit timers, Number of Instances
|
||||
//
|
||||
#define BTMR_MAX_INSTANCE (4ul)
|
||||
|
||||
//
|
||||
// Offset between instances of the TMR blocks
|
||||
//
|
||||
#define BTMR_INSTANCE_BITPOS (5ul)
|
||||
#define BTMR_INSTANCE_OFFSET (1ul << (BTMR_INSTANCE_BITPOS))
|
||||
|
||||
//
|
||||
// Basic Timer Count Register (Offset +00h), 32-bit, uses b[15:0]
|
||||
//
|
||||
#define BTMR_CNT_MASK (0x0000FFFFUL)
|
||||
|
||||
//
|
||||
// Basic Timer Preload Register (Offset +04h), 32-bit, uses b[15:0]
|
||||
//
|
||||
#define BTMR_PRELOAD_MASK (0x0000FFFFUL)
|
||||
|
||||
//
|
||||
// Basic Timer Status Register (Offset +08h), 32-bit, uses b[0] (R/W1C)
|
||||
//
|
||||
#define BTMR_STATUS_ACTIVE (0x01UL)
|
||||
|
||||
//
|
||||
// Basic Timer Interrupt Enable Register (Offset +0Ch), 32-bit, uses b[0]
|
||||
//
|
||||
#define BTMR_INTEN (0x01UL)
|
||||
#define BTMR_INTDIS (0ul)
|
||||
|
||||
//
|
||||
// Basic Timer Control Register (Offset +10h), 32-bit, uses b[31:0]
|
||||
//
|
||||
#define BTMR_CNTL (0x10UL)
|
||||
//
|
||||
#define BTMR_CNTL_PRESCALE_MASK (0xFFFF0000UL)
|
||||
#define BTMR_CNTL_PRESCALE_BITPOS (16U)
|
||||
#define BTMR_CNTL_PRESCALE_FIELD_WIDTH (16U)
|
||||
#define BTMR_CNTL_RSVD_MASK (0x0000FF02UL)
|
||||
#define BTMR_CNTL_HALT (0x80UL)
|
||||
#define BTMR_CNTL_RELOAD (0x40UL)
|
||||
#define BTMR_CNTL_START (0x20UL)
|
||||
#define BTMR_CNTL_SOFT_RESET (0x10UL)
|
||||
#define BTMR_CNTL_AUTO_RESTART (0x08UL)
|
||||
#define BTMR_CNTL_COUNT_UP (0x04UL)
|
||||
#define BTMR_CNTL_ENABLE (0x01UL)
|
||||
//
|
||||
#define BTMR_CNTL_HALT_BIT (7U)
|
||||
#define BTMR_CNTL_RELOAD_BIT (6U)
|
||||
#define BTMR_CNTL_START_BIT (5U)
|
||||
#define BTMR_CNTRL_SOFT_RESET_BIT (4U)
|
||||
#define BTMR_CNTL_AUTO_RESTART_BIT (3U)
|
||||
#define BTMR_CNTL_COUNT_DIR_BIT (2U)
|
||||
#define BTMR_CNTL_ENABLE_BIT (0U)
|
||||
|
||||
/*******************************************************************************
|
||||
* RTOS Timer
|
||||
******************************************************************************/
|
||||
#define RTMR_MAX_INSTANCE (1)
|
||||
|
||||
/* RTOS Timer clock input is 32KHz.
|
||||
* FW must enable 32KHz clock domain.
|
||||
* NOTE: AHB register interface uses 48MHz
|
||||
* clock domain.
|
||||
*/
|
||||
#define RTMR_CLOCK_SRC_FREQ_HZ (32768ul)
|
||||
|
||||
//
|
||||
// +00h Count Value, 32-bit Read-Only
|
||||
// NOTE: Register must be read as 32-bit, there is no
|
||||
// latch mechanism.
|
||||
//
|
||||
#define RTMR_COUNT_RO_OFS (0ul)
|
||||
|
||||
//
|
||||
// +04h Pre-load, 32-bit Read-Write
|
||||
//
|
||||
#define RTMR_PRELOAD_OFS (4ul)
|
||||
|
||||
//
|
||||
// +08h Control, 32-bit Read-Write
|
||||
// Implements bits[4:0]
|
||||
//
|
||||
#define RTMR_CONTROL_OFS (8ul)
|
||||
#define RTMR_CONTROL_MASK (0x1Ful)
|
||||
#define RTMR_BLOCK_EN_BITPOS (0)
|
||||
#define RTMR_BLOCK_EN (1ul << (RTMR_BLOCK_EN_BITPOS))
|
||||
#define RTMR_AUTO_RELOAD_BITPOS (1)
|
||||
#define RTMR_AUTO_RELOAD_EN (1ul << (RTMR_AUTO_RELOAD_BITPOS))
|
||||
#define RTMR_START_BITPOS (2)
|
||||
#define RTMR_START (1ul << (RTMR_START_BITPOS))
|
||||
#define RTMR_EXT_HW_HALT_EN_BITPOS (3)
|
||||
#define RTMR_EXT_HW_HALT_EN (1ul << (RTMR_EXT_HW_HALT_EN_BITPOS))
|
||||
#define RTMR_FW_HALT_BITPOS (4)
|
||||
#define RTMR_FW_HALT (1ul << (RTMR_FW_HALT_BITPOS))
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hibernation Timer
|
||||
******************************************************************************/
|
||||
#define HIBTMR_MAX_INSTANCE (1)
|
||||
|
||||
/* Hibernation Timer clock input is 32KHz.
|
||||
* FW must enable 32KHz clock domain.
|
||||
* NOTE: AHB register interface uses 48MHz
|
||||
* clock domain.
|
||||
*/
|
||||
#define HIBTMR_CLOCK_SRC_FREQ_HZ (32768ul)
|
||||
|
||||
//
|
||||
// +00h Preload, 16-bit Read-Write
|
||||
//
|
||||
#define HIBTMR_PRELOAD_OFS (0ul)
|
||||
/* Write 0 to Preload to disable timer, non-zero loads COUNT
|
||||
* and starts timer */
|
||||
#define HIBTMR_PRELOAD_DISABLE (0)
|
||||
|
||||
|
||||
//
|
||||
// +04h Control, 16-bit Read-Write
|
||||
// Implements bit[0]
|
||||
//
|
||||
#define HIBTMR_CNTRL_OFS (4ul)
|
||||
#define HIBTMR_CNTRL_RESERVED_MASK (0xFFFEu)
|
||||
#define HIBTMR_CNTRL_MASK (0x01ul)
|
||||
#define HIBTMR_CNTRL_FREQ_32KHZ (0)
|
||||
#define HIBTMR_CNTRL_FREQ_8HZ (1)
|
||||
|
||||
//
|
||||
// +08h Count, 16-bit Read-Only
|
||||
//
|
||||
#define HIBTMR_COUNT_RO_OFS (8ul)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* RTC/Week Timer
|
||||
******************************************************************************/
|
||||
#define WKTMR_MAX_INSTANCE (1)
|
||||
|
||||
/* Week Timer clock input is 32KHz.
|
||||
* FW must enable 32KHz clock domain.
|
||||
* NOTE: AHB register interface uses 48MHz
|
||||
* clock domain.
|
||||
*/
|
||||
#define WKTMR_CLOCK_SRC_FREQ_HZ (32768ul)
|
||||
|
||||
//
|
||||
// +00h Control, 8-bit Read-Write
|
||||
//
|
||||
#define WKTMR_CNTRL_OFS (0ul)
|
||||
#define WKTMR_CNTRL_MASK (0x61u)
|
||||
#define WKTMR_CNTRL_RESERVED_MASK (~(WKTMR_CNTRL_MASK))
|
||||
#define WKTMR_CNTRL_EN_BITPOS (0)
|
||||
#define WKTMR_CNTRL_EN (1ul << (WKTMR_CNTRL_EN_BITPOS))
|
||||
#define WKTMR_BGPO_BITPOS (5)
|
||||
#define WKTMR_BGPO_LO (0ul << (WKTMR_BGPO_BITPOS))
|
||||
#define WKTMR_BGPO_HI (1ul << (WKTMR_BGPO_BITPOS))
|
||||
#define WKTMR_PWRUP_EVENT_EN_BITPOS (6)
|
||||
#define WKTMR_PWRUP_EVENT_EN (1ul << (WKTMR_PWRUP_EVENT_EN_BITPOS))
|
||||
|
||||
//
|
||||
// +04h 1-second COUNT, 32-bit Read-Write
|
||||
// Implements bits[27:0]
|
||||
//
|
||||
#define WKTMR_COUNT_1S_OFS (4ul)
|
||||
#define WKTMR_COUNT_1S_MASK (0x0FFFFFFFul)
|
||||
|
||||
//
|
||||
// +08h COMPARE, 32-bit Read-Write
|
||||
// Implements bits[27:0]
|
||||
//
|
||||
#define WKTMR_COMPARE_OFS (8ul)
|
||||
#define WKTMR_COUNT_1S_MASK (0x0FFFFFFFul)
|
||||
|
||||
//
|
||||
// +0Ch Clock Divider, 32-bit Read-Only
|
||||
// Implements b[14:0]
|
||||
//
|
||||
#define WKTMR_CLOCK_DIVIDER_RO_OFS (0x0Cul)
|
||||
#define WKTMR_CLOCK_DIVIDER_RO_MASK (0x7FFFul)
|
||||
|
||||
//
|
||||
// +10h Sub-second Interrupt Events Select, 32-bit Read-Write
|
||||
// Implements bits[3:0]
|
||||
//
|
||||
#define WKTMR_SUBSEC_EVENTS_SEL_OFS (0x10ul)
|
||||
#define WKTMR_SUBSEC_EVENTS_SEL_MASK (0x0Ful)
|
||||
#define WKTMR_SUBSEC_EV_DIS (0u)
|
||||
#define WKTMR_SUBSEC_EV_2HZ (1u)
|
||||
#define WKTMR_SUBSEC_EV_4HZ (2u)
|
||||
#define WKTMR_SUBSEC_EV_8HZ (3u)
|
||||
#define WKTMR_SUBSEC_EV_16HZ (4u)
|
||||
#define WKTMR_SUBSEC_EV_32HZ (5u)
|
||||
#define WKTMR_SUBSEC_EV_64HZ (6u)
|
||||
#define WKTMR_SUBSEC_EV_128HZ (7u)
|
||||
#define WKTMR_SUBSEC_EV_256HZ (8u)
|
||||
#define WKTMR_SUBSEC_EV_512HZ (9u)
|
||||
#define WKTMR_SUBSEC_EV_1024HZ (10u)
|
||||
#define WKTMR_SUBSEC_EV_2048HZ (11u)
|
||||
#define WKTMR_SUBSEC_EV_4096HZ (12u)
|
||||
#define WKTMR_SUBSEC_EV_8192HZ (13u)
|
||||
#define WKTMR_SUBSEC_EV_16384HZ (14u)
|
||||
#define WKTMR_SUBSEC_EV_32768HZ (15u)
|
||||
|
||||
//
|
||||
// +14h Sub-Week Control, 32-bit Read-Write
|
||||
// Implements bits[9:4, 1:0]
|
||||
// Bits[1:0] = Read-Write-1-Clear
|
||||
// Bit[4] = Read-Only
|
||||
// Bits[9:5] = Read-Write
|
||||
//
|
||||
#define WKTMR_SUB_CNTRL_OFS (0x14ul)
|
||||
#define WKTMR_SUB_CNTRL_MASK (0x3F3ul)
|
||||
#define WKTMR_SUB_CNTRL_RESERVED_MASK (~(WKTMR_SUB_CNTRL_MASK))
|
||||
#define WKTMR_SC_PWRUP_EV_STS_BITPOS (0)
|
||||
#define WKTMR_SC_PWRUP_EV_STS (1ul << (WKTMR_SC_PWRUP_EV_STS_BITPOS))
|
||||
#define WKTMR_WK_PWRUP_EV_STS_BITPOS (1)
|
||||
#define WKTMR_WK_PWRUP_EV_STS (1ul << (WKTMR_WK_PWRUP_EV_STS_BITPOS))
|
||||
#define WKTMR_SC_SYSPWR_PRES_STS_BITPOS (4)
|
||||
#define WKTMR_SC_SYSPWR_PRES_STS (1ul << (WKTMR_SC_SYSPWR_PRES_STS_BITPOS))
|
||||
#define WKTMR_SC_SYSPWR_PRES_EN_BITPOS (5)
|
||||
#define WKTMR_SC_SYSPWR_PRES_EN (1ul << (WKTMR_SC_SYSPWR_PRES_EN_BITPOS))
|
||||
#define WKTMR_SC_AUTO_RELOAD_EN_BITPOS (6)
|
||||
#define WKTMR_SC_AUTO_RELOAD_EN (1ul << (WKTMR_SC_AUTO_RELOAD_EN_BITPOS))
|
||||
#define WKTMR_SC_CLKSRC_BITPOS (7)
|
||||
#define WKTMR_SC_CLKSRC_MASK (0x07ul << (WKTMR_SC_CLKSRC_BITPOS))
|
||||
|
||||
//
|
||||
// +18h Sub-Week Count, 32-bit Read-Write
|
||||
// Implements bits[24:16, 8:0]
|
||||
// Bit2[24:16] = Read-Only
|
||||
// Bits[8:0] = Read-Write
|
||||
//
|
||||
#define WKTMR_SUBWK_COUNT_OFS (0x18ul)
|
||||
#define WKTMR_SUBWK_COUNT_MASK (0x01FF01FFul)
|
||||
#define WKTMR_SUBWK_COUNT_RESERVED_MASK (~(WKTMR_SUBWK_COUNT_MASK))
|
||||
#define WKTMR_SUBWK_CNT_LOAD_BITPOS (0)
|
||||
#define WKTMR_SUBWK_CNT_LOAD_MASK (0x1FFul)
|
||||
#define WKTMR_SUBWK_CNT_VAL_RO_BITPOS (16)
|
||||
#define WKTMR_SUBWK_CNT_VAL_RO_MASK (0x01FFul)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Basic 16-bit Timer API
|
||||
******************************************************************************/
|
||||
|
||||
//
|
||||
// Logical Basic Timer ID for API calls
|
||||
//
|
||||
|
||||
#define BTMR0_ID (0x00u)
|
||||
#define BTMR1_ID (0x01u)
|
||||
#define BTMR2_ID (0x02u)
|
||||
#define BTMR3_ID (0x03u)
|
||||
#define BTMR_ID_MAX (0x04u)
|
||||
|
||||
//
|
||||
// Logical flags for tmr_cntl parameter of TMRInit
|
||||
// b[31:16] = prescaler
|
||||
//
|
||||
#define BTMR_AUTO_RESTART (0x08u)
|
||||
#define BTMR_ONE_SHOT (0u)
|
||||
#define BTMR_COUNT_UP (0x04u)
|
||||
#define BTMR_COUNT_DOWN (0u)
|
||||
#define BTMR_INT_EN (0x01u)
|
||||
#define BTMR_NO_INT (0u)
|
||||
|
||||
uint32_t btmr_get_hw_addr(uint8_t btmr_id);
|
||||
|
||||
void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en);
|
||||
void btmr_reset(uint8_t tmr_id);
|
||||
void btmr_init(uint8_t tmr_id,
|
||||
uint16_t tmr_cntl,
|
||||
uint16_t prescaler,
|
||||
uint32_t initial_count,
|
||||
uint32_t preload_count);
|
||||
|
||||
void btmr_ien(uint8_t tmr_id, uint8_t ien);
|
||||
uint8_t btmr_get_clr_ists(uint8_t tmr_id);
|
||||
|
||||
void btmr_reload(uint8_t tmr_id);
|
||||
void btmr_set_count(uint8_t tmr_id, uint32_t count);
|
||||
uint32_t btmr_count(uint8_t tmr_id);
|
||||
void btmr_start(uint8_t tmr_id);
|
||||
void btmr_stop(uint8_t tmr_id);
|
||||
uint8_t btmr_is_stopped(uint8_t tmr_id);
|
||||
void btmr_halt(uint8_t tmr_id);
|
||||
void btmr_uhalt(uint8_t tmr_id);
|
||||
|
||||
/*******************************************************************************
|
||||
* End Basic 16-bit Timer API
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_TIMERS_H
|
||||
/* end mec14xx_timers.h */
|
||||
/** @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file mec14xx_trace_func.h
|
||||
*MEC14xx TFDP Peripheral Library API
|
||||
*/
|
||||
/** @defgroup MEC14xx Peripherals Trace
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_TRACE_FUNC_H
|
||||
#define _MEC14XX_TRACE_FUNC_H
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "mec14xx.h"
|
||||
#include "mec14xx_tfdp.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_TFDP_TRACE
|
||||
|
||||
#ifdef ENABLE_TRACE_HOST_LINK
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
|
||||
#define TFDP_SLEEP_EN (1u)
|
||||
#define TFDP_SLEEP_DIS (0u)
|
||||
#define TFDP_EN (1u)
|
||||
#define TFDP_DIS (0u)
|
||||
#define TFDP_CFG_PINS (1u)
|
||||
#define TFDP_NO_CFG_PINS (0u)
|
||||
|
||||
void tfdp_sleep_en(uint8_t sleep_en);
|
||||
void tfdp_enable(uint8_t en, uint8_t pin_cfg);
|
||||
void TFDPTrace0( uint16_t nbr, uint8_t b );
|
||||
void TFDPTrace1( uint16_t nbr, uint8_t b, uint32_t p1 );
|
||||
void TFDPTrace2( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 );
|
||||
void TFDPTrace3( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3);
|
||||
void TFDPTrace4( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4);
|
||||
void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1);
|
||||
void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2);
|
||||
|
||||
#if defined(ENABLE_TRACE_HOST_LINK)
|
||||
#define TRACE0(nbr,cat,b,str) printf(str)
|
||||
#define TRACE1(nbr,cat,b,str,p1) printf(str,p1)
|
||||
#define TRACE2(nbr,cat,b,str,p1,p2) printf(str,p1,p2)
|
||||
#define TRACE3(nbr,cat,b,str,p1,p2,p3) printf(str,p1,p2,p3)
|
||||
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) printf(str,p1,p2,p3,p4)
|
||||
#define TRACE11(nbr,cat,b,str,p1) printf(str,p1)
|
||||
#define TRACE12(nbr,cat,b,str,p1,p2) printf(str,p1,p2)
|
||||
#elif defined(TRACE_NO_PREPROC)
|
||||
/* C pre-processor - don't substitute TRACE macros */
|
||||
#else // not ENABLE_TRACE_HOST_LINK
|
||||
#define TRACE0(nbr,cat,b,str) TFDPTrace0(nbr,b)
|
||||
#define TRACE1(nbr,cat,b,str,p1) TFDPTrace1(nbr,b,p1)
|
||||
#define TRACE2(nbr,cat,b,str,p1,p2) TFDPTrace2(nbr,b,p1,p2)
|
||||
#define TRACE3(nbr,cat,b,str,p1,p2,p3) TFDPTrace3(nbr,b,p1,p2,p3)
|
||||
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) TFDPTrace4(nbr,b,p1,p2,p3,p4)
|
||||
#define TRACE11(nbr,cat,b,str,p1) TFDPTrace11(nbr,b,p1)
|
||||
#define TRACE12(nbr,cat,b,str,p1,p2) TFDPTrace12(nbr,b,p1,p2)
|
||||
#endif
|
||||
|
||||
#else // #ifdef ENABLE_TFDP_TRACE
|
||||
|
||||
#define tfdp_sleep_en(sleep_en)
|
||||
#define tfdp_enable(en,pin_cfg)
|
||||
#define TRACE0(nbr,cat,b,str)
|
||||
#define TRACE1(nbr,cat,b,str,p1)
|
||||
#define TRACE2(nbr,cat,b,str,p1,p2)
|
||||
#define TRACE3(nbr,cat,b,str,p1,p2,p3)
|
||||
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4)
|
||||
#define TRACE11(nbr,cat,b,str,p1)
|
||||
#define TRACE12(nbr,cat,b,str,p1,p2)
|
||||
|
||||
#endif // #ifdef ENABLE_TFDP_TRACE
|
||||
|
||||
#define trace0(nbr,cat,b,str)
|
||||
#define trace1(nbr,cat,b,str,p1)
|
||||
#define trace2(nbr,cat,b,str,p1,p2)
|
||||
#define trace3(nbr,cat,b,str,p1,p2,p3)
|
||||
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
|
||||
#define trace11(nbr,cat,b,str,p1)
|
||||
#define trace12(nbr,cat,b,str,p1,p2)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_TRACE_FUNC_H
|
||||
/* end mec14xx_trace_func.h */
|
||||
/** @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/** @file mec14xx_trace_inline.h
|
||||
*MEC14xx Inline TRACE macros
|
||||
*/
|
||||
/** @defgroup MEC14xx TRACE
|
||||
*/
|
||||
|
||||
#ifndef _MEC14XX_TRACE_INLINE_H
|
||||
#define _MEC14XX_TRACE_INLINE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define INLINE_TRACE_ENABLE
|
||||
|
||||
#ifdef INLINE_TRACE_ENABLE
|
||||
|
||||
|
||||
#define TRDA (0xA0008c00ul)
|
||||
|
||||
#define TRHDR() *(volatile uint8_t *)(TRDA)=0xFDu
|
||||
#define TRB0(v) *(volatile uint8_t *)(TRDA)=(uint8_t)v
|
||||
#define TRB1(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>8)
|
||||
#define TRB2(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>16)
|
||||
#define TRB3(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>24)
|
||||
|
||||
#define TRACE0(nbr,cat,b,str) TRHDR();TRB0(nbr);TRB1(nbr);
|
||||
#define TRACE1(nbr,cat,b,str,p1) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);
|
||||
#define TRACE2(nbr,cat,b,str,p1,p2) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);
|
||||
#define TRACE3(nbr,cat,b,str,p1,p2,p3) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);TRB0(p3);TRB1(p3);
|
||||
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);TRB0(p3);TRB1(p3);TRB0(p4);TRB1(p4);
|
||||
#define TRACE11(nbr,cat,b,str,p1) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB2(p1);TRB3(p1);
|
||||
#define TRACE12(nbr,cat,b,str,p1,p2) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB2(p1);TRB3(p1);TRB0(p2);TRB1(p2);TRB2(p2);TRB3(p2);
|
||||
|
||||
#else // #ifdef INLINE_TRACE_ENABLE
|
||||
|
||||
#define TRACE0(nbr,cat,b,str)
|
||||
#define TRACE1(nbr,cat,b,str,p1)
|
||||
#define TRACE2(nbr,cat,b,str,p1,p2)
|
||||
#define TRACE3(nbr,cat,b,str,p1,p2,p3)
|
||||
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4)
|
||||
#define TRACE11(nbr,cat,b,str,p1)
|
||||
#define TRACE12(nbr,cat,b,str,p1,p2)
|
||||
#define trace0(nbr,cat,b,str)
|
||||
#define trace1(nbr,cat,b,str,p1)
|
||||
#define trace2(nbr,cat,b,str,p1,p2)
|
||||
#define trace3(nbr,cat,b,str,p1,p2,p3)
|
||||
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
|
||||
#define trace11(nbr,cat,b,str,p1)
|
||||
#define trace12(nbr,cat,b,str,p1,p2)
|
||||
|
||||
#endif // #ifdef PLIB_TRACE_ENABLE
|
||||
|
||||
#define trace0(nbr,cat,b,str)
|
||||
#define trace1(nbr,cat,b,str,p1)
|
||||
#define trace2(nbr,cat,b,str,p1,p2)
|
||||
#define trace3(nbr,cat,b,str,p1,p2,p3)
|
||||
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
|
||||
#define trace11(nbr,cat,b,str,p1)
|
||||
#define trace12(nbr,cat,b,str,p1,p2)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _MEC14XX_TRACE_INLINE_H
|
||||
/* end mec14xx_trace_inline.h */
|
||||
/** @}
|
||||
*/
|
||||
137
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/appcfg.h
Normal file
137
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/appcfg.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file appcfg.h
|
||||
*MEC14xx build configuration
|
||||
*/
|
||||
/** @defgroup common
|
||||
*/
|
||||
|
||||
#ifndef _APPCFG_H
|
||||
#define _APPCFG_H
|
||||
|
||||
#define ADISABLE (0)
|
||||
#define AENABLE (1)
|
||||
|
||||
#define FALSE (0)
|
||||
#define TRUE (1)
|
||||
|
||||
#define OFF (0)
|
||||
#define ON (1)
|
||||
|
||||
/*
|
||||
* Choose MEC1404 or MEC1418 Device
|
||||
*/
|
||||
#define MEC1403_DEVID (0x00011000) /* Code 96KB, 84-pin */
|
||||
#define MEC1404_DEVID (0x00021000) /* Code 96KB, 128-pin */
|
||||
#define MEC1405_DEVID (0x00031000) /* Code 128KB 84-pin */
|
||||
#define MEC1406_DEVID (0x00041000) /* Code 128KB 128-pin */
|
||||
#define MEC1407_DEVID (0x00051000) /* Code 160KB 84-pin */
|
||||
#define MEC1408_DEVID (0x00061000) /* Code 160KB 128-pin */
|
||||
#define MEC1413_DEVID (0x00071000) /* Code 96KB 84-pin */
|
||||
#define MEC1414_DEVID (0x00081000) /* Code 96KB 128-pin */
|
||||
#define MEC1415_DEVID (0x00091000) /* Code 128KB 84-pin */
|
||||
#define MEC1416_DEVID (0x000A1000) /* Code 128KB 128-pin */
|
||||
#define MEC1417_DEVID (0x000B1000) /* Code 160KB 84-pin */
|
||||
#define MEC1418_DEVID (0x000C1000) /* Code 160KB 128-pin */
|
||||
|
||||
#define MEC14XX_DEVID (MEC1404_DEVID)
|
||||
|
||||
/*
|
||||
* MEC14xx Power-Control-Reset Processor clock divider value
|
||||
* MIPS M14K Processor clock = Chip_Input_Clock / PCR_PROC_CLK_DIV
|
||||
* MEC14xx POR PCR Processor Clock divider = 4
|
||||
*
|
||||
* Silicon Chip_Input_Clock = 48MHz
|
||||
*
|
||||
*/
|
||||
#define PCR_CLOCK_DIVIDER (1)
|
||||
|
||||
|
||||
// GPIO_0102/KSO9 0102(octal)=0x42.
|
||||
#define CR_STRAP_GPIO (0x42ul)
|
||||
#define CR_STRAP_GPIO_BANK (2u)
|
||||
#define CR_STRAP_BITPOS (2u)
|
||||
|
||||
/* GPIO_0123 0:[0,37], 1:[40,77], 2:[100,137], 3:[140,177], 4[200,237] */
|
||||
#define SPI0_CS0_REG_IDX (0x53u)
|
||||
#define SPI0_CS0_GPIO_BANK (2ul)
|
||||
#define SPI0_CS0_BITPOS (19u)
|
||||
/* GPIO_0015 0:[0,37], 1:[40,77], 2:[100,137], 3:[140,177], 4[200,237] */
|
||||
#define SPI1_CS0_REG_IDX (0x0Du)
|
||||
#define SPI1_CS0_GPIO_BANK (0ul)
|
||||
#define SPI1_CS0_BITPOS (13u)
|
||||
|
||||
|
||||
/*
|
||||
* ASIC at full speed (48MHz)
|
||||
* M14K CP0 Counter increments at 1/2 CPU core clock.
|
||||
*/
|
||||
#define M14K_TIMER_COMPARE_2SEC (0x00B71B00ul)
|
||||
#define M14K_TIMER_COMPARE_1SEC (0x005B8D80ul)
|
||||
#define M14K_TIMER_COMPARE_10MS (0x0000EA60ul)
|
||||
#define M14K_TIMER_COMPARE (M14K_TIMER_COMPARE_2SEC)
|
||||
|
||||
/* 16-bit Timer 0 */
|
||||
// Prescale value for 10KHz tick rate
|
||||
#define BASIC_TIMER0_PRESCALE_10KHZ_ASIC (4799ul)
|
||||
#define BASIC_TIMER0_PRESCALE_1KHZ_ASIC (47999ul)
|
||||
// Preload/Count value for 1.733 seconds
|
||||
#define BASIC_TIMER0_PRESCALE (BASIC_TIMER0_PRESCALE_1KHZ_ASIC)
|
||||
#define BASIC_TIMER0_PRELOAD (2000ul)
|
||||
|
||||
/* RTOS Timer (32KHz) */
|
||||
#define RTOS_TIMER_COUNT_10MS (328ul)
|
||||
|
||||
|
||||
/*
|
||||
* Enable check of GPIO access in mec14xx_gpio module
|
||||
*/
|
||||
#define ENABLE_GPIO_PIN_VALIDATION
|
||||
|
||||
/*
|
||||
* Enable check of Basic Timer ID in API calls
|
||||
*/
|
||||
#define MEC14XX_BTIMER_CHECK_ID
|
||||
|
||||
/*
|
||||
* Enable GPIO Pin Debug
|
||||
*/
|
||||
//#define DEBUG_GPIO_PIN
|
||||
|
||||
/*
|
||||
* Enable TFDP TRACE
|
||||
*/
|
||||
#define ENABLE_TFDP_TRACE
|
||||
|
||||
/*
|
||||
* Use C-library printf for TFDP Trace
|
||||
*
|
||||
#define ENABLE_TRACE_HOST_LINK
|
||||
*/
|
||||
|
||||
/*
|
||||
* Delay between writes to TFDP data register
|
||||
*/
|
||||
#define TFDP_DELAY()
|
||||
|
||||
#endif // #ifndef _APPCFG_H
|
||||
/** @}
|
||||
*/
|
||||
177
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/platform.h
Normal file
177
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/platform.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*****************************************************************************
|
||||
* © 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file platform.h
|
||||
*MEC14xx platform/cpu abstractions
|
||||
*/
|
||||
/** @defgroup MEC14xx
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_H
|
||||
#define _PLATFORM_H
|
||||
|
||||
#if defined(__GNUC__) && defined(__mips__)
|
||||
|
||||
#if defined(__XC32__) // Microchip XC32 GCC
|
||||
|
||||
/* Pull in MIPS32 specific special instructions instrinsics for
|
||||
* interrupt control, NOP, Wait-for-Interrupt and accessing
|
||||
* MSR's.
|
||||
* Issue: MPLAB-X IDE editor and the CPU macros in xc.h & cp0defs.h.
|
||||
* The IDE editor will show red ! on every line of code using the above
|
||||
* macros due to a bug in the IDE's C language preprocessor.
|
||||
*/
|
||||
#include <xc.h>
|
||||
|
||||
#define CPU_DISABLE_INTERRUPTS() __builtin_disable_interrupts()
|
||||
#define CPU_GET_DISABLE_INTERRUPTS(x) { x=_CP0_GET_STATUS()&0x1ul; __builtin_disable_interrupts() }
|
||||
#define CPU_ENABLE_INTERRUPTS() __builtin_enable_interrupts()
|
||||
#define CPU_RESTORE_INTERRUPTS(x) { if (x) { __builtin_enable_interrupts(); } }
|
||||
|
||||
#define Disable_Irq() CPU_DISABLE_INTERRUPTS()
|
||||
#define Enable_Irq() CPU_ENABLE_INTERRUPTS()
|
||||
|
||||
#define __CLZ(x) __builtin_clz(x)
|
||||
#define __CTZ(x) __builtin_ctz (x)
|
||||
#define __CLO(x) _clo(x)
|
||||
|
||||
#define __INS(tgt,val,pos,sz) _ins(tgt,val,pos,sz)
|
||||
#define __EXT(x,pos,sz) _ext(x,pos,sz)
|
||||
|
||||
#define CPU_NOP() __asm__ __volatile ("%(ssnop%)" : :)
|
||||
|
||||
#define CPU_WAIT_FOR_INTR() __asm__ __volatile ("wait")
|
||||
|
||||
#define __REV(x) _bswapw(x)
|
||||
|
||||
#define __EHB() _ehb()
|
||||
|
||||
#else
|
||||
|
||||
/* Include MIPS specific inline assembly functions for accessing
|
||||
* MIPS CP0 registers, NOP, WAIT, ASET, ACLR, byte-reverse, etc.
|
||||
*/
|
||||
#include "mipscpu.h"
|
||||
|
||||
|
||||
#define CPU_DISABLE_INTERRUPTS() mips32r2_dis_intr()
|
||||
#define CPU_GET_DISABLE_INTERRUPTS(x) x=mips32r2_dis_intr()
|
||||
#define CPU_ENABLE_INTERRUPTS() mips32r2_en_intr()
|
||||
#define CPU_RESTORE_INTERRUPTS(x) mips32r2_restore_intr(x)
|
||||
|
||||
#define Disable_Irq() CPU_DISABLE_INTERRUPTS()
|
||||
#define Enable_Irq() CPU_ENABLE_INTERRUPTS()
|
||||
|
||||
#define __CLZ(x) __builtin_clz(x)
|
||||
#define __CTZ(x) __builtin_ctz (x)
|
||||
|
||||
#define __CLO(x) __extension__({ \
|
||||
unsigned int __x = (x); \
|
||||
unsigned int __v; \
|
||||
__asm__ ("clo %0,%1" : "=d" (__v) : "d" (__x)); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
/* MIPS32r2 insert bits */
|
||||
#define __INS(tgt,val,pos,sz) __extension__({ \
|
||||
unsigned int __t = (tgt), __v = (val); \
|
||||
__asm__ ("ins %0,%z1,%2,%3" \
|
||||
: "+d" (__t) \
|
||||
: "dJ" (__v), "I" (pos), "I" (sz)); \
|
||||
__t; \
|
||||
})
|
||||
|
||||
/* MIPS32r2 extract bits */
|
||||
#define __EXT(x,pos,sz) __extension__({ \
|
||||
unsigned int __x = (x), __v; \
|
||||
__asm__ ("ext %0,%z1,%2,%3" \
|
||||
: "=d" (__v) \
|
||||
: "dJ" (__x), "I" (pos), "I" (sz)); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
#define CPU_NOP() __asm__ __volatile ("%(ssnop%)" : :)
|
||||
|
||||
#define CPU_WAIT_FOR_INTR() __asm__ __volatile ("wait")
|
||||
|
||||
#define __REV(x) mips32r2_rev_word(x)
|
||||
|
||||
#define __EHB() __asm__ __volatile__ ("%(ehb%)" : :)
|
||||
|
||||
#define _CP0_GET_BADVADDR() mips32r2_cp0_badvaddr_get()
|
||||
|
||||
#define _CP0_GET_COUNT() mips32r2_cp0_count_get()
|
||||
#define _CP0_SET_COUNT(val) mips32r2_cp0_count_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_COMPARE() mips32r2_cp0_compare_get()
|
||||
#define _CP0_SET_COMPARE(val) mips32r2_cp0_compare_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_STATUS() mips32r2_cp0_status_get()
|
||||
#define _CP0_SET_STATUS(val) mips32r2_cp0_status_set((unsigned long)val)
|
||||
#define _CP0_BIC_STATUS(val) mips32r2_cp0_status_bic(val)
|
||||
#define _CP0_BIS_STATUS(val) mips32r2_cp0_status_bis(val)
|
||||
|
||||
#define _CP0_GET_INTCTL() mips32r2_cp0_intctl_get()
|
||||
#define _CP0_SET_INTCTL(val) mips32r2_cp0_intctl_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_VIEW_IPL() mips32r2_cp0_view_ipl_get()
|
||||
#define _CP0_SET_VIEW_IPL(val) mips32r2_cp0_view_ipl_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_CAUSE() mips32r2_cp0_cause_get()
|
||||
#define _CP0_SET_CAUSE(val) mips32r2_cp0_cause_set((unsigned long)val)
|
||||
#define _CP0_BIC_CAUSE(val) mips32r2_cp0_cause_bic((unsigned long)val)
|
||||
#define _CP0_BIS_CAUSE(val) mips32r2_cp0_cause_bis((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_VIEW_RIPL() mips32r2_cp0_view_ripl_get()
|
||||
#define _CP0_SET_VIEW_RIPL(val) mips32r2_cp0_view_ripl_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_EPC() mips32r2_cp0_epc_get()
|
||||
#define _CP0_SET_EPC(val) mips32r2_cp0_epc_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_EBASE() mips32r2_cp0_ebase_get()
|
||||
#define _CP0_SET_EBASE(val) mips32r2_cp0_ebase_set((unsigned long)val)
|
||||
|
||||
#define _CP0_GET_CONFIG() mips32r2_cp0_config_get()
|
||||
#define _CP0_GET_CONFIG3() mips32r2_cp0_config3_get()
|
||||
|
||||
#define _CP0_GET_DEPC() mips32r2_cp0_depc_get()
|
||||
|
||||
#endif
|
||||
|
||||
#else // Any other compiler
|
||||
|
||||
#error "FORCED BUILD ERROR: Unknown compiler"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
Need to define NULL
|
||||
*/
|
||||
#ifndef NULL
|
||||
#ifdef __CPLUSPLUS__
|
||||
#define NULL 0
|
||||
#else
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif // #ifndef _PLATFORM_H
|
||||
/** @}
|
||||
*/
|
||||
Loading…
Add table
Add a link
Reference in a new issue