mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add PIC32MEC14xx port and demo application.
This commit is contained in:
Richard Barry
parent
f19497c3d6
commit
a29dc8d6c6
103 changed files with 49682 additions and 6 deletions
224
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq08.c
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224
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq08.c
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@ -0,0 +1,224 @@
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/*****************************************************************************
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* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
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* You may use this software and any derivatives exclusively with
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* Microchip products.
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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* OF THESE TERMS.
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*****************************************************************************/
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/** @file girq08.c
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*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
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*/
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/** @defgroup MEC14xx ISR
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* @{
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*/
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#include "appcfg.h"
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#include "platform.h"
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#include "MEC14xx/mec14xx.h"
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#include "MEC14xx/mec14xx_girqs.h"
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#include "MEC14xx/mec14xx_gpio.h"
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#include "MEC14xx/mec14xx_trace_func.h"
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#if GIRQ08_DISAGG == 0
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/*
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* Aggregated mode handler, must handle all enabled
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* GIRQ08 sources.
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*/
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void __attribute__((weak, interrupt, nomips16, section(".girqs")))
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girq08_isr( void )
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{
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JTVIC_GROUP_EN_CLR->w = (1ul<<0);
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}
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#else
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/*
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* Disaggregated GIRQ08 subhandlers, one for each
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* source. Called by assembly language wrapper.
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*/
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void __attribute__((weak, interrupt, nomips16))
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girq08_b0(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 0);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b1(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 1);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b2(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 2);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b3(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 3);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b4(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 4);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b5(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 5);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b6(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b7(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 7);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b8(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 8);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b9(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 9);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b10(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 10);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b11(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 11);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b12(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 12);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b13(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 13);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b14(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 14);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b15(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 15);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b16(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 16);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b17(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 17);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b18(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 18);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b19(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b20(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 20);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b21(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 21);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq08_b22(void)
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{
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jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22);
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}
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#endif
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/* end girq08.c */
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/** @}
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*/
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@ -0,0 +1,166 @@
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/*
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Copyright (C) 2014 Microchip Inc.
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All rights reserved
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1 tab == 4 spaces!
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*/
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#ifdef __XC32
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#include <xc.h>
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#include <sys/asm.h>
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#else
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#include "Regs.S"
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#endif
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#include "MEC14xx/mec14xx_girqm.h"
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/******************************************************************/
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/***************************************************************
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* MEC14xx GIRQ08 Disaggregated Vector Jump table
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*
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***************************************************************/
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.extern girq08_b0
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.extern girq08_b1
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.extern girq08_b2
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.extern girq08_b3
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.extern girq08_b4
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.extern girq08_b5
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.extern girq08_b6
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.extern girq08_b7
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.extern girq08_b8
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.extern girq08_b9
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.extern girq08_b10
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.extern girq08_b11
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.extern girq08_b12
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.extern girq08_b13
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.extern girq08_b14
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.extern girq08_b15
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.extern girq08_b16
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.extern girq08_b17
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.extern girq08_b18
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.extern girq08_b19
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.extern girq08_b20
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.extern girq08_b21
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.extern girq08_b22
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#if GIRQ08_DISAGG != 0
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/*
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* Disaggregated girq08v
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* Program address of this version of girq23v into JTVIC GIRQ08
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* Aggregator Control register with bit[0] = 1.
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*/
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.insn
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#ifdef __XC32
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.section .girqs.girq08_isr,code
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#else
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.section .girqs.girq08_isr,"x"
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#endif
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.set nomips16
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.set micromips
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.set noreorder
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.set noat
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.global girq08_isr
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.ent girq08_isr
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.align 2
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girq08_isr:
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J girq08_b0
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NOP
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.align 2
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J girq08_b1
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NOP
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.align 2
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J girq08_b2
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NOP
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.align 2
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J girq08_b3
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NOP
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.align 2
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J girq08_b4
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NOP
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.align 2
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J girq08_b5
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NOP
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.align 2
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J girq08_b6
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NOP
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.align 2
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J girq08_b7
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NOP
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.align 2
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J girq08_b8
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NOP
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.align 2
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J girq08_b9
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NOP
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.align 2
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J girq08_b10
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NOP
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.align 2
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J girq08_b11
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NOP
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.align 2
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J girq08_b12
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NOP
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.align 2
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J girq08_b13
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NOP
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.align 2
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J girq08_b14
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NOP
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.align 2
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J girq08_b15
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NOP
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.align 2
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J girq08_b16
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NOP
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.align 2
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J girq08_b17
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NOP
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.align 2
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J girq08_b18
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NOP
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.align 2
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J girq08_b19
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NOP
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.align 2
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J girq08_b20
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NOP
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.align 2
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J girq08_b21
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NOP
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.align 2
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J girq08_b22
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NOP
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.end girq08_isr
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/******************************************************************/
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#endif
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275
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq09.c
Normal file
275
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq09.c
Normal file
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@ -0,0 +1,275 @@
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/*****************************************************************************
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* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
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/** @file girq09.c
|
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*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
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*/
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/** @defgroup MEC14xx ISR
|
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* @{
|
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*/
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#include "appcfg.h"
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#include "platform.h"
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#include "MEC14xx/mec14xx.h"
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#include "MEC14xx/mec14xx_girqs.h"
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#include "MEC14xx/mec14xx_gpio.h"
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#include "MEC14xx/mec14xx_trace_func.h"
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#if GIRQ09_DISAGG == 0
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/*
|
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* Aggregated mode handler, must handle all enabled
|
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* GIRQ08 sources.
|
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*/
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void __attribute__((weak, interrupt, nomips16, section(".girqs")))
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girq09_isr( void )
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{
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JTVIC_GROUP_EN_CLR->w = (1ul<<1);
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}
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#else
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void __attribute__((weak, interrupt, nomips16))
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girq09_b0(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 0);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 0);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b1(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 1);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 1);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b2(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 2);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 2);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b3(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 3);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 3);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b4(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 4);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 4);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b5(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 5);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 5);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b6(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 6);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 6);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b7(void)
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{
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 7);
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JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 7);
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}
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void __attribute__((weak, interrupt, nomips16))
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girq09_b8(void)
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||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 8);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b9(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 9);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 9);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b10(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 10);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 10);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b11(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 11);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 11);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b12(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 12);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 12);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b13(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 13);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 13);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b14(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 14);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 14);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b15(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 15);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 15);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b16(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 16);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 16);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b17(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 17);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 17);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b18(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 18);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 18);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b19(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 19);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 19);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b20(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 20);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 20);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b21(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 21);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 21);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b22(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 22);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 22);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b23(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 23);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 23);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b24(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 24);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 24);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b25(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 25);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 25);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b26(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 26);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 26);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b27(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 27);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 27);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b28(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 28);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 28);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b29(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 29);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 29);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq09_b30(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 30);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 30);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq09.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ09 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq09_b0
|
||||
.extern girq09_b1
|
||||
.extern girq09_b2
|
||||
.extern girq09_b3
|
||||
.extern girq09_b4
|
||||
.extern girq09_b5
|
||||
.extern girq09_b6
|
||||
.extern girq09_b7
|
||||
.extern girq09_b8
|
||||
.extern girq09_b9
|
||||
.extern girq09_b10
|
||||
.extern girq09_b11
|
||||
.extern girq09_b12
|
||||
.extern girq09_b13
|
||||
.extern girq09_b14
|
||||
.extern girq09_b15
|
||||
.extern girq09_b16
|
||||
.extern girq09_b17
|
||||
.extern girq09_b18
|
||||
.extern girq09_b19
|
||||
.extern girq09_b20
|
||||
.extern girq09_b21
|
||||
.extern girq09_b22
|
||||
.extern girq09_b23
|
||||
.extern girq09_b24
|
||||
.extern girq09_b25
|
||||
.extern girq09_b26
|
||||
.extern girq09_b27
|
||||
.extern girq09_b28
|
||||
.extern girq09_b29
|
||||
.extern girq09_b30
|
||||
|
||||
#if GIRQ09_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq09v
|
||||
* Program address of this version of girq23v into JTVIC GIRQ09
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq09_isr, code
|
||||
#else
|
||||
.section .girqs.girq09_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.global girq09_isr
|
||||
.ent girq09_isr
|
||||
.align 2
|
||||
|
||||
girq09_isr:
|
||||
J girq09_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b9
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b10
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b11
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b12
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b13
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b14
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b15
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b16
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b17
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b18
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b19
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b20
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b21
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b22
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b23
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b24
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b25
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b26
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b27
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b28
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b29
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq09_b30
|
||||
NOP
|
||||
|
||||
.end girq09_isr
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
197
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq10.c
Normal file
197
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq10.c
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq10.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ10_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq10_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<2);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b12(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b13(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b14(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b15(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b16(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b17(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b18(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b19(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b20(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b21(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b22(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq10_b23(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq10.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ10 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq10_b0
|
||||
.extern girq10_b1
|
||||
.extern girq10_b2
|
||||
.extern girq10_b3
|
||||
.extern girq10_b4
|
||||
.extern girq10_b5
|
||||
.extern girq10_b6
|
||||
.extern girq10_b7
|
||||
.extern girq10_b8
|
||||
.extern girq10_b9
|
||||
.extern girq10_b10
|
||||
.extern girq10_b11
|
||||
.extern girq10_b12
|
||||
.extern girq10_b13
|
||||
.extern girq10_b14
|
||||
.extern girq10_b15
|
||||
.extern girq10_b16
|
||||
.extern girq10_b17
|
||||
.extern girq10_b18
|
||||
.extern girq10_b19
|
||||
.extern girq10_b20
|
||||
.extern girq10_b21
|
||||
.extern girq10_b22
|
||||
.extern girq10_b23
|
||||
|
||||
#if GIRQ10_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq10_isr
|
||||
* Program address of this version of girq23_isr into JTVIC GIRQ09
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq10_isr, code
|
||||
#else
|
||||
.section .girqs.girq10_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq10_isr
|
||||
.global girq10_isr
|
||||
.align 2
|
||||
|
||||
girq10_isr:
|
||||
J girq10_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b9
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b10
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b11
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b12
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b13
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b14
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b15
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b16
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b17
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b18
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b19
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b20
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b21
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b22
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq10_b23
|
||||
NOP
|
||||
|
||||
.end girq10_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
238
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq11.c
Normal file
238
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq11.c
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq11.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ11_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq11_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<3);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b0(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 1, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 2, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 3, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 4, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 5, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 6, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 7, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 9, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 10, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 11, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b12(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 12, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b13(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 13, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b14(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 14, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b15(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 15, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b16(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 16, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b17(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 17, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b18(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 18, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b19(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 19, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b20(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 20, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b21(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 21, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b22(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 22, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b23(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 23, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b24(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 24, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b25(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 25, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b26(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 26, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b27(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 27, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b28(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 28, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b29(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 29, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq11_b30(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 30, JTVIC_CLR_SRC);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq11.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ11 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq11_b0
|
||||
.extern girq11_b1
|
||||
.extern girq11_b2
|
||||
.extern girq11_b3
|
||||
.extern girq11_b4
|
||||
.extern girq11_b5
|
||||
.extern girq11_b6
|
||||
.extern girq11_b7
|
||||
.extern girq11_b8
|
||||
.extern girq11_b9
|
||||
.extern girq11_b10
|
||||
.extern girq11_b11
|
||||
.extern girq11_b12
|
||||
.extern girq11_b13
|
||||
.extern girq11_b14
|
||||
.extern girq11_b15
|
||||
.extern girq11_b16
|
||||
.extern girq11_b17
|
||||
.extern girq11_b18
|
||||
.extern girq11_b19
|
||||
.extern girq11_b20
|
||||
.extern girq11_b21
|
||||
.extern girq11_b22
|
||||
.extern girq11_b23
|
||||
.extern girq11_b24
|
||||
.extern girq11_b25
|
||||
.extern girq11_b26
|
||||
.extern girq11_b27
|
||||
.extern girq11_b28
|
||||
.extern girq11_b30
|
||||
|
||||
#if GIRQ11_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq11_isr
|
||||
* Program address of this version of girq23v into JTVIC GIRQ11
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq11_isr, code
|
||||
#else
|
||||
.section .girqs.girq11_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq11_isr
|
||||
.global girq11_isr
|
||||
.align 2
|
||||
|
||||
girq11_isr:
|
||||
#if 1
|
||||
J girq11_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b9
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b10
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b11
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b12
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b13
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b14
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b15
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b16
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b17
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b18
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b19
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b20
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b21
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b22
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b23
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b24
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b25
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b26
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b27
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b28
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b29
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq11_b30
|
||||
NOP
|
||||
|
||||
.end girq11_isr
|
||||
#else
|
||||
gen_jump_table 11,0,30
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq12.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ12_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq12_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<4);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq12_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq12_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq12_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq12.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ12 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq12_b0
|
||||
.extern girq12_b1
|
||||
.extern girq12_b2
|
||||
|
||||
#if GIRQ12_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq12_isr
|
||||
* Program address of this version of girq23v into JTVIC GIRQ12
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq12_isr, code
|
||||
#else
|
||||
.section .girqs.girq12_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq12_isr
|
||||
.global girq12_isr
|
||||
.align 2
|
||||
|
||||
girq12_isr:
|
||||
J girq12_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq12_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq12_b2
|
||||
NOP
|
||||
|
||||
.end girq12_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq13.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ13_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq13_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<5);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq13_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 6);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq13.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ13 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq13_b0
|
||||
.extern girq13_b1
|
||||
.extern girq13_b2
|
||||
.extern girq13_b3
|
||||
.extern girq13_b4
|
||||
.extern girq13_b5
|
||||
.extern girq13_b6
|
||||
|
||||
#if GIRQ13_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq13_isr
|
||||
* Program address of this version of girq23v into JTVIC GIRQ13
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq13_isr, code
|
||||
#else
|
||||
.section .girqs.girq13_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq13_isr
|
||||
.global girq13_isr
|
||||
.align 2
|
||||
|
||||
girq13_isr:
|
||||
J girq13_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq13_b6
|
||||
NOP
|
||||
|
||||
.end girq13_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq14.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ14_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq14_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<6);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq14_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq14.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ14 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq14_b0
|
||||
.extern girq14_b1
|
||||
.extern girq14_b2
|
||||
.extern girq14_b3
|
||||
.extern girq14_b4
|
||||
.extern girq14_b5
|
||||
|
||||
#if GIRQ14_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq14_isr
|
||||
* Program address of this version of girq14_isr into JTVIC GIRQ14
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq14_isr, code
|
||||
#else
|
||||
.section .girqs.girq14_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq14_isr
|
||||
.global girq14_isr
|
||||
.align 2
|
||||
|
||||
girq14_isr:
|
||||
J girq14_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq14_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq14_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq14_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq14_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq14_b5
|
||||
NOP
|
||||
|
||||
.end girq14_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
166
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq15.c
Normal file
166
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq15.c
Normal file
|
|
@ -0,0 +1,166 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq15.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ15_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq15_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<7);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 9);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 10);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 11);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b12(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 12);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b13(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 13);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b14(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 14);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b15(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 15);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b16(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 16);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b17(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 17);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq15_b18(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 18);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq15.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ15 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
.extern girq15_b0
|
||||
.extern girq15_b1
|
||||
.extern girq15_b2
|
||||
.extern girq15_b3
|
||||
.extern girq15_b4
|
||||
.extern girq15_b5
|
||||
.extern girq15_b6
|
||||
.extern girq15_b7
|
||||
.extern girq15_b8
|
||||
.extern girq15_b9
|
||||
.extern girq15_b10
|
||||
.extern girq15_b11
|
||||
.extern girq15_b12
|
||||
.extern girq15_b13
|
||||
.extern girq15_b14
|
||||
.extern girq15_b15
|
||||
.extern girq15_b16
|
||||
.extern girq15_b17
|
||||
.extern girq15_b18
|
||||
|
||||
#if GIRQ15_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq15_isr
|
||||
* Program address of this version of girq15_isr into JTVIC GIRQ15
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq15_isr, code
|
||||
#else
|
||||
.section .girqs.girq15_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq15_isr
|
||||
.global girq15_isr
|
||||
.align 2
|
||||
|
||||
girq15_isr:
|
||||
J girq15_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b9
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b10
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b11
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b12
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b13
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b14
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b15
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b16
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b17
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq15_b18
|
||||
NOP
|
||||
|
||||
.end girq15_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
112
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq16.c
Normal file
112
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq16.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq16.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ16_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq16_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<8);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq16_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 9);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq16.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ16 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq16_b0
|
||||
.extern girq16_b1
|
||||
.extern girq16_b2
|
||||
.extern girq16_b3
|
||||
.extern girq16_b4
|
||||
.extern girq16_b5
|
||||
.extern girq16_b6
|
||||
.extern girq16_b7
|
||||
.extern girq16_b8
|
||||
.extern girq16_b9
|
||||
|
||||
#if GIRQ16_DISAGG != 0
|
||||
/*
|
||||
* Disaggregated girq16_isr
|
||||
* Program address of this version of girq16_isr into JTVIC GIRQ16
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq16_isr, code
|
||||
#else
|
||||
.section .girqs.girq16_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq16_isr
|
||||
.global girq16_isr
|
||||
.align 2
|
||||
|
||||
girq16_isr:
|
||||
J girq16_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq16_b9
|
||||
NOP
|
||||
|
||||
.end girq16_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
128
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq17.c
Normal file
128
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq17.c
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq17.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ17_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq17_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<9);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b0(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 0);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b1(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 1);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b2(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 2);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b3(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 3);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b4(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 4);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b5(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 5);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b6(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 6);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b7(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 7);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b8(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 8);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b9(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 9);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 9);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq17_b10(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 10);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 10);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq17.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ17 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq17_b0
|
||||
.extern girq17_b1
|
||||
.extern girq17_b2
|
||||
.extern girq17_b3
|
||||
.extern girq17_b4
|
||||
.extern girq17_b5
|
||||
.extern girq17_b6
|
||||
.extern girq17_b7
|
||||
.extern girq17_b8
|
||||
.extern girq17_b9
|
||||
.extern girq17_b10
|
||||
|
||||
#if GIRQ17_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq17_isr
|
||||
* Program address of this version of girq17_isr into JTVIC GIRQ17
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq17_isr, code
|
||||
#else
|
||||
.section .girqs.girq17_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq17_isr
|
||||
.global girq17_isr
|
||||
.align 2
|
||||
|
||||
girq17_isr:
|
||||
J girq17_b0
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b1
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b2
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b3
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b4
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b5
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b6
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b7
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b8
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b9
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
J girq17_b10
|
||||
NOP
|
||||
|
||||
.end girq17_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq18.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ18_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq18_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<10);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq18_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ18_ID, 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq18.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ18 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq18_b0
|
||||
|
||||
#if GIRQ18_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq18_isr
|
||||
* Program address of this version of girq18_isr into JTVIC GIRQ18
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: GIRQ18 has only one source, no need for indirect jumps.
|
||||
*/
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq18_isr, code
|
||||
#else
|
||||
.section .girqs.girq18_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq18_isr
|
||||
.global girq18_isr
|
||||
.align 2
|
||||
|
||||
girq18_isr:
|
||||
J girq18_b0
|
||||
g18b0b:
|
||||
NOP
|
||||
g18end:
|
||||
.end girq18_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
106
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq19.c
Normal file
106
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq19.c
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq19.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ19_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq19_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<11);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq19_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 8);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq19.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ19 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq19_b0
|
||||
.extern girq19_b1
|
||||
.extern girq19_b2
|
||||
.extern girq19_b3
|
||||
.extern girq19_b4
|
||||
.extern girq19_b5
|
||||
.extern girq19_b6
|
||||
.extern girq19_b7
|
||||
.extern girq19_b8
|
||||
|
||||
#if GIRQ19_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq19_isr
|
||||
* Program address of this version of girq19_isr into JTVIC GIRQ19
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq19_isr, code
|
||||
#else
|
||||
.section .girqs.girq19_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq19_isr
|
||||
.global girq19_isr
|
||||
.align 2
|
||||
|
||||
girq19_isr:
|
||||
J girq19_b0
|
||||
g19b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b1a:
|
||||
J girq19_b1
|
||||
g19b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b2a:
|
||||
J girq19_b2
|
||||
g19b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b3a:
|
||||
J girq19_b3
|
||||
g19b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b4a:
|
||||
J girq19_b4
|
||||
g19b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b5a:
|
||||
J girq19_b5
|
||||
g19b5b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b6a:
|
||||
J girq19_b6
|
||||
g19b6b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b7a:
|
||||
J girq19_b7
|
||||
g19b7b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g19b8a:
|
||||
J girq19_b8
|
||||
g19b8b:
|
||||
NOP
|
||||
g19end:
|
||||
.end girq19_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq20.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ20_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq20_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<12);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq20_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 5);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq20.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ20 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq20_b0
|
||||
.extern girq20_b1
|
||||
.extern girq20_b2
|
||||
.extern girq20_b3
|
||||
.extern girq20_b4
|
||||
.extern girq20_b5
|
||||
|
||||
#if GIRQ20_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq20_isr
|
||||
* Program address of this version of girq20_isr into JTVIC GIRQ20
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq20_isr, code
|
||||
#else
|
||||
.section .girqs.girq20_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq20_isr
|
||||
.global girq20_isr
|
||||
.align 2
|
||||
|
||||
girq20_isr:
|
||||
J girq20_b0
|
||||
g20b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g20b1a:
|
||||
J girq20_b1
|
||||
g20b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g20b2a:
|
||||
J girq20_b2
|
||||
g20b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g20b3a:
|
||||
J girq20_b3
|
||||
g20b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g20b4a:
|
||||
J girq20_b4
|
||||
g20b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g20b5a:
|
||||
J girq20_b5
|
||||
g20b5b:
|
||||
NOP
|
||||
g20end:
|
||||
.end girq20_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq21.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ21_DISAGG == 0
|
||||
|
||||
/*
|
||||
* GIRQ21 is a wake peripheral logic only interrupt.
|
||||
* It's purpose is to allow the peripheral logic such as SMBus or LPC to
|
||||
* wake an service HW event without waking the EC.
|
||||
* This handler is superfluous.
|
||||
*/
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq21_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq21_b0(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq21.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ21 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq21_b0
|
||||
|
||||
#if GIRQ21_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq21_isr
|
||||
* Program address of this version of girq21_isr into JTVIC GIRQ21
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
* NOTE: GIRQ21 has no sources, it is a wake only and actually
|
||||
* does not send an interrupt message to the M14K.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq21_isr, code
|
||||
#else
|
||||
.section .girqs.girq21_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq21_isr
|
||||
.global girq21_isr
|
||||
.align 2
|
||||
girq21_isr:
|
||||
|
||||
J girq21_b0
|
||||
g21b0b:
|
||||
NOP
|
||||
g21end:
|
||||
.end girq21_isr
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
112
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq22.c
Normal file
112
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq22.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq22.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ22_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq22_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<14);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq22_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 9);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq22.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ22 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq22_b0
|
||||
.extern girq22_b1
|
||||
.extern girq22_b2
|
||||
.extern girq22_b3
|
||||
.extern girq22_b4
|
||||
.extern girq22_b5
|
||||
.extern girq22_b6
|
||||
.extern girq22_b7
|
||||
.extern girq22_b8
|
||||
.extern girq22_b9
|
||||
|
||||
#if GIRQ22_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq22_isr
|
||||
* Program address of this version of girq22_isr into JTVIC GIRQ22
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq22_isr, code
|
||||
#else
|
||||
.section .girqs.girq22_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq22_isr
|
||||
.global girq22_isr
|
||||
.align 2
|
||||
|
||||
girq22_isr:
|
||||
J girq22_b0
|
||||
g22b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b1a:
|
||||
J girq22_b1
|
||||
g22b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b2a:
|
||||
J girq22_b2
|
||||
g22b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b3a:
|
||||
J girq22_b3
|
||||
g22b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b4a:
|
||||
J girq22_b4
|
||||
g22b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b5a:
|
||||
J girq22_b5
|
||||
g22b5b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b6a:
|
||||
J girq22_b6
|
||||
g22b6b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b7a:
|
||||
J girq22_b7
|
||||
g22b7b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b8a:
|
||||
J girq22_b8
|
||||
g22b8b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g22b9a:
|
||||
J girq22_b9
|
||||
g22b9b:
|
||||
NOP
|
||||
g22end:
|
||||
.end girq22_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
255
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23.c
Normal file
255
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq23.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_bbled.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
typedef void (* GIRQ23_FPVU8)(uint8_t);
|
||||
|
||||
#if GIRQ23_DISAGG == 0
|
||||
|
||||
/*
|
||||
* FreeRTOS ISR for HW timer used as RTOS tick.
|
||||
* Implemented in MEC14xx FreeRTOS porting layer, port_asm.S
|
||||
* It save/restores CPU context and clears HW timer interrupt
|
||||
* status in JTVIC. On each timer tick it checks if any task
|
||||
* requires service. If yes then it triggers the PendSV low
|
||||
* priority software interrupt.
|
||||
* Issue:
|
||||
* When aggregated girq23_isr save CPU context but this context
|
||||
* is not the same as a FreeRTOS context save. If the RTOS timer
|
||||
* is active then girq23_isr would call vPortTickInterruptHandler
|
||||
* which uses FreeRTOS portSAVE_CONTEXT macro to save RTOS + CPU
|
||||
* context. At this point you have two context saves on the stack.
|
||||
* There is a problem:
|
||||
* vPortTickInterruptHandler does not return but exits using
|
||||
* portRESTORE_CONTEXT. This means the context save performed
|
||||
* by aggregated girq23_isr is left on the stack. Eventually
|
||||
* a stack overflow will occur.
|
||||
*
|
||||
* Solutions:
|
||||
* 1. vPortTickInterruptHandler must be modified to handle scan
|
||||
* GIRQ23 Result bits and all the respective handler. All
|
||||
* other GIRQ23 source are called as hook functions.
|
||||
*
|
||||
* 2. Do not use vPortTickInterruptHandler.
|
||||
* Modify girq23_isr here to use FreeRTOS portSAVE_CONTEXT
|
||||
* and portRESTORE_CONTEXT macros.
|
||||
* If RTOS timer is active interrupt then call vPortIncrementTick
|
||||
* as vPortTickInterruptHandler does.
|
||||
* For all other GIRQ23 sources call the respective handlers.
|
||||
*
|
||||
* NOTE: for both of the above solutions a we must either:
|
||||
* A. Service one source only resulting in GIRQ23 firing multiple
|
||||
* times if more than one source is active.
|
||||
* B. Service all active sources with RTOS Timer checked first.
|
||||
*
|
||||
* We will implement 1A with a single hook for all other sources.
|
||||
*
|
||||
*/
|
||||
|
||||
extern void vPortIncrementTick(void);
|
||||
|
||||
void girq23_dflt_handler(uint8_t inum)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].EN_CLR = (1ul << inum);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << inum);
|
||||
}
|
||||
|
||||
void __attribute__((weak)) rtos_tmr_handler(uint8_t inum)
|
||||
{
|
||||
(void) inum;
|
||||
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
|
||||
}
|
||||
|
||||
const GIRQ23_FPVU8 girq23_htable[GIRQ23_NUM_SOURCES] =
|
||||
{
|
||||
girq23_dflt_handler, /* btmr0_handler, */
|
||||
girq23_dflt_handler, /* btmr1_handler, */
|
||||
girq23_dflt_handler, /* btmr2_handler, */
|
||||
girq23_dflt_handler, /* btmr3_handler, */
|
||||
vPortIncrementTick,
|
||||
girq23_dflt_handler, /* hib_tmr_handler, */
|
||||
girq23_dflt_handler, /* week_tmr_handler, */
|
||||
girq23_dflt_handler, /* week_tmr_handler, */
|
||||
girq23_dflt_handler, /* week_tmr_handler, */
|
||||
girq23_dflt_handler, /* week_tmr_handler, */
|
||||
girq23_dflt_handler, /* week_tmr_handler, */
|
||||
girq23_dflt_handler, /* vci_handler, */
|
||||
girq23_dflt_handler, /* vci_handler, */
|
||||
girq23_dflt_handler, /* vci_handler, */
|
||||
};
|
||||
|
||||
/* Called by FreeRTOS vPortTickInterruptHandler(girq23_isr)
|
||||
* after saving FreeRTOS context
|
||||
*/
|
||||
void girq23_handler(void)
|
||||
{
|
||||
uint32_t d;
|
||||
uint8_t bitpos;
|
||||
|
||||
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
|
||||
while ( 0 != d )
|
||||
{
|
||||
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
|
||||
(girq23_htable[bitpos])(bitpos);
|
||||
d &= ~(1ul << bitpos);
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq23_isr(void)
|
||||
{
|
||||
uint32_t d;
|
||||
uint8_t bitpos;
|
||||
|
||||
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
|
||||
while ( 0 != d )
|
||||
{
|
||||
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
|
||||
(girq23_htable[bitpos])(bitpos);
|
||||
d &= ~(1ul << bitpos);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
|
||||
/* 16-bit Basic Timer 0 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b0(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0);
|
||||
}
|
||||
|
||||
/* 16-bit Basic Timer 1 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);
|
||||
}
|
||||
|
||||
/* 16-bit Basic Timer 2 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);
|
||||
}
|
||||
|
||||
/* 16-bit Basic Timer 3 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);
|
||||
}
|
||||
|
||||
/* RTOS Timer */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b4(void)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
|
||||
|
||||
}
|
||||
|
||||
/* Hibernation Timer */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);
|
||||
}
|
||||
|
||||
/* Week Alarm */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);
|
||||
}
|
||||
|
||||
/* Sub-Week Alarm */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);
|
||||
}
|
||||
|
||||
/* Week Alarm One Second */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);
|
||||
}
|
||||
|
||||
/* Week Alarm Sub Second */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);
|
||||
}
|
||||
|
||||
/* Week Alarm System Power Present Pin */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);
|
||||
}
|
||||
|
||||
/* VCI OVRD Input */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);
|
||||
}
|
||||
|
||||
/* VCI IN0 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b12(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);
|
||||
}
|
||||
|
||||
/* VCI IN1 */
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq23_b13(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* end girq23.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ23 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq23_b0
|
||||
.extern girq23_b1
|
||||
.extern girq23_b2
|
||||
.extern girq23_b3
|
||||
.extern girq23_b4
|
||||
.extern girq23_b5
|
||||
.extern girq23_b6
|
||||
.extern girq23_b7
|
||||
.extern girq23_b8
|
||||
.extern girq23_b9
|
||||
.extern girq23_b10
|
||||
.extern girq23_b11
|
||||
.extern girq23_b12
|
||||
.extern girq23_b13
|
||||
|
||||
#if GIRQ23_DISAGG != 0
|
||||
|
||||
/*
|
||||
* FreeRTOS Handler for MEC14xx RTOS Timer
|
||||
* implemented in the porting layer.
|
||||
*/
|
||||
.extern vPortTickInterruptHandler
|
||||
|
||||
/*
|
||||
* Disaggregated girq23_isr
|
||||
* Program address of this version of girq23_isr into JTVIC GIRQ23
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq23_isr, code
|
||||
#else
|
||||
.section .girqs.girq23_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq23_isr
|
||||
.global girq23_isr
|
||||
.align 2
|
||||
|
||||
girq23_isr:
|
||||
|
||||
J girq23_b0
|
||||
g23b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b1a:
|
||||
J girq23_b1
|
||||
g23b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b2a:
|
||||
J girq23_b2
|
||||
g23b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b3a:
|
||||
J girq23_b3
|
||||
g23b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b4a:
|
||||
J girq23_b4
|
||||
g23b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b5a:
|
||||
J girq23_b5
|
||||
g23b5b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b6a:
|
||||
J girq23_b6
|
||||
g23b6b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b7a:
|
||||
J girq23_b7
|
||||
g23b7b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b8a:
|
||||
J girq23_b8
|
||||
g23b8b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b9a:
|
||||
J girq23_b9
|
||||
g23b9b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b10a:
|
||||
J girq23_b10
|
||||
g23b10b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b11a:
|
||||
J girq23_b11
|
||||
g23b11b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b12a:
|
||||
J girq23_b12
|
||||
g23b12b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g23b13a:
|
||||
J girq23_b13
|
||||
g23b13b:
|
||||
NOP
|
||||
g23end:
|
||||
.end girq23_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
172
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24.c
Normal file
172
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24.c
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq24.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_bbled.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
typedef void (* GIRQ24_FPVU8)(uint8_t);
|
||||
|
||||
|
||||
/* MIPS M14K internal counter is connected to GIRQ24 bit[0]
|
||||
* It is a simple counter which fires an interrupt when its
|
||||
* count value is equal to a match value.
|
||||
*
|
||||
*/
|
||||
|
||||
#if GIRQ24_DISAGG == 0
|
||||
|
||||
|
||||
void girq24_dflt_handler(uint8_t inum)
|
||||
{
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);
|
||||
}
|
||||
|
||||
void __attribute__((weak)) m14k_counter_handler(uint8_t inum)
|
||||
{
|
||||
uint32_t r;
|
||||
|
||||
(void) inum;
|
||||
|
||||
r = _CP0_GET_COUNT();
|
||||
r += (M14K_TIMER_COMPARE);
|
||||
/* Write of CP0.Compare clears status in M14K */
|
||||
_CP0_SET_COUNT(r);
|
||||
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO - FreeRTOS M14K Software Interrupt 0 handler
|
||||
* is vPortYieldISR in port_asm.S
|
||||
* vPortYieldISR was designed to be entered directly by the
|
||||
* CPU not via a higher level ISR handler.
|
||||
* One work-around is to modify vPortYieldISR to do the work
|
||||
* of girq24_handler below. It must determine which GIRQ24 source
|
||||
* was active: M14K counter, SoftIRQ0, or SoftIRQ1.
|
||||
*/
|
||||
void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)
|
||||
{
|
||||
(void) inum;
|
||||
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);
|
||||
|
||||
}
|
||||
|
||||
void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)
|
||||
{
|
||||
(void) inum;
|
||||
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);
|
||||
|
||||
}
|
||||
|
||||
void girq24_b_0_2( void )
|
||||
{
|
||||
uint32_t d;
|
||||
|
||||
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
|
||||
|
||||
if ( d & (1ul << 0) )
|
||||
{
|
||||
m14k_counter_handler(0);
|
||||
}
|
||||
|
||||
if ( d & (1ul << 2) )
|
||||
{
|
||||
m14k_soft_irq1(2);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =
|
||||
{
|
||||
m14k_counter_handler, /* m14k_counter_handler, */
|
||||
m14k_soft_irq0, /* m14k_soft_irq0, */
|
||||
m14k_soft_irq1, /* m14k_soft_irq1 */
|
||||
};
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq24_isr(void)
|
||||
{
|
||||
uint32_t d;
|
||||
uint8_t bitpos;
|
||||
|
||||
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
|
||||
while ( 0 != d )
|
||||
{
|
||||
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
|
||||
(girq24_htable[bitpos])(bitpos);
|
||||
d &= ~(1ul << bitpos);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq24_b0(void)
|
||||
{
|
||||
uint32_t r;
|
||||
|
||||
r = _CP0_GET_COUNT();
|
||||
r += (M14K_TIMER_COMPARE);
|
||||
_CP0_SET_COUNT(r);
|
||||
|
||||
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq24_b1(void)
|
||||
{
|
||||
|
||||
_CP0_BIC_CAUSE(0x100ul);
|
||||
|
||||
jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq24_b2(void)
|
||||
{
|
||||
|
||||
_CP0_BIC_CAUSE(0x200ul);
|
||||
|
||||
jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq24.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ24 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq24_b0
|
||||
.extern girq24_b1
|
||||
.extern girq24_b2
|
||||
|
||||
#if GIRQ24_DISAGG != 0
|
||||
|
||||
/*
|
||||
* FreeRTOS Handler for MIPS M14K Software Interrupt 0
|
||||
* implemented in the porting layer.
|
||||
*/
|
||||
.extern vPortYieldISR
|
||||
|
||||
/*
|
||||
* Disaggregated girq24_isr
|
||||
* Program address of this version of girq24_isr into JTVIC GIRQ24
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq24_isr, code
|
||||
#else
|
||||
.section .girqs.girq24_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq24_isr
|
||||
.global girq24_isr
|
||||
.align 2
|
||||
|
||||
girq24_isr:
|
||||
J girq24_b0
|
||||
g24b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g24b1a:
|
||||
J vPortYieldISR /* girq24_b1 */
|
||||
g24b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g24b2a:
|
||||
J girq24_b2
|
||||
g24b2b:
|
||||
NOP
|
||||
g24end:
|
||||
.end girq24_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
220
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq25.c
Normal file
220
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq25.c
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq25.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ25_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq25_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<15);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 9);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 10);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 11);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b12(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 12);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b13(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 13);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b14(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 14);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b15(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 15);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b16(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 16);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b17(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 17);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b18(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 18);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b19(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b20(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 20);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b21(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 21);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b22(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 22);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b23(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 23);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b24(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 24);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b25(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 25);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b26(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 26);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq25_b27(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq25.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ25 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq25_b0
|
||||
.extern girq25_b1
|
||||
.extern girq25_b2
|
||||
.extern girq25_b3
|
||||
.extern girq25_b4
|
||||
.extern girq25_b5
|
||||
.extern girq25_b6
|
||||
.extern girq25_b7
|
||||
.extern girq25_b8
|
||||
.extern girq25_b9
|
||||
.extern girq25_b10
|
||||
.extern girq25_b11
|
||||
.extern girq25_b12
|
||||
.extern girq25_b13
|
||||
.extern girq25_b14
|
||||
.extern girq25_b15
|
||||
.extern girq25_b16
|
||||
.extern girq25_b17
|
||||
.extern girq25_b18
|
||||
.extern girq25_b19
|
||||
.extern girq25_b20
|
||||
.extern girq25_b21
|
||||
.extern girq25_b22
|
||||
.extern girq25_b23
|
||||
.extern girq25_b24
|
||||
.extern girq25_b25
|
||||
.extern girq25_b26
|
||||
.extern girq25_b27
|
||||
|
||||
#if GIRQ25_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq25_isr
|
||||
* Program address of this version of girq25_isr into JTVIC GIRQ25
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq25_isr, code
|
||||
#else
|
||||
.section .girqs.girq25_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq25_isr
|
||||
.global girq25_isr
|
||||
.align 2
|
||||
|
||||
girq25_isr:
|
||||
J girq25_b0
|
||||
g25b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b1a:
|
||||
J girq25_b1
|
||||
g25b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b2a:
|
||||
J girq25_b2
|
||||
g25b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b3a:
|
||||
J girq25_b3
|
||||
g25b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b4a:
|
||||
J girq25_b4
|
||||
g25b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b5a:
|
||||
J girq25_b5
|
||||
g25b5b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b6a:
|
||||
J girq25_b6
|
||||
g25b6b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b7a:
|
||||
J girq25_b7
|
||||
g25b7b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b8a:
|
||||
J girq25_b8
|
||||
g25b8b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b9a:
|
||||
J girq25_b9
|
||||
g25b9b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b10a:
|
||||
J girq25_b10
|
||||
g25b10b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b11a:
|
||||
J girq25_b11
|
||||
g25b11b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b12a:
|
||||
J girq25_b12
|
||||
g25b12b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b13a:
|
||||
J girq25_b13
|
||||
g25b13b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b14a:
|
||||
J girq25_b14
|
||||
g25b14b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b15a:
|
||||
J girq25_b15
|
||||
g25b15b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b16a:
|
||||
J girq25_b16
|
||||
g25b16b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b17a:
|
||||
J girq25_b17
|
||||
g25b17b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b18a:
|
||||
J girq25_b18
|
||||
g25b18b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b19a:
|
||||
J girq25_b19
|
||||
g25b19b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b20a:
|
||||
J girq25_b20
|
||||
g25b20b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b21a:
|
||||
J girq25_b21
|
||||
g25b21b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b22a:
|
||||
J girq25_b22
|
||||
g25b22b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b23a:
|
||||
J girq25_b23
|
||||
g25b23b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b24a:
|
||||
J girq25_b24
|
||||
g25b24b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b25a:
|
||||
J girq25_b25
|
||||
g25b25b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b26a:
|
||||
J girq25_b26
|
||||
g25b26b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g25b27a:
|
||||
J girq25_b27
|
||||
g25b27b:
|
||||
NOP
|
||||
g25end:
|
||||
.end girq25_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
125
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq26.c
Normal file
125
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq26.c
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/*****************************************************************************
|
||||
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girq26.c
|
||||
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
|
||||
*/
|
||||
/** @defgroup MEC14xx ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
#if GIRQ26_DISAGG == 0
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
|
||||
girq26_isr(void)
|
||||
{
|
||||
JTVIC_GROUP_EN_CLR->w = (1ul<<16);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b0(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 0);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b1(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 1);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b2(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 2);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b3(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 3);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b4(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 4);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b5(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 5);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b6(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 6);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b7(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 7);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b8(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 8);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b9(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 9);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b10(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 10);
|
||||
}
|
||||
|
||||
void __attribute__((weak, interrupt, nomips16))
|
||||
girq26_b11(void)
|
||||
{
|
||||
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 11);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* end girq26.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
Copyright (C) 2014 Microchip Inc.
|
||||
All rights reserved
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifdef __XC32
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
#else
|
||||
#include "Regs.S"
|
||||
#endif
|
||||
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* MEC14xx GIRQ26 Disaggregated Vector Jump table
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.extern girq26_b0
|
||||
.extern girq26_b1
|
||||
.extern girq26_b2
|
||||
.extern girq26_b3
|
||||
.extern girq26_b4
|
||||
.extern girq26_b5
|
||||
.extern girq26_b6
|
||||
.extern girq26_b7
|
||||
.extern girq26_b8
|
||||
.extern girq26_b9
|
||||
.extern girq26_b10
|
||||
.extern girq26_b11
|
||||
|
||||
#if GIRQ26_DISAGG != 0
|
||||
|
||||
/*
|
||||
* Disaggregated girq26_isr
|
||||
* Program address of this version of girq26_isr into JTVIC GIRQ26
|
||||
* Aggregator Control register with bit[0] = 1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: All the additional labels surrounding every instruction are
|
||||
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
|
||||
*/
|
||||
|
||||
.insn
|
||||
#ifdef __XC32
|
||||
.section .girqs.girq26_isr, code
|
||||
#else
|
||||
.section .girqs.girq26_isr,"x"
|
||||
#endif
|
||||
.set nomips16
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
.ent girq26_isr
|
||||
.global girq26_isr
|
||||
.align 2
|
||||
|
||||
girq26_isr:
|
||||
J girq26_b0
|
||||
g26b0b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b1a:
|
||||
J girq26_b1
|
||||
g26b1b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b2a:
|
||||
J girq26_b2
|
||||
g26b2b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b3a:
|
||||
J girq26_b3
|
||||
g26b3b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b4a:
|
||||
J girq26_b4
|
||||
g26b4b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b5a:
|
||||
J girq26_b5
|
||||
g26b5b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b6a:
|
||||
J girq26_b6
|
||||
g26b6b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b7a:
|
||||
J girq26_b7
|
||||
g26b7b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b8a:
|
||||
J girq26_b8
|
||||
g26b8b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b9a:
|
||||
J girq26_b9
|
||||
g26b9b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b10a:
|
||||
J girq26_b10
|
||||
g26b10b:
|
||||
NOP
|
||||
|
||||
.align 2
|
||||
g26b11a:
|
||||
J girq26_b11
|
||||
g26b11b:
|
||||
NOP
|
||||
g26end:
|
||||
.end girq26_isr
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
225
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girqs.c
Normal file
225
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girqs.c
Normal file
|
|
@ -0,0 +1,225 @@
|
|||
/*****************************************************************************
|
||||
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
/** @file girqs.c
|
||||
*MEC14xx JTVIC default configuration table
|
||||
*/
|
||||
/** @defgroup MEC140x ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "appcfg.h"
|
||||
#include "platform.h"
|
||||
#include "MEC14xx/mec14xx.h"
|
||||
#include "MEC14xx/mec14xx_girqm.h"
|
||||
#include "MEC14xx/mec14xx_girqs.h"
|
||||
#include "MEC14xx/mec14xx_gpio.h"
|
||||
#include "MEC14xx/mec14xx_trace_func.h"
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Service Routine prototypes for each GIRQn
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Table for initializing MEC14xx JTVIC.
|
||||
* Each GIRQn handler's address must be programmed into
|
||||
* respective JTVIC register.
|
||||
*/
|
||||
const JTVIC_CFG dflt_ih_table[MEC14xx_NUM_JTVIC_INTS] = {
|
||||
{
|
||||
(uint32_t)girq08_isr,
|
||||
{
|
||||
(GIRQ08_PRI_A),
|
||||
(GIRQ08_PRI_B),
|
||||
(GIRQ08_PRI_C),
|
||||
(GIRQ08_PRI_D)
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq09_isr,
|
||||
{
|
||||
(GIRQ09_PRI_A),
|
||||
(GIRQ09_PRI_B),
|
||||
(GIRQ09_PRI_C),
|
||||
(GIRQ09_PRI_D)
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq10_isr,
|
||||
{
|
||||
(GIRQ10_PRI_A),
|
||||
(GIRQ10_PRI_B),
|
||||
(GIRQ10_PRI_C),
|
||||
(GIRQ10_PRI_D)
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq11_isr,
|
||||
{
|
||||
GIRQ11_PRI_A,
|
||||
GIRQ11_PRI_B,
|
||||
GIRQ11_PRI_C,
|
||||
GIRQ11_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq12_isr,
|
||||
{
|
||||
GIRQ12_PRI_A,
|
||||
GIRQ12_PRI_B,
|
||||
GIRQ12_PRI_C,
|
||||
GIRQ12_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq13_isr,
|
||||
{
|
||||
GIRQ13_PRI_A,
|
||||
GIRQ13_PRI_B,
|
||||
GIRQ13_PRI_C,
|
||||
GIRQ13_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq14_isr,
|
||||
{
|
||||
GIRQ14_PRI_A,
|
||||
GIRQ14_PRI_B,
|
||||
GIRQ14_PRI_C,
|
||||
GIRQ14_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq15_isr,
|
||||
{
|
||||
GIRQ15_PRI_A,
|
||||
GIRQ15_PRI_B,
|
||||
GIRQ15_PRI_C,
|
||||
GIRQ15_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq16_isr,
|
||||
{
|
||||
GIRQ16_PRI_A,
|
||||
GIRQ16_PRI_B,
|
||||
GIRQ16_PRI_C,
|
||||
GIRQ16_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq17_isr,
|
||||
{
|
||||
GIRQ17_PRI_A,
|
||||
GIRQ17_PRI_B,
|
||||
GIRQ17_PRI_C,
|
||||
GIRQ17_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq18_isr,
|
||||
{
|
||||
GIRQ18_PRI_A,
|
||||
GIRQ18_PRI_B,
|
||||
GIRQ18_PRI_C,
|
||||
GIRQ18_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq19_isr,
|
||||
{
|
||||
GIRQ19_PRI_A,
|
||||
GIRQ19_PRI_B,
|
||||
GIRQ19_PRI_C,
|
||||
GIRQ19_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq20_isr,
|
||||
{
|
||||
GIRQ20_PRI_A,
|
||||
GIRQ20_PRI_B,
|
||||
GIRQ20_PRI_C,
|
||||
GIRQ20_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq21_isr,
|
||||
{
|
||||
GIRQ21_PRI_A,
|
||||
GIRQ21_PRI_B,
|
||||
GIRQ21_PRI_C,
|
||||
GIRQ21_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq22_isr,
|
||||
{
|
||||
GIRQ22_PRI_A,
|
||||
GIRQ22_PRI_B,
|
||||
GIRQ22_PRI_C,
|
||||
GIRQ22_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq23_isr,
|
||||
{
|
||||
GIRQ23_PRI_A,
|
||||
GIRQ23_PRI_B,
|
||||
GIRQ23_PRI_C,
|
||||
GIRQ23_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq24_isr,
|
||||
{
|
||||
GIRQ24_PRI_A,
|
||||
GIRQ24_PRI_B,
|
||||
GIRQ24_PRI_C,
|
||||
GIRQ24_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq25_isr,
|
||||
{
|
||||
GIRQ25_PRI_A,
|
||||
GIRQ25_PRI_B,
|
||||
GIRQ25_PRI_C,
|
||||
GIRQ25_PRI_D
|
||||
}
|
||||
},
|
||||
{
|
||||
(uint32_t)girq26_isr,
|
||||
{
|
||||
GIRQ26_PRI_A,
|
||||
GIRQ26_PRI_B,
|
||||
GIRQ26_PRI_C,
|
||||
GIRQ26_PRI_D
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/* end girqs.c */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue