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Add PIC32MEC14xx port and demo application.

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This commit is contained in:
Richard Barry 2015-09-12 20:47:59 +00:00
parent f19497c3d6
commit a29dc8d6c6
103 changed files with 49682 additions and 6 deletions
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97
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception.c Normal file
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file general_exception.c
*MEC14xx General Exception Handler
*/
/** @defgroup MEC14xx Exceptions
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_trace_inline.h"
typedef struct gen_except_capture
{
uint32_t stack_ptr;
uint32_t cp0_status;
uint32_t cp0_cause;
uint32_t cp0_epc;
uint32_t cp0_error_epc;
uint32_t cp0_nexc;
uint32_t cp0_nepc;
uint32_t cp0_badvaddr;
uint32_t ahb_err;
} GEN_EXCEPT_CAPTURE;
GEN_EXCEPT_CAPTURE gexc_cap;
void
__attribute__((nomips16, noreturn)) _general_exception_handler (void)
{
/*
* MEC14xx Application General Exception handler
*/
uint32_t e;
/* Get current Stack Pointer. Note: this is not SP at
* exception. XC32 wraps _general_exception_handler in
* assembly code which saves state resulting is a
* modified SP. Wrapper allocates 88 bytes for context
* save. Original SP = SPcurrent + 88.
*/
__asm__ __volatile (
"move %0,$sp \n\t"
"nop \n\t"
:"=r" (e)
::);
gexc_cap.stack_ptr = e;
gexc_cap.cp0_status = _CP0_GET_STATUS();
gexc_cap.cp0_cause = _CP0_GET_CAUSE();
gexc_cap.cp0_epc = _CP0_GET_EPC();
gexc_cap.cp0_error_epc = _CP0_GET_ERROREPC();
gexc_cap.cp0_nexc = _CP0_GET_NESTEDEXC();
gexc_cap.cp0_nepc = _CP0_GET_NESTEDEPC();
gexc_cap.cp0_badvaddr = _CP0_GET_BADVADDR();
trace0(0, AP3GENEXCEPT, 0, "Application General Exception Handler (BEV=0)");
TRACE11(601, AP3GENEXCEPT, 0, "Current SP = 0x%08x",gexc_cap.stack_ptr);
TRACE11(602, AP3GENEXCEPT, 0, "CP0 STATUS = 0x%08x",gexc_cap.cp0_status);
TRACE11(603, AP3GENEXCEPT, 0, "CP0 CAUSE = 0x%08x",gexc_cap.cp0_cause);
TRACE11(604, AP3GENEXCEPT, 0, "CP0 EPC = 0x%08x",gexc_cap.cp0_epc);
TRACE11(605, AP3GENEXCEPT, 0, "CP0 ERROREPC = 0x%08x",gexc_cap.cp0_error_epc);
TRACE11(606, AP3GENEXCEPT, 0, "CP0 NEXC = 0x%08x",gexc_cap.cp0_nexc);
TRACE11(607, AP3GENEXCEPT, 0, "CP0 NEPC = 0x%08x",gexc_cap.cp0_nepc);
TRACE11(608, AP3GENEXCEPT, 0, "CP0 BADVADDR = 0x%08x",gexc_cap.cp0_badvaddr);
for (;;) {
__asm__ __volatile ("%(ssnop%)" : :);
}
}
/* end general_exception.c */
/** @}
*/

128
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S Normal file
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/*********************************************************************
*
* General Exception
*
*********************************************************************
* Filename: general-exception.S
*
* Processor: PIC32
*
* Compiler: MPLAB XC32 v1.00
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#include <xc.h>
#ifdef __LIBBUILD__
.file 1 "general-exception.S"
.loc 1 0
#endif
###################
# Default general exception handler
###################
.extern _general_exception_handler
.section .text.general_exception, code
.set noreorder
.set noat
.set nomips16
.globl _general_exception_context
.ent _general_exception_context
_general_exception_context:
# Save off the non-callee saved registers that may get mucked with
addiu sp, sp, -88
sw $1, 4(sp)
sw v0, 8(sp)
sw v1, 12(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw t0, 32(sp)
sw t1, 36(sp)
sw t2, 40(sp)
sw t3, 44(sp)
sw t4, 48(sp)
sw t5, 52(sp)
sw t6, 56(sp)
sw t7, 60(sp)
sw t8, 64(sp)
sw t9, 68(sp)
sw ra, 72(sp)
mflo t0
sw t0, 76(sp)
mfhi t0
sw t0, 80(sp)
la k0,_general_exception_handler
nop
# Pass Cause and Status to the handler function
mfc0 a0, _CP0_CAUSE
mfc0 a1, _CP0_STATUS
jalr k0
nop
lw t0, 80(sp)
mthi t0
lw t0, 76(sp)
mtlo t0
lw $1, 4(sp)
lw v0, 8(sp)
lw v1, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw t0, 32(sp)
lw t1, 36(sp)
lw t2, 40(sp)
lw t3, 44(sp)
lw t4, 48(sp)
lw t5, 52(sp)
lw t6, 56(sp)
lw t7, 60(sp)
lw t8, 64(sp)
lw t9, 68(sp)
lw ra, 72(sp)
addiu sp, sp, 88
ehb
eret
.end _general_exception_context

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq08.c Normal file
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq08.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ08_DISAGG == 0
/*
* Aggregated mode handler, must handle all enabled
* GIRQ08 sources.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq08_isr( void )
{
JTVIC_GROUP_EN_CLR->w = (1ul<<0);
}
#else
/*
* Disaggregated GIRQ08 subhandlers, one for each
* source. Called by assembly language wrapper.
*/
void __attribute__((weak, interrupt, nomips16))
girq08_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 18);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 20);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 21);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22);
}
#endif
/* end girq08.c */
/** @}
*/

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq08d.S Normal file
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ08 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq08_b0
.extern girq08_b1
.extern girq08_b2
.extern girq08_b3
.extern girq08_b4
.extern girq08_b5
.extern girq08_b6
.extern girq08_b7
.extern girq08_b8
.extern girq08_b9
.extern girq08_b10
.extern girq08_b11
.extern girq08_b12
.extern girq08_b13
.extern girq08_b14
.extern girq08_b15
.extern girq08_b16
.extern girq08_b17
.extern girq08_b18
.extern girq08_b19
.extern girq08_b20
.extern girq08_b21
.extern girq08_b22
#if GIRQ08_DISAGG != 0
/*
* Disaggregated girq08v
* Program address of this version of girq23v into JTVIC GIRQ08
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq08_isr,code
#else
.section .girqs.girq08_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.global girq08_isr
.ent girq08_isr
.align 2
girq08_isr:
J girq08_b0
NOP
.align 2
J girq08_b1
NOP
.align 2
J girq08_b2
NOP
.align 2
J girq08_b3
NOP
.align 2
J girq08_b4
NOP
.align 2
J girq08_b5
NOP
.align 2
J girq08_b6
NOP
.align 2
J girq08_b7
NOP
.align 2
J girq08_b8
NOP
.align 2
J girq08_b9
NOP
.align 2
J girq08_b10
NOP
.align 2
J girq08_b11
NOP
.align 2
J girq08_b12
NOP
.align 2
J girq08_b13
NOP
.align 2
J girq08_b14
NOP
.align 2
J girq08_b15
NOP
.align 2
J girq08_b16
NOP
.align 2
J girq08_b17
NOP
.align 2
J girq08_b18
NOP
.align 2
J girq08_b19
NOP
.align 2
J girq08_b20
NOP
.align 2
J girq08_b21
NOP
.align 2
J girq08_b22
NOP
.end girq08_isr
/******************************************************************/
#endif

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq09.c Normal file
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq09.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ09_DISAGG == 0
/*
* Aggregated mode handler, must handle all enabled
* GIRQ08 sources.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq09_isr( void )
{
JTVIC_GROUP_EN_CLR->w = (1ul<<1);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq09_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 0);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b1(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 1);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b2(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 2);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 2);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b3(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 3);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 3);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 4);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 4);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b5(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 5);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 5);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b6(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 6);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 6);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b7(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 7);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 7);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b8(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 8);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 8);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b9(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 9);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 9);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b10(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 10);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 10);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b11(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 11);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 11);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b12(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 12);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 12);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b13(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 13);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 13);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b14(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 14);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 14);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b15(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 15);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 15);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b16(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 16);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 16);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b17(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 17);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 17);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b18(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 18);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 18);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b19(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 19);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 19);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b20(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 20);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 20);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b21(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 21);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 21);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b22(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 22);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 22);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b23(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 23);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 23);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b24(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 24);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 24);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b25(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 25);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 25);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b26(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 26);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 26);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b27(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 27);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 27);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b28(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 28);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 28);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b29(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 29);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 29);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b30(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 30);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 30);
}
#endif
/* end girq09.c */
/** @}
*/

209
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ09 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq09_b0
.extern girq09_b1
.extern girq09_b2
.extern girq09_b3
.extern girq09_b4
.extern girq09_b5
.extern girq09_b6
.extern girq09_b7
.extern girq09_b8
.extern girq09_b9
.extern girq09_b10
.extern girq09_b11
.extern girq09_b12
.extern girq09_b13
.extern girq09_b14
.extern girq09_b15
.extern girq09_b16
.extern girq09_b17
.extern girq09_b18
.extern girq09_b19
.extern girq09_b20
.extern girq09_b21
.extern girq09_b22
.extern girq09_b23
.extern girq09_b24
.extern girq09_b25
.extern girq09_b26
.extern girq09_b27
.extern girq09_b28
.extern girq09_b29
.extern girq09_b30
#if GIRQ09_DISAGG != 0
/*
* Disaggregated girq09v
* Program address of this version of girq23v into JTVIC GIRQ09
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq09_isr, code
#else
.section .girqs.girq09_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.global girq09_isr
.ent girq09_isr
.align 2
girq09_isr:
J girq09_b0
NOP
.align 2
J girq09_b1
NOP
.align 2
J girq09_b2
NOP
.align 2
J girq09_b3
NOP
.align 2
J girq09_b4
NOP
.align 2
J girq09_b5
NOP
.align 2
J girq09_b6
NOP
.align 2
J girq09_b7
NOP
.align 2
J girq09_b8
NOP
.align 2
J girq09_b9
NOP
.align 2
J girq09_b10
NOP
.align 2
J girq09_b11
NOP
.align 2
J girq09_b12
NOP
.align 2
J girq09_b13
NOP
.align 2
J girq09_b14
NOP
.align 2
J girq09_b15
NOP
.align 2
J girq09_b16
NOP
.align 2
J girq09_b17
NOP
.align 2
J girq09_b18
NOP
.align 2
J girq09_b19
NOP
.align 2
J girq09_b20
NOP
.align 2
J girq09_b21
NOP
.align 2
J girq09_b22
NOP
.align 2
J girq09_b23
NOP
.align 2
J girq09_b24
NOP
.align 2
J girq09_b25
NOP
.align 2
J girq09_b26
NOP
.align 2
J girq09_b27
NOP
.align 2
J girq09_b28
NOP
.align 2
J girq09_b29
NOP
.align 2
J girq09_b30
NOP
.end girq09_isr
#endif
/******************************************************************/

197
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq10.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ10_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq10_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<2);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq10_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);
}
#endif
/* end girq10.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ10 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq10_b0
.extern girq10_b1
.extern girq10_b2
.extern girq10_b3
.extern girq10_b4
.extern girq10_b5
.extern girq10_b6
.extern girq10_b7
.extern girq10_b8
.extern girq10_b9
.extern girq10_b10
.extern girq10_b11
.extern girq10_b12
.extern girq10_b13
.extern girq10_b14
.extern girq10_b15
.extern girq10_b16
.extern girq10_b17
.extern girq10_b18
.extern girq10_b19
.extern girq10_b20
.extern girq10_b21
.extern girq10_b22
.extern girq10_b23
#if GIRQ10_DISAGG != 0
/*
* Disaggregated girq10_isr
* Program address of this version of girq23_isr into JTVIC GIRQ09
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq10_isr, code
#else
.section .girqs.girq10_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq10_isr
.global girq10_isr
.align 2
girq10_isr:
J girq10_b0
NOP
.align 2
J girq10_b1
NOP
.align 2
J girq10_b2
NOP
.align 2
J girq10_b3
NOP
.align 2
J girq10_b4
NOP
.align 2
J girq10_b5
NOP
.align 2
J girq10_b6
NOP
.align 2
J girq10_b7
NOP
.align 2
J girq10_b8
NOP
.align 2
J girq10_b9
NOP
.align 2
J girq10_b10
NOP
.align 2
J girq10_b11
NOP
.align 2
J girq10_b12
NOP
.align 2
J girq10_b13
NOP
.align 2
J girq10_b14
NOP
.align 2
J girq10_b15
NOP
.align 2
J girq10_b16
NOP
.align 2
J girq10_b17
NOP
.align 2
J girq10_b18
NOP
.align 2
J girq10_b19
NOP
.align 2
J girq10_b20
NOP
.align 2
J girq10_b21
NOP
.align 2
J girq10_b22
NOP
.align 2
J girq10_b23
NOP
.end girq10_isr
#endif
/******************************************************************/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq11.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ11_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq11_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<3);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq11_b0(void)
{
return;
}
void __attribute__((weak, interrupt, nomips16))
girq11_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 1, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 2, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 3, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 4, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 5, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 6, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 7, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 9, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 10, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 11, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 12, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 13, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 14, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 15, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 16, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 17, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 18, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 19, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 20, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 21, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 22, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 23, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b24(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 24, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b25(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 25, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b26(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 26, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b27(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 27, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b28(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 28, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b29(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 29, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b30(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 30, JTVIC_CLR_SRC);
}
#endif
/* end girq11.c */
/** @}
*/

211
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ11 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq11_b0
.extern girq11_b1
.extern girq11_b2
.extern girq11_b3
.extern girq11_b4
.extern girq11_b5
.extern girq11_b6
.extern girq11_b7
.extern girq11_b8
.extern girq11_b9
.extern girq11_b10
.extern girq11_b11
.extern girq11_b12
.extern girq11_b13
.extern girq11_b14
.extern girq11_b15
.extern girq11_b16
.extern girq11_b17
.extern girq11_b18
.extern girq11_b19
.extern girq11_b20
.extern girq11_b21
.extern girq11_b22
.extern girq11_b23
.extern girq11_b24
.extern girq11_b25
.extern girq11_b26
.extern girq11_b27
.extern girq11_b28
.extern girq11_b30
#if GIRQ11_DISAGG != 0
/*
* Disaggregated girq11_isr
* Program address of this version of girq23v into JTVIC GIRQ11
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq11_isr, code
#else
.section .girqs.girq11_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq11_isr
.global girq11_isr
.align 2
girq11_isr:
#if 1
J girq11_b0
NOP
.align 2
J girq11_b1
NOP
.align 2
J girq11_b2
NOP
.align 2
J girq11_b3
NOP
.align 2
J girq11_b4
NOP
.align 2
J girq11_b5
NOP
.align 2
J girq11_b6
NOP
.align 2
J girq11_b7
NOP
.align 2
J girq11_b8
NOP
.align 2
J girq11_b9
NOP
.align 2
J girq11_b10
NOP
.align 2
J girq11_b11
NOP
.align 2
J girq11_b12
NOP
.align 2
J girq11_b13
NOP
.align 2
J girq11_b14
NOP
.align 2
J girq11_b15
NOP
.align 2
J girq11_b16
NOP
.align 2
J girq11_b17
NOP
.align 2
J girq11_b18
NOP
.align 2
J girq11_b19
NOP
.align 2
J girq11_b20
NOP
.align 2
J girq11_b21
NOP
.align 2
J girq11_b22
NOP
.align 2
J girq11_b23
NOP
.align 2
J girq11_b24
NOP
.align 2
J girq11_b25
NOP
.align 2
J girq11_b26
NOP
.align 2
J girq11_b27
NOP
.align 2
J girq11_b28
NOP
.align 2
J girq11_b29
NOP
.align 2
J girq11_b30
NOP
.end girq11_isr
#else
gen_jump_table 11,0,30
#endif
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq12.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ12_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq12_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<4);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq12_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq12_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq12_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2);
}
#endif
/* end girq12.c */
/** @}
*/

68
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ12 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq12_b0
.extern girq12_b1
.extern girq12_b2
#if GIRQ12_DISAGG != 0
/*
* Disaggregated girq12_isr
* Program address of this version of girq23v into JTVIC GIRQ12
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq12_isr, code
#else
.section .girqs.girq12_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq12_isr
.global girq12_isr
.align 2
girq12_isr:
J girq12_b0
NOP
.align 2
J girq12_b1
NOP
.align 2
J girq12_b2
NOP
.end girq12_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq13.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ13_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq13_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<5);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq13_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 6);
}
#endif
/* end girq13.c */
/** @}
*/

88
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ13 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq13_b0
.extern girq13_b1
.extern girq13_b2
.extern girq13_b3
.extern girq13_b4
.extern girq13_b5
.extern girq13_b6
#if GIRQ13_DISAGG != 0
/*
* Disaggregated girq13_isr
* Program address of this version of girq23v into JTVIC GIRQ13
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq13_isr, code
#else
.section .girqs.girq13_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq13_isr
.global girq13_isr
.align 2
girq13_isr:
J girq13_b0
NOP
.align 2
J girq13_b1
NOP
.align 2
J girq13_b2
NOP
.align 2
J girq13_b3
NOP
.align 2
J girq13_b4
NOP
.align 2
J girq13_b5
NOP
.align 2
J girq13_b6
NOP
.end girq13_isr
#endif
/******************************************************************/

88
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq14.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ14_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq14_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<6);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq14_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5);
}
#endif
/* end girq14.c */
/** @}
*/

83
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ14 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq14_b0
.extern girq14_b1
.extern girq14_b2
.extern girq14_b3
.extern girq14_b4
.extern girq14_b5
#if GIRQ14_DISAGG != 0
/*
* Disaggregated girq14_isr
* Program address of this version of girq14_isr into JTVIC GIRQ14
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq14_isr, code
#else
.section .girqs.girq14_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq14_isr
.global girq14_isr
.align 2
girq14_isr:
J girq14_b0
NOP
.align 2
J girq14_b1
NOP
.align 2
J girq14_b2
NOP
.align 2
J girq14_b3
NOP
.align 2
J girq14_b4
NOP
.align 2
J girq14_b5
NOP
.end girq14_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq15.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ15_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq15_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<7);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq15_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 18);
}
#endif
/* end girq15.c */
/** @}
*/

147
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ15 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq15_b0
.extern girq15_b1
.extern girq15_b2
.extern girq15_b3
.extern girq15_b4
.extern girq15_b5
.extern girq15_b6
.extern girq15_b7
.extern girq15_b8
.extern girq15_b9
.extern girq15_b10
.extern girq15_b11
.extern girq15_b12
.extern girq15_b13
.extern girq15_b14
.extern girq15_b15
.extern girq15_b16
.extern girq15_b17
.extern girq15_b18
#if GIRQ15_DISAGG != 0
/*
* Disaggregated girq15_isr
* Program address of this version of girq15_isr into JTVIC GIRQ15
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq15_isr, code
#else
.section .girqs.girq15_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq15_isr
.global girq15_isr
.align 2
girq15_isr:
J girq15_b0
NOP
.align 2
J girq15_b1
NOP
.align 2
J girq15_b2
NOP
.align 2
J girq15_b3
NOP
.align 2
J girq15_b4
NOP
.align 2
J girq15_b5
NOP
.align 2
J girq15_b6
NOP
.align 2
J girq15_b7
NOP
.align 2
J girq15_b8
NOP
.align 2
J girq15_b9
NOP
.align 2
J girq15_b10
NOP
.align 2
J girq15_b11
NOP
.align 2
J girq15_b12
NOP
.align 2
J girq15_b13
NOP
.align 2
J girq15_b14
NOP
.align 2
J girq15_b15
NOP
.align 2
J girq15_b16
NOP
.align 2
J girq15_b17
NOP
.align 2
J girq15_b18
NOP
.end girq15_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq16.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ16_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq16_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<8);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq16_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 9);
}
#endif
/* end girq16.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ16 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq16_b0
.extern girq16_b1
.extern girq16_b2
.extern girq16_b3
.extern girq16_b4
.extern girq16_b5
.extern girq16_b6
.extern girq16_b7
.extern girq16_b8
.extern girq16_b9
#if GIRQ16_DISAGG != 0
/*
* Disaggregated girq16_isr
* Program address of this version of girq16_isr into JTVIC GIRQ16
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq16_isr, code
#else
.section .girqs.girq16_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq16_isr
.global girq16_isr
.align 2
girq16_isr:
J girq16_b0
NOP
.align 2
J girq16_b1
NOP
.align 2
J girq16_b2
NOP
.align 2
J girq16_b3
NOP
.align 2
J girq16_b4
NOP
.align 2
J girq16_b5
NOP
.align 2
J girq16_b6
NOP
.align 2
J girq16_b7
NOP
.align 2
J girq16_b8
NOP
.align 2
J girq16_b9
NOP
.end girq16_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq17.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ17_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq17_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<9);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq17_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 0);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b1(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 1);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b2(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 2);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 2);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b3(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 3);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 3);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 4);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 4);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b5(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 5);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 5);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b6(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 6);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 6);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b7(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 7);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 7);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b8(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 8);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 8);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b9(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 9);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 9);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b10(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 10);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 10);
}
#endif
/* end girq17.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ17 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq17_b0
.extern girq17_b1
.extern girq17_b2
.extern girq17_b3
.extern girq17_b4
.extern girq17_b5
.extern girq17_b6
.extern girq17_b7
.extern girq17_b8
.extern girq17_b9
.extern girq17_b10
#if GIRQ17_DISAGG != 0
/*
* Disaggregated girq17_isr
* Program address of this version of girq17_isr into JTVIC GIRQ17
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq17_isr, code
#else
.section .girqs.girq17_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq17_isr
.global girq17_isr
.align 2
girq17_isr:
J girq17_b0
NOP
.align 2
J girq17_b1
NOP
.align 2
J girq17_b2
NOP
.align 2
J girq17_b3
NOP
.align 2
J girq17_b4
NOP
.align 2
J girq17_b5
NOP
.align 2
J girq17_b6
NOP
.align 2
J girq17_b7
NOP
.align 2
J girq17_b8
NOP
.align 2
J girq17_b9
NOP
.align 2
J girq17_b10
NOP
.end girq17_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq18.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ18_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq18_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<10);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq18_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ18_ID, 0);
}
#endif
/* end girq18.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ18 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq18_b0
#if GIRQ18_DISAGG != 0
/*
* Disaggregated girq18_isr
* Program address of this version of girq18_isr into JTVIC GIRQ18
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
/*
* NOTE: GIRQ18 has only one source, no need for indirect jumps.
*/
.insn
#ifdef __XC32
.section .girqs.girq18_isr, code
#else
.section .girqs.girq18_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq18_isr
.global girq18_isr
.align 2
girq18_isr:
J girq18_b0
g18b0b:
NOP
g18end:
.end girq18_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq19.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ19_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq19_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<11);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq19_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 8);
}
#endif
/* end girq19.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ19 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq19_b0
.extern girq19_b1
.extern girq19_b2
.extern girq19_b3
.extern girq19_b4
.extern girq19_b5
.extern girq19_b6
.extern girq19_b7
.extern girq19_b8
#if GIRQ19_DISAGG != 0
/*
* Disaggregated girq19_isr
* Program address of this version of girq19_isr into JTVIC GIRQ19
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq19_isr, code
#else
.section .girqs.girq19_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq19_isr
.global girq19_isr
.align 2
girq19_isr:
J girq19_b0
g19b0b:
NOP
.align 2
g19b1a:
J girq19_b1
g19b1b:
NOP
.align 2
g19b2a:
J girq19_b2
g19b2b:
NOP
.align 2
g19b3a:
J girq19_b3
g19b3b:
NOP
.align 2
g19b4a:
J girq19_b4
g19b4b:
NOP
.align 2
g19b5a:
J girq19_b5
g19b5b:
NOP
.align 2
g19b6a:
J girq19_b6
g19b6b:
NOP
.align 2
g19b7a:
J girq19_b7
g19b7b:
NOP
.align 2
g19b8a:
J girq19_b8
g19b8b:
NOP
g19end:
.end girq19_isr
#endif
/******************************************************************/

88
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq20.c Normal file
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq20.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ20_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq20_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<12);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq20_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 5);
}
#endif
/* end girq20.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ20 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq20_b0
.extern girq20_b1
.extern girq20_b2
.extern girq20_b3
.extern girq20_b4
.extern girq20_b5
#if GIRQ20_DISAGG != 0
/*
* Disaggregated girq20_isr
* Program address of this version of girq20_isr into JTVIC GIRQ20
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq20_isr, code
#else
.section .girqs.girq20_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq20_isr
.global girq20_isr
.align 2
girq20_isr:
J girq20_b0
g20b0b:
NOP
.align 2
g20b1a:
J girq20_b1
g20b1b:
NOP
.align 2
g20b2a:
J girq20_b2
g20b2b:
NOP
.align 2
g20b3a:
J girq20_b3
g20b3b:
NOP
.align 2
g20b4a:
J girq20_b4
g20b4b:
NOP
.align 2
g20b5a:
J girq20_b5
g20b5b:
NOP
g20end:
.end girq20_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq21.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ21_DISAGG == 0
/*
* GIRQ21 is a wake peripheral logic only interrupt.
* It's purpose is to allow the peripheral logic such as SMBus or LPC to
* wake an service HW event without waking the EC.
* This handler is superfluous.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq21_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq21_b0(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
}
#endif
/* end girq21.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ21 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq21_b0
#if GIRQ21_DISAGG != 0
/*
* Disaggregated girq21_isr
* Program address of this version of girq21_isr into JTVIC GIRQ21
* Aggregator Control register with bit[0] = 1.
* NOTE: GIRQ21 has no sources, it is a wake only and actually
* does not send an interrupt message to the M14K.
*
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq21_isr, code
#else
.section .girqs.girq21_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq21_isr
.global girq21_isr
.align 2
girq21_isr:
J girq21_b0
g21b0b:
NOP
g21end:
.end girq21_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq22.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ22_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq22_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<14);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq22_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 9);
}
#endif
/* end girq22.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ22 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq22_b0
.extern girq22_b1
.extern girq22_b2
.extern girq22_b3
.extern girq22_b4
.extern girq22_b5
.extern girq22_b6
.extern girq22_b7
.extern girq22_b8
.extern girq22_b9
#if GIRQ22_DISAGG != 0
/*
* Disaggregated girq22_isr
* Program address of this version of girq22_isr into JTVIC GIRQ22
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq22_isr, code
#else
.section .girqs.girq22_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq22_isr
.global girq22_isr
.align 2
girq22_isr:
J girq22_b0
g22b0b:
NOP
.align 2
g22b1a:
J girq22_b1
g22b1b:
NOP
.align 2
g22b2a:
J girq22_b2
g22b2b:
NOP
.align 2
g22b3a:
J girq22_b3
g22b3b:
NOP
.align 2
g22b4a:
J girq22_b4
g22b4b:
NOP
.align 2
g22b5a:
J girq22_b5
g22b5b:
NOP
.align 2
g22b6a:
J girq22_b6
g22b6b:
NOP
.align 2
g22b7a:
J girq22_b7
g22b7b:
NOP
.align 2
g22b8a:
J girq22_b8
g22b8b:
NOP
.align 2
g22b9a:
J girq22_b9
g22b9b:
NOP
g22end:
.end girq22_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq23.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_trace_func.h"
typedef void (* GIRQ23_FPVU8)(uint8_t);
#if GIRQ23_DISAGG == 0
/*
* FreeRTOS ISR for HW timer used as RTOS tick.
* Implemented in MEC14xx FreeRTOS porting layer, port_asm.S
* It save/restores CPU context and clears HW timer interrupt
* status in JTVIC. On each timer tick it checks if any task
* requires service. If yes then it triggers the PendSV low
* priority software interrupt.
* Issue:
* When aggregated girq23_isr save CPU context but this context
* is not the same as a FreeRTOS context save. If the RTOS timer
* is active then girq23_isr would call vPortTickInterruptHandler
* which uses FreeRTOS portSAVE_CONTEXT macro to save RTOS + CPU
* context. At this point you have two context saves on the stack.
* There is a problem:
* vPortTickInterruptHandler does not return but exits using
* portRESTORE_CONTEXT. This means the context save performed
* by aggregated girq23_isr is left on the stack. Eventually
* a stack overflow will occur.
*
* Solutions:
* 1. vPortTickInterruptHandler must be modified to handle scan
* GIRQ23 Result bits and all the respective handler. All
* other GIRQ23 source are called as hook functions.
*
* 2. Do not use vPortTickInterruptHandler.
* Modify girq23_isr here to use FreeRTOS portSAVE_CONTEXT
* and portRESTORE_CONTEXT macros.
* If RTOS timer is active interrupt then call vPortIncrementTick
* as vPortTickInterruptHandler does.
* For all other GIRQ23 sources call the respective handlers.
*
* NOTE: for both of the above solutions a we must either:
* A. Service one source only resulting in GIRQ23 firing multiple
* times if more than one source is active.
* B. Service all active sources with RTOS Timer checked first.
*
* We will implement 1A with a single hook for all other sources.
*
*/
extern void vPortIncrementTick(void);
void girq23_dflt_handler(uint8_t inum)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].EN_CLR = (1ul << inum);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << inum);
}
void __attribute__((weak)) rtos_tmr_handler(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
}
const GIRQ23_FPVU8 girq23_htable[GIRQ23_NUM_SOURCES] =
{
girq23_dflt_handler, /* btmr0_handler, */
girq23_dflt_handler, /* btmr1_handler, */
girq23_dflt_handler, /* btmr2_handler, */
girq23_dflt_handler, /* btmr3_handler, */
vPortIncrementTick,
girq23_dflt_handler, /* hib_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* vci_handler, */
girq23_dflt_handler, /* vci_handler, */
girq23_dflt_handler, /* vci_handler, */
};
/* Called by FreeRTOS vPortTickInterruptHandler(girq23_isr)
* after saving FreeRTOS context
*/
void girq23_handler(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq23_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq23_isr(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq23_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
#else
/* 16-bit Basic Timer 0 */
void __attribute__((weak, interrupt, nomips16))
girq23_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0);
}
/* 16-bit Basic Timer 1 */
void __attribute__((weak, interrupt, nomips16))
girq23_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);
}
/* 16-bit Basic Timer 2 */
void __attribute__((weak, interrupt, nomips16))
girq23_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);
}
/* 16-bit Basic Timer 3 */
void __attribute__((weak, interrupt, nomips16))
girq23_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);
}
/* RTOS Timer */
void __attribute__((weak, interrupt, nomips16))
girq23_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
}
/* Hibernation Timer */
void __attribute__((weak, interrupt, nomips16))
girq23_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);
}
/* Week Alarm */
void __attribute__((weak, interrupt, nomips16))
girq23_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);
}
/* Sub-Week Alarm */
void __attribute__((weak, interrupt, nomips16))
girq23_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);
}
/* Week Alarm One Second */
void __attribute__((weak, interrupt, nomips16))
girq23_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);
}
/* Week Alarm Sub Second */
void __attribute__((weak, interrupt, nomips16))
girq23_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);
}
/* Week Alarm System Power Present Pin */
void __attribute__((weak, interrupt, nomips16))
girq23_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);
}
/* VCI OVRD Input */
void __attribute__((weak, interrupt, nomips16))
girq23_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);
}
/* VCI IN0 */
void __attribute__((weak, interrupt, nomips16))
girq23_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);
}
/* VCI IN1 */
void __attribute__((weak, interrupt, nomips16))
girq23_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);
}
#endif
/* end girq23.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/***************************************************************
* MEC14xx GIRQ23 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq23_b0
.extern girq23_b1
.extern girq23_b2
.extern girq23_b3
.extern girq23_b4
.extern girq23_b5
.extern girq23_b6
.extern girq23_b7
.extern girq23_b8
.extern girq23_b9
.extern girq23_b10
.extern girq23_b11
.extern girq23_b12
.extern girq23_b13
#if GIRQ23_DISAGG != 0
/*
* FreeRTOS Handler for MEC14xx RTOS Timer
* implemented in the porting layer.
*/
.extern vPortTickInterruptHandler
/*
* Disaggregated girq23_isr
* Program address of this version of girq23_isr into JTVIC GIRQ23
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq23_isr, code
#else
.section .girqs.girq23_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq23_isr
.global girq23_isr
.align 2
girq23_isr:
J girq23_b0
g23b0b:
NOP
.align 2
g23b1a:
J girq23_b1
g23b1b:
NOP
.align 2
g23b2a:
J girq23_b2
g23b2b:
NOP
.align 2
g23b3a:
J girq23_b3
g23b3b:
NOP
.align 2
g23b4a:
J girq23_b4
g23b4b:
NOP
.align 2
g23b5a:
J girq23_b5
g23b5b:
NOP
.align 2
g23b6a:
J girq23_b6
g23b6b:
NOP
.align 2
g23b7a:
J girq23_b7
g23b7b:
NOP
.align 2
g23b8a:
J girq23_b8
g23b8b:
NOP
.align 2
g23b9a:
J girq23_b9
g23b9b:
NOP
.align 2
g23b10a:
J girq23_b10
g23b10b:
NOP
.align 2
g23b11a:
J girq23_b11
g23b11b:
NOP
.align 2
g23b12a:
J girq23_b12
g23b12b:
NOP
.align 2
g23b13a:
J girq23_b13
g23b13b:
NOP
g23end:
.end girq23_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq24.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_trace_func.h"
typedef void (* GIRQ24_FPVU8)(uint8_t);
/* MIPS M14K internal counter is connected to GIRQ24 bit[0]
* It is a simple counter which fires an interrupt when its
* count value is equal to a match value.
*
*/
#if GIRQ24_DISAGG == 0
void girq24_dflt_handler(uint8_t inum)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);
}
void __attribute__((weak)) m14k_counter_handler(uint8_t inum)
{
uint32_t r;
(void) inum;
r = _CP0_GET_COUNT();
r += (M14K_TIMER_COMPARE);
/* Write of CP0.Compare clears status in M14K */
_CP0_SET_COUNT(r);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
}
/*
* TODO - FreeRTOS M14K Software Interrupt 0 handler
* is vPortYieldISR in port_asm.S
* vPortYieldISR was designed to be entered directly by the
* CPU not via a higher level ISR handler.
* One work-around is to modify vPortYieldISR to do the work
* of girq24_handler below. It must determine which GIRQ24 source
* was active: M14K counter, SoftIRQ0, or SoftIRQ1.
*/
void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);
}
void girq24_b_0_2( void )
{
uint32_t d;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
if ( d & (1ul << 0) )
{
m14k_counter_handler(0);
}
if ( d & (1ul << 2) )
{
m14k_soft_irq1(2);
}
}
const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =
{
m14k_counter_handler, /* m14k_counter_handler, */
m14k_soft_irq0, /* m14k_soft_irq0, */
m14k_soft_irq1, /* m14k_soft_irq1 */
};
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq24_isr(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq24_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
#else
void __attribute__((weak, interrupt, nomips16))
girq24_b0(void)
{
uint32_t r;
r = _CP0_GET_COUNT();
r += (M14K_TIMER_COMPARE);
_CP0_SET_COUNT(r);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq24_b1(void)
{
_CP0_BIC_CAUSE(0x100ul);
jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq24_b2(void)
{
_CP0_BIC_CAUSE(0x200ul);
jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);
}
#endif
/* end girq24.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ24 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq24_b0
.extern girq24_b1
.extern girq24_b2
#if GIRQ24_DISAGG != 0
/*
* FreeRTOS Handler for MIPS M14K Software Interrupt 0
* implemented in the porting layer.
*/
.extern vPortYieldISR
/*
* Disaggregated girq24_isr
* Program address of this version of girq24_isr into JTVIC GIRQ24
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq24_isr, code
#else
.section .girqs.girq24_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq24_isr
.global girq24_isr
.align 2
girq24_isr:
J girq24_b0
g24b0b:
NOP
.align 2
g24b1a:
J vPortYieldISR /* girq24_b1 */
g24b1b:
NOP
.align 2
g24b2a:
J girq24_b2
g24b2b:
NOP
g24end:
.end girq24_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq25.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ25_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq25_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<15);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq25_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 18);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 20);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 21);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 22);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 23);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b24(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 24);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b25(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 25);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b26(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 26);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b27(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27);
}
#endif
/* end girq25.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ25 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq25_b0
.extern girq25_b1
.extern girq25_b2
.extern girq25_b3
.extern girq25_b4
.extern girq25_b5
.extern girq25_b6
.extern girq25_b7
.extern girq25_b8
.extern girq25_b9
.extern girq25_b10
.extern girq25_b11
.extern girq25_b12
.extern girq25_b13
.extern girq25_b14
.extern girq25_b15
.extern girq25_b16
.extern girq25_b17
.extern girq25_b18
.extern girq25_b19
.extern girq25_b20
.extern girq25_b21
.extern girq25_b22
.extern girq25_b23
.extern girq25_b24
.extern girq25_b25
.extern girq25_b26
.extern girq25_b27
#if GIRQ25_DISAGG != 0
/*
* Disaggregated girq25_isr
* Program address of this version of girq25_isr into JTVIC GIRQ25
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq25_isr, code
#else
.section .girqs.girq25_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq25_isr
.global girq25_isr
.align 2
girq25_isr:
J girq25_b0
g25b0b:
NOP
.align 2
g25b1a:
J girq25_b1
g25b1b:
NOP
.align 2
g25b2a:
J girq25_b2
g25b2b:
NOP
.align 2
g25b3a:
J girq25_b3
g25b3b:
NOP
.align 2
g25b4a:
J girq25_b4
g25b4b:
NOP
.align 2
g25b5a:
J girq25_b5
g25b5b:
NOP
.align 2
g25b6a:
J girq25_b6
g25b6b:
NOP
.align 2
g25b7a:
J girq25_b7
g25b7b:
NOP
.align 2
g25b8a:
J girq25_b8
g25b8b:
NOP
.align 2
g25b9a:
J girq25_b9
g25b9b:
NOP
.align 2
g25b10a:
J girq25_b10
g25b10b:
NOP
.align 2
g25b11a:
J girq25_b11
g25b11b:
NOP
.align 2
g25b12a:
J girq25_b12
g25b12b:
NOP
.align 2
g25b13a:
J girq25_b13
g25b13b:
NOP
.align 2
g25b14a:
J girq25_b14
g25b14b:
NOP
.align 2
g25b15a:
J girq25_b15
g25b15b:
NOP
.align 2
g25b16a:
J girq25_b16
g25b16b:
NOP
.align 2
g25b17a:
J girq25_b17
g25b17b:
NOP
.align 2
g25b18a:
J girq25_b18
g25b18b:
NOP
.align 2
g25b19a:
J girq25_b19
g25b19b:
NOP
.align 2
g25b20a:
J girq25_b20
g25b20b:
NOP
.align 2
g25b21a:
J girq25_b21
g25b21b:
NOP
.align 2
g25b22a:
J girq25_b22
g25b22b:
NOP
.align 2
g25b23a:
J girq25_b23
g25b23b:
NOP
.align 2
g25b24a:
J girq25_b24
g25b24b:
NOP
.align 2
g25b25a:
J girq25_b25
g25b25b:
NOP
.align 2
g25b26a:
J girq25_b26
g25b26b:
NOP
.align 2
g25b27a:
J girq25_b27
g25b27b:
NOP
g25end:
.end girq25_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq26.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ26_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq26_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<16);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq26_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 11);
}
#endif
/* end girq26.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ26 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq26_b0
.extern girq26_b1
.extern girq26_b2
.extern girq26_b3
.extern girq26_b4
.extern girq26_b5
.extern girq26_b6
.extern girq26_b7
.extern girq26_b8
.extern girq26_b9
.extern girq26_b10
.extern girq26_b11
#if GIRQ26_DISAGG != 0
/*
* Disaggregated girq26_isr
* Program address of this version of girq26_isr into JTVIC GIRQ26
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq26_isr, code
#else
.section .girqs.girq26_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq26_isr
.global girq26_isr
.align 2
girq26_isr:
J girq26_b0
g26b0b:
NOP
.align 2
g26b1a:
J girq26_b1
g26b1b:
NOP
.align 2
g26b2a:
J girq26_b2
g26b2b:
NOP
.align 2
g26b3a:
J girq26_b3
g26b3b:
NOP
.align 2
g26b4a:
J girq26_b4
g26b4b:
NOP
.align 2
g26b5a:
J girq26_b5
g26b5b:
NOP
.align 2
g26b6a:
J girq26_b6
g26b6b:
NOP
.align 2
g26b7a:
J girq26_b7
g26b7b:
NOP
.align 2
g26b8a:
J girq26_b8
g26b8b:
NOP
.align 2
g26b9a:
J girq26_b9
g26b9b:
NOP
.align 2
g26b10a:
J girq26_b10
g26b10b:
NOP
.align 2
g26b11a:
J girq26_b11
g26b11b:
NOP
g26end:
.end girq26_isr
#endif
/******************************************************************/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girqs.c
*MEC14xx JTVIC default configuration table
*/
/** @defgroup MEC140x ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqm.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
/*
* Interrupt Service Routine prototypes for each GIRQn
*/
/*
* Table for initializing MEC14xx JTVIC.
* Each GIRQn handler's address must be programmed into
* respective JTVIC register.
*/
const JTVIC_CFG dflt_ih_table[MEC14xx_NUM_JTVIC_INTS] = {
{
(uint32_t)girq08_isr,
{
(GIRQ08_PRI_A),
(GIRQ08_PRI_B),
(GIRQ08_PRI_C),
(GIRQ08_PRI_D)
}
},
{
(uint32_t)girq09_isr,
{
(GIRQ09_PRI_A),
(GIRQ09_PRI_B),
(GIRQ09_PRI_C),
(GIRQ09_PRI_D)
}
},
{
(uint32_t)girq10_isr,
{
(GIRQ10_PRI_A),
(GIRQ10_PRI_B),
(GIRQ10_PRI_C),
(GIRQ10_PRI_D)
}
},
{
(uint32_t)girq11_isr,
{
GIRQ11_PRI_A,
GIRQ11_PRI_B,
GIRQ11_PRI_C,
GIRQ11_PRI_D
}
},
{
(uint32_t)girq12_isr,
{
GIRQ12_PRI_A,
GIRQ12_PRI_B,
GIRQ12_PRI_C,
GIRQ12_PRI_D
}
},
{
(uint32_t)girq13_isr,
{
GIRQ13_PRI_A,
GIRQ13_PRI_B,
GIRQ13_PRI_C,
GIRQ13_PRI_D
}
},
{
(uint32_t)girq14_isr,
{
GIRQ14_PRI_A,
GIRQ14_PRI_B,
GIRQ14_PRI_C,
GIRQ14_PRI_D
}
},
{
(uint32_t)girq15_isr,
{
GIRQ15_PRI_A,
GIRQ15_PRI_B,
GIRQ15_PRI_C,
GIRQ15_PRI_D
}
},
{
(uint32_t)girq16_isr,
{
GIRQ16_PRI_A,
GIRQ16_PRI_B,
GIRQ16_PRI_C,
GIRQ16_PRI_D
}
},
{
(uint32_t)girq17_isr,
{
GIRQ17_PRI_A,
GIRQ17_PRI_B,
GIRQ17_PRI_C,
GIRQ17_PRI_D
}
},
{
(uint32_t)girq18_isr,
{
GIRQ18_PRI_A,
GIRQ18_PRI_B,
GIRQ18_PRI_C,
GIRQ18_PRI_D
}
},
{
(uint32_t)girq19_isr,
{
GIRQ19_PRI_A,
GIRQ19_PRI_B,
GIRQ19_PRI_C,
GIRQ19_PRI_D
}
},
{
(uint32_t)girq20_isr,
{
GIRQ20_PRI_A,
GIRQ20_PRI_B,
GIRQ20_PRI_C,
GIRQ20_PRI_D
}
},
{
(uint32_t)girq21_isr,
{
GIRQ21_PRI_A,
GIRQ21_PRI_B,
GIRQ21_PRI_C,
GIRQ21_PRI_D
}
},
{
(uint32_t)girq22_isr,
{
GIRQ22_PRI_A,
GIRQ22_PRI_B,
GIRQ22_PRI_C,
GIRQ22_PRI_D
}
},
{
(uint32_t)girq23_isr,
{
GIRQ23_PRI_A,
GIRQ23_PRI_B,
GIRQ23_PRI_C,
GIRQ23_PRI_D
}
},
{
(uint32_t)girq24_isr,
{
GIRQ24_PRI_A,
GIRQ24_PRI_B,
GIRQ24_PRI_C,
GIRQ24_PRI_D
}
},
{
(uint32_t)girq25_isr,
{
GIRQ25_PRI_A,
GIRQ25_PRI_B,
GIRQ25_PRI_C,
GIRQ25_PRI_D
}
},
{
(uint32_t)girq26_isr,
{
GIRQ26_PRI_A,
GIRQ26_PRI_B,
GIRQ26_PRI_C,
GIRQ26_PRI_D
}
}
};
/* end girqs.c */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_bbled.c
*MEC14xx Breating-Blinking LED definitions
*/
/** @defgroup MEC14xx Peripherals BBLED
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#ifdef __cplusplus
extern "C" {
#endif
static uint32_t led_addr(uint8_t led_id)
{
if (led_id < (LED_ID_MAX) )
{
return ((LED0_BASE) + (led_id << 8));
}
else
{
return (LED0_BASE);
}
}
#ifdef LED_ENABLE_VALID_CHECK
static uint8_t led_is_valid(uint8_t led_id)
{
if (led_id < (LED_ID_MAX)) {
return true;
}
return false;
}
#else
static uint8_t led_is_valid(uint8_t led_id) { ( void ) led_id; return (MEC14XX_TRUE); }
#endif
/**
@brief MEC1404 LED are alternate functions of GPIO pins.
@note -
LED0 is GPIO157 Function 1
LED1 is GPIO156 Function 1
LED2 is GPIO104 Function 1
*/
static const uint8_t led_pcr_slp2_bitpos[LED_ID_MAX] = {
(PCR_EC2_LED0_SLP_BITPOS),
(PCR_EC2_LED1_SLP_BITPOS),
(PCR_EC2_LED2_SLP_BITPOS)
};
static const uint16_t led_gpio_tbl[LED_ID_MAX] = {
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0157_ID),
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0156_ID),
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0104_ID)
};
/**
* led_sleep_en - Enable/Disable gating of clocks on idle to the
* BBLED block
*
*
* @param uint8_t sleep_en (1=Enable sleep on idle), (0=No sleep
* on idle).
* @param uint8_t LED ID (0-3)
* @note if LED ID > 3 no action taken.
*/
void led_sleep_en(uint8_t led_id, uint8_t sleep_en)
{
uint32_t slp_mask;
uint32_t laddr;
slp_mask = 0ul;
if ( led_is_valid(led_id) ) {
slp_mask = (1ul << led_pcr_slp2_bitpos[led_id]);
if ( sleep_en ) {
PCR->EC_SLEEP_EN2 |= slp_mask;
laddr = led_addr(led_id);
((BBLED_TypeDef *)laddr)->CONFIG &= ~(0x03ul);
} else {
PCR->EC_SLEEP_EN2 &= ~(slp_mask);
}
}
}
/**
* led_reset - Reset the specified LED hardware block.
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note Sets the LED's soft reset bit and waits for hardware to
* clear it. Will wait up to 0x10000 times.
*/
void led_reset(uint8_t led_id)
{
uint32_t p;
uint32_t cnt;
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = (LED_CFG_RESET);
cnt = 0x100000UL;
while ( ((BBLED_TypeDef *)p)->CONFIG & (LED_CFG_RESET) ) {
if ( cnt != 0UL ) {
cnt--;
} else {
break;
}
}
}
uint8_t led_get_gpio_num(uint8_t led_id)
{
return led_gpio_tbl[(led_id & ((LED_ID_MAX)-1u))];
}
/**
* led_init - Initialize the specified LED
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note Configures the LED's GPIO pin for LED function and then
* peforms a soft reset of the LED hardware.
*/
void led_init(uint8_t led_id)
{
uint16_t ledi;
if ( led_id < LED_ID_MAX )
{
/* bits[7:0] = GPIO_ID, bits[15:8] = GPIO Function */
ledi = led_gpio_tbl[led_id];
GPIOPropertySet((ledi & 0xFF), GPIO_PROP_MUX_SEL, (ledi >> 8) & 0xFF);
led_reset(ledi & 0xFF);
}
}
/**
* led_mode_blink - Enable LED hardware blink
*
* @author sworley
*
* @param led_id 0-based LED ID
* @param duty_cycle duty cycle (0x80 = 50%)
* @param prescale sets the blink frequency
* @note Blink frequency is (32768 * 255)/(prescale + 1) Hz
*/
void led_mode_blink(uint8_t led_id,
uint8_t duty_cycle,
uint16_t prescale)
{
uint32_t pLed;
pLed = 0UL;
if (led_is_valid(led_id)) {
pLed = led_addr(led_id);
((BBLED_TypeDef *)pLed)->CONFIG = LED_CFG_CNTL_BLINK;
((BBLED_TypeDef *)pLed)->LIMIT = (uint32_t)duty_cycle;
((BBLED_TypeDef *)pLed)->DELAY = (uint32_t)prescale;
((BBLED_TypeDef *)pLed)->CONFIG |= (LED_CFG_EN_UPDATE);
}
}
/**
* led_out_toggle - Toggle the LED output pin.
*
* @author sworley
*
* @param led_id 0-based LED ID.
*/
void led_out_toggle(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
if (((BBLED_TypeDef *)p)->CONFIG & LED_CFG_CNTL_MASK) {
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
} else {
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
}
}
}
/**
* led_out_high - Set the LED block to drive the pin High
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note The LED controller will drive the pin High. Depending
* upon the external circuit the LED may be in ON or OFF
* state.
*/
void led_out_high(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
}
}
/**
* led_out_low - Set the LED block to drive the pin Low
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note The LED controller will drive the pin Low. Depending
* upon the external circuit the LED may be in ON or OFF
* state.
*/
void led_out_low(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
}
}
#ifdef __cplusplus
}
#endif
/* end mec14xx_bbled.h */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_gpio.c
*MEC14xx GPIO hardware access
*/
/** @defgroup MEC14xx Peripherals GPIO
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_gpio.h"
static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id );
#ifdef ENABLE_GPIO_PIN_VALIDATION
static const uint32_t gpio_port_bitmaps[NUM_GPIO_PORTS] =
{
(GPIO_PORT_A_BITMAP),
(GPIO_PORT_B_BITMAP),
(GPIO_PORT_C_BITMAP),
(GPIO_PORT_D_BITMAP)
};
#endif
//
// Drive Strength Register bitmap
//
static const uint32_t gpio_drv_str_bitmap[NUM_GPIO_PORTS] =
{
(GPIO_PORT_A_DRVSTR_BITMAP),
(GPIO_PORT_B_DRVSTR_BITMAP),
(GPIO_PORT_C_DRVSTR_BITMAP),
(GPIO_PORT_D_DRVSTR_BITMAP)
};
struct gpio_cfg
{
uint16_t bit_mask;
uint8_t bit_pos;
};
static const struct gpio_cfg gpio_cfg_tbl[GPIO_PROP_MAX] =
{
{ 0x0003u, 0x00u },
{ 0x000Cu, 0x02u },
{ 0x00F0u, 0x04u },
{ 0x0100u, 0x08u },
{ 0x0200u, 0x09u },
{ 0x0400u, 0x0Au },
{ 0x0800u, 0x0Bu },
{ 0x3000u, 0x0Cu },
{ 0x3FFFu, 0x00u }
};
static uint32_t gpio_pin_ctrl_addr(enum gpio_id_t gpio_id)
{
return ((uint32_t)(GPIO_BASE) + (uint32_t)(gpio_id << 2));
}
#ifdef ENABLE_GPIO_PIN_VALIDATION
/**
* gpio_is_valid - local helper checks if GPIO pin is
* implemented in this hardware.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t Non-zero(GPIO Pin implemented), 0(not
* implemented).
*/
static uint8_t gpio_is_valid ( enum gpio_id_t gpio_id )
{
uint16_t gp_bank;
gp_bank = 0;
if ( (uint16_t)gpio_id < (uint16_t)(MAX_GPIO_ID) )
{
gp_bank = (uint16_t)gpio_id >> 5;
if ( gpio_port_bitmaps[gp_bank] & (1 << (gpio_id & 0x001Fu)) )
{
return true;
}
}
return false;
}
#else
static uint32_t gpio_is_valid(enum gpio_id_t gpio_id) { return true; }
#endif
static uint8_t gpio_bank_num(enum gpio_id_t gpio_id)
{
return (uint8_t)(gpio_id) >> 5;
}
static uint8_t gpio_pin_num(enum gpio_id_t gpio_id)
{
return (uint8_t)(gpio_id) & 0x1Fu;
}
/**
* gpio_has_drv_str - Local helper to check if GPIO pin has
* associated drive strength register.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint32_t 0(No Drive Strength), Non-zero(Physical
* address of Drive Strength Register).
*/
static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id )
{
uint32_t bank, bitpos, addr;
addr = 0ul;
if ( gpio_id < MAX_GPIO_ID )
{
bank = gpio_bank_num(gpio_id);
bitpos = gpio_pin_num(gpio_id);
if ( gpio_drv_str_bitmap[bank] & (1ul << bitpos) )
{
addr = (GPIO_PCTRL2_BASE) + ((uint32_t)(gpio_id) << 2);
if ( gpio_id > GPIO_0077_ID )
{
addr -= 0x20ul;
}
}
}
return addr;
}
uint16_t GPIOGetConfig(enum gpio_id_t gpio_id)
{
if (gpio_is_valid(gpio_id)) {
return *((volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id));
} else {
return 0u;
}
}
void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config)
{
volatile uint16_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
*p = config;
}
}
void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask)
{
volatile uint16_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
*p = (*p & and_mask) | or_mask;
}
}
uint32_t GPIOGetControl(enum gpio_id_t gpio_id)
{
if (gpio_is_valid(gpio_id)) {
return *((volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id));
} else {
return 0xFFFFFFFFul;
}
}
void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val)
{
volatile uint32_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
*p = ctrl_val;
}
}
void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask)
{
volatile uint32_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
*p = (*p & and_mask) | or_mask;
}
}
/**
* GPIOPropertySet - Program specified GPIO Pin configuration
* item.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param gpio_prop enumerated GPIO Property(configuration item)
* @param prop_val new property value
*/
void GPIOPropertySet ( enum gpio_id_t gpio_id,
enum gpio_prop_t gpio_prop,
uint16_t prop_val
)
{
volatile uint16_t * p;
uint16_t gp_cfg;
gp_cfg = 0u;
if ( gpio_is_valid(gpio_id) && ((uint16_t)gpio_prop < (uint16_t)GPIO_PROP_MAX) )
{
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
gp_cfg = *p;
gp_cfg &= ~(gpio_cfg_tbl[gpio_prop].bit_mask);
gp_cfg |= (prop_val << gpio_cfg_tbl[gpio_prop].bit_pos) &
gpio_cfg_tbl[gpio_prop].bit_mask;
*p = gp_cfg;
}
}
/**
* GPIOGetSlewRate - Return GPIO Pin Slew Rate
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t GPIO Pin Slew Rate: 0(Slow) or 1(Fast)
*/
uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id )
{
uint32_t addr;
uint8_t slew;
addr = gpio_has_drv_str(gpio_id);
if ( 0ul != addr )
{
slew = ((*(volatile uint8_t *)addr) >> GPIO_DRV_SLEW_BITPOS) & 0x01u;
}
else
{
slew = 0u;
}
return slew;
}
/**
* GPIOSetSlewRate - Program GPIO Pin's Slew Rate
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param slew_rate new slew rate: 0(Slow), Non-zero(Fast)
*/
void GPIOSetSlewRate ( enum gpio_id_t gpio_id,
enum gpio_slew_rate_t slew_rate )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
*(volatile uint8_t *)addr = (*(volatile uint8_t *)addr &
~(GPIO_DRV_SLEW_MASK)) |
((slew_rate << (GPIO_DRV_SLEW_BITPOS)) & (GPIO_DRV_SLEW_MASK));
}
}
/**
* GPIOGetDriveStr - Get GPIO Pin's Drive Strength
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t Pin Drive Strength: 0=2mA, 1=4mA, 2=8mA,
* 3=12mA.
*/
uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
return ((*(volatile uint8_t *)addr) >> GPIO_DRV_STR_BITPOS) & (GPIO_DRV_STR_MASK);
}
else
{
return 0u;
}
}
/**
* GPIOSetDriveStr - Program GPIO Pin's Drive Strength
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param drv_str enumerated drive strength: 0=2mA, 1=4mA,
* 2=8mA, 3=12mA
*/
void GPIOSetDriveStr ( enum gpio_id_t gpio_id,
enum gpio_drv_str_t drv_str )
{
uint32_t addr;
uint8_t r8;
addr = gpio_has_drv_str(gpio_id);
if ( addr )
{
r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_STR_MASK);
r8 += ((drv_str << GPIO_DRV_STR_BITPOS) & GPIO_DRV_STR_MASK);
*(volatile uint8_t *)addr = r8;
}
}
/**
* GPIOGetDriveStrAndSlew - Return combined value representing
* Drive Strength and Slew Rate.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t bit[0] = Slew Rate, bits[3:1]=0(Reserved),
* bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
*/
uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
return (*(volatile uint8_t *)addr);
}
else
{
return 0u;
}
}
/**
* GPIOSetDriveStrAndSlew - Program GPIO Pin's drive strength
* and slew rate.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param drv_and_slew bit[0] = Slew Rate, bits[3:1]=0(Reserved),
* bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
*/
void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,
uint8_t drv_and_slew )
{
uint32_t addr;
uint8_t r8;
addr = gpio_has_drv_str(gpio_id);
if ( addr )
{
r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK);
r8 |= (drv_and_slew & (GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK));
*(volatile uint8_t *)addr = r8;
}
}
/**
* GPIOSetOutput - Program GPIO Pin's output state using Pin
* configuration register (not parallel output register).
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param gpio_state pin state: actual pin state at pad will
* depend upon GPIO Output invert
* configuration.
* @note peforms a byte wide write to byte offset 2 of the GPIO
* Pin's 32-bit configuration register. No
* read-modify-write.
*/
void GPIOSetOutput ( enum gpio_id_t gpio_id,
uint8_t gpio_state
)
{
volatile uint8_t * p;
if ( gpio_is_valid(gpio_id) )
{
p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
if (gpio_state) {
*p = 0x01u;
} else {
*p = 0u;
}
}
}
void GPIOToggleOutput ( enum gpio_id_t gpio_id )
{
volatile uint8_t * p;
if ( gpio_is_valid(gpio_id) )
{
p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
*p ^= 0x01u;
}
}
/**
* GPIOReadPin - Read GPIO Pin's Pad Input from configuration
* register.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID.
*
* @return uint8_t 0 or 1 depending upon the state of the GPIO
* pad.
* @note performs a byte read of offset 3 of the GPIO Pin's
* 32-bit configuration register.
*/
uint8_t GPIOReadPin( enum gpio_id_t gpio_id )
{
if ( gpio_is_valid(gpio_id) )
{
return *((volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 3ul));
}
else
{
return 0u;
}
}
/** GPIOPinLock - Lock specified GPIO's control register.
* @param enum gpio_id_t zero based GPIO ID
* @note Lock bit is only cleared on POR. Lock registers
* are in reverse order, first register is at top address.
* GPIO_LOCK_BASE defined to top(first) register address.
* */
void GPIOPinLock(enum gpio_id_t gpio_id)
{
uint32_t addr;
uint8_t bank, bitpos;
if (gpio_is_valid(gpio_id)) {
bank = gpio_bank_num(gpio_id); // 0 - 4
bitpos = gpio_pin_num(gpio_id); // 0 - 31
addr = (uint32_t)(GPIO_LOCK_BASE) - (bank << 2);
*(volatile uint32_t *)addr |= (1ul << bitpos);
}
}
/* end mec14xx_gpio.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_jtvic.c
*MEC14xx JTVIC
*/
/** @defgroup MEC14xx Peripherals JTVIC
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_jtvic.h"
void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags)
{
uint32_t d;
uint8_t i, j, pidx;
JTVIC_CTRL->w = (1ul << 0); // Soft-Reset
d = 0ul;
if ( cflags & (1ul << 0) )
{
d = (1ul << 8);
}
JTVIC_CTRL->w = d; // HW does not automatically clear Soft-Reset
for (i = 0u; i < (MEC14xx_NUM_JTVIC_INTS); i++) {
pidx = i << 2;
for (j = 0u; j < 4u; j++) {
JTVIC_PRI->REG32[pidx+j] = (uint32_t)(ih_table[i].pri[j]);
}
d = ih_table[i].isr_addr & ~(1ul << 0);
if (disagg_bitmap & (1ul << i)) {
d |= (1ul << 0); // dis-aggregate this GIRQ
}
JTVIC_ACTRL->REG32[i] = d;
}
JTVIC_GROUP_EN_SET->w = 0xFFFFFFFFul; // Enable GIRQ08 - GIRQ18 (all)
}
/* Clear JTVIC GIRQn source bit
*
*/
void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
}
/* Disable GIRQn source with optional clearing of source.
* girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
* bit_num = [0, 31]
*/
void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
JTVIC_GIRQ->REGS[girq_num].EN_CLR = (1ul << bit_num);
if ( 0 != clr_src )
{
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
}
}
/* Enable with optional source clear before enable.
* girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
* bit_num = [0, 31]
*/
void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
if ( 0 != clr_src )
{
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
JTVIC_GIRQ->REGS[girq_num].EN_SET = (1ul << bit_num);
}
}
/* end mec14xx_jtvic.c */
/** @}
*/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_system.c
*MEC14xx system functions
*/
/** @defgroup MEC14xx System
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_system.h"
#include "MEC14xx/mec14xx_jtvic.h"
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
PCR->PROC_CLOCK_CNTRL = (PCR_CLOCK_DIVIDER);
}
/*---------------------------------------------------------------------------*/
uint32_t sys_code_sram_base(void)
{
#if MEC14XX_DEVID == MEC1418_DEVID
return (uint32_t)(MEC1418_ICODE_PSRAM_BASE);
#else
return (uint32_t)(MEC1404_ICODE_PSRAM_BASE);
#endif
}
/*---------------------------------------------------------------------------*/
uint8_t sys_valid_sram_addr(void * const p)
{
uint32_t base;
base = sys_code_sram_base();
if ((uint32_t)p >= base) {
if ((uint32_t)p < (MEC14XX_DCODE_VSRAM_LIMIT)) {
return 1u;
}
}
return 0u;
}
/*---------------------------------------------------------------------------*/
uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len)
{
uint32_t base;
base = sys_code_sram_base();
if ((uint32_t)p >= base) {
if (((uint32_t)p + byte_len) < (MEC14XX_DCODE_VSRAM_LIMIT)) {
return 1u;
}
}
return 0u;
}
/*---------------------------------------------------------------------------*/
void sys_cpu_en_timer(uint32_t counts, uint8_t ien)
{
/* Disable Counter by setting DC bit to 1 in CP0.Cause */
_CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);
_CP0_SET_COUNT(counts);
if (ien) {
jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);
} else {
jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);
}
/* Enable Counter */
_CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);
}
/*---------------------------------------------------------------------------*/
uint32_t cpu_microsecond_count(void)
{
return _CP0_GET_COUNT();
}
/*---------------------------------------------------------------------------*/
/*
* Assumes M14K CPU is running at clock divide by 1 (48MHz)
* 1us = 48 counts.
* NOTE: We need to find out from DE what the pipeline rate is.
* M14K counter ticks at pipeline rate.
*/
uint32_t cpu_microsecond_interval(uint32_t start_count)
{
uint32_t curr_count;
curr_count = _CP0_GET_COUNT();
if (curr_count >= start_count) {
return ((curr_count - start_count) >> 4)/ 3ul;
} else {
return (((0xFFFFFFFFul - start_count) + curr_count) >> 4) / 3ul;
}
}
/*---------------------------------------------------------------------------*/
/* end mec14xx_system.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_tfdp.c
*MEC14xx Trace FIFO Data Port hardware access
*/
/** @defgroup MEC14xx Peripherals TFDP
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#ifdef ENABLE_TFDP_TRACE
#undef TFDP_PIN_1
#undef TFDP_PIN_2
#define TFDP_PIN_1 (GPIO_0116_ID) // Func1 PullUp enabled
#define TFDP_PIN_2 (GPIO_0117_ID) // Func1 PullUp enabled
static void tfdp_xmit_header(uint16_t nbr)
{
TFDP->DATA = TFDP_FRAME_START;
TFDP_DELAY();
TFDP->DATA = (uint8_t)nbr;
TFDP_DELAY();
TFDP->DATA = (uint8_t)(nbr >> 8);
TFDP_DELAY();
}
static void tfdp_xmit_hword(uint16_t hword)
{
TFDP->DATA = (uint8_t)hword;
TFDP_DELAY();
TFDP->DATA = (uint8_t)(hword >> 8);
TFDP_DELAY();
}
static void tfdp_xmit_word(uint32_t word)
{
uint8_t i;
for (i = 0u; i < 4; i++) {
TFDP->DATA = (uint8_t)word;
word >>= 8;
TFDP_DELAY();
}
}
/**
* tfdp_sleep_en - Gate clocks On/Off to TFDP block when idle
*
* @author C21969 (2/4/2014)
*
* @param sleep_en (1=Gate clocks when idle), (0=Do not gate
* clocks when idle)
*/
void tfdp_sleep_en(uint8_t sleep_en)
{
if ( sleep_en ) {
PCR->EC_SLEEP_EN |= (PCR_EC_TFDP_SLP_CLK);
} else {
PCR->EC_SLEEP_EN &= ~(PCR_EC_TFDP_SLP_CLK);
}
}
/**
* tfdp_enable - Init Trace FIFO Data Port
* @param boolean true=enable TFDP, false=disable TFDP
* @param boolean true=change TFDP pin configuration.
* If TFDP is enabled then GPIO103/104 set to Alt. Func. 1
* Else GPIO103/104 set to GPIO input, internal PU enabled.
* @note -
*/
void tfdp_enable(uint8_t en, uint8_t pin_cfg)
{
uint32_t delay;
if (en) {
if (pin_cfg) {
// Input with AltOut=1 to drive high when switched to output
GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16);
GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16);
delay = 128;
while ( delay-- )
{
CPU_NOP();
}
// GPIO Output enabled (drive based on above settings)
GPIO_CTRL->REG[TFDP_PIN_1].w |= (1ul << 9);
GPIO_CTRL->REG[TFDP_PIN_2].w |= (1ul << 9);
delay = 128;
while ( delay-- )
{
CPU_NOP();
}
// Switch to Function 1 (TFDP mode b[13:12]=01b)
GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16) + (1ul << 12);
GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16) + (1ul << 12);
}
/* b[0]=1(Enable)
* b[1]=0(Shift data out on rising edge)
* b[3:2]=00b TFDP shift clocks = AHB_CLK/2
* b[6:4]=000b 1 clock inter-packet delay
*/
TFDP->CONTROL = 0x01u;
}
else
{
TFDP->CONTROL = 0x00u;
if (pin_cfg)
{ /* Set to POR value (tri-stated input) */
GPIO_CTRL->REG[TFDP_PIN_1].w = 0;
GPIO_CTRL->REG[TFDP_PIN_2].w = 0;
}
}
} // end tfdp_enable()
/**
* TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
* over TFDP.
*
* @author sworley
*
* @param nbr 16-bit trace number
* @param b unused
*
* @return uint8_t always TRUE
* @note Function implements critical section.
* Uses tool kit __disable_irq()/__enable_irq() pair which may use
* priviledged Cortex-Mx instructions.
*/
void TFDPTrace0 ( uint16_t nbr, uint8_t b )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
* and 16-bit data lsb first over TFDP.
*
* @author sworley
*
* @param nbr 16-bit trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
*
* @return uint8_t always TRUE
* @note Function implements critical section.
* Uses tool kit __disable_irq()/__enable_irq() pair which may use
* priviledged Cortex-Mx instructions.
*/
void TFDPTrace1 ( uint16_t nbr, uint8_t b, uint32_t p1 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
* and two 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace2 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
* and three 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
* @param uint32_t p3 16-bit data3 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace3 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
tfdp_xmit_hword(p3);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
* and four 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
* @param uint32_t p3 16-bit data3 in b[15:0]
* @param uint32_t p4 16-bit data4 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace4 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
tfdp_xmit_hword(p3);
tfdp_xmit_hword(p4);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace11 - Transmit one 32-bit data item over TFDP
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 32-bit data to be transmitted
*
*/
void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_word(p1);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace12 - Transmit two 32-bit data items over TFDP
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 32-bit data1 to be transmitted
* @param uint32_t p2 32-bit data2 to be transmitted
*
*/
void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_word(p1);
tfdp_xmit_word(p2);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
#endif // #ifdef ENABLE_TFDP_TRACE
/* end mec14xx_tfdp.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_timers.c
*MEC14xx Timers
*/
/** @defgroup MEC14xx Peripherals Timers
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_timers.h"
// pairs of bytes (sleep reg, bit position)
// sleep reg = 0 for EC_SLEEP_EN or 1 for EC_SLEEP_EN2
//
struct btmr_sleep_info_s {
uint8_t slp_reg;
uint8_t bit_pos;
};
static const struct btmr_sleep_info_s btmr_slp_info[BTMR_MAX_INSTANCE] = {
{ 0, PCR_EC_TIMER0_SLP_BITPOS },
{ 0, PCR_EC_TIMER1_SLP_BITPOS },
{ 1, PCR_EC2_TIMER2_SLP_BITPOS },
{ 1, PCR_EC2_TIMER3_SLP_BITPOS }
};
#ifdef MEC14XX_BTIMER_CHECK_ID
/**
* tmr_valid - Local helper that checks if logical Timer ID is
* valid.
*
* @author sworley
*
* @param tmr_id 0-based Timer ID
*
* @return uint8_t Non-zero(VALID), 0(Invalid)
*/
static uint8_t btmr_valid(uint8_t tmr_id)
{
if ( tmr_id < (BTMR_ID_MAX ) ) {
return true;
}
return false;
}
#else
/**
* @brief - This version of tmr_valid skips checking always
* returning TRUE. Compiler may optimize it out.
*
*/
static uint8_t btmr_valid(uint8_t tmr_id)
{
(void) tmr_id;
return true;
}
#endif
uint32_t btmr_get_hw_addr(uint8_t btmr_id)
{
return (uint32_t)(BTMR0_BASE) +
((uint32_t)(btmr_id) << (BTMR_INSTANCE_BITPOS));
}
/**
* btmr_sleep_en - Enable/Disable clock gating on idle of a
* timer
*
* @author sworley (8/16/2013)
*
* @param tmr_id zero based timer ID.
* @param pwr_on boolean true=ON, false=OFF
*/
void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en)
{
uint32_t sleep_mask;
uint32_t volatile * p;
sleep_mask = 0ul;
if ( btmr_valid(tmr_id) ) {
if (btmr_slp_info[tmr_id].slp_reg) {
p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN2);
} else {
p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN);
}
sleep_mask = (1ul << btmr_slp_info[tmr_id].bit_pos);
if (sleep_en) {
*p |= (sleep_mask);
} else {
*p &= ~(sleep_mask);
}
}
}
/**
* btmr_reset - Peform soft reset of specified timer.
*
* @author sworley
*
* @param tmr_id 0-based Timer ID
* @note Soft reset set all registers to POR values.
* Spins 256 times waiting on hardware to clear reset bit.
*/
void btmr_reset(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint32_t wait_cnt;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL = (BTMR_CNTL_SOFT_RESET);
wait_cnt = 256ul;
do {
if ( 0ul == (p->CONTROL & BTMR_CNTL_SOFT_RESET) ) {
break;
}
}
while ( wait_cnt-- );
}
}
/**
* btmr_init - Initialize specified timer
* @param zero based timer ID
* @param tmr_cntl b[15:0] = timer configuration flags.
* @param initial_count
* @param preload_count
* @note performs a soft reset of the timer before
* configuration.
*/
void btmr_init(uint8_t tmr_id,
uint16_t tmr_cntl,
uint16_t prescaler,
uint32_t initial_count,
uint32_t preload_count)
{
BTMR_TypeDef * pTMR;
pTMR = NULL;
if (btmr_valid(tmr_id)) {
btmr_reset(tmr_id);
pTMR = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
// Ungate timer clocks and program prescale
pTMR->CONTROL = ((uint32_t)prescaler << 16) + (BTMR_CNTL_ENABLE);
// Program Preload & initial counter value
pTMR->PRELOAD = preload_count;
pTMR->COUNT = initial_count;
// Program control register, interrupt enable, and clear status
if (tmr_cntl & BTMR_COUNT_UP) {
pTMR->CONTROL |= BTMR_CNTL_COUNT_UP;
}
if (tmr_cntl & BTMR_AUTO_RESTART) {
pTMR->CONTROL |= BTMR_CNTL_AUTO_RESTART;
}
if (tmr_cntl & BTMR_INT_EN) {
pTMR->INTEN = 0x01u; // enable first
pTMR->STATUS = 0x01u; // clear status
}
}
}
/**
* btmr_ien - Enable specified timer's interrupt.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @param ien Non-zero enable interrupt in timer block, 0
* disable.
* @note Write 0 or 1 to timer's INTEN register.
*/
void btmr_ien(uint8_t tmr_id, uint8_t ien)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if (ien) {
p->INTEN = (BTMR_INTEN);
} else {
p->INTEN = (BTMR_INTDIS);
}
}
}
/**
* tmr_get_clr_ists - Read Timer interrupt status and clear if
* set.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint8_t true (Timer interrupt status set) else false.
* @note If timer interrupt status is set then clear it before
* returning.
*/
uint8_t btmr_get_clr_ists(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint8_t rc;
rc = (MEC14XX_FALSE);
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if ( p->STATUS ) {
p->STATUS = (BTMR_STATUS_ACTIVE);
rc = true;
}
}
return rc;
}
/**
* btmr_reload - Force timer to reload counter from preload
* register.
*
* @param tmr_id zero based timer ID.
* @note Hardware will only reload counter if timer is running.
*/
void btmr_reload(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if (p->CONTROL & BTMR_CNTL_START) {
p->CONTROL |= BTMR_CNTL_RELOAD;
}
}
}
/**
* btmr_set_count - Program timer's counter register.
*
* @author sworley
*
* @param tmr_id zero based timer ID
* @param count new counter value
* @note Timer hardware may implement a 16-bit or 32-bit
* hardware counter. If the timer is 16-bit only the lower
* 16-bits of the count paramter are used.
*/
void btmr_set_count(uint8_t tmr_id, uint32_t count)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->COUNT = count;
}
}
/**
* btmr_count - Return current value of timer's count register.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint32_t timer count may be 32 or 16 bits depending
* upon the hardware. On MEC1322 Timers 0-3 are 16-bit
* and Timers 4-5 are 32-bit.
*/
uint32_t btmr_count(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint32_t cnt;
cnt = 0ul;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
cnt = (uint32_t)(p->COUNT);
}
return cnt;
}
/**
* btmr_start - Start timer counting.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*/
void btmr_start(uint8_t btmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(btmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(btmr_id);
p->CONTROL |= BTMR_CNTL_START;
}
}
/**
* btmr_stop - Stop timer.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @note When a stopped timer is started again it will reload
* the count register from preload value.
*/
void btmr_stop(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL &= ~(BTMR_CNTL_START);
}
}
/**
* btmr_is_stopped - Return state of timer's START bit.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint8_t false(timer not started), true(timer started)
*/
uint8_t btmr_is_stopped(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint8_t rc;
rc = (MEC14XX_TRUE);
if (btmr_valid(tmr_id)) {
rc = (MEC14XX_FALSE);
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if ((p->CONTROL & BTMR_CNTL_START) == 0) {
rc = (MEC14XX_TRUE);
}
}
return rc;
}
/**
* btmr_halt - Halt timer counting with no reload on unhalt.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @note A halted timer will not reload the count register when
* unhalted, it will continue counting from the current
* count value.
*/
void btmr_halt(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL |= (BTMR_CNTL_HALT);
}
}
/**
* btmr_unhalt - Unhalt timer counting.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*/
void btmr_unhalt(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL &= ~(BTMR_CNTL_HALT);
}
}
/* end mec14xx_timers.c */
/** @}
*/

616
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S Normal file
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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crt0.S
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#include <xc.h>
#include <cp0defs.h>
/* MEC14xx */
#define PIC32_SRS_SET_COUNT 1
#define INIT_SSX
#undef INIT_MMU_MZ_FIXED
#undef INIT_L1_CACHE
/* MEC14xx fill stack with sentinel value */
#define EN_STACK_FILL */
#if (__XC32_VERSION > 1000) && !defined(CPP_INIT)
#define CPP_INIT
#endif
#if !defined(PIC32_SRS_SET_COUNT)
# warning PIC32_SRS_SET_COUNT not defined on build line
# define PIC32_SRS_SET_COUNT 2
#endif
#if !defined(STACK_FILL_VALUE)
# define STACK_FILL_VALUE 0xDEADBEEFul
#endif
/* This file contains 32-bit assembly code */
.set nomips16
##################################################################
# Entry point of the entire application
##################################################################
.section .reset,code,keep
.align 2
.set noreorder
.ent _reset
############################
# Begin ISA switching code #
############################
#if defined(__PIC32_HAS_MICROMIPS) || defined(__mips_micromips)
#if defined (__mips_micromips)
.set micromips
#endif
_reset:
.word 0x10000003 /* MIPS32: branch to 0xBFC00010 from here */
/* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop) */
/* DO NOT change the relative branch */
.word 0x00000000 /* NOP */
__reset_micromips_isa:
.set micromips
jal _startup
nop
.align 2
/* Device not in proper ISA mode */
.set nomicromips
__reset_switch_isa:
jal _startup
nop
#else
_reset:
jal _startup
nop
#endif /* __PIC32_HAS_MICROMIPS */
.align 2
.end _reset
.globl _reset
.size _reset, .-_reset
.section .reset.startup,code,keep
.align 2
.set noreorder
#if defined (__mips_micromips)
.set micromips
#else
.set nomicromips
#endif
############################
# End ISA switching code #
############################
##################################################################
# Startup code
##################################################################
.align 2
.set noreorder
.ent _startup
_startup:
##################################################################
# New - Set BEV=1 for the cases where M14K instruction pointer
# is changed to force ROM to run again. CP0.BEV must be 1 to
# safely write CP0.EBASE
##################################################################
mfc0 k0, _CP0_STATUS
lui k1, 0x0040
or k0, k0, k1 # CP0.STATUS.BEV(bit[22]) = 1
mtc0 k0, _CP0_STATUS
ehb
##################################################################
# Initialize Stack Pointer
# _stack is initialized by the linker script to point to the
# starting location of the stack in DRM
##################################################################
la sp,_stack
##################################################################
# Initialize Global Pointer
# _gp is initialized by the linker script to point to "middle"
# of the small variables region
##################################################################
la gp,_gp
#if (PIC32_SRS_SET_COUNT == 2)
##################################################################
# Initialize Global Pointer in Shadow Set
# The SRSCtl's PSS field must be set to the shadow set in which
# to initialize the global pointer. Since we have only a
# single shadow set (besides the normal), we will initialize
# SRSCtl<PSS> to SRSCtl<HSS>. We then write the global pointer
# to the previous shadow set to ensure that on interrupt, the
# global pointer has been initialized.
##################################################################
mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
add t3,t1,zero # Save off current SRSCtl
ext t2,t1,26,4 # to obtain HSS field
ins t1,t2,6,4 # Put HSS field
mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
ehb # Clear hazard before using new SRSCTL
wrpgpr gp,gp # Set global pointer in PSS
mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
ehb
#elif (PIC32_SRS_SET_COUNT > 2)
##################################################################
# Initialize Global Pointer in Shadow Set(s)
# The SRSCtl PSS field must be set to the shadow set in which
# to initialize the global pointer. We will initialize
# SRSCtl<PSS> to the number of reg sets and work down to set zero.
# We write the global pointer to the previous shadow set to
# ensure that on interrupt, the global pointer has been
# initialized.
##################################################################
mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
add t3,t1,zero # Save off current SRSCtl
li t2,(PIC32_SRS_SET_COUNT-1)
1: ins t1,t2,6,4 # Put next shadow set field
mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
ehb # Clear hazard before using new SRSCTL
wrpgpr gp,gp # Set global pointer in PSS
addiu t2,t2,-1 # Next lower shadow set
# Loop for all sets
bne t2,$0,1b # Down to zero (normal GPR set)
nop
mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
ehb
#endif /* (PIC32_SRS_SET_COUNT > 2) */
##################################################################
# Call the "on reset" procedure
##################################################################
la t0,_on_reset
jalr t0
nop
#if defined(INIT_MMU_MZ_FIXED)
##################################################################
# Initialize TLB for fixed mapping to EBI and SQI
##################################################################
.extern __pic32_tlb_init_ebi_sqi
la t0,__pic32_tlb_init_ebi_sqi
jalr t0
nop
#endif
#if defined(INIT_L1_CACHE)
##################################################################
# Initialize L1 cache register
##################################################################
.extern __pic32_init_cache
la t0,__pic32_init_cache
jalr t0
nop
#endif
#if defined(EN_STACK_FILL)
##################################################################
# Fill stack
# TODO - handle different stack lengths:
# mulitple of 4, 8, 16, or 32
##################################################################
la t0,_stack_start
la t1,_stack
b _stack_check
_stack_init:
sw zero,0x0(t0)
sw zero,0x4(t0)
sw zero,0x8(t0)
sw zero,0xc(t0)
addu t0,16
_stack_check:
bltu t0,t1,_stack_init
nop
#endif
##################################################################
# Clear uninitialized data sections
##################################################################
la t0,_bss_begin
la t1,_bss_end
b _bss_check
nop
_bss_init:
sw zero,0x0(t0)
sw zero,0x4(t0)
sw zero,0x8(t0)
sw zero,0xc(t0)
addu t0,16
_bss_check:
bltu t0,t1,_bss_init
nop
##################################################################
# Initialize data using the linker-generated .dinit table
##################################################################
.equiv FMT_CLEAR,0
.equiv FMT_COPY,1
_dinit_init:
la t0,_dinit_addr
#define SRC t0
#define DST t1
#define LEN t2
#define FMT t3
0: lw DST,0(SRC)
beqz DST,9f
addu SRC,4
lw LEN,0(SRC)
addu SRC,4
lw FMT,0(SRC)
beq FMT,$0,_dinit_clear
addu SRC,4
_dinit_copy:
lbu t4,0(SRC)
subu LEN,1
addu SRC,1
sb t4,0(DST)
bne LEN,$0,_dinit_copy
addu DST,1
b _dinit_end
nop
_dinit_clear:
sb $0,(DST)
subu LEN,1
bne LEN,$0,_dinit_clear
addu DST,1
_dinit_end:
addu SRC,3
addiu LEN,$0,0xFFFFFFFC
and SRC,LEN,SRC
lw DST,0(SRC)
bne DST,$0,0b
nop
9:
##################################################################
# If there are no RAM functions, skip the next section --
# initializing bus matrix registers.
##################################################################
la t1,_ramfunc_begin
beqz t1,_ramfunc_done
nop
#if defined(INIT_SSX)
/* No initialization required */
#else /* Use BMX */
##################################################################
# Initialize bus matrix registers if RAM functions exist in the
# application
##################################################################
la t1,_bmxdkpba_address
la t2,BMXDKPBA
sw t1,0(t2)
la t1,_bmxdudba_address
la t2,BMXDUDBA
sw t1,0(t2)
la t1,_bmxdupba_address
la t2,BMXDUPBA
sw t1,0(t2)
#endif /* INIT_SSX */
_ramfunc_done:
##################################################################
# Initialize CP0 registers
##################################################################
# Initialize Count register
##################################################################
mtc0 zero,_CP0_COUNT
##################################################################
# Initialize Compare register
##################################################################
li t2,-1
mtc0 t2,_CP0_COMPARE
##################################################################
# Initialize EBase register
##################################################################
la t1,_ebase_address
mtc0 t1,_CP0_EBASE
##################################################################
# Initialize IntCtl register
##################################################################
la t1,_vector_spacing
li t2,0 # Clear t2 and
ins t2,t1,5,5 # shift value to VS field
mtc0 t2,_CP0_INTCTL
##################################################################
# Initialize CAUSE registers
# - Enable counting of Count register <DC = 0>
# - Use special exception vector <IV = 1>
# - Clear pending software interrupts <IP1:IP0 = 0>
##################################################################
li t1,0x00800000
mtc0 t1,_CP0_CAUSE
##################################################################
# Initialize STATUS register
# - Access to Coprocessor 0 not allowed in user mode <CU0 = 0>
# - User mode uses configured endianness <RE = 0>
# - Preserve Bootstrap Exception vectors <BEV>
# - Preserve soft reset <SR> and non-maskable interrupt <NMI>
# - CorExtend enabled based on whether CorExtend User Defined
# Instructions have been implemented <CEE = Config<UDI>>
# - Disable any pending interrups <IM7..IM2 = 0, IM1..IM0 = 0>
# - Disable hardware interrupts <IPL7:IPL2 = 0>
# - Base mode is Kernel mode <UM = 0>
# - Error level is normal <ERL = 0>
# - Exception level is normal <EXL = 0>
# - Interrupts are disabled <IE = 0>
# - DSPr2 ASE is enabled for devices that support it <MX = 1>
##################################################################
mfc0 t0,_CP0_CONFIG
ext t1,t0,22,1 # Extract UDI from Config register
sll t1,t1,17 # Move UDI to Status.CEE location
mfc0 t0,_CP0_STATUS
and t0,t0,0x00580000 # Preserve SR, NMI, and BEV
#if defined(INIT_DSPR2)
li t2, 0x01000000 # Set the Status.MX bit to enable DSP
or t0,t2,t0
#endif
or t0,t1,t0 # Include Status.CEE (from UDI)
mtc0 t0,_CP0_STATUS
##################################################################
# Call the "on bootstrap" procedure
##################################################################
la t0,_on_bootstrap
jalr t0
nop
##################################################################
# Initialize Status<BEV> for normal exception vectors
##################################################################
mfc0 t0,_CP0_STATUS
and t0,t0,0xffbfffff # Clear BEV
mtc0 t0,_CP0_STATUS
##################################################################
# Call main. We do this via a thunk in the text section so that
# a normal jump and link can be used, enabling the startup code
# to work properly whether main is written in MIPS16 or MIPS32
# code. I.e., the linker will correctly adjust the JAL to JALX if
# necessary
##################################################################
and a0,a0,0
and a1,a1,0
la t0,_main_entry
jr t0
nop
.end _startup
##################################################################
# General Exception Vector Handler
# Jumps to _general_exception_context
##################################################################
.section .gen_handler,code
.set noreorder
.ent _gen_exception
_gen_exception:
0: la k0,_general_exception_context
jr k0
nop
.end _gen_exception
#if defined(INIT_MMU_MZ_FIXED)
##################################################################
# Simple TLB-Refill Exception Vector
# Jumps to _simple_tlb_refill_exception_context
##################################################################
.section .simple_tlb_refill_vector,code,keep
.set noreorder
.ent simple_tlb_refill_vector
simple_tlb_refill_vector:
la k0,_simple_tlb_refill_exception_context
jr k0
nop
.end simple_tlb_refill_vector
#endif
#if defined(INIT_L1_CACHE)
##################################################################
# Cache-Error Exception Vector Handler
# Jumps to _cache_err_exception_context
##################################################################
.section .cache_err_vector,code,keep
.set noreorder
.ent _cache_err_vector
_cache_err_vector:
la k0,_cache_err_exception_context
jr k0
nop
.end _cache_err_vector
#endif
.section .text.main_entry,code,keep
.ent _main_entry
_main_entry:
#if defined(CPP_INIT)
.weak _init
# call .init section to run constructors etc
lui a0,%hi(_init)
addiu sp,sp,-24
addiu a0,a0,%lo(_init)
beq a0,$0,2f
sw $31,20(sp) #,
jalr a0
nop
2:
#endif
and a0,a0,0
and a1,a1,0
##################################################################
# Call main
##################################################################
jal main
nop
#if defined(CALL_EXIT)
##################################################################
# Call exit()
##################################################################
jal exit
nop
#endif
##################################################################
# Just in case, go into infinite loop
# Call a software breakpoint only with -mdebugger compiler option
##################################################################
.weak __exception_handler_break
__crt0_exit:
1:
la v0,__exception_handler_break
beq v0,0,0f
nop
jalr v0
nop
0: b 1b
nop
.globl __crt0_exit
.end _main_entry
###############################################################
# launch_fw
###############################################################
.globl rom_launch_fw
.set nomips16
.set micromips
.ent rom_launch_fw
.type rom_launch_fw, @function
rom_launch_fw:
.set noreorder
.set nomacro
lfw1:
di
lfw2:
ehb
lfw3:
nop
# turn off core timer
lfw4:
mfc0 t0, _CP0_CAUSE
lfw5:
lui t1, 0xf7ff
lfw6:
ori t1, t1, 0xffff
lfw7:
and t0, t0, t1
lfw8:
mtc0 t0, _CP0_CAUSE
lfw9:
ehb
lfw10:
nop
lfw11:
mfc0 t0, _CP0_STATUS
lfw12:
lui t1, 0x0040
lfw13:
or t0, t0, t1 # BEV(bit[22]) = 1
lfw14:
mtc0 t0, _CP0_STATUS
lfw15:
ehb
lfw16:
nop
lfw17:
JR.HB a0
lfw18:
nop
0:
j 0b # should not get here
lfw19:
nop
.set macro
.set reorder
.end rom_launch_fw
.size rom_launch_fw, .-rom_launch_fw

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S Normal file
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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crti.s
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#ifdef __LIBBUILD__
# Replace the standard debugging information with a simple filename. This
# prevents the library build directory from showing up in MPLAB IDE. It
# also effectively disables source-line debugging.
.file 1 "libpic32/startup/crti.s"
.loc 1 0
#endif
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
.section .init, code
.globl _init
.type _init,@function
_init:
addu $sp,$sp,-32
sw $31,20($sp)
.section .fini, code
.globl _fini
.type _fini,@function
_fini:
addu $sp,$sp,-32
sw $31,20($sp)

62
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S Normal file
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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crtn.s
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#ifdef __LIBBUILD__
# Replace the standard debugging information with a simple filename. This
# prevents the library build directory from showing up in MPLAB IDE. It
# also effectively disables source-line debugging.
.file 1 "libpic32/startup/crtn.s"
.loc 1 0
#endif
.section .init, code
lw $31,20($sp)
addu $sp,$sp,32
j $31
.section .fini, code
lw $31,20($sp)
addu $sp,$sp,32
j $31

43
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/default-on-bootstrap.c Normal file
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/*********************************************************************
*
* Default _on_bootstrap Implementation
*
*********************************************************************
* Filename: default-on-bootstrap.c
*
* Processor: PIC32
*
* Compiler: MPLAB C Compiler for PIC32 MCUs
* MPLAB IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* The software supplied herewith by Microchip Technology Incorporated
* (the 'Company') for its PIC32/PIC24F Microcontroller is intended
* and supplied to you, the Company's customer, for use solely and
* exclusively on Microchip PIC32/PIC24F Microcontroller products.
* The software is owned by the Company and/or its supplier, and is
* protected under applicable copyright laws. All rights are reserved.
* Any use in violation of the foregoing restrictions may subject the
* user to criminal sanctions under applicable laws, as well as to
* civil liability for the breach of the terms and conditions of this
* license.
*
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
********************************************************************/
/* This is a default definition of an _on_bootstrap() function.
* It does nothing and just goes returns. If the user
* application supplies a handler function, this function will not be
* referenced and thus not pulled in from the library.
*/
void
_on_bootstrap (void)
{
}

63
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/on_reset.c Normal file
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file on_reset.c
*MEC14xx XC32 M14K Startup code _on_reset handler
*/
/** @defgroup MEC14xx Startup
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
/*
* From linker command file
*/
extern uint32_t _ebase_address[];
/** _on_reset - Very early HW initialization.
* @note XC32 startup code has initialized SP & GP. No other
* C features have been initialized (before .bss clear and
* global data init.) NOTE: MIPS M14K is still in Boot-Strap
* mode and EBASE has not been programmed. Any exception or
* interrupts will vector to the BEV Exception handler!
*/
void
__attribute__((nomips16)) _on_reset (void)
{
/* Enable JTAG */
ECS_REG->JTAG_ENABLE |= 1u;
/* Disable WDT */
WDT->CONTROL = 0u;
/* Set CPU clock divider specified in appcfg.h */
PCR->PROC_CLOCK_CNTRL = ( PCR_CLOCK_DIVIDER );
__EHB();
CPU_NOP();
}