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Update platform studio project for MicroBlaze with full Ethernet.

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This commit is contained in:
Richard Barry 2011-08-27 11:55:55 +00:00
parent dbb0c1d13a
commit a16be7fb4e
15 changed files with 19223 additions and 197 deletions
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12
Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs
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@ -126,7 +126,7 @@ BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
PARAMETER HW_VER = 3.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END
@ -135,7 +135,7 @@ BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
PARAMETER HW_VER = 3.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END
@ -201,7 +201,7 @@ BEGIN mdm
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
PARAMETER C_BASEADDR = 0x74800000
PARAMETER C_HIGHADDR = 0x7480ffff
PARAMETER C_HIGHADDR = 0x748FFFFF
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
@ -273,12 +273,7 @@ BEGIN axi_s6_ddrx
PARAMETER HW_VER = 1.02.a
PARAMETER C_MCB_RZQ_LOC = K7
PARAMETER C_MCB_ZIO_LOC = R7
PARAMETER C_MEM_TYPE = DDR3
PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E
PARAMETER C_MEM_BANKADDR_WIDTH = 3
PARAMETER C_MEM_NUM_COL_BITS = 10
PARAMETER C_SKIP_IN_TERM_CAL = 0
PARAMETER C_S0_AXI_ENABLE = 1
PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1
PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1
@ -287,6 +282,7 @@ BEGIN axi_s6_ddrx
PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1
PARAMETER C_S0_AXI_BASEADDR = 0x80000000
PARAMETER C_S0_AXI_HIGHADDR = 0x87ffffff
PARAMETER C_S0_AXI_STRICT_COHERENCY = 0
BUS_INTERFACE S0_AXI = axi4_0
PORT mcbx_dram_clk = mcbx_dram_clk
PORT mcbx_dram_clk_n = mcbx_dram_clk_n