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Fix compiler warning in psp_test.c when compiled with ARM compiler.
Add portYIELD_FROM_ISR() macros to Cortex-M ports. The new macro just calls the exiting portEND_SWITCHING_ISR() macro. Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
This commit is contained in:
Richard Barry
parent
9b153b3e06
commit
a03b171992
12 changed files with 73 additions and 72 deletions
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@ -56,19 +56,19 @@
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
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fully thread aware and reentrant UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
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indemnification and middleware, under the OpenRTOS brand.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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@ -121,6 +121,7 @@ extern void vPortYield( void );
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -56,19 +56,19 @@
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
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fully thread aware and reentrant UDP/IP stack.
|
||||
|
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
|
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
|
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indemnification and middleware, under the OpenRTOS brand.
|
||||
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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@ -121,6 +121,7 @@ extern void vPortYield( void );
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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@ -56,19 +56,19 @@
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
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license and Real Time Engineers Ltd. contact details.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
||||
fully thread aware and reentrant UDP/IP stack.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
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Integrity Systems, who sell the code with commercial support,
|
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
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Integrity Systems, who sell the code with commercial support,
|
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indemnification and middleware, under the OpenRTOS brand.
|
||||
|
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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@ -162,6 +162,7 @@ typedef struct MPU_SETTINGS
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#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )
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#define portNVIC_PENDSVSET 0x10000000
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -181,7 +182,7 @@ typedef struct MPU_SETTINGS
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/*
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* Set basepri back to 0 without effective other registers.
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
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*/
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#define portCLEAR_INTERRUPT_MASK() \
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@ -192,7 +193,7 @@ typedef struct MPU_SETTINGS
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:::"r0" \
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)
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
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@ -213,7 +214,7 @@ extern void vPortExitCritical( void );
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#define portNOP()
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/* There are an uneven number of items on the initial stack, so
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/* There are an uneven number of items on the initial stack, so
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portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */
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#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )
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@ -121,6 +121,7 @@ extern void vPortYield( void );
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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