mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Riscv re-factoring (#444)
* Refactor RISCV port Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Changes to make re-factoring work on ESP32-C3 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Remove alignment and place handlers in separate sections Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Correct section names This is needed so that the assemblers correctly recognizes functions. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move mtvec programming to the application Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Refactor mtimer udpate code Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move critical nesting to port layer Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Respect configTASK_RETURN_ADDRESS Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Formatting changes Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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Gaurav-Aggarwal-AWS
GitHub
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_SIFIVE_CLINT 0
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#define portasmHAS_MTIME 0
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#define portasmADDITIONAL_CONTEXT_SIZE 0
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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/* No additional registers to save, so this macro does nothing. */
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* No additional registers to restore, so this macro does nothing. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -27,7 +27,7 @@
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*/
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*/
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/*-----------------------------------------------------------
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the RISC-V RV32 port.
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* Implementation of functions defined in portable.h for the RISC-V port.
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*----------------------------------------------------------*/
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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/* Scheduler includes. */
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@ -39,44 +39,42 @@
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#include "string.h"
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#include "string.h"
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#ifdef configCLINT_BASE_ADDRESS
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#ifdef configCLINT_BASE_ADDRESS
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#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#endif
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#ifndef configMTIME_BASE_ADDRESS
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#ifndef configMTIME_BASE_ADDRESS
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#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#endif
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#ifndef configMTIMECMP_BASE_ADDRESS
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#ifndef configMTIMECMP_BASE_ADDRESS
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#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#endif
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/* Let the user override the pre-loading of the initial LR with the address of
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/* Let the user override the pre-loading of the initial RA. */
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#define portTASK_RETURN_ADDRESS 0
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#endif
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#endif
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/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
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/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
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to use a statically allocated array as the interrupt stack. Alternative leave
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* to use a statically allocated array as the interrupt stack. Alternative leave
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configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
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* configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
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linker variable names __freertos_irq_stack_top has the same value as the top
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* linker variable names __freertos_irq_stack_top has the same value as the top
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of the stack used by main. Using the linker script method will repurpose the
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* of the stack used by main. Using the linker script method will repurpose the
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stack that was used by main before the scheduler was started for use as the
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* stack that was used by main before the scheduler was started for use as the
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interrupt stack after the scheduler has started. */
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* interrupt stack after the scheduler has started. */
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#ifdef configISR_STACK_SIZE_WORDS
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#ifdef configISR_STACK_SIZE_WORDS
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
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const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
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the task stacks, and so will legitimately appear in many positions within
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the task stacks, and so will legitimately appear in many positions within
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the ISR stack. */
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the ISR stack. */
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#define portISR_STACK_FILL_BYTE 0xee
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#define portISR_STACK_FILL_BYTE 0xee
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#else
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#else
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extern const uint32_t __freertos_irq_stack_top[];
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extern const uint32_t __freertos_irq_stack_top[];
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const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
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const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
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#endif
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#endif
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/*
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/*
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uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
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uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
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volatile uint64_t * pullMachineTimerCompareRegister = NULL;
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volatile uint64_t * pullMachineTimerCompareRegister = NULL;
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/* Holds the critical nesting value - deliberately non-zero at start up to
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* ensure interrupts are not accidentally enabled before the scheduler starts. */
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size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa;
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size_t *pxCriticalNesting = &xCriticalNesting;
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/* Used to catch tasks that attempt to return from their implementing function. */
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size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
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/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
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/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
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stack checking. A problem in the ISR stack will trigger an assert, not call the
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* stack checking. A problem in the ISR stack will trigger an assert, not call
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stack overflow hook function (because the stack overflow hook is specific to a
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* the stack overflow hook function (because the stack overflow hook is specific
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task stack, not the ISR stack). */
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* to a task stack, not the ISR stack). */
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#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#warning This path not tested, or even compiled yet.
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#warning This path not tested, or even compiled yet.
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static const uint8_t ucExpectedStackBytes[] = {
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static const uint8_t ucExpectedStackBytes[] = {
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
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#else
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#else
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/* Define the function away. */
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/* Define the function away. */
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#define portCHECK_ISR_STACK()
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#define portCHECK_ISR_STACK()
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
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#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
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void vPortSetupTimerInterrupt( void )
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void vPortSetupTimerInterrupt( void )
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{
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{
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
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volatile uint32_t ulHartId;
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volatile uint32_t ulHartId;
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__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
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__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
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pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
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pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
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do
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do
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{
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{
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ulCurrentTimeHigh = *pulTimeHigh;
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ulCurrentTimeHigh = *pulTimeHigh;
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ulCurrentTimeLow = *pulTimeLow;
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ulCurrentTimeLow = *pulTimeLow;
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} while( ulCurrentTimeHigh != *pulTimeHigh );
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} while( ulCurrentTimeHigh != *pulTimeHigh );
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ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
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ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
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ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
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ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
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ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
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ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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*pullMachineTimerCompareRegister = ullNextTime;
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*pullMachineTimerCompareRegister = ullNextTime;
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/* Prepare the time to use after the next tick interrupt. */
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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}
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}
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#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
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#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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@ -152,62 +158,46 @@ BaseType_t xPortStartScheduler( void )
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{
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{
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extern void xPortStartFirstTask( void );
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extern void xPortStartFirstTask( void );
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#if( configASSERT_DEFINED == 1 )
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#if( configASSERT_DEFINED == 1 )
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{
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{
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volatile uint32_t mtvec = 0;
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/* Check alignment of the interrupt stack - which is the same as the
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* stack that was being used by main() prior to the scheduler being
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* started. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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/* Check the least significant two bits of mtvec are 00 - indicating
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#ifdef configISR_STACK_SIZE_WORDS
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single vector mode. */
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{
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__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
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memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
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configASSERT( ( mtvec & 0x03UL ) == 0 );
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}
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#endif /* configISR_STACK_SIZE_WORDS */
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}
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#endif /* configASSERT_DEFINED */
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/* Check alignment of the interrupt stack - which is the same as the
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/* If there is a CLINT then it is ok to use the default implementation
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stack that was being used by main() prior to the scheduler being
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* in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
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started. */
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* configure whichever clock is to be used to generate the tick interrupt. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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vPortSetupTimerInterrupt();
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#ifdef configISR_STACK_SIZE_WORDS
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#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
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{
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{
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memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt,
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}
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* 1<<11 for external interrupt. _RB_ What happens here when mtime is
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#endif /* configISR_STACK_SIZE_WORDS */
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* not present as with pulpino? */
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}
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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#endif /* configASSERT_DEFINED */
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}
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#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
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|
|
||||||
/* If there is a CLINT then it is ok to use the default implementation
|
xPortStartFirstTask();
|
||||||
in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
|
|
||||||
configure whichever clock is to be used to generate the tick interrupt. */
|
|
||||||
vPortSetupTimerInterrupt();
|
|
||||||
|
|
||||||
#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
|
/* Should not get here as after calling xPortStartFirstTask() only tasks
|
||||||
{
|
* should be executing. */
|
||||||
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
|
return pdFAIL;
|
||||||
for external interrupt. _RB_ What happens here when mtime is not present as
|
|
||||||
with pulpino? */
|
|
||||||
__asm volatile( "csrs mie, %0" :: "r"(0x880) );
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
{
|
|
||||||
/* Enable external interrupts. */
|
|
||||||
__asm volatile( "csrs mie, %0" :: "r"(0x800) );
|
|
||||||
}
|
|
||||||
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
|
|
||||||
|
|
||||||
xPortStartFirstTask();
|
|
||||||
|
|
||||||
/* Should not get here as after calling xPortStartFirstTask() only tasks
|
|
||||||
should be executing. */
|
|
||||||
return pdFAIL;
|
|
||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
void vPortEndScheduler( void )
|
void vPortEndScheduler( void )
|
||||||
{
|
{
|
||||||
/* Not implemented. */
|
/* Not implemented. */
|
||||||
for( ;; );
|
for( ;; );
|
||||||
}
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,444 +1,376 @@
|
||||||
/*
|
/*
|
||||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: MIT
|
* SPDX-License-Identifier: MIT
|
||||||
*
|
*
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
* this software and associated documentation files (the "Software"), to deal in
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
* the Software without restriction, including without limitation the rights to
|
* the Software without restriction, including without limitation the rights to
|
||||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
* subject to the following conditions:
|
* subject to the following conditions:
|
||||||
*
|
*
|
||||||
* The above copyright notice and this permission notice shall be included in all
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
* copies or substantial portions of the Software.
|
* copies or substantial portions of the Software.
|
||||||
*
|
*
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
*
|
*
|
||||||
* https://www.FreeRTOS.org
|
* https://www.FreeRTOS.org
|
||||||
* https://github.com/FreeRTOS
|
* https://github.com/FreeRTOS
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
* common across all currently supported RISC-V chips (implementations of the
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
|
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
|
||||||
*
|
*
|
||||||
* + The code that is common to all RISC-V chips is implemented in
|
* + The code that is common to all RISC-V chips is implemented in
|
||||||
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
|
||||||
* portASM.S file because the same file is used no matter which RISC-V chip is
|
* portASM.S file because the same file is used no matter which RISC-V chip is
|
||||||
* in use.
|
* in use.
|
||||||
*
|
*
|
||||||
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
|
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
|
||||||
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
|
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
|
||||||
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
|
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
|
||||||
* RISC-V chip that both includes a standard CLINT and does not add to the
|
* RISC-V chip that both includes a standard CLINT and does not add to the
|
||||||
* base set of RISC-V registers. There are additional
|
* base set of RISC-V registers. There are additional
|
||||||
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
|
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
|
||||||
* that do not include a standard CLINT or do add to the base set of RISC-V
|
* that do not include a standard CLINT or do add to the base set of RISC-V
|
||||||
* registers.
|
* registers.
|
||||||
*
|
*
|
||||||
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
|
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
|
||||||
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
|
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
|
||||||
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
|
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
|
||||||
* header file ensure the path to the correct header file is in the assembler's
|
* header file ensure the path to the correct header file is in the assembler's
|
||||||
* include path.
|
* include path.
|
||||||
*
|
*
|
||||||
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
|
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
|
||||||
* that include a standard CLINT and do not add to the base set of RISC-V
|
* that include a standard CLINT and do not add to the base set of RISC-V
|
||||||
* registers.
|
* registers.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
#if __riscv_xlen == 64
|
|
||||||
#define portWORD_SIZE 8
|
#include "portContext.h"
|
||||||
#define store_x sd
|
|
||||||
#define load_x ld
|
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
|
||||||
#elif __riscv_xlen == 32
|
definitions. */
|
||||||
#define store_x sw
|
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
|
||||||
#define load_x lw
|
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
#define portWORD_SIZE 4
|
#endif
|
||||||
#else
|
|
||||||
#error Assembler did not define __riscv_xlen
|
#ifdef portasmHAS_CLINT
|
||||||
#endif
|
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#define portasmHAS_MTIME portasmHAS_CLINT
|
||||||
#include "freertos_risc_v_chip_specific_extensions.h"
|
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
|
||||||
|
#endif
|
||||||
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
|
|
||||||
definitions. */
|
#ifndef portasmHAS_MTIME
|
||||||
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
|
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
#endif
|
||||||
#endif
|
|
||||||
|
#ifndef portasmHAS_SIFIVE_CLINT
|
||||||
#ifdef portasmHAS_CLINT
|
#define portasmHAS_SIFIVE_CLINT 0
|
||||||
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
#endif
|
||||||
#define portasmHAS_MTIME portasmHAS_CLINT
|
|
||||||
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
|
.global xPortStartFirstTask
|
||||||
#endif
|
.global pxPortInitialiseStack
|
||||||
|
.global freertos_risc_v_trap_handler
|
||||||
#ifndef portasmHAS_MTIME
|
.global freertos_risc_v_exception_handler
|
||||||
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
.global freertos_risc_v_interrupt_handler
|
||||||
#endif
|
.global freertos_risc_v_mtimer_interrupt_handler
|
||||||
|
|
||||||
#ifndef portasmHANDLE_INTERRUPT
|
.extern vTaskSwitchContext
|
||||||
#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
.extern xTaskIncrementTick
|
||||||
#endif
|
.extern pullMachineTimerCompareRegister
|
||||||
|
.extern pullNextTime
|
||||||
#ifndef portasmHAS_SIFIVE_CLINT
|
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
|
||||||
#define portasmHAS_SIFIVE_CLINT 0
|
.extern xTaskReturnAddress
|
||||||
#endif
|
|
||||||
|
.weak freertos_risc_v_application_exception_handler
|
||||||
/* Only the standard core registers are stored by default. Any additional
|
.weak freertos_risc_v_application_interrupt_handler
|
||||||
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
|
/*-----------------------------------------------------------*/
|
||||||
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
|
|
||||||
specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
|
.macro portUPDATE_MTIMER_COMPARE_REGISTER
|
||||||
at the top of this file. */
|
load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
|
||||||
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
|
load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
|
||||||
|
|
||||||
.global xPortStartFirstTask
|
#if( __riscv_xlen == 32 )
|
||||||
.global freertos_risc_v_trap_handler
|
|
||||||
.global pxPortInitialiseStack
|
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
|
||||||
.extern pxCurrentTCB
|
li t4, -1
|
||||||
.extern ulPortTrapHandler
|
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
|
||||||
.extern vTaskSwitchContext
|
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
|
||||||
.extern xTaskIncrementTick
|
sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
|
||||||
.extern Timer_IRQHandler
|
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
|
||||||
.extern pullMachineTimerCompareRegister
|
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
|
||||||
.extern pullNextTime
|
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
||||||
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
|
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
|
||||||
.extern xISRStackTop
|
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
|
||||||
.extern portasmHANDLE_INTERRUPT
|
add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
|
||||||
|
sw t4, 0(t1) /* Store new low word of ullNextTime. */
|
||||||
/*-----------------------------------------------------------*/
|
sw t6, 4(t1) /* Store new high word of ullNextTime. */
|
||||||
|
|
||||||
.align 8
|
#endif /* __riscv_xlen == 32 */
|
||||||
.func
|
|
||||||
freertos_risc_v_trap_handler:
|
#if( __riscv_xlen == 64 )
|
||||||
addi sp, sp, -portCONTEXT_SIZE
|
|
||||||
store_x x1, 1 * portWORD_SIZE( sp )
|
/* Update the 64-bit mtimer compare match value. */
|
||||||
store_x x5, 2 * portWORD_SIZE( sp )
|
ld t2, 0(t1) /* Load ullNextTime into t2. */
|
||||||
store_x x6, 3 * portWORD_SIZE( sp )
|
sd t2, 0(t0) /* Store ullNextTime into compare register. */
|
||||||
store_x x7, 4 * portWORD_SIZE( sp )
|
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
||||||
store_x x8, 5 * portWORD_SIZE( sp )
|
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
|
||||||
store_x x9, 6 * portWORD_SIZE( sp )
|
sd t4, 0(t1) /* Store ullNextTime. */
|
||||||
store_x x10, 7 * portWORD_SIZE( sp )
|
|
||||||
store_x x11, 8 * portWORD_SIZE( sp )
|
#endif /* __riscv_xlen == 64 */
|
||||||
store_x x12, 9 * portWORD_SIZE( sp )
|
.endm
|
||||||
store_x x13, 10 * portWORD_SIZE( sp )
|
/*-----------------------------------------------------------*/
|
||||||
store_x x14, 11 * portWORD_SIZE( sp )
|
|
||||||
store_x x15, 12 * portWORD_SIZE( sp )
|
/*
|
||||||
store_x x16, 13 * portWORD_SIZE( sp )
|
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
|
||||||
store_x x17, 14 * portWORD_SIZE( sp )
|
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
|
||||||
store_x x18, 15 * portWORD_SIZE( sp )
|
* for the function is as per the other ports:
|
||||||
store_x x19, 16 * portWORD_SIZE( sp )
|
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
||||||
store_x x20, 17 * portWORD_SIZE( sp )
|
*
|
||||||
store_x x21, 18 * portWORD_SIZE( sp )
|
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
||||||
store_x x22, 19 * portWORD_SIZE( sp )
|
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
||||||
store_x x23, 20 * portWORD_SIZE( sp )
|
*
|
||||||
store_x x24, 21 * portWORD_SIZE( sp )
|
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
||||||
store_x x25, 22 * portWORD_SIZE( sp )
|
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
||||||
store_x x26, 23 * portWORD_SIZE( sp )
|
*
|
||||||
store_x x27, 24 * portWORD_SIZE( sp )
|
* Register ABI Name Description Saver
|
||||||
store_x x28, 25 * portWORD_SIZE( sp )
|
* x0 zero Hard-wired zero -
|
||||||
store_x x29, 26 * portWORD_SIZE( sp )
|
* x1 ra Return address Caller
|
||||||
store_x x30, 27 * portWORD_SIZE( sp )
|
* x2 sp Stack pointer Callee
|
||||||
store_x x31, 28 * portWORD_SIZE( sp )
|
* x3 gp Global pointer -
|
||||||
|
* x4 tp Thread pointer -
|
||||||
csrr t0, mstatus /* Required for MPIE bit. */
|
* x5-7 t0-2 Temporaries Caller
|
||||||
store_x t0, 29 * portWORD_SIZE( sp )
|
* x8 s0/fp Saved register/Frame pointer Callee
|
||||||
|
* x9 s1 Saved register Callee
|
||||||
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
|
* x10-11 a0-1 Function Arguments/return values Caller
|
||||||
|
* x12-17 a2-7 Function arguments Caller
|
||||||
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
* x18-27 s2-11 Saved registers Callee
|
||||||
store_x sp, 0( t0 ) /* Write sp to first TCB member. */
|
* x28-31 t3-6 Temporaries Caller
|
||||||
|
*
|
||||||
csrr a0, mcause
|
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
||||||
csrr a1, mepc
|
* where the global and thread pointers are currently assumed to be constant so
|
||||||
|
* are not saved:
|
||||||
test_if_asynchronous:
|
*
|
||||||
srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
|
* mstatus
|
||||||
beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
|
* xCriticalNesting
|
||||||
store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
|
* x31
|
||||||
|
* x30
|
||||||
handle_asynchronous:
|
* x29
|
||||||
|
* x28
|
||||||
#if( portasmHAS_MTIME != 0 )
|
* x27
|
||||||
|
* x26
|
||||||
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
|
* x25
|
||||||
|
* x24
|
||||||
addi t0, x0, 1
|
* x23
|
||||||
|
* x22
|
||||||
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
|
* x21
|
||||||
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
|
* x20
|
||||||
bne a0, t1, test_if_external_interrupt
|
* x19
|
||||||
|
* x18
|
||||||
load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
|
* x17
|
||||||
load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
|
* x16
|
||||||
|
* x15
|
||||||
#if( __riscv_xlen == 32 )
|
* x14
|
||||||
|
* x13
|
||||||
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
|
* x12
|
||||||
li t4, -1
|
* x11
|
||||||
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
|
* pvParameters
|
||||||
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
|
* x9
|
||||||
sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
|
* x8
|
||||||
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
|
* x7
|
||||||
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
|
* x6
|
||||||
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
* x5
|
||||||
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
|
* portTASK_RETURN_ADDRESS
|
||||||
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
|
* [chip specific registers go here]
|
||||||
add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
|
* pxCode
|
||||||
sw t4, 0(t1) /* Store new low word of ullNextTime. */
|
*/
|
||||||
sw t6, 4(t1) /* Store new high word of ullNextTime. */
|
pxPortInitialiseStack:
|
||||||
|
csrr t0, mstatus /* Obtain current mstatus value. */
|
||||||
#endif /* __riscv_xlen == 32 */
|
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
||||||
|
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
||||||
#if( __riscv_xlen == 64 )
|
slli t1, t1, 4
|
||||||
|
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||||
/* Update the 64-bit mtimer compare match value. */
|
|
||||||
ld t2, 0(t1) /* Load ullNextTime into t2. */
|
addi a0, a0, -portWORD_SIZE
|
||||||
sd t2, 0(t0) /* Store ullNextTime into compare register. */
|
store_x t0, 0(a0) /* mstatus onto the stack. */
|
||||||
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
|
||||||
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
|
store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
|
||||||
sd t4, 0(t1) /* Store ullNextTime. */
|
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||||
|
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||||
#endif /* __riscv_xlen == 64 */
|
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||||
|
load_x t0, xTaskReturnAddress
|
||||||
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
store_x t0, 0(a0) /* Return address onto the stack. */
|
||||||
jal xTaskIncrementTick
|
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||||
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
|
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||||
jal vTaskSwitchContext
|
beq t0, x0, 1f /* No more chip specific registers to save. */
|
||||||
j processed_source
|
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||||
|
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||||
test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
|
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||||
addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
|
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||||
bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
|
1:
|
||||||
|
addi a0, a0, -portWORD_SIZE
|
||||||
#endif /* portasmHAS_MTIME */
|
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||||
|
ret
|
||||||
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
/*-----------------------------------------------------------*/
|
||||||
jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
|
|
||||||
j processed_source
|
xPortStartFirstTask:
|
||||||
|
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
handle_synchronous:
|
load_x sp, 0( sp ) /* Read sp from first TCB member. */
|
||||||
addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
|
|
||||||
store_x a1, 0( sp ) /* Save updated exception return address. */
|
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
||||||
|
|
||||||
test_if_environment_call:
|
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
li t0, 11 /* 11 == environment call. */
|
|
||||||
bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
|
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||||
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||||
jal vTaskSwitchContext
|
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||||
j processed_source
|
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||||
is_exception:
|
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||||
csrr t0, mcause /* For viewing in the debugger only. */
|
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||||
csrr t1, mepc /* For viewing in the debugger only */
|
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||||
csrr t2, mstatus
|
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||||
j is_exception /* No other exceptions handled yet. */
|
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||||
as_yet_unhandled:
|
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||||
csrr t0, mcause /* For viewing in the debugger only. */
|
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||||
j as_yet_unhandled
|
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||||
processed_source:
|
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||||
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
|
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||||
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
|
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||||
/* Load mret with the address of the next instruction in the task to run next. */
|
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||||
load_x t0, 0( sp )
|
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||||
csrw mepc, t0
|
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||||
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||||
/* Load mstatus with the interrupt enable bits used by the task. */
|
|
||||||
load_x t0, 29 * portWORD_SIZE( sp )
|
load_x x5, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
|
||||||
csrw mstatus, t0 /* Required for MPIE bit. */
|
load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
|
||||||
|
store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
|
||||||
load_x x1, 1 * portWORD_SIZE( sp )
|
|
||||||
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
load_x x5, 30 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
|
||||||
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
|
||||||
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
|
||||||
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
|
||||||
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
|
||||||
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
|
||||||
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
|
||||||
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
ret
|
||||||
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
/*-----------------------------------------------------------*/
|
||||||
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
|
||||||
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
freertos_risc_v_application_exception_handler:
|
||||||
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
csrr t0, mcause /* For viewing in the debugger only. */
|
||||||
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
csrr t1, mepc /* For viewing in the debugger only */
|
||||||
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
csrr t2, mstatus /* For viewing in the debugger only */
|
||||||
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
j freertos_risc_v_application_exception_handler
|
||||||
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
/*-----------------------------------------------------------*/
|
||||||
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
|
||||||
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
freertos_risc_v_application_interrupt_handler:
|
||||||
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
csrr t0, mcause /* For viewing in the debugger only. */
|
||||||
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
csrr t1, mepc /* For viewing in the debugger only */
|
||||||
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
csrr t2, mstatus /* For viewing in the debugger only */
|
||||||
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
j freertos_risc_v_application_interrupt_handler
|
||||||
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
/*-----------------------------------------------------------*/
|
||||||
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
|
||||||
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
.section .text.freertos_risc_v_exception_handler
|
||||||
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
freertos_risc_v_exception_handler:
|
||||||
addi sp, sp, portCONTEXT_SIZE
|
portcontextSAVE_EXCEPTION_CONTEXT
|
||||||
|
/* a0 now contains mcause. */
|
||||||
mret
|
li t0, 11 /* 11 == environment call. */
|
||||||
.endfunc
|
bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
|
||||||
/*-----------------------------------------------------------*/
|
call vTaskSwitchContext
|
||||||
|
portcontextRESTORE_CONTEXT
|
||||||
.align 8
|
|
||||||
.func
|
other_exception:
|
||||||
xPortStartFirstTask:
|
call freertos_risc_v_application_exception_handler
|
||||||
|
portcontextRESTORE_CONTEXT
|
||||||
#if( portasmHAS_SIFIVE_CLINT != 0 )
|
/*-----------------------------------------------------------*/
|
||||||
/* If there is a clint then interrupts can branch directly to the FreeRTOS
|
|
||||||
trap handler. Otherwise the interrupt controller will need to be configured
|
.section .text.freertos_risc_v_interrupt_handler
|
||||||
outside of this file. */
|
freertos_risc_v_interrupt_handler:
|
||||||
la t0, freertos_risc_v_trap_handler
|
portcontextSAVE_INTERRUPT_CONTEXT
|
||||||
csrw mtvec, t0
|
call freertos_risc_v_application_interrupt_handler
|
||||||
#endif /* portasmHAS_CLILNT */
|
portcontextRESTORE_CONTEXT
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
|
||||||
load_x sp, 0( sp ) /* Read sp from first TCB member. */
|
.section .text.freertos_risc_v_mtimer_interrupt_handler
|
||||||
|
freertos_risc_v_mtimer_interrupt_handler:
|
||||||
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
portcontextSAVE_INTERRUPT_CONTEXT
|
||||||
|
portUPDATE_MTIMER_COMPARE_REGISTER
|
||||||
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
call xTaskIncrementTick
|
||||||
|
beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
|
||||||
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
call vTaskSwitchContext
|
||||||
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
exit_without_context_switch:
|
||||||
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
portcontextRESTORE_CONTEXT
|
||||||
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
/*-----------------------------------------------------------*/
|
||||||
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
|
||||||
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
.section .text.freertos_risc_v_trap_handler
|
||||||
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
freertos_risc_v_trap_handler:
|
||||||
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
portcontextSAVE_CONTEXT_INTERNAL
|
||||||
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
|
||||||
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
csrr a0, mcause
|
||||||
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
csrr a1, mepc
|
||||||
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
|
||||||
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
bge a0, x0, synchronous_exception
|
||||||
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
|
||||||
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
asynchronous_interrupt:
|
||||||
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
|
||||||
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||||
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
j handle_interrupt
|
||||||
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
|
||||||
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
synchronous_exception:
|
||||||
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
|
||||||
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
store_x a1, 0( sp ) /* Save updated exception return address. */
|
||||||
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||||
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
j handle_exception
|
||||||
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
|
||||||
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
handle_interrupt:
|
||||||
|
#if( portasmHAS_MTIME != 0 )
|
||||||
load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */
|
|
||||||
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
|
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
|
||||||
csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
|
addi t0, x0, 1
|
||||||
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
|
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
|
||||||
|
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
|
||||||
addi sp, sp, portCONTEXT_SIZE
|
bne a0, t1, application_interrupt_handler
|
||||||
ret
|
|
||||||
.endfunc
|
portUPDATE_MTIMER_COMPARE_REGISTER
|
||||||
/*-----------------------------------------------------------*/
|
call xTaskIncrementTick
|
||||||
|
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
|
||||||
/*
|
call vTaskSwitchContext
|
||||||
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
|
j processed_source
|
||||||
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
|
|
||||||
* for the function is as per the other ports:
|
#endif /* portasmHAS_MTIME */
|
||||||
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
|
||||||
*
|
application_interrupt_handler:
|
||||||
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
call freertos_risc_v_application_interrupt_handler
|
||||||
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
j processed_source
|
||||||
*
|
|
||||||
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
handle_exception:
|
||||||
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
/* a0 contains mcause. */
|
||||||
*
|
li t0, 11 /* 11 == environment call. */
|
||||||
* Register ABI Name Description Saver
|
bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
|
||||||
* x0 zero Hard-wired zero -
|
call vTaskSwitchContext
|
||||||
* x1 ra Return address Caller
|
j processed_source
|
||||||
* x2 sp Stack pointer Callee
|
|
||||||
* x3 gp Global pointer -
|
application_exception_handler:
|
||||||
* x4 tp Thread pointer -
|
call freertos_risc_v_application_exception_handler
|
||||||
* x5-7 t0-2 Temporaries Caller
|
j processed_source /* No other exceptions handled yet. */
|
||||||
* x8 s0/fp Saved register/Frame pointer Callee
|
|
||||||
* x9 s1 Saved register Callee
|
processed_source:
|
||||||
* x10-11 a0-1 Function Arguments/return values Caller
|
portcontextRESTORE_CONTEXT
|
||||||
* x12-17 a2-7 Function arguments Caller
|
/*-----------------------------------------------------------*/
|
||||||
* x18-27 s2-11 Saved registers Callee
|
|
||||||
* x28-31 t3-6 Temporaries Caller
|
|
||||||
*
|
|
||||||
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
|
||||||
* where the global and thread pointers are currently assumed to be constant so
|
|
||||||
* are not saved:
|
|
||||||
*
|
|
||||||
* mstatus
|
|
||||||
* x31
|
|
||||||
* x30
|
|
||||||
* x29
|
|
||||||
* x28
|
|
||||||
* x27
|
|
||||||
* x26
|
|
||||||
* x25
|
|
||||||
* x24
|
|
||||||
* x23
|
|
||||||
* x22
|
|
||||||
* x21
|
|
||||||
* x20
|
|
||||||
* x19
|
|
||||||
* x18
|
|
||||||
* x17
|
|
||||||
* x16
|
|
||||||
* x15
|
|
||||||
* x14
|
|
||||||
* x13
|
|
||||||
* x12
|
|
||||||
* x11
|
|
||||||
* pvParameters
|
|
||||||
* x9
|
|
||||||
* x8
|
|
||||||
* x7
|
|
||||||
* x6
|
|
||||||
* x5
|
|
||||||
* portTASK_RETURN_ADDRESS
|
|
||||||
* [chip specific registers go here]
|
|
||||||
* pxCode
|
|
||||||
*/
|
|
||||||
.align 8
|
|
||||||
.func
|
|
||||||
pxPortInitialiseStack:
|
|
||||||
|
|
||||||
csrr t0, mstatus /* Obtain current mstatus value. */
|
|
||||||
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
|
||||||
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
|
||||||
slli t1, t1, 4
|
|
||||||
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
|
||||||
|
|
||||||
addi a0, a0, -portWORD_SIZE
|
|
||||||
store_x t0, 0(a0) /* mstatus onto the stack. */
|
|
||||||
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
|
||||||
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
|
||||||
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
|
||||||
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
|
||||||
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
|
||||||
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
|
||||||
beq t0, x0, 1f /* No more chip specific registers to save. */
|
|
||||||
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
|
||||||
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
|
||||||
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
|
||||||
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
|
||||||
1:
|
|
||||||
addi a0, a0, -portWORD_SIZE
|
|
||||||
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
|
||||||
ret
|
|
||||||
.endfunc
|
|
||||||
/*-----------------------------------------------------------*/
|
|
||||||
|
|
|
||||||
177
portable/GCC/RISC-V/portContext.h
Normal file
177
portable/GCC/RISC-V/portContext.h
Normal file
|
|
@ -0,0 +1,177 @@
|
||||||
|
/*
|
||||||
|
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef PORTCONTEXT_H
|
||||||
|
#define PORTCONTEXT_H
|
||||||
|
|
||||||
|
#if __riscv_xlen == 64
|
||||||
|
#define portWORD_SIZE 8
|
||||||
|
#define store_x sd
|
||||||
|
#define load_x ld
|
||||||
|
#elif __riscv_xlen == 32
|
||||||
|
#define store_x sw
|
||||||
|
#define load_x lw
|
||||||
|
#define portWORD_SIZE 4
|
||||||
|
#else
|
||||||
|
#error Assembler did not define __riscv_xlen
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "freertos_risc_v_chip_specific_extensions.h"
|
||||||
|
|
||||||
|
/* Only the standard core registers are stored by default. Any additional
|
||||||
|
* registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
|
||||||
|
* portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
|
||||||
|
* specific version of freertos_risc_v_chip_specific_extensions.h. See the
|
||||||
|
* notes at the top of portASM.S file. */
|
||||||
|
#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.extern pxCurrentTCB
|
||||||
|
.extern xISRStackTop
|
||||||
|
.extern xCriticalNesting
|
||||||
|
.extern pxCriticalNesting
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.macro portcontextSAVE_CONTEXT_INTERNAL
|
||||||
|
addi sp, sp, -portCONTEXT_SIZE
|
||||||
|
store_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
store_x x5, 2 * portWORD_SIZE( sp )
|
||||||
|
store_x x6, 3 * portWORD_SIZE( sp )
|
||||||
|
store_x x7, 4 * portWORD_SIZE( sp )
|
||||||
|
store_x x8, 5 * portWORD_SIZE( sp )
|
||||||
|
store_x x9, 6 * portWORD_SIZE( sp )
|
||||||
|
store_x x10, 7 * portWORD_SIZE( sp )
|
||||||
|
store_x x11, 8 * portWORD_SIZE( sp )
|
||||||
|
store_x x12, 9 * portWORD_SIZE( sp )
|
||||||
|
store_x x13, 10 * portWORD_SIZE( sp )
|
||||||
|
store_x x14, 11 * portWORD_SIZE( sp )
|
||||||
|
store_x x15, 12 * portWORD_SIZE( sp )
|
||||||
|
store_x x16, 13 * portWORD_SIZE( sp )
|
||||||
|
store_x x17, 14 * portWORD_SIZE( sp )
|
||||||
|
store_x x18, 15 * portWORD_SIZE( sp )
|
||||||
|
store_x x19, 16 * portWORD_SIZE( sp )
|
||||||
|
store_x x20, 17 * portWORD_SIZE( sp )
|
||||||
|
store_x x21, 18 * portWORD_SIZE( sp )
|
||||||
|
store_x x22, 19 * portWORD_SIZE( sp )
|
||||||
|
store_x x23, 20 * portWORD_SIZE( sp )
|
||||||
|
store_x x24, 21 * portWORD_SIZE( sp )
|
||||||
|
store_x x25, 22 * portWORD_SIZE( sp )
|
||||||
|
store_x x26, 23 * portWORD_SIZE( sp )
|
||||||
|
store_x x27, 24 * portWORD_SIZE( sp )
|
||||||
|
store_x x28, 25 * portWORD_SIZE( sp )
|
||||||
|
store_x x29, 26 * portWORD_SIZE( sp )
|
||||||
|
store_x x30, 27 * portWORD_SIZE( sp )
|
||||||
|
store_x x31, 28 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
|
||||||
|
store_x t0, 29 * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
|
||||||
|
|
||||||
|
csrr t0, mstatus /* Required for MPIE bit. */
|
||||||
|
store_x t0, 30 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
store_x sp, 0( t0 ) /* Write sp to first TCB member. */
|
||||||
|
|
||||||
|
.endm
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.macro portcontextSAVE_EXCEPTION_CONTEXT
|
||||||
|
portcontextSAVE_CONTEXT_INTERNAL
|
||||||
|
csrr a0, mcause
|
||||||
|
csrr a1, mepc
|
||||||
|
addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
|
||||||
|
store_x a1, 0( sp ) /* Save updated exception return address. */
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||||
|
.endm
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.macro portcontextSAVE_INTERRUPT_CONTEXT
|
||||||
|
portcontextSAVE_CONTEXT_INTERNAL
|
||||||
|
csrr a0, mcause
|
||||||
|
csrr a1, mepc
|
||||||
|
store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||||
|
.endm
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.macro portcontextRESTORE_CONTEXT
|
||||||
|
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
|
||||||
|
|
||||||
|
/* Load mepc with the address of the instruction in the task to run next. */
|
||||||
|
load_x t0, 0( sp )
|
||||||
|
csrw mepc, t0
|
||||||
|
|
||||||
|
/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS
|
||||||
|
|
||||||
|
/* Load mstatus with the interrupt enable bits used by the task. */
|
||||||
|
load_x t0, 30 * portWORD_SIZE( sp )
|
||||||
|
csrw mstatus, t0 /* Required for MPIE bit. */
|
||||||
|
|
||||||
|
load_x t0, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
|
||||||
|
load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
|
||||||
|
store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
|
||||||
|
|
||||||
|
load_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
load_x x5, 2 * portWORD_SIZE( sp )
|
||||||
|
load_x x6, 3 * portWORD_SIZE( sp )
|
||||||
|
load_x x7, 4 * portWORD_SIZE( sp )
|
||||||
|
load_x x8, 5 * portWORD_SIZE( sp )
|
||||||
|
load_x x9, 6 * portWORD_SIZE( sp )
|
||||||
|
load_x x10, 7 * portWORD_SIZE( sp )
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp )
|
||||||
|
load_x x12, 9 * portWORD_SIZE( sp )
|
||||||
|
load_x x13, 10 * portWORD_SIZE( sp )
|
||||||
|
load_x x14, 11 * portWORD_SIZE( sp )
|
||||||
|
load_x x15, 12 * portWORD_SIZE( sp )
|
||||||
|
load_x x16, 13 * portWORD_SIZE( sp )
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp )
|
||||||
|
load_x x18, 15 * portWORD_SIZE( sp )
|
||||||
|
load_x x19, 16 * portWORD_SIZE( sp )
|
||||||
|
load_x x20, 17 * portWORD_SIZE( sp )
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp )
|
||||||
|
load_x x22, 19 * portWORD_SIZE( sp )
|
||||||
|
load_x x23, 20 * portWORD_SIZE( sp )
|
||||||
|
load_x x24, 21 * portWORD_SIZE( sp )
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp )
|
||||||
|
load_x x26, 23 * portWORD_SIZE( sp )
|
||||||
|
load_x x27, 24 * portWORD_SIZE( sp )
|
||||||
|
load_x x28, 25 * portWORD_SIZE( sp )
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp )
|
||||||
|
load_x x30, 27 * portWORD_SIZE( sp )
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp )
|
||||||
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
|
|
||||||
|
mret
|
||||||
|
.endm
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#endif /* PORTCONTEXT_H */
|
||||||
|
|
@ -46,45 +46,43 @@ extern "C" {
|
||||||
|
|
||||||
/* Type definitions. */
|
/* Type definitions. */
|
||||||
#if __riscv_xlen == 64
|
#if __riscv_xlen == 64
|
||||||
#define portSTACK_TYPE uint64_t
|
#define portSTACK_TYPE uint64_t
|
||||||
#define portBASE_TYPE int64_t
|
#define portBASE_TYPE int64_t
|
||||||
#define portUBASE_TYPE uint64_t
|
#define portUBASE_TYPE uint64_t
|
||||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
|
||||||
#define portPOINTER_SIZE_TYPE uint64_t
|
#define portPOINTER_SIZE_TYPE uint64_t
|
||||||
#elif __riscv_xlen == 32
|
#elif __riscv_xlen == 32
|
||||||
#define portSTACK_TYPE uint32_t
|
#define portSTACK_TYPE uint32_t
|
||||||
#define portBASE_TYPE int32_t
|
#define portBASE_TYPE int32_t
|
||||||
#define portUBASE_TYPE uint32_t
|
#define portUBASE_TYPE uint32_t
|
||||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||||
#else
|
#else
|
||||||
#error Assembler did not define __riscv_xlen
|
#error Assembler did not define __riscv_xlen
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
typedef portSTACK_TYPE StackType_t;
|
typedef portSTACK_TYPE StackType_t;
|
||||||
typedef portBASE_TYPE BaseType_t;
|
typedef portBASE_TYPE BaseType_t;
|
||||||
typedef portUBASE_TYPE UBaseType_t;
|
typedef portUBASE_TYPE UBaseType_t;
|
||||||
typedef portUBASE_TYPE TickType_t;
|
typedef portUBASE_TYPE TickType_t;
|
||||||
|
|
||||||
/* Legacy type definitions. */
|
/* Legacy type definitions. */
|
||||||
#define portCHAR char
|
#define portCHAR char
|
||||||
#define portFLOAT float
|
#define portFLOAT float
|
||||||
#define portDOUBLE double
|
#define portDOUBLE double
|
||||||
#define portLONG long
|
#define portLONG long
|
||||||
#define portSHORT short
|
#define portSHORT short
|
||||||
|
|
||||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||||
not need to be guarded with a critical section. */
|
* not need to be guarded with a critical section. */
|
||||||
#define portTICK_TYPE_IS_ATOMIC 1
|
#define portTICK_TYPE_IS_ATOMIC 1
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
/* Architecture specifics. */
|
/* Architecture specifics. */
|
||||||
#define portSTACK_GROWTH ( -1 )
|
#define portSTACK_GROWTH ( -1 )
|
||||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||||
#define portBYTE_ALIGNMENT 16
|
#define portBYTE_ALIGNMENT 16
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
/* Scheduler utilities. */
|
/* Scheduler utilities. */
|
||||||
extern void vTaskSwitchContext( void );
|
extern void vTaskSwitchContext( void );
|
||||||
#define portYIELD() __asm volatile( "ecall" );
|
#define portYIELD() __asm volatile( "ecall" );
|
||||||
|
|
@ -92,91 +90,98 @@ extern void vTaskSwitchContext( void );
|
||||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
/* Critical section management. */
|
/* Critical section management. */
|
||||||
#define portCRITICAL_NESTING_IN_TCB 1
|
#define portCRITICAL_NESTING_IN_TCB 0
|
||||||
extern void vTaskEnterCritical( void );
|
|
||||||
extern void vTaskExitCritical( void );
|
|
||||||
|
|
||||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
|
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
|
||||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
|
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
|
||||||
#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
|
|
||||||
#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
|
#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
|
||||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
|
||||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
|
||||||
|
extern size_t xCriticalNesting;
|
||||||
|
#define portENTER_CRITICAL() \
|
||||||
|
{ \
|
||||||
|
portDISABLE_INTERRUPTS(); \
|
||||||
|
xCriticalNesting++; \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define portEXIT_CRITICAL() \
|
||||||
|
{ \
|
||||||
|
xCriticalNesting--; \
|
||||||
|
if( xCriticalNesting == 0 ) \
|
||||||
|
{ \
|
||||||
|
portENABLE_INTERRUPTS(); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
/* Architecture specific optimisations. */
|
/* Architecture specific optimisations. */
|
||||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||||
|
|
||||||
/* Check the configuration. */
|
/* Check the configuration. */
|
||||||
#if( configMAX_PRIORITIES > 32 )
|
#if( configMAX_PRIORITIES > 32 )
|
||||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Store/clear the ready priorities in a bit map. */
|
/* Store/clear the ready priorities in a bit map. */
|
||||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
|
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
|
||||||
|
|
||||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||||
not necessary for to use this port. They are defined so the common demo files
|
* not necessary for to use this port. They are defined so the common demo
|
||||||
(which build with all the ports) will build. */
|
* files (which build with all the ports) will build. */
|
||||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
#define portNOP() __asm volatile ( " nop " )
|
#define portNOP() __asm volatile( " nop " )
|
||||||
|
#define portINLINE __inline
|
||||||
#define portINLINE __inline
|
|
||||||
|
|
||||||
#ifndef portFORCE_INLINE
|
#ifndef portFORCE_INLINE
|
||||||
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
|
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
|
||||||
configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
|
* configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
|
||||||
backward compatibility derive the newer definitions from the old if the old
|
* backward compatibility derive the newer definitions from the old if the old
|
||||||
definition is found. */
|
* definition is found. */
|
||||||
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
|
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
|
||||||
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
|
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
|
||||||
there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
|
* there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
|
||||||
addresses to 0. */
|
* addresses to 0. */
|
||||||
#define configMTIME_BASE_ADDRESS ( 0 )
|
#define configMTIME_BASE_ADDRESS ( 0 )
|
||||||
#define configMTIMECMP_BASE_ADDRESS ( 0 )
|
#define configMTIMECMP_BASE_ADDRESS ( 0 )
|
||||||
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
|
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
|
||||||
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
|
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
|
||||||
the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
|
* the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
|
||||||
from the CLINT address. */
|
* from the CLINT address. */
|
||||||
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
|
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
|
||||||
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
|
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
|
||||||
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
|
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
|
||||||
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* PORTMACRO_H */
|
#endif /* PORTMACRO_H */
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue