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Riscv re-factoring (#444)
* Refactor RISCV port Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Changes to make re-factoring work on ESP32-C3 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Remove alignment and place handlers in separate sections Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Correct section names This is needed so that the assemblers correctly recognizes functions. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move mtvec programming to the application Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Refactor mtimer udpate code Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move critical nesting to port layer Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Respect configTASK_RETURN_ADDRESS Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Formatting changes Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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177
portable/GCC/RISC-V/portContext.h
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portable/GCC/RISC-V/portContext.h
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTCONTEXT_H
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#define PORTCONTEXT_H
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#elif __riscv_xlen == 32
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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#include "freertos_risc_v_chip_specific_extensions.h"
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/* Only the standard core registers are stored by default. Any additional
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* registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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* portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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* specific version of freertos_risc_v_chip_specific_extensions.h. See the
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* notes at the top of portASM.S file. */
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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/*-----------------------------------------------------------*/
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.extern pxCurrentTCB
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.extern xISRStackTop
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.extern xCriticalNesting
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.extern pxCriticalNesting
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_CONTEXT_INTERNAL
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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store_x x16, 13 * portWORD_SIZE( sp )
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store_x x17, 14 * portWORD_SIZE( sp )
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store_x x18, 15 * portWORD_SIZE( sp )
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store_x x19, 16 * portWORD_SIZE( sp )
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store_x x20, 17 * portWORD_SIZE( sp )
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store_x x21, 18 * portWORD_SIZE( sp )
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store_x x22, 19 * portWORD_SIZE( sp )
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store_x x23, 20 * portWORD_SIZE( sp )
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store_x x24, 21 * portWORD_SIZE( sp )
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store_x x25, 22 * portWORD_SIZE( sp )
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store_x x26, 23 * portWORD_SIZE( sp )
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store_x x27, 24 * portWORD_SIZE( sp )
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store_x x28, 25 * portWORD_SIZE( sp )
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store_x x29, 26 * portWORD_SIZE( sp )
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, 29 * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, 30 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_EXCEPTION_CONTEXT
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
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store_x a1, 0( sp ) /* Save updated exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_INTERRUPT_CONTEXT
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextRESTORE_CONTEXT
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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/* Load mepc with the address of the instruction in the task to run next. */
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load_x t0, 0( sp )
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csrw mepc, t0
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, 30 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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load_x t0, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp )
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load_x x6, 3 * portWORD_SIZE( sp )
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load_x x7, 4 * portWORD_SIZE( sp )
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load_x x8, 5 * portWORD_SIZE( sp )
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load_x x9, 6 * portWORD_SIZE( sp )
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load_x x10, 7 * portWORD_SIZE( sp )
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load_x x11, 8 * portWORD_SIZE( sp )
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load_x x12, 9 * portWORD_SIZE( sp )
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load_x x13, 10 * portWORD_SIZE( sp )
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load_x x14, 11 * portWORD_SIZE( sp )
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load_x x15, 12 * portWORD_SIZE( sp )
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load_x x16, 13 * portWORD_SIZE( sp )
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load_x x17, 14 * portWORD_SIZE( sp )
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load_x x18, 15 * portWORD_SIZE( sp )
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load_x x19, 16 * portWORD_SIZE( sp )
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load_x x20, 17 * portWORD_SIZE( sp )
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load_x x21, 18 * portWORD_SIZE( sp )
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load_x x22, 19 * portWORD_SIZE( sp )
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load_x x23, 20 * portWORD_SIZE( sp )
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load_x x24, 21 * portWORD_SIZE( sp )
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load_x x25, 22 * portWORD_SIZE( sp )
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load_x x26, 23 * portWORD_SIZE( sp )
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load_x x27, 24 * portWORD_SIZE( sp )
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load_x x28, 25 * portWORD_SIZE( sp )
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load_x x29, 26 * portWORD_SIZE( sp )
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load_x x30, 27 * portWORD_SIZE( sp )
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load_x x31, 28 * portWORD_SIZE( sp )
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endm
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/*-----------------------------------------------------------*/
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#endif /* PORTCONTEXT_H */
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