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Core kernel files:

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+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction.  The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap.  This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.

Demo application:
+ Add demo for SAMA5D4 using IAR.
This commit is contained in:
Richard Barry 2014-10-08 20:31:14 +00:00
parent ee541a347d
commit 9e66637bec
196 changed files with 70548 additions and 72 deletions
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736
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/board.h Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \page sama5d4_ek_board_desc sama5d4-EK - Board Description
*
* \section Purpose
*
* This file is dedicated to describe the sama5d4-EK board.
*
* \section Contents
*
* - sama5d4-EK
* - For sama5d4-EK information, see \subpage sama5d4_ek_board_info.
* - For operating frequency information, see \subpage sama5d4_ek_opfreq.
* - For using portable PIO definitions, see \subpage sama5d4_ek_piodef.
* - For on-board memories, see \subpage sama5d4_ek_mem.
* - Several USB definitions are included here, see \subpage sama5d4_ek_usb.
* - For External components, see \subpage sama5d4_ek_extcomp.
* - For Individual chip definition, see \subpage sama5d4_ek_chipdef.
*
* To get more software details and the full list of parameters related to the
* sama5d4-EK board configuration, please have a look at the source file:
* \ref board.h\n
*
* \section Usage
*
* - The code for booting the board is provided by board_cstartup_xxx.c and
* board_lowlevel.c.
* - For using board PIOs, board characteristics (clock, etc.) and external
* components, see board.h.
* - For manipulating memories, see board_memories.h.
*
* This file can be used as a template and modified to fit a custom board, with
* specific PIOs usage or memory connections.
*/
/**
* \file board.h
*
* Definition of sama5d4-EK
* characteristics, sama5d4-dependant PIOs and external components interfacing.
*/
#ifndef _BOARD_
#define _BOARD_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/**
* Libc porting layers
*/
#if defined ( __CC_ARM ) /* Keil uvision 4 */
# include "include/rand.h"
#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
# include "include/rand.h"
#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68/2010q1-188 */
# include "include/rand.h"
# include "include/syscalls.h" /** RedHat Newlib minimal stub */
#endif
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_board_info "sama5d4-EK - Board informations"
* This page lists several definition related to the board description.
*
* \section Definitions
* - \ref BOARD_NAME
*/
/** Name of the board */
#define BOARD_NAME "sama5d4x-EK"
/** Board definition */
#define sama5d4ek
/** Family definition (already defined) */
#if !defined sama5d4
#define sama5d4
#endif
/** Core definition */
#define cortexa5
//#define BOARD_REV_A_VB
//#define BOARD_REV_A_EK
#define BOARD_REV_B_EK
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_opfreq "sama5d4-EK - Operating frequencies"
* This page lists several definition related to the board operating frequency
* (when using the initialization done by board_lowlevel.c).
*
* \section Definitions
* - \ref BOARD_MAINOSC
* - \ref BOARD_MCK
*/
/** Frequency of the board main oscillator */
#define BOARD_MAINOSC 12000000
/** Master clock frequency (when using board_lowlevel.c) */
#define BOARD_MCK ((unsigned long)((BOARD_MAINOSC / 3 / 2) * 88 ))
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_piodef "sama5d4-EK - PIO definitions"
* This pages lists all the pio definitions contained in board.h. The constants
* are named using the following convention: PIN_* for a constant which defines
* a single Pin instance (but may include several PIOs sharing the same
* controller), and PINS_* for a list of Pin instances.
*
* DBGU
* - \ref PINS_DBGU
*
* USART0
* - \ref PIN_USART0_TXD
* - \ref PIN_USART0_RXD
* - \ref PIN_USART0_RTS
* - \ref PIN_USART0_CTS
* - \ref PIN_USART0_SCK
*
* TWI0
* - \ref PIN_TWI_TWD0
* - \ref PIN_TWI_TWCK0
* - \ref PINS_TWI0
*
* SPI0
* - \ref PIN_SPI0_MISO
* - \ref PIN_SPI0_MOSI
* - \ref PIN_SPI0_SPCK
* - \ref PIN_SPI0_NPCS0
* - \ref PINS_SPI0
*
* SSC
* - \ref PIN_SSC_TD
* - \ref PIN_SSC_TK
* - \ref PIN_SSC_TF
* - \ref PIN_SSC_RD
* - \ref PIN_SSC_RK
* - \ref PIN_SSC_RF
* - \ref PINS_SSC_CODEC
*
* EMAC0
* - \ref PIN_EMAC0_TXCK
* - \ref PIN_EMAC0_TX0
* - \ref PIN_EMAC0_TX1
* - \ref PIN_EMAC0_TX2
* - \ref PIN_EMAC0_TX3
* - \ref PIN_EMAC0_TXEN
* - \ref PIN_EMAC0_RXER
* - \ref PIN_EMAC0_RXDV
* - \ref PIN_EMAC0_RX0
* - \ref PIN_EMAC0_RX1
* - \ref PIN_EMAC0_RX2
* - \ref PIN_EMAC0_RX3
* - \ref PIN_EMAC0_MDC
* - \ref PIN_EMAC0_MDIO
* - \ref PIN_EMAC0_INTR
* - \ref PINS_EMAC0_MII
* - \ref PINS_EMAC0_RMII
* LCD
* - \ref PINS_LCD
*
* ADC
* - \ref PIN_ADTRG
*
* ISI
* - \ref PIN_ISI_MCK
* - \ref PIN_ISI_VSYNC
* - \ref PIN_ISI_HSYNC
* - \ref PIN_ISI_PCK
* - \ref PIN_ISI_PINS_DATA
* - \ref PINS_ISI
*/
/** List of all DBGU pin definitions. */
/** DBGU Monitor IO pin (detect any DBGU operation). */
#define PIN_DBGU_MON {PIO_PB24A_DRXD, PIOB, ID_PIOB, PIO_INPUT, PIO_IT_RISE_EDGE}
/** DBGU pin definition. */
#define PINS_DBGU {PIO_PB24A_DRXD | PIO_PB25A_DTXD, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** List of all USART pin definitions. */
/** USART0 TXD pin definition. */
#define PIN_USART0_TXD {PIO_PD13A_TXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 RXD pin definition. */
#define PIN_USART0_RXD {PIO_PD12A_RXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 RTS pin definition. */
#define PIN_USART0_RTS {PIO_PD11A_RTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 CTS pin definition. */
#define PIN_USART0_CTS {PIO_PD10A_CTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 SCK pin definition. */
#define PIN_USART0_SCK {PIO_PD28A_SCK0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 TXD pin definition. */
#define PIN_USART1_TXD {PIO_PD17A_TXD1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 RXD pin definition. */
#define PIN_USART1_RXD {PIO_PD16A_RXD1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 RTS pin definition. */
#define PIN_USART1_RTS {PIO_PD15A_RTS1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 CTS pin definition. */
#define PIN_USART1_CTS {PIO_PD14A_CTS1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 SCK pin definition. */
#define PIN_USART1_SCK {PIO_PD29A_SCK1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART2 TXD pin definition. */
#define PIN_USART2_TXD {PIO_PE26B_TXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 RXD pin definition. */
#define PIN_USART2_RXD {PIO_PE25B_RXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 RTS pin definition. */
#define PIN_USART2_RTS {PIO_PE24B_RTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 CTS pin definition. */
#define PIN_USART2_CTS {PIO_PE23B_CTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 SCK pin definition. */
#define PIN_USART2_SCK {PIO_PE20B_SCK2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART3 TXD pin definition. */
#define PIN_USART3_TXD {PIO_PE17B_TXD3, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART3 RXD pin definition. */
#define PIN_USART3_RXD {PIO_PE16B_RXD3, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART3 SCK pin definition. */
#define PIN_USART3_SCK {PIO_PE15B_SCK3, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART4 TXD pin definition. */
//#define PIN_USART4_TXD {PIO_PE27B_TXD4, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART4 RXD pin definition. */
//#define PIN_USART4_RXD {PIO_PE26B_RXD4, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART4 RTS pin definition. */
//#define PIN_USART4_RTS {PIO_PE28B_RTS4, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART4 CTS pin definition. */
//#define PIN_USART4_CTS {PIO_PE0C_CTS4, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT}
/** USART4 SCK pin definition. */
//#define PIN_USART4_SCK {PIO_PE25B_SCK4, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** PIN used for reset the smartcard */
#define PIN_ISO7816_RSTMC {1 << 10, PIOD, ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT}
/** Pins used for connect the smartcard */
#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK,PIN_ISO7816_RSTMC
/** List of all TWI pin definitions. */
/** TWI0 data pin */
#define PIN_TWI_TWD0 {PIO_PA30A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI0 clock pin */
#define PIN_TWI_TWCK0 {PIO_PA31A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI0 pins */
#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0
/** TWI1 data pin */
#define PIN_TWI_TWD1 {PIO_PE29C_TWD1, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT}
/** TWI1 clock pin */
#define PIN_TWI_TWCK1 {PIO_PE30C_TWCK1, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT}
/** TWI1 pins */
#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1
/** TWI2 data pin */
#define PIN_TWI_TWD2 {PIO_PB29A_TWD2, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI2 clock pin */
#define PIN_TWI_TWCK2 {PIO_PB30A_TWCK2, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI2 pins */
#define PINS_TWI2 PIN_TWI_TWD2, PIN_TWI_TWCK2
/** TWI3 data pin */
#define PIN_TWI_TWD3 {PIO_PC25B_TWD3, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** TWI3 clock pin */
#define PIN_TWI_TWCK3 {PIO_PC26B_TWCK3, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** TWI3 pins */
#define PINS_TWI3 PIN_TWI_TWD3, PIN_TWI_TWCK3
/** List of all CAN pin deinitions. */
/** CAN0 pin TX */
#define PIN_CAN0_TX {PIO_PD15C_CANTX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
/** CAN0 pin RX */
#define PIN_CAN0_RX {PIO_PD14C_CANRX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
/** CAN0 pins */
#define PINS_CAN0 PIN_CAN0_TX, PIN_CAN0_RX
/** CAN1 pin TX */
#define PIN_CAN1_TX {PIO_PB15B_CANTX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** CAN1 pin RX */
#define PIN_CAN1_RX {PIO_PB14B_CANRX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** CAN0 pins */
#define PINS_CAN1 PIN_CAN1_TX, PIN_CAN1_RX
/** List of all SPI pin definitions. */
/** SPI0 MISO pin definition. */
#define PIN_SPI0_MISO {PIO_PC0A_SPI0_MISO, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 MOSI pin definition. */
#define PIN_SPI0_MOSI {PIO_PC1A_SPI0_MOSI, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 SPCK pin definition. */
#define PIN_SPI0_SPCK {PIO_PC2A_SPI0_SPCK, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 chip select pin definition. */
#define PIN_SPI0_NPCS0 {PIO_PC3A_SPI0_NPCS0, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** List of SPI0 pin definitions (MISO, MOSI & SPCK). */
#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK
/** SPI1 MISO pin definition. */
#define PIN_SPI1_MISO {PIO_PB18A_SPI1_MISO, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 MOSI pin definition. */
#define PIN_SPI1_MOSI {PIO_PB19A_SPI1_MOSI, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 SPCK pin definition. */
#define PIN_SPI1_SPCK {PIO_PB20A_SPI1_SPCK, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 chip select pin definition. */
#define PIN_SPI1_NPCS0 {PIO_PB21A_SPI1_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 chip select pin definition. */
#define PIN_SPI1_NPCS2 {PIO_PB23A_SPI1_NPCS2, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** List of SPI1 pin definitions (MISO, MOSI & SPCK). */
#define PINS_SPI1 PIN_SPI1_MISO, PIN_SPI1_MOSI, PIN_SPI1_SPCK
/** SPI2 MISO pin definition. */
#define PIN_SPI2_MISO {PIO_PD11B_SPI2_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** SPI2 MOSI pin definition. */
#define PIN_SPI2_MOSI {PIO_PD13B_SPI2_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** SPI2 SPCK pin definition. */
#define PIN_SPI2_SPCK {PIO_PD15B_SPI2_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** SPI2 chip select 0 pin definition. */
#define PIN_SPI2_NPCS0 {PIO_PD17B_SPI2_NPCS0, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** SPI2 chip select 1 pin definition. */
#define PIN_SPI2_NPCS1 {PIO_PB14B_SPI2_NPCS1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** List of SPI1 pin definitions (MISO, MOSI & SPCK). */
#define PINS_SPI2 PIN_SPI2_MISO, PIN_SPI2_MOSI, PIN_SPI2_SPCK
/** List of all SSC pin definitions. */
/** SSC pin Transmitter Data (TD) */
#define PIN_SSC_TD0 {PIO_PB28B_TD0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin Transmitter Clock (TK) */
#define PIN_SSC_TK0 {PIO_PB27B_TK0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin Transmitter FrameSync (TF) */
#define PIN_SSC_TF0 {PIO_PB31B_TF0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RD */
#define PIN_SSC_RD0 {PIO_PB29B_RD0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RK */
#define PIN_SSC_RK0 {PIO_PB26B_RK0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RF */
#define PIN_SSC_RF0 {PIO_PB30B_RF0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin Transmitter Data (TD) */
#define PIN_SSC_TD1 {0x1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin Transmitter Clock (TK) */
#define PIN_SSC_TK1 {0x1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin Transmitter FrameSync (TF) */
#define PIN_SSC_TF1 {0x1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RD */
#define PIN_SSC_RD1 {0x1 << 23, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RK */
#define PIN_SSC_RK1 {0x1 << 24, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pin RF */
#define PIN_SSC_RF1 {0x1 << 22, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** SSC pins definition for codec. */
#define PINS_SSC_CODEC PIN_SSC_TD0, PIN_SSC_TK0, PIN_SSC_TF0, PIN_SSC_RD0, PIN_SSC_RK0, PIN_SSC_RF0
/** LCD pin list. */
#define PINS_LCD_PIOA {0x3FFEFEFE, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
#define PINS_LCD PINS_LCD_PIOA
/** ADC ADTRG pin (PD19). */
#define PIN_ADTRG {PIO_PE31A_ADTRG, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_PULLUP}
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_usb "sama5d4-EK - USB device"
*
* \section Definitions
* - \ref BOARD_USB_BMATTRIBUTES
* - \ref CHIP_USB_UDP
* - \ref CHIP_USB_PULLUP_INTERNAL
* - \ref CHIP_USB_NUMENDPOINTS
* - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE
* - \ref CHIP_USB_ENDPOINTS_BANKS
*/
/** USB VBus pin */
#define PIN_USB_VBUS {PIO_PE31, PIOE, ID_PIOE, PIO_INPUT, PIO_DEFAULT}
/** USB OverCurrent detection*/
#define PIN_USB_OVCUR {PIO_PD9, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP}
/** USB Power Enable A:MicroAB:Active low */
#define PIN_USB_POWER_ENA {PIO_PE10, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
/** USB Power Enable B:A:Active low */
#define PIN_USB_POWER_ENB {PIO_PE11, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
/** USB Power Enable C:A:Active low */
#define PIN_USB_POWER_ENC {PIO_PE12, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
/** USB attributes configuration descriptor (bus or self powered, remote wakeup) */
#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_mem "sama5d4-EK - Memories"
* This page lists definitions related to internal & external on-board memories.
*
* \section Sdram
*
* - \ref EBI_SDRAM_PINS
*
* \section Nandflash
* - \ref PINS_NANDFLASH
* - \ref BOARD_NF_IO_PINS
* - \ref BOARD_NF_CE_PIN
* - \ref BOARD_NF_RB_PIN
*/
/** Nandflash IO pin definition.*/
#define BOARD_NF_IO_PINS {0x0007FFE0, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
#define BOARD_NF_CE_PIN {0, 0, 0, 0, 0}
/** Nandflash controller peripheral pins definition. */
#define PINS_NANDFLASH BOARD_NF_IO_PINS
/** Address for transferring command bytes to the nandflash, CLE A22*/
#define BOARD_NF_COMMAND_ADDR 0x80400000
/** Address for transferring address bytes to the nandflash, ALE A21*/
#define BOARD_NF_ADDRESS_ADDR 0x80200000
/** Address for transferring data bytes to the nandflash.*/
#define BOARD_NF_DATA_ADDR 0x80000000
/** Address for transferring command bytes to the norflash. */
#define BOARD_NORFLASH_ADDR 0x10000000
/** Default NOR bus size after power up reset */
#define BOARD_NORFLASH_DFT_BUS_SIZE 16
/** Ddram type */
#define DDRAM_MT47H64M16HR 0
#define DDRAM_MT47H128M16RT 1
#define BOARD_DDRAM_TYPE DDRAM_MT47H128M16RT
/** PHY address */
#define BOARD_EMAC_PHY_ADDR 1
/** PHY Component */
#define BOARD_EMAC_PHY_COMP_KSZ8051RNL 1
/** Board EMAC power control - ALWAYS ON */
#define BOARD_EMAC_POWER_ALWAYS_ON
/** Board EMAC work mode - RMII/MII ( 1 / 0 ) */
#define BOARD_EMAC_MODE_RMII 1
/** The PIN list of PIO for EMAC */
#define BOARD_EMAC_PINS {0x3FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT},\
{(1<<30),PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** The runtime pin configure list for EMAC */
#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS
/** PHY address */
#define BOARD_GMAC_PHY_ADDR 0
#define BOARD_GMAC_PHY_COMP_KSZ9021RNL 1
#define BOARD_GMAC_PHY_COMP_KSZ8081RNL 1
#define BOARD_GMAC_POWER_ALWAYS_ON
#define BOARD_GMAC_MODE_RGMII 1
/// The PIN list of PIO for EMAC
#define BOARD_GMAC_PINS0 {0x333C5, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT},\
{(1<<6),PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/// The runtime pin configure list for EMAC
#define BOARD_GMAC_RUN_PINS0 BOARD_GMAC_PINS0
/// The PIN list of PIO for EMAC
#define BOARD_GMAC_PINS1 {0xC0FC14, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT},\
{(1<<7),PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/// The runtime pin configure list for EMAC
#define BOARD_GMAC_RUN_PINS1 BOARD_GMAC_PINS1
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_extcomp "sama5d4-EK - External components"
* This page lists the definitions related to external on-board components
* located in the board.h file for the sama5d4-EK.
*
* \section board_sdmmc SD/MMC
* - \ref BOARD_MCI0_PINS
* - \ref BOARD_MCI0_PIN_CD
* - \ref BOARD_MCI1_PINS
* - \ref BOARD_MCI1_PIN_CD
* - \ref BOARD_NUM_MCI
*
* \section board_emac EMAC
* - \ref BOARD_EMAC_RST_PINS
* - \ref BOARD_EMAC_PHY_ADDR
* - \ref BOARD_EMAC_RUN_PINS
*
* \section board_lcd LCD Properties
* - \ref BOARD_LCD_WIDTH
* - \ref BOARD_LCD_HEIGHT
* - \ref BOARD_LCD_IFWIDTH
* - \ref BOARD_LCD_FRAMESIZE
* - \ref BOARD_LCD_TIMING_VFP
* - \ref BOARD_LCD_TIMING_VBP
* - \ref BOARD_LCD_TIMING_VPW
* - \ref BOARD_LCD_TIMING_HFP
* - \ref BOARD_LCD_TIMING_HBP
* - \ref BOARD_LCD_TIMING_HPW
* - \ref BOARD_LCD_FRAMERATE
* - \ref BOARD_LCD_PIXELCLOCK
*
* \section board_ts Touchscreen ADC Properties
* - \ref BOARD_TOUCHSCREEN_ADCCLK
* - \ref BOARD_TOUCHSCREEN_STARTUP
* - \ref BOARD_TOUCHSCREEN_SHTIM
* - \ref BOARD_TOUCHSCREEN_DEBOUNCE
*/
/** MCI0 Card detect pin definition. (PE5) */
#define BOARD_MCI0_PIN_CD {PIO_PE5, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** MCI0 power control. */
//#define BOARD_MCI0_PIN_POWER {PIO_PE15, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_PULLUP}
/** MCI0 Clock . */
#define BOARD_MCI0_PIN_CK {PIO_PC4, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** MCI0 Solt A IO pins definition. (PC4-PC13) */
#define BOARD_MCI0_PINS_SLOTA {0x3FF0, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
//MCI0_CDB PE0, MCI0_DB0, MCI0_DB1,MCI0_DB2, MCI0_DB3
/** MCI1 Card detect pin definition. (PE14) */
#define BOARD_MCI1_PIN_CD {PIO_PE6, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** MCI1 power control */
#define BOARD_MCI1_PIN_POWER {PIO_PE15, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_PULLUP}
#define BOARD_MCI0_PINS BOARD_MCI0_PINS_SLOTA
/** MCI1 IO pins definition. (PE18-PE23) */
#define BOARD_MCI1_PINS {0xFC0000, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT}
/** Total number of MCI interface */
#define BOARD_NUM_MCI 2
/** Display width in pixels. */
#define BOARD_LCD_WIDTH 800
/** Display height in pixels. */
#define BOARD_LCD_HEIGHT 480
/** Display interface width in bits. */
#define BOARD_LCD_IFWIDTH 24
/** Frame size in words (height * width * bpp / 32) */
#define BOARD_LCD_FRAMESIZE (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT * BOARD_LCD_IFWIDTH / 32)
/** Vertical front porch in number of lines. */
#define BOARD_LCD_TIMING_VFP 22
/** Vertical back porch in number of lines. */
#define BOARD_LCD_TIMING_VBP 21
/** Vertical pulse width in number of lines. */
#define BOARD_LCD_TIMING_VPW 2
/** Horizontal front porch in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HFP 64
/** Horizontal back porch in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HBP 64
/** Horizontal pulse width in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HPW 128
/** Frame rate in Hz. */
#define BOARD_LCD_FRAMERATE 40
/** Pixel clock rate in Hz (HS period * VS period * BOARD_LCD_FRAMERATE). */
#define BOARD_LCD_PIXELCLOCK ((BOARD_LCD_TIMING_HPW+BOARD_LCD_TIMING_HBP+BOARD_LCD_WIDTH+BOARD_LCD_TIMING_HFP)\
*(BOARD_LCD_TIMING_VPW+BOARD_LCD_TIMING_VBP+BOARD_LCD_HEIGHT+BOARD_LCD_TIMING_VFP)\
*BOARD_LCD_FRAMERATE)
#define BOARD_ISI_VSYNC {PIO_PB3C_ISI_VSYNC, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_HSYNC {PIO_PB4C_ISI_HSYNC, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_PCK {PIO_PB1C_ISI_PCK, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_PINS_DATA {0x07F80000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} //pc19-26
//#define BOARD_ISI_PINS_DATA2 {0x00000003, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
#define PIN_ISI_RST {1 << 11, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}
#define PIN_ISI_RSTN {1 << 5, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}
#define PINS_ISI BOARD_ISI_VSYNC, BOARD_ISI_HSYNC, BOARD_ISI_PCK , BOARD_ISI_PINS_DATA
/** Touchscreen ADC clock frequency to use. */
#define BOARD_TOUCHSCREEN_ADCCLK 300000 /* 8MHz max */
/** Touchscreen ADC startup time in µseconds. */
#define BOARD_TOUCHSCREEN_STARTUP 40
/** Touchscreen ADC track and hold time in nanoseconds. */
#define BOARD_TOUCHSCREEN_SHTIM 2000 /* min 1µs at 8MHz */
/** Touchscreen pen debounce time in nanoseconds. */
#define BOARD_TOUCHSCREEN_DEBOUNCE 10000000
#define PIN_AD0 {PIO_PC27A_AD0, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
#define PIN_AD1 {PIO_PC28A_AD1, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
#define PIN_AD2 {PIO_PC29A_AD2, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
#define PIN_AD3 {PIO_PC30A_AD3, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
#define PIN_AD4 {PIO_PC31A_AD4, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
//#define PINS_TOUCH_SCREEN PIN_AD0_XP, PIN_AD1_XM, PIN_AD2_YP, PIN_AD3_YM, PIN_AD4_LR
/** HDMI reset pins. */
#define PIN_HDMI_RESET_L {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}
#define PIN_HDMI_RESET_H {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
/*----------------------------------------------------------------------------*/
/**
* \page sama5d4_ek_chipdef "sama5d4-EK - Individual chip definition"
* This page lists the definitions related to different chip's definition
* located in the board.h file for the sama5d4-EK.
*
* LEDs
* - \ref PIN_LED_0
* - \ref PIN_LED_1
* - \ref PIN_LED_2
* - \ref PINS_LEDS
*
* Push buttons
* - \ref PIN_PUSHBUTTON_1
* - \ref PINS_PUSHBUTTONS
*
* PCK0
* - \ref PIN_PCK0
*
* PCK1
* - \ref PIN_PCK1
*/
#if defined(BOARD_REV_A_EK)||defined(BOARD_REV_B_EK)
#define LED_BLUE 0
#define LED_RED 1
/** LED #0 pin definition (LED_BLUE). */
#define PIN_LED_0 {(PIO_PE8), PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
/** LED #1 pin definition (LED_RED). */
#define PIN_LED_1 {(PIO_PE9), PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT}
/** LED #2 pin definition (LED_GREEN). */
#define PIN_LED_2 {(PIO_PE28), PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT}
/** List of all LEDs definitions. */
#define PINS_LEDS PIN_LED_0, PIN_LED_1,PIN_LED_2
#endif
/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
#define PIN_PUSHBUTTON_1 {PIO_PE13, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}
#define PIN_PUSHBUTTON_2 {PIO_PE13, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}
/** List of all push button definitions. */
#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1
/** Push button #1 index. */
#define PUSHBUTTON_BP1 0
/** Push button #2 index. */
#define PUSHBUTTON_BP2 1
/** catb button */
#define PIN_SBUTTON0 {1 << 18, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_SBUTTON1 {1 << 19, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_SBUTTON2 {1 << 20, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_SBUTTON3 {1 << 21, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_SBUTTON4 {1 << 22, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_SBUTTON_DIS {1 << 29, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
#define PINS_SBUTTON PIN_SBUTTON0, PIN_SBUTTON1, PIN_SBUTTON2, PIN_SBUTTON3, PIN_SBUTTON4, PIN_SBUTTON_DIS
/** PCK0 */
#define PIN_PCK0 {PIO_PB26A_PCK0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** PCK1 */
#define PIN_PCK1 {PIO_PD31B_PCK1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
//#define PIN_PCK1 {PIO_PC4C_PCK1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
/** PCK2 */
#define PIN_PCK2 {PIO_PB10B_PCK2, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** PWM0 */
/*----------------------------------------------------------------------------
* Headers for board
*----------------------------------------------------------------------------*/
#include "include/board_lowlevel.h"
#include "include/bmp.h"
#include "include/dbgu_console.h"
#include "include/dbg_util.h"
#include "include/hamming.h"
#include "include/led.h"
#include "include/math.h"
#include "include/timetick.h"
#include "include/wav.h"
#include "include/twid.h"
#include "include/xdma_hardware_interface.h"
#include "include/xdmad.h"
#include "include/board_memories.h"
#include "include/iso7816_4.h"
#include "include/lcdd.h"
#include "include/lcd_draw.h"
#include "include/lcd_font10x14.h"
#include "include/lcd_font.h"
#include "include/lcd_color.h"
#include "include/mcid.h"
#include "include/gmii.h"
#include "include/gmacd.h"
#include "include/gmacb.h"
#include "include/ov.h"
#include "include/omnivision.h"
#include "include/ovyuv.h"
#include "include/tsd.h"
#include "include/tsd_com.h"
#include "include/wm8904.h"
#include "include/rtc_calib.h"
#endif /* #ifndef _BOARD_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for ADS7843 driver.
*/
#ifndef _ADS7843_
#define _ADS7843_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ADS7843_Initialize( void ) ;
extern void ADS7843_Reset( void ) ;
extern void ADS7843_GetPosition( uint32_t *px_pos, uint32_t *py_pos ) ;
#endif /* #ifndef _ADS7843_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* \section Purpose
*
* Utility for BMP
*
*/
#ifndef BMP_H
#define BMP_H
/** BMP magic number ('BM'). */
#define BMP_TYPE 0x4D42
/** headerSize must be set to 40 */
#define BITMAPINFOHEADER 40
/*------------------------------------------------------------------------------
* Exported types
*------------------------------------------------------------------------------*/
/*
* In case of IAR EWARM use, we define an empty macro to turn useless GCC and MDK __attribute__ keyword
*/
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack( 1 )
#endif
/** BMP (Windows) File Header Format */
typedef struct _BMPFileHeader
{
/** signature, must be 4D42 hex */
uint16_t type;
/** size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/** reserved, must be zero */
uint16_t reserved1;
/** reserved, must be zero */
uint16_t reserved2;
/** offset to start of image data in bytes */
uint32_t offset;
} BMPFileHeader;
/** BMP (Windows 2.x) Header */
typedef struct _BMP2XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
uint16_t width;
/** image height in pixels */
uint16_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
} BMP2XHeader;
/** BMP (Windows 3.x) Header, 40 bytes */
typedef struct _BMP3XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
} BMP3XHeader;
/** BMP (Windows 95, V4) Header, 108 bytes */
typedef struct _BMP4Header
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
/** Mask identifying bits of red component */
uint32_t redMask;
/** Mask identifying bits of green component */
uint32_t greenMask;
/** Mask identifying bits of blue component */
uint32_t blueMask;
/** Mask identifying bits of alpha component */
uint32_t alphaMask;
/** Color space type */
uint32_t csType;
/** X coordinate of red endpoint */
int32_t redX;
/** Y coordinate of red endpoint */
int32_t redY;
/** Z coordinate of red endpoint */
int32_t redZ;
/** X coordinate of green endpoint */
int32_t greenX;
/** Y coordinate of green endpoint */
int32_t greenY;
/** Z coordinate of green endpoint */
int32_t greenZ;
/** X coordinate of blue endpoint */
int32_t blueX;
/** Y coordinate of blue endpoint */
int32_t blueY;
/** Z coordinate of blue endpoint */
int32_t blueZ;
/** Gamma red coordinate scale value */
uint32_t gammaRed;
/** Gamma green coordinate scale value */
uint32_t gammaGreen;
/** Gamma blue coordinate scale value */
uint32_t gammaBlue;
} BMP4Header;
/** BMP (Windows) Header Format */
typedef struct _BMPHeader
{
/* signature, must be 4D42 hex */
uint16_t type;
/* size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/* reserved, must be zero */
uint16_t reserved1;
/* reserved, must be zero */
uint16_t reserved2;
/* offset to start of image data in bytes */
uint32_t offset;
/* size of BITMAPINFOHEADER structure, must be 40 */
uint32_t headerSize;
/* image width in pixels */
uint32_t width;
/* image height in pixels */
uint32_t height;
/* number of planes in the image, must be 1 */
uint16_t planes;
/* number of bits per pixel (1, 4, 8, 16, 24, 32) */
uint16_t bits;
/* compression type (0=none, 1=RLE-8, 2=RLE-4) */
uint32_t compression;
/* size of image data in bytes (including padding) */
uint32_t imageSize;
/* horizontal resolution in pixels per meter (unreliable) */
uint32_t xresolution;
/* vertical resolution in pixels per meter (unreliable) */
uint32_t yresolution;
/* number of colors in image, or zero */
uint32_t ncolours;
/* number of important colors, or zero */
uint32_t importantcolours;
} BMPHeader ; // GCC
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack()
#endif
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint8_t BMP_IsValid(void *file);
extern uint32_t BMP_GetFileSize(void *file);
extern uint8_t BMP_Decode(
void *file,
uint8_t*buffer,
uint32_t width,
uint32_t height,
unsigned char bpp);
extern void WriteBMPheader(uint32_t* pAddressHeader,
uint32_t bmpHSize,
uint32_t bmpVSize,
uint8_t bmpRgb,
uint8_t nbByte_Pixels);
extern void BMP_displayHeader(uint32_t* pAddressHeader);
extern void RGB565toBGR555(
uint8_t *fileSource,
uint8_t *fileDestination,
uint32_t width,
uint32_t height,
uint8_t bpp);
#endif //#ifndef BMP_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for the low-level initialization function.
*
*/
#ifndef BOARD_LOWLEVEL_H
#define BOARD_LOWLEVEL_H
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void defaultSpuriousHandler( void );
extern void defaultFiqHandler( void );
extern void defaultIrqHandler( void );
/* Cortex-A5 core handlers */
/*
*/
extern void SYS_IrqHandler( void ) ;
extern void Spurious_handler( void ) ;
/* Peripherals handlers */
extern void SAIC0_Handler(void);
extern void ARM_IrqHandler(void);
extern void PIT_IrqHandler(void);
extern void WDT_IrqHandler(void);
extern void PIOD_IrqHandler(void);
extern void USART0_IrqHandler(void);
extern void USART1_IrqHandler(void);
extern void XDMAC0_IrqHandler(void);
extern void ICM_IrqHandler(void);
extern void PKCC_IrqHandler(void);
extern void SCI_IrqHandler(void);
extern void AES_IrqHandler(void);
extern void AESB_IrqHandler(void);
extern void TDES_IrqHandler(void);
extern void SHA_IrqHandler(void);
extern void MPDDRC_IrqHandler(void);
extern void H32MX_IrqHandler(void);
extern void H64MX_IrqHandler(void);
extern void VDEC_IrqHandler(void);
extern void SECUMOD_IrqHandler(void);
extern void MSADCC_IrqHandler(void);
extern void HSMC_IrqHandler(void);
extern void PIOA_IrqHandler(void);
extern void PIOB_IrqHandler(void);
extern void PIOC_IrqHandler(void);
extern void PIOE_IrqHandler(void);
extern void UART0_IrqHandler(void);
extern void UART1_IrqHandler(void);
extern void USART2_IrqHandler(void);
extern void USART3_IrqHandler(void);
extern void USART4_IrqHandler(void);
extern void TWI0_IrqHandler(void);
extern void TWI1_IrqHandler(void);
extern void TWI2_IrqHandler(void);
extern void HSMCI0_IrqHandler(void);
extern void HSMCI1_IrqHandler(void);
extern void SPI0_IrqHandler(void);
extern void SPI1_IrqHandler(void);
extern void SPI2_IrqHandler(void);
extern void TC0_IrqHandler(void);
extern void TC1_IrqHandler(void);
extern void TC2_IrqHandler(void);
extern void PWM_IrqHandler(void);
extern void ADC_IrqHandler(void);
extern void DBGU_IrqHandler(void);
extern void UHPHS_IrqHandler(void);
extern void UDPHS_IrqHandler(void);
extern void SSC0_IrqHandler(void);
extern void SSC1_IrqHandler(void);
extern void XDMAC1_IrqHandler(void);
extern void LCDC_IrqHandler(void);
extern void ISI_IrqHandler(void);
extern void TRNG_IrqHandler(void);
extern void GMAC0_IrqHandler(void);
extern void GMAC1_IrqHandler(void);
extern void AIC0_IrqHandler(void);
extern void SFC_IrqHandler(void);
extern void SECURAM_IrqHandler(void);
extern void CTB_IrqHandler(void);
extern void SMD_IrqHandler(void);
extern void TWI3_IrqHandler(void);
extern void CATB_IrqHandler(void);
extern void SFR_IrqHandler(void);
extern void AIC1_IrqHandler(void);
extern void SAIC1_IrqHandler(void);
extern void L2CC_IrqHandler(void);
extern void LowLevelInit( void ) ;
#endif /* BOARD_LOWLEVEL_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for memories configuration on board.
*
*/
#ifndef BOARD_MEMORIES_H
#define BOARD_MEMORIES_H
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void BOARD_RemapRom( void );
extern void BOARD_RemapRam( void );
extern void BOARD_ConfigureVddMemSel(uint8_t VddMemSel) ;
extern void BOARD_ConfigureDdram( void );
extern void BOARD_ConfigureSdram( void );
extern void BOARD_ConfigureNandFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureNorFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureLpDdram(void);
#endif /* #ifndef BOARD_MEMORIES_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Implements DBG utility that uses DBGU and System tick to get byte or binary
* stream from DBGU console.
*/
#ifndef _DBG_UTIL_
#define _DBG_UTIL_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint8_t DbgReceiveByte(uint8_t * pByte,uint32_t timeOut);
extern uint32_t DbgReceiveBinary(uint8_t start,
uint32_t address,
uint32_t maxSize);
extern uint32_t DbgReceive1KXModem(uint8_t * pktBuffer,
uint32_t address,
uint32_t maxSize);
#endif /* _DBG_UTIL_ */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _DBGU_CONSOLE_
#define _DBGU_CONSOLE_
#include <stdint.h>
/** Console baudrate always using 115200. */
#define CONSOLE_BAUDRATE 115200
extern void DBGU_ConsoleUseDBGU(void);
extern void DBGU_ConsoleUseUSART0(void);
extern void DBGU_ConsoleUseUSART1(void);
extern void DBGU_ConsoleUseUSART3(void);
extern void DBGU_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ;
extern void DBGU_PutChar( uint8_t uc ) ;
extern uint32_t DBGU_GetChar( void ) ;
extern uint32_t DBGU_IsRxReady( void ) ;
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ;
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ;
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue ) ;
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax ) ;
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue ) ;
#endif /* _DBGU_CONSOLE_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacb_module Ethernet GMACB Driver
*@{
* Implement GEMAC PHY driver, that initialize the PHY to prepare for
* ethernet transfer.
*
* \section Usage
* -# EMAC related pins and Driver should be initialized at first.
* -# Initialize GMACB Driver instance by invoking GMACB_Init().
* -# Initialize PHY connected via GMACB_InitPhy(), PHY address is
* automatically adjusted by attempt to read.
* -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so
* connection established.
*
*
* Related files:\n
* \ref gmacb.h\n
* \ref gmacb.c\n
* \ref gmii.h.\n
*
*/
/**@}*/
#ifndef _GMACB_H
#define _GMACB_H
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** The reset length setting for external reset configuration */
#define GMACB_RESET_LENGTH 0xD
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** The DM9161 instance */
typedef struct _GMacb {
sGmacd *pGmacd; /**< Driver */
/** The retry & timeout settings */
uint32_t retryMax;
/** PHY address ( pre-defined by pins on reset ) */
uint8_t phyAddress;
} GMacb;
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax);
extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress);
extern uint8_t GMACB_InitPhy(GMacb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins);
extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb);
extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings);
extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size);
extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size);
extern void GMACB_DumpRegisters(GMacb *pMacb);
extern uint8_t GMACB_ResetPhy(GMacb *pMacb);
#endif // #ifndef _GMACB_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacd_module
* @{
* Implement GMAC data transfer and PHY management functions.
*
* \section Usage
* -# Implement GMAC interrupt handler, which must invoke GMACD_Handler()
* to handle GMAC interrupt events.
* -# Implement sGmacd instance in application.
* -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(),
* so that GMAC data can be transmitted/received.
* -# Some management callbacks can be set by GMACD_SetRxCallback()
* and GMACD_SetTxWakeupCallback().
* -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used
* to check the free space in TX queue.
* -# Check and obtain received ethernet packets via GMACD_Poll().
*
* \sa \ref gmacb_module, \ref gmac_module
*
* Related files:\n
* \ref gmacd.c\n
* \ref gmacd.h.\n
*
* \defgroup gmacd_defines GMAC Driver Defines
* \defgroup gmacd_types GMAC Driver Types
* \defgroup gmacd_functions GMAC Driver Functions
*/
/**@}*/
#ifndef _GMACD_H_
#define _GMACD_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_defines
@{*/
/** \addtogroup gmacd_buf_size GMACD Default Buffer Size
@{*/
#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */
#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */
/** @}*/
/** \addtogroup gmacd_rc GMACD Return Codes
@{*/
#define GMACD_OK 0 /**< Operation OK */
#define GMACD_TX_BUSY 1 /**< TX in progress */
#define GMACD_RX_NULL 1 /**< No data received */
/** Buffer size not enough */
#define GMACD_SIZE_TOO_SMALL 2
/** Parameter error, TX packet invalid or RX size too small */
#define GMACD_PARAM 3
/** Transter is not initialized */
#define GMACD_NOT_INITIALIZED 4
/** @}*/
/** @}*/
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_types
@{*/
/** RX callback */
typedef void (*fGmacdTransferCallback)(uint32_t status);
/** Wakeup callback */
typedef void (*fGmacdWakeupCallback)(void);
/**
* GMAC driver struct.
*/
typedef struct _GmacDriver {
/** Pointer to HW register base */
Gmac *pHw;
uint8_t *pTxBuffer;
/** Pointer to allocated RX buffer */
uint8_t *pRxBuffer;
/** Pointer to Rx TDs (must be 8-byte aligned) */
sGmacRxDescriptor *pRxD;
/** Pointer to Tx TDs (must be 8-byte aligned) */
sGmacTxDescriptor *pTxD;
/** Optional callback to be invoked once a frame has been received */
fGmacdTransferCallback fRxCb;
/** Optional callback to be invoked once several TD have been released */
fGmacdWakeupCallback fWakupCb;
/** Optional callback list to be invoked once TD has been processed */
fGmacdTransferCallback *fTxCbList;
/** RX TD list size */
uint16_t wRxListSize;
/** RX index for current processing TD */
uint16_t wRxI;
/** TX TD list size */
uint16_t wTxListSize;
/** Circular buffer head pointer by upper layer (buffer to be sent) */
uint16_t wTxHead;
/** Circular buffer tail pointer incremented by handlers (buffer sent) */
uint16_t wTxTail;
/** Number of free TD before wakeup callback is invoked */
uint8_t bWakeupThreshold;
/** HW ID */
uint8_t bId;
} sGmacd;
/** @}*/
/** \addtogroup gmacd_functions
@{*/
/*---------------------------------------------------------------------------
* GMAC Exported functions
*---------------------------------------------------------------------------*/
extern void GMACD_Handler(sGmacd *pGmacd );
extern void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC );
extern uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer,
sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer,
sGmacTxDescriptor *pTxD,
fGmacdTransferCallback *pTxCb,
uint16_t wTxSize);
extern void GMACD_Reset(sGmacd *pGmacd);
extern uint8_t GMACD_Send(sGmacd *pGmacd,
void *pBuffer,
uint32_t size,
fGmacdTransferCallback fTxCb );
extern uint32_t GMACD_TxLoad(sGmacd *pGmacd);
extern uint8_t GMACD_Poll(sGmacd * pGmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize);
extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb);
extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,
fGmacdWakeupCallback fWakeup,
uint8_t bThreshold);
/** @}*/
#endif // #ifndef _GMACD_H_

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GMII_DEFINE_H
#define _GMII_DEFINE_H
//-----------------------------------------------------------------------------
/// Definitions
//-----------------------------------------------------------------------------
//IEEE defined Registers
#define GMII_BMCR 0x0 // Basic Mode Control Register
#define GMII_BMSR 0x1 // Basic Mode Status Register
#define GMII_PHYID1R 0x2 // PHY Idendifier Register 1
#define GMII_PHYID2R 0x3 // PHY Idendifier Register 2
#define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register
#define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register
#define GMII_ANER 0x6 // Auto-negotiation Expansion Register
#define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register
#define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register
#define GMII_DRCR 0x10 // Digital Reserved Control Register
#define GMII_AFEC1R 0x11 // AFE Control 1 Register
#define GMII_RXERCR 0x15 // RXER Couter Register
#define GMII_OMSOR 0x16 // Operation Mode Strap Override Register
#define GMII_OMSSR 0x17 // Operation Mode Strap Status Register
#define GMII_ECR 0x18 // Expanded Control Register
#define GMII_ICSR 0x1B // Interrupt Control/Status Register
#define GMII_LCSR 0x1D // LinkMD® Control/Status Register
#define GMII_PC1R 0x1E // PHY Control 1 Register
#define GMII_PC2R 0x1F // PHY Control 2 Register
// PHY ID Identifier Register
#define GMII_LSB_MASK 0xF
// definitions: MII_PHYID1
#define GMII_OUI_MSB 0x0022
// definitions: MII_PHYID2
#define GMII_OUI_LSB 0x1560
// Basic Mode Control Register (BMCR)
// Bit definitions: MII_BMCR
#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps
#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
// Reserved 7 // Read as 0, ignore on write
#define GMII_SPEED_SELECT_MSB (1 << 6) //
// Reserved 5 to 0 // Read as 0, ignore on write
// Basic Mode Status Register (BMSR)
// Bit definitions: MII_BMSR
#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
// Reserved 10 to 9 // Read as 0, ignore on write
#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
// Reserved 7
#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
#define GMII_LINK_STATUS (1 << 2) // Link Status
#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
// Auto-negotiation Advertisement Register (ANAR)
// Auto-negotiation Link Partner Ability Register (ANLPAR)
// Bit definitions: MII_ANAR, MII_ANLPAR
#define GMII_NP (1 << 15) // Next page Indication
// Reserved 7
#define GMII_RF (1 << 13) // Remote Fault
// Reserved 12 // Write as 0, ignore on read
#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
// 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
#define GMII_T4 (1 << 9) // 100BASE-T4 Support
#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support
#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
#define GMII_10_HDX (1 << 5) // 10BASE-T Support
// Selector 4 to 0 // Protocol Selection Bits
#define GMII_AN_IEEE_802_3 0x0001
#endif // #ifndef _MII_DEFINE_H

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _HAMMING_
#define _HAMMING_
/*------------------------------------------------------------------------------
* Defines
*------------------------------------------------------------------------------*/
/**
* These are the possible errors when trying to verify a block of data encoded
* using a Hamming code:
*
* \section Errors
* - Hamming_ERROR_SINGLEBIT
* - Hamming_ERROR_ECC
* - Hamming_ERROR_MULTIPLEBITS
*/
/** A single bit was incorrect but has been recovered. */
#define Hamming_ERROR_SINGLEBIT 1
/** The original code has been corrupted. */
#define Hamming_ERROR_ECC 2
/** Multiple bits are incorrect in the data and they cannot be corrected. */
#define Hamming_ERROR_MULTIPLEBITS 3
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern void Hamming_Compute256x( const uint8_t* pucData, uint32_t dwSize, uint8_t* pucCode ) ;
extern uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) ;
#endif /* _HAMMING_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/** \page
*
* \section Purpose
*
* Definition of methods for ISO7816 driver.
*
* \section Usage
*
* -# ISO7816_Init
* -# ISO7816_IccPowerOff
* -# ISO7816_XfrBlockTPDU_T0
* -# ISO7816_Escape
* -# ISO7816_RestartClock
* -# ISO7816_StopClock
* -# ISO7816_toAPDU
* -# ISO7816_Datablock_ATR
* -# ISO7816_SetDataRateandClockFrequency
* -# ISO7816_StatusReset
* -# ISO7816_cold_reset
* -# ISO7816_warm_reset
* -# ISO7816_Decode_ATR
*----------------------------------------------------------------------------*/
#ifndef ISO7816_4_H
#define ISO7816_4_H
/*------------------------------------------------------------------------------
* Constants Definition
*----------------------------------------------------------------------------*/
/** Size max of Answer To Reset */
#define ATR_SIZE_MAX 55
/** NULL byte to restart byte procedure */
#define ISO_NULL_VAL 0x60
/*------------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ISO7816_Init( const Pin pPinIso7816RstMC );
extern void ISO7816_IccPowerOff(void);
extern uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU,
uint8_t *pMessage,
uint16_t wLength );
extern void ISO7816_Escape( void );
extern void ISO7816_RestartClock(void);
extern void ISO7816_StopClock( void );
extern void ISO7816_toAPDU( void );
extern void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength );
extern void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate );
extern uint8_t ISO7816_StatusReset( void );
extern void ISO7816_cold_reset( void );
extern void ISO7816_warm_reset( void );
extern void ISO7816_Decode_ATR( uint8_t* pAtr );
#endif /* ISO7816_4_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef COLOR_H
#define COLOR_H
/**
* \file
*
* RGB 24-bits color table definition.
*
*/
/*
* RGB 24 Bpp
* RGB 888
* R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0
*/
#define COLOR_BLACK 0x000000
#define COLOR_WHITE 0xFFFFFF
#define COLOR_BLUE 0x0000FF
#define COLOR_GREEN 0x00FF00
#define COLOR_RED 0xFF0000
#define COLOR_NAVY 0x000080
#define COLOR_DARKBLUE 0x00008B
#define COLOR_DARKGREEN 0x006400
#define COLOR_DARKCYAN 0x008B8B
#define COLOR_CYAN 0x00FFFF
#define COLOR_TURQUOISE 0x40E0D0
#define COLOR_INDIGO 0x4B0082
#define COLOR_DARKRED 0x800000
#define COLOR_OLIVE 0x808000
#define COLOR_GRAY 0x808080
#define COLOR_SKYBLUE 0x87CEEB
#define COLOR_BLUEVIOLET 0x8A2BE2
#define COLOR_LIGHTGREEN 0x90EE90
#define COLOR_DARKVIOLET 0x9400D3
#define COLOR_YELLOWGREEN 0x9ACD32
#define COLOR_BROWN 0xA52A2A
#define COLOR_DARKGRAY 0xA9A9A9
#define COLOR_SIENNA 0xA0522D
#define COLOR_LIGHTBLUE 0xADD8E6
#define COLOR_GREENYELLOW 0xADFF2F
#define COLOR_SILVER 0xC0C0C0
#define COLOR_LIGHTGREY 0xD3D3D3
#define COLOR_LIGHTCYAN 0xE0FFFF
#define COLOR_VIOLET 0xEE82EE
#define COLOR_AZUR 0xF0FFFF
#define COLOR_BEIGE 0xF5F5DC
#define COLOR_MAGENTA 0xFF00FF
#define COLOR_TOMATO 0xFF6347
#define COLOR_GOLD 0xFFD700
#define COLOR_ORANGE 0xFFA500
#define COLOR_SNOW 0xFFFAFA
#define COLOR_YELLOW 0xFFFF00
#endif /* #define COLOR_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_draw Drawing On LCD
*
* Interface for drawing function on LCD.
*
* \note Before drawing, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* Following functions can use:
* - Simple drawing:
* - LCDD_Fill()
* - LCDD_DrawPixel()
* - LCDD_ReadPixel()
* - LCDD_DrawLine()
* - LCDD_DrawRectangle(), LCDD_DrawFilledRectangle()
* - LCDD_DrawCircle(), LCDD_DrawFilledCircle()
* - LCDD_DrawImage()
* - String related:
* - LCDD_DrawString()
* - LCDD_GetStringSize()
*
* \sa \ref lcdd_module, \ref lcdd_font
*/
#ifndef DRAW_H
#define DRAW_H
/** \addtogroup lcdd_draw
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
#include "lcd_gimp_image.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_draw_func LCD Drawing Functions */
/** @{*/
extern void LCDD_Fill0( void ) ;
extern void LCDD_Fill( uint32_t color ) ;
extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t c ) ;
extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) ;
extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color ) ;
extern void LCDD_DrawRectangle( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2, uint32_t dwColor ) ;
extern void LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color ) ;
extern void LCDD_DrawFilledCircle(uint32_t dwX,uint32_t dwY,uint32_t dwR,uint32_t dwColor);
extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color ) ;
extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) ;
extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight ) ;
extern void LCDD_DrawImage( uint32_t x, uint32_t y, const uint8_t *pImage, uint32_t width, uint32_t height ) ;
void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage, uint32_t dwWidth, uint32_t dwHeight ) ;
extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
/** @}*/
/**@}*/
#endif /* #ifndef DRAW_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for draw font on LCD.
*
*/
/**
* \addtogroup lcdd_font LCD Font Drawing
*
* \section Purpose
*
* The lcd_font.h files declares a font structure and a LCDD_DrawChar() function
* that must be implemented by a font definition file to be used with the
* LCDD_DrawString() method of draw.h.
*
* The font10x14.c implements the necessary variable and function for a 10x14
* font.
*
* \note Before drawing fonts, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* \section Usage
*
* -# Declare a gFont global variable with the necessary Font information.
* -# Implement an LCDD_DrawChar() function which displays the specified
* character on the LCD.
* -# Select or create canvas via LCDD_SelectCanvas() or LCDD_CreateCanvas().
* -# Use the LCDD_DrawString() method defined in draw.h to display a complete
* string.
*
* \sa \ref lcdd_module, \ref lcdd_draw.
*/
#ifndef _LCD_FONT_
#define _LCD_FONT_
/** \addtogroup lcdd_font
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \brief Describes the font (width, height, supported characters, etc.) used by
* the LCD driver draw API.
*/
typedef struct _Font {
/* Font width in pixels. */
uint8_t width;
/* Font height in pixels. */
uint8_t height;
} Font;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
extern const Font gFont;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_font_func Font Functions */
/** @{*/
extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) ;
extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor );
/** @}*/
/**@}*/
#endif /* #ifndef LCD_FONT_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_font
* @{
* \addtogroup font_10x14 Font 10x14
*/
/**@}*/
#ifndef _LCD_FONT_10x14_
#define _LCD_FONT_10x14_
/** \addtogroup font_10x14
* @{
*/
#include <stdint.h>
extern const uint8_t pCharset10x14[] ;
/** @}*/
#endif /* #ifdef _LCD_FONT_10x14_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GIMP_IMAGE_
#define _GIMP_IMAGE_
#include <stdint.h>
typedef struct _SGIMPImage
{
uint32_t dwWidth;
uint32_t dwHeight;
uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */
uint8_t* pucPixel_data ;
} SGIMPImage ;
#endif // _GIMP_IMAGE_

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup lib_board
* \addtogroup lcdd_module LCD Driver
*
* \section Purpose
*
* Implement driver functions for LCD control and image display.
* - Implement basic LCD controler configuration.
* - Implement display functions for LCD layers.
* - Implement simple drawing functions.
* - Implement string display functions.
*
* \section lcdd_base_usage Usage
*
* Uses following functions for LCD basic configuration and displaying:
* -# Uses LCDD_Initialize() to initialize the controller and LCD.
* -# LCDD_On() and LCDD_Off() is used to turn LCD ON/OFF.
* -# LCDD_SetBacklight() is used to change LCD backlight level.
* -# To display a image (BMP format) on LCD, LCDD_ShowBMPRotated()
* LCDD_ShowBMPScaled() and LCDD_ShowBMP() can be used.
* -# To change configuration for an overlay layer, the following functions
* can use:
* -# LCDD_EnableLayer(), LCDD_IsLayerOn(): Turn ON/OFF layer, check status.
* -# LCDD_SetPosition(), LCDD_SetPrioty(), LCDD_EnableAlpha(),
* LCDD_SetAlpha(), LCDD_SetColorKeying(): Change display options.
* -# Shortcuts for layer display are as following:
* -# LCDD_ShowBase(), LCDD_StopBase()
* -# LCDD_ShowOvr1(), LCDD_StopOvr1()
* -# LCDD_ShowHeo(), LCDD_StopHeo()
* -# LCDD_ShowHcr(), LCDD_StopHcr()
* -# Drawing supporting fucntions, for drawing canvas:
* -# LCDD_CreateCanvas(): Create blank canvas on specified layer for
* drawing on
* -# LCDD_SelectCanvas(): Select a displayer as canvas to drawing on
* -# LCDD_GetCanvas(): Get current selected canvas layer
*
* For LCD drawing functions, refer to \ref lcdd_draw.
*
* For LCD string display, refer to \ref lcdd_font.
*
* @{
* \defgroup lcdd_base LCD Driver General Operations
* @{
* Implementation of LCD driver, Include LCD initialization,
* LCD on/off and LCD backlight control.
*
* \sa \ref lcdd_base_usage "LCD Driver General Usage"
* @}
* \defgroup lcdd_draw LCD Driver Simple Drawing
* @{
* @}
* \defgroup lcdd_font LCD Driver Font Display
* @{
* @}
* @}
*/
#ifndef LCDD_H
#define LCDD_H
/** \addtogroup lcdd_base
* @{
*/
/*----------------------------------------------------------------------------
* Defines
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_disp_id LCD display layers IDs
* @{
*/
/** LCD controller ID, no display, configuration ONLY */
#define LCDD_CONTROLLER 0
/** LCD base layer, display fixed size image */
#define LCDD_BASE 1
/** LCD Overlay 1 */
#define LCDD_OVR1 2
/** LCD Overlay 2 */
#define LCDD_OVR2 4
/** LCD HighEndOverlay, support resize */
#define LCDD_HEO 3
/** LCD Cursor, max size 128x128 */
#define LCDD_CUR 6
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** LCD display layer information */
typedef struct _LcddLayer {
void* pBuffer; /**< Display image buffer */
uint16_t wImgW; /**< Display image width */
uint16_t wImgH; /**< Display image height */
uint8_t bMode; /**< Image bpp (16,24,32) for RGB mode */
uint8_t bLayer; /**< Layer ID */
} sLCDDLayer;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void LCDD_Initialize(void);
extern void LCDD_On(void);
extern void LCDD_Off(void);
extern void LCDD_SetBacklight (uint32_t step);
extern void LCDD_EnableLayer(uint8_t bLayer,uint8_t bEnDis);
extern uint8_t LCDD_IsLayerOn(uint8_t bLayer);
extern void LCDD_SetPosition(uint8_t bLayer,uint32_t x,uint32_t y);
extern void LCDD_SetPrioty(uint8_t bLayer,uint8_t bPri);
extern uint8_t LCDD_GetPrioty(uint8_t bLayer);
extern void LCDD_EnableAlpha(uint8_t bLayer,uint8_t bEnDisLA,uint8_t bEnDisGA);
extern void LCDD_SetAlpha(uint8_t bLayer, uint8_t bReverse, uint8_t bAlpha);
extern uint8_t LCDD_GetAlpha(uint8_t bLayer);
extern void LCDD_SetColorKeying(uint8_t bLayer,
uint8_t bDstSrc,
uint32_t dwColor,uint32_t dwMask);
extern void LCDD_DisableColorKeying(uint8_t bLayer);
extern void LCDD_SetCLUT(uint8_t bLayer,
uint32_t * pCLUT,
uint8_t bpp,uint8_t nbColors);
extern void LCDD_Refresh(uint8_t bLayer);
extern void *LCDD_ShowBMPRotated(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH,
int16_t wRotate);
extern void *LCDD_ShowBMPScaled(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH);
extern void *LCDD_ShowBMP(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void *LCDD_ShowBase(void * pBuffer, uint8_t bpp, uint8_t bScanBottomUp);
extern void LCDD_StopBase(void);
extern void *LCDD_ShowOvr1(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopOvr1(void);
extern void *LCDD_ShowHeo(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t memW,uint32_t memH);
extern void LCDD_StopHeo(void);
extern void *LCDD_ShowHcr(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopHcr(void);
extern sLCDDLayer *LCDD_GetCanvas(void);
extern uint8_t LCDD_SelectCanvas(uint8_t bLayer);
extern void *LCDD_CreateCanvas(uint8_t bLayer,
void * pBuffer,uint8_t bBPP,
uint16_t wX,uint16_t wY,uint16_t wW,uint16_t wH);
extern void LCDD_Flush_CurrentCanvas(void);
/** @}*/
#endif /* #ifndef LCDD_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Small set of functions for simple and portable LED usage.
*
* \section Usage
*
* -# Configure one or more LEDs using LED_Configure and
* LED_ConfigureAll.
* -# Set, clear and toggle LEDs using LED_Set, LED_Clear and
* LED_Toggle.
*
* LEDs are numbered starting from 0; the number of LEDs depend on the
* board being used. All the functions defined here will compile properly
* regardless of whether the LED is defined or not; they will simply
* return 0 when a LED which does not exist is given as an argument.
* Also, these functions take into account how each LED is connected on to
* board; thus, \ref LED_Set might change the level on the corresponding pin
* to 0 or 1, but it will always light the LED on; same thing for the other
* methods.
*/
#ifndef _LED_
#define _LED_
#include <stdint.h>
//------------------------------------------------------------------------------
// Global Functions
//------------------------------------------------------------------------------
extern uint32_t LED_Configure( uint32_t dwLed ) ;
extern uint32_t LED_Set( uint32_t dwLed ) ;
extern uint32_t LED_Clear( uint32_t dwLed ) ;
extern uint32_t LED_Toggle( uint32_t dwLed ) ;
#endif /* #ifndef LED_H */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _MATH_
#define _MATH_
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint32_t min( uint32_t dwA, uint32_t dwB ) ;
extern uint32_t absv( int32_t lValue ) ;
extern uint32_t power( uint32_t dwX, uint32_t dwY ) ;
#endif /* #ifndef _MATH_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup sdmmc_hal
* \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib)
*
* \section Purpose
*
* This driver implements SD(IO)/MMC command operations and MCI configuration
* routines to perform SD(IO)/MMC access. It's used for upper layer
* (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations.
*
* \section Usage
*
* -# MCID_Init(): Initializes a MCI driver instance and the underlying
* peripheral.
* -# MCID_SendCmd(): Starts a MCI transfer which described by
* \ref sSdmmcCommand.
* -# MCID_CancelCmd(): Cancel a pending command.
* -# MCID_IsCmdCompleted(): Check if MCI transfer is finished.
* -# MCID_Handler(): Interrupt handler which is called by ISR handler.
* -# MCID_IOCtrl(): IO control function to report HW attributes to upper
* layer driver and modify HW settings (such as clock
* frequency, High-speed support, etc. See
* \ref sdmmc_ioctrls).
*
* \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI",
* \ref libsdmmc_module "SD/MMC Library"
*
* Related files:\n
* \ref mcid.h\n
* \ref mcid_dma.c.\n
*/
#ifndef MCID_H
#define MCID_H
/** \addtogroup mcid_module
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#include <stdio.h>
/** \addtogroup mcid_defines MCI Driver Defines
* @{*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** MCI States */
#define MCID_IDLE 0 /**< Idle */
#define MCID_LOCKED 1 /**< Locked for specific slot */
#define MCID_CMD 2 /**< Processing the command */
#define MCID_ERROR 3 /**< Command error */
/** MCI Initialize clock 400K Hz */
#define MCI_INITIAL_SPEED 400000
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_structs MCI Driver Data Structs
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief MCI Driver
*/
typedef struct _Mcid
{
/** Pointer to a MCI peripheral. */
Hsmci *pMciHw;
/** Pointer to a DMA driver */
sXdmad *pXdmad;
/** Pointer to currently executing command. */
void *pCmd;
/** MCK source, Hz */
uint32_t dwMck;
/** DMA transfer channel */
uint32_t dwDmaCh;
/** DMA transferred data index (bytes) */
uint32_t dwXfrNdx;
/** DMA transfer size (bytes) */
uint32_t dwXSize;
/** MCI peripheral identifier. */
uint8_t bID;
/** Polling mode */
uint8_t bPolling;
/** Reserved */
uint8_t reserved;
/** state. */
volatile uint8_t bState;
} sMcid;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_functions MCI Driver Functions
@{*/
extern void MCID_Init(sMcid * pMcid,
Hsmci * pMci, uint8_t bID, uint32_t dwMck,
sXdmad * pXdmad,
uint8_t bPolling);
extern void MCID_Reset(sMcid * pMcid);
extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot);
extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot);
extern uint32_t MCID_Release(sMcid * pMcid);
extern void MCID_Handler(sMcid * pMcid);
extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd);
extern uint32_t MCID_CancelCmd(sMcid * pMcid);
extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid);
extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param);
#ifdef __cplusplus
}
#endif
/** @}*/
/**@}*/
#endif //#ifndef HSMCID_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OMNIVISION_H
#define OMNIVISION_H
/*---------------------------------------------------------------------------
* TYPE
*---------------------------------------------------------------------------*/
/** define a structure for ovxxxx register initialization values */
struct ov_reg
{
/* Register to be written */
uint16_t reg;
/* Value to be written in the register */
uint8_t val;
};
/*---------------------------------------------------------------------------
* DEFINITAION
*---------------------------------------------------------------------------*/
#define OV_2640 0x00
#define OV_2643 0x01
#define OV_5640 0x02
#define OV_7740 0x03
#define OV_9740 0x04
#define OV_UNKNOWN 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t ov_init(Twid *pTwid);
extern void ov_DumpRegisters8(Twid *pTwid);
extern void ov_DumpRegisters16(Twid *pTwid);
extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist);
extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist);
extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData);
extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData);
extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val);
extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val);
extern void isOV5640_AF_InitDone(Twid *pTwid);
extern uint32_t ov_5640_AF_single(Twid *pTwid);
extern uint32_t ov_5640_AF_continue(Twid *pTwid);
extern uint32_t ov_5640_AFPause(Twid *pTwid);
extern uint32_t ov_5640_AFrelease(Twid *pTwid);
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OV_H
#define OV_H
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** Captor capture size */
struct capture_size {
uint32_t width;
uint32_t height;
};
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth);
extern void ov_5640Afc_Firmware(Twid *pTwid);
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _YUV_H_
#define _YUV_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Exported variable
*---------------------------------------------------------------------------*/
extern const struct ov_reg ov2640_yuv_vga[];
extern const struct ov_reg ov2640_yuv_qvga[];
extern const struct ov_reg ov2643_yuv_vga[];
extern const struct ov_reg ov2643_yuv_swvga[];
extern const struct ov_reg ov2643_yuv_uxga[];
extern const struct ov_reg ov5640_yuv_vga[];
extern const struct ov_reg ov5640_yuv_sxga[];
extern const struct ov_reg ov5640_afc[];
extern const struct ov_reg ov7740_yuv_vga[];
extern const struct ov_reg ov9740_yuv_sxga[];
extern const struct ov_reg ov9740_yuv_vga[];
#endif // #ifndef _YUV_H_

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation QT1070 driver.
*
*/
#ifndef QT1070_H
#define QT1070_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** Slave address */
#define QT1070_SLAVE_ADDRESS 0x1B
/** Internal Register Address Allocation */
/** Chip ID register*/
#define QT1070_CHIP_ID 0
/** Firmware version register*/
#define QT1070_REG_FIRMWARE_VERSION 1
/** Detection status*/
#define QT1070_REG_DETECTION_STATUS 2
/** Key status*/
#define QT1070_REG_KEY_STATUS 3
/** Key signal */
#define QT1070_REG_KEY0_SIGNAL_MSB 4
#define QT1070_REG_KEY0_SIGNAL_LSB 5
#define QT1070_REG_KEY1_SIGNAL_MSB 6
#define QT1070_REG_KEY1_SIGNAL_LSB 7
#define QT1070_REG_KEY2_SIGNAL_MSB 8
#define QT1070_REG_KEY2_SIGNAL_LSB 9
#define QT1070_REG_KEY3_SIGNAL_MSB 10
#define QT1070_REG_KEY3_SIGNAL_LSB 11
#define QT1070_REG_KEY4_SIGNAL_MSB 12
#define QT1070_REG_KEY4_SIGNAL_LSB 13
#define QT1070_REG_KEY5_SIGNAL_MSB 14
#define QT1070_REG_KEY5_SIGNAL_LSB 15
#define QT1070_REG_KEY6_SIGNAL_MSB 16
#define QT1070_REG_KEY6_SIGNAL_LSB 17
/** Reference date */
#define QT1070_REG_REFDATA0_MSB 18
#define QT1070_REG_REFDATA0_LSB 19
#define QT1070_REG_REFDATA1_MSB 20
#define QT1070_REG_REFDATA1_LSB 21
#define QT1070_REG_REFDATA2_MSB 22
#define QT1070_REG_REG_REFDATA2_LSB 23
#define QT1070_REG_REFDATA3_MSB 24
#define QT1070_REG_REG_REFDATA3_LSB 25
#define QT1070_REG_REFDATA4_MSB 26
#define QT1070_REG_REFDATA4_LSB 27
#define QT1070_REG_REFDATA5_MSB 28
#define QT1070_REG_REFDATA5_LSB 29
#define QT1070_REG_REFDATA6_MSB 30
#define QT1070_REG_REFDATA6_LSB 31
/** Negative threshold level */
#define QT1070_REG_NTHR_KEY0 32
#define QT1070_REG_NTHR_KEY1 33
#define QT1070_REG_NTHR_KEY2 34
#define QT1070_REG_NTHR_KEY3 35
#define QT1070_REG_NTHR_KEY4 36
#define QT1070_REG_NTHR_KEY5 37
#define QT1070_REG_NTHR_KEY6 38
/** Adjacent key suppression level */
#define QT1070_REG_AVEAKS_KEY0 39
#define QT1070_REG_AVEAKS_KEY1 40
#define QT1070_REG_AVEAKS_KEY2 41
#define QT1070_REG_AVEAKS_KEY3 42
#define QT1070_REG_AVEAKS_KEY4 43
#define QT1070_REG_AVEAKS_KEY5 44
#define QT1070_REG_AVEAKS_KEY6 45
/** Detection interator conter for key*/
#define QT1070_REG_DI_KEY0 46
#define QT1070_REG_DI_KEY1 47
#define QT1070_REG_DI_KEY2 48
#define QT1070_REG_DI_KEY3 49
#define QT1070_REG_DI_KEY4 50
#define QT1070_REG_DI_KEY5 51
#define QT1070_REG_DI_KEY6 52
/** Low power mode */
#define QT1070_REG_LOWPOWER_MODE 54
/** Maximum on duration */
#define QT1070_REG_MAX_DURATION 55
/** Calibrate */
#define QT1070_REG_CALIRATE 56
/** Reset */
#define QT1070_REG_RESET 57
/** Detection Status. */
/** This bit is set during a calibration sequence.*/
#define QT_CALIBRATE_BIT 7
/** This bit is set if the time to acquire all key signals exceeds 8 ms*/
#define QT_OVERFLOW_BIT 6
/** This bit is set if Comms mode is enabled. */
#define QT_COMMSENABLED_BIT 5
/** This bit is set if any keys are in detect. */
#define QT_TOUCH_BIT 0
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t QT1070_GetChipId(Twid *pTwid);
extern uint8_t QT1070_GetFirmwareVersion(Twid *pTwid);
extern uint8_t QT1070_GetDetection_Status(Twid *pTwid);
extern uint8_t QT1070_GetKey_Status(Twid *pTwid);
extern uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key);
extern uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key);
extern void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold);
extern void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks);
extern void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di);
extern void QT1070_StartCalibrate(Twid *pTwid);
extern void QT1070_StartReset(Twid *pTwid);
#endif // QT1070_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* \file
*
* \section Purpose
* Small function for gererating random number.
*
*------------------------------------------------------------------------------*/
#ifndef _RAND_
#define _RAND_
/*------------------------------------------------------------------------------
* Global Functions
*------------------------------------------------------------------------------*/
extern void srand( uint32_t dwSeed ) ;
extern uint32_t rand( void ) ;
#endif /* #ifndef _RAND_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for Real Time Clock calibration (RTC) .
*
*/
/** RTC crystal **/
typedef struct
{
int8_t Tempr;
int16_t PPM;
uint8_t NEGPPM;
uint8_t HIGHPPM;
uint16_t CORRECTION;
}RTC_PPMLookup;
extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr);

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file syscalls.h
*
* Implementation of newlib syscall.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdarg.h>
#include <sys/types.h>
#include <sys/stat.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern caddr_t _sbrk ( int incr ) ;
extern int link( char *old, char *new ) ;
extern int _close( int file ) ;
extern int _fstat( int file, struct stat *st ) ;
extern int _isatty( int file ) ;
extern int _lseek( int file, int ptr, int dir ) ;
extern int _read(int file, char *ptr, int len) ;
extern int _write( int file, char *ptr, int len ) ;

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \par Purpose
*
* Methods and definitions for Global time tick and wait functions.
*
* Defines a common and simpliest use of Time Tick, to increase tickCount
* every 1ms, the application can get this value through GetTickCount().
*
* \par Usage
*
* -# Configure the System Tick with TimeTick_Configure() when MCK changed
* \note
* Must be done before any invoke of GetTickCount(), Wait() or Sleep().
* -# Uses GetTickCount to get current tick value.
* -# Uses Wait to wait several ms.
* -# Uses Sleep to enter wait for interrupt mode to wait several ms.
*
*/
#ifndef _TIMETICK_
#define _TIMETICK_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;
extern void TimeTick_Increment( uint32_t dwInc ) ;
extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick);
extern uint32_t GetTickCount( void ) ;
extern void Wait( volatile uint32_t dwMs ) ;
extern void Sleep( volatile uint32_t dwMs ) ;
#endif /* _TIMETICK_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup tsd_module TouchScreen Driver
*
* \section Purpose
*
* This unit provides a very powerful touchscreen driver which handles all the
* complexity. This includes touchscreen calibration, retrieving measurements,
* configuring the TSADC, etc.
*
* \section Usage
*
* -# Implement ADC interrupt handler in application, to invoke TSD_Handler()
* to handle ADC sampling events for touchscreen monitor.
* -# Call TSD_Initialize() to initialize ADC used for touchscreen.
* -# Call TSD_Calibrate() to do touchscreen calibration with LCD, and enable
* touchscreen monitor if calibration success.
* -# Call TSD_Enable() to enable or disable touchscreen monitoring.
* -# Declare a global TSD_PenPressed() function anywhere in your code. This
* function will get called every time the pen is pressed on the screen.
* -# Declare a global TSD_PenMoved() function, which will get called whenever
* the pen stays in contact with the screen but changes position.
* -# Declare a global TSD_PenReleased() function, which will be invoked as the
* pen is lifted from the screen.
*/
#ifndef TSD_H
#define TSD_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSD_Handler(uint32_t dwAdcStatus);
extern void TSD_Initialize(void);
extern void TSD_DeInitialize(void);
extern void TSD_Enable(uint8_t bEnDis);
extern uint8_t TSD_Calibrate(void);
/* calibration used functions */
extern void TSD_GetRawMeasurement(uint32_t * pData);
extern void TSD_WaitPenPressed(void);
extern void TSD_WaitPenReleased(void);
/* callbacks */
extern void TSD_PenPressed(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenMoved(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenReleased(uint32_t x, uint32_t y);
#endif //#ifndef TSD_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
#ifndef TSD_COM_H
#define TSD_COM_H
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSDCom_InterpolateMeasurement(
const uint32_t *pData,
uint32_t *pPoint);
uint8_t TSDCom_Calibrate(void);
uint8_t TSDCom_IsCalibrationOk(void);
void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size);
void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size);
#endif /* #ifndef TSD_COM_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _TWID_
#define _TWID_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/** TWI driver is currently busy. */
#define TWID_ERROR_BUSY 1
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \brief TWI driver structure. Holds the internal state of the driver.*/
typedef struct _Twid
{
/** Pointer to the underlying TWI peripheral.*/
Twi *pTwi ;
/** Current asynchronous transfer being processed.*/
Async *pTransfer ;
} Twid;
/*----------------------------------------------------------------------------
* Export functions
*----------------------------------------------------------------------------*/
extern void TWID_Initialize( Twid *pTwid, Twi *pTwi ) ;
extern void TWID_Handler( Twid *pTwid ) ;
extern uint8_t TWID_Read(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync);
extern uint8_t TWID_DmaRead(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID);
extern uint8_t TWID_Write(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync);
extern uint8_t TWID_DmaWrite(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID);
#ifdef __cplusplus
}
#endif
#endif //#ifndef TWID_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef WAV_H
#define WAV_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
/* Standard WAV file header information. */
typedef struct _WavHeader
{
/* Contains the letters "RIFF" in ASCII form. */
unsigned int chunkID;
/* Size of the rest of the chunk following this number.*/
unsigned int chunkSize;
/* Contains the letters "WAVE".*/
unsigned int format;
/* Contains the letters "fmt ".*/
unsigned int subchunk1ID;
/* 16 for PCM. This is the size of the rest of the Subchunk which follows this number.*/
unsigned int subchunk1Size;
/* PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression.*/
unsigned short audioFormat;
/* Mono = 1, Stereo = 2, etc.*/
unsigned short numChannels;
/* 8000, 44100, etc.*/
unsigned int sampleRate;
/* SampleRate * NumChannels * BitsPerSample/8*/
unsigned int byteRate;
/* NumChannels * BitsPerSample/8*/
unsigned short blockAlign;
/* 8 bits = 8, 16 bits = 16, etc.*/
unsigned short bitsPerSample;
/* Contains the letters "data".*/
unsigned int subchunk2ID;
/* Number of bytes in the data.*/
unsigned int subchunk2Size;
} WavHeader;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern unsigned char WAV_IsValid(const WavHeader *header);
extern void WAV_DisplayInfo(const WavHeader *header);
#endif //#ifndef WAV_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation WM8904 driver.
*
*/
#ifndef WM8904_H
#define WM8904_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
#define WM8904_CSB_STATE (0x0 << 0)
/** Slave address */
#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE
/** Reset register*/
#define WM8904_REG_RESET 0x00
/** Bias control 0 register*/
#define WM8904_REG_BIAS_CTRL0 0x04
/** VMID control 0 register*/
#define WM8904_REG_VMID_CTRL0 0x05
/** MIC Bias control 0 register*/
#define WM8904_REG_MICBIAS_CTRL0 0x06
/** Bias control 1 register*/
#define WM8904_REG_BIAS_CTRL1 0x07
/** Power management control 0 register*/
#define WM8904_REG_POWER_MANG0 0x0C
/** Power management control 2 register*/
#define WM8904_REG_POWER_MANG2 0x0E
/** Power management control 3 register*/
#define WM8904_REG_POWER_MANG3 0x0F
/** Power management control 6 register*/
#define WM8904_REG_POWER_MANG6 0x12
/** Clock rate0 register*/
#define WM8904_REG_CLOCK_RATE0 0x14
/** Clock rate1 register*/
#define WM8904_REG_CLOCK_RATE1 0x15
/** Clock rate2 register*/
#define WM8904_REG_CLOCK_RATE2 0x16
/** Audio interface0 register*/
#define WM8904_REG_AUD_INF0 0x18
/** Audio interface1 register*/
#define WM8904_REG_AUD_INF1 0x19
/** Audio interface2 register*/
#define WM8904_REG_AUD_INF2 0x1A
/** Audio interface3 register*/
#define WM8904_REG_AUD_INF3 0x1B
/** ADC digital 0 register*/
#define WM8904_REG_ADC_DIG0 0x20
/** ADC digital 1 register*/
#define WM8904_REG_ADC_DIG1 0x21
/** Analogue left input 0 register*/
#define WM8904_REG_ANALOGUE_LIN0 0x2C
/** Analogue right input 0 register*/
#define WM8904_REG_ANALOGUE_RIN0 0x2D
/** Analogue left input 1 register*/
#define WM8904_REG_ANALOGUE_LIN1 0x2E
/** Analogue right input 1 register*/
#define WM8904_REG_ANALOGUE_RIN1 0x2F
/** Analogue left output 1 register*/
#define WM8904_REG_ANALOGUE_LOUT1 0x39
/** Analogue right output 1 register*/
#define WM8904_REG_ANALOGUE_ROUT1 0x3A
/** Analogue left output 2 register*/
#define WM8904_REG_ANALOGUE_LOUT2 0x3B
/** Analogue right output 2 register*/
#define WM8904_REG_ANALOGUE_ROUT2 0x3C
/** Analogue output 12 ZC register*/
#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D
/** DC servo 0 register*/
#define WM8904_REG_DC_SERVO0 0x43
/** Analogue HP 0 register*/
#define WM8904_REG_ANALOGUE_HP0 0x5A
/** Charge pump 0 register*/
#define WM8904_REG_CHARGE_PUMP0 0x62
/** Class W 0 register*/
#define WM8904_REG_CLASS0 0x68
/** FLL control 1 register*/
#define WM8904_REG_FLL_CRTL1 0x74
/** FLL control 2 register*/
#define WM8904_REG_FLL_CRTL2 0x75
/** FLL control 3 register*/
#define WM8904_REG_FLL_CRTL3 0x76
/** FLL control 4 register*/
#define WM8904_REG_FLL_CRTL4 0x77
/** FLL control 5 register*/
#define WM8904_REG_FLL_CRTL5 0x78
/** DUMMY register*/
#define WM8904_REG_END 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr);
extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data);
extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK);
extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value);
extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device);
#endif // WM8904_H

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/include/xdma_hardware_interface.h Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _XDMAD_IF_H
#define _XDMAD_IF_H
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** DMA hardware interface */
typedef struct _XdmaHardwareInterface {
uint8_t bXdmac; /**< DMA Controller number */
uint32_t bPeriphID; /**< Peripheral ID */
uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/
uint8_t bIfID; /**< DMA Interface ID */
} XdmaHardwareInterface;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bXdmac, uint8_t bPeriphID);
extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bXdmac, uint8_t bPeriphID, uint8_t bTransfer);
#endif //#ifndef _XDMAD_IF_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _XDMAD_H
#define _XDMAD_H
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
/** \addtogroup dmad_defines DMA Driver Defines
@{*/
/*----------------------------------------------------------------------------
* Consts
*----------------------------------------------------------------------------*/
#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */
#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */
#define XDMAD_TRANSFER_TX 0
#define XDMAD_TRANSFER_RX 1
/* XDMA_MBR_UBC */
#define XDMA_UBC_NDE (0x1u << 24)
#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)
#define XDMA_UBC_NSEN (0x1u << 25)
#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)
#define XDMA_UBC_NDEN (0x1u << 26)
#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)
#define XDMA_UBC_NVIEW_Pos 27
#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)
#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)
/*----------------------------------------------------------------------------
* MACRO
*----------------------------------------------------------------------------*/
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_structs DMA Driver Structs
@{*/
/** DMA status or return code */
typedef enum _XdmadStatus {
XDMAD_OK = 0, /**< Operation is sucessful */
XDMAD_PARTIAL_DONE,
XDMAD_DONE,
XDMAD_BUSY, /**< Channel occupied or transfer not finished */
XDMAD_ERROR, /**< Operation failed */
XDMAD_CANCELED /**< Operation canceled */
} eXdmadStatus, eXdmadRC;
/** DMA state for channel */
typedef enum _XdmadState {
XDMAD_STATE_FREE = 0, /**< Free channel */
XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */
XDMAD_STATE_START, /**< DMA started */
XDMAD_STATE_IN_XFR, /**< DMA in trasfering */
XDMAD_STATE_DONE, /**< DMA transfer done */
} eXdmadState;
/** DMA transfer callback */
typedef void (*XdmadTransferCallback)(uint32_t status, void* pArg);
/** DMA driver channel */
typedef struct _XdmadChannel {
XdmadTransferCallback fCallback; /**< Callback */
void* pArg; /**< Callback argument */
uint8_t bIrqOwner; /**< Uses DMA handler or external one */
uint8_t bSrcPeriphID; /**< HW ID for source */
uint8_t bDstPeriphID; /**< HW ID for destination */
uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */
uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */
uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */
uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */
volatile uint8_t state; /**< DMA channel state */
} sXdmadChannel;
/** DMA driver instance */
typedef struct _Xdmad {
Xdmac *pXdmacs[2];
sXdmadChannel XdmaChannels[2][16];
uint8_t numControllers;
uint8_t numChannels;
uint8_t pollingMode;
uint8_t pollingTimeout;
} sXdmad;
typedef struct _XdmadCfg {
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
/** Block Control Member. */
uint32_t mbr_bc;
/** Data Stride Member. */
uint32_t mbr_ds;
/** Source Microblock Stride Member. */
uint32_t mbr_sus;
/** Destination Microblock Stride Member. */
uint32_t mbr_dus;
} sXdmadCfg;
/** \brief Structure for storing parameters for DMA view0 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView0
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Transfer Address Member. */
uint32_t mbr_ta;
}LinkedListDescriporView0;
/** \brief Structure for storing parameters for DMA view1 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView1
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
}LinkedListDescriporView1;
/** \brief Structure for storing parameters for DMA view2 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView2
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
}LinkedListDescriporView2;
/** \brief Structure for storing parameters for DMA view3 that can be
* performed by the DMA Master transfer.*/
typedef struct _LinkedListDescriporView3
{
/** Next Descriptor Address number. */
uint32_t mbr_nda;
/** Microblock Control Member. */
uint32_t mbr_ubc;
/** Source Address Member. */
uint32_t mbr_sa;
/** Destination Address Member. */
uint32_t mbr_da;
/** Configuration Register. */
uint32_t mbr_cfg;
/** Block Control Member. */
uint32_t mbr_bc;
/** Data Stride Member. */
uint32_t mbr_ds;
/** Source Microblock Stride Member. */
uint32_t mbr_sus;
/** Destination Microblock Stride Member. */
uint32_t mbr_dus;
}LinkedListDescriporView3;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_functions DMA Driver Functionos
@{*/
extern void XDMAD_Initialize( sXdmad *pXdmad,
uint8_t bPollingMode );
extern void XDMAD_Handler( sXdmad *pDmad);
extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,
uint8_t bSrcID, uint8_t bDstID);
extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,
uint32_t dwChannel,
sXdmadCfg *pXdmaParam,
uint32_t dwXdmaDescCfg,
uint32_t dwXdmaDescAddr);
extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel);
extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel );
extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad,
uint32_t dwChannel,
XdmadTransferCallback fCallback,
void* pArg );
extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel );
/** @}*/
/**@}*/
#endif //#ifndef _XDMAD_H

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/resources/ewarm/sama5d4x-ek-ddram.mac Normal file
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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d4-ek-ddram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
__var REG_CKGR_MOR;
__var CKGR_MOR_MOSCXTEN;
__var CKGR_MOR_MOSCXTBY;
__var CKGR_MOR_MOSCRCEN;
__var CKGR_MOR_MOSCSEL;
__var REG_CKGR_MCFR;
__var CKGR_MCFR_MAINFRDY;
__var REG_PMC_SR;
__var PMC_SR_MCKRDY;
__var PMC_SR_LOCKA;
__var PMC_PCK_CSS_MAIN_CLK;
__var REG_CKGR_PLLAR;
__var REG_PMC_PLLICPR;
__var REG_PMC_MCKR;
__var PMC_MCKR_PLLADIV2_DIV2;
__var PMC_MCKR_PRES_Msk;
__var PMC_MCKR_PRES_CLOCK;
__var PMC_MCKR_MDIV_Msk;
__var PMC_MCKR_MDIV_PCK_DIV3;
__var PMC_MCKR_CSS_PLLA_CLK;
__var PMC_SR_MOSCSELS;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
ini();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0x1D3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__tempo_var = __readMemory32(0xF0018028,"Memory"); // PLL A reg addr is 0xF0018028
if (__tempo_var == 0x215C3F01)
{
__message " ----------- PLL A is already set to 1056 MHz - Skip DDR2 init -----------";
__tempo_var = __readMemory32(0xF001000C,"Memory");
if (__tempo_var == 0x2223A338)
{
__message " ----------- DDR2 is already Up - skip initialization -----------";
}
else
{
__initDDR2(); //* Init DDR2 memory
__message "------------ DDR2 is initialized ------------";
}
}
else
{
__writeMemory32(0x00FFFFFF,0xF001C210,"Memory"); // SLAVE 4
__writeMemory32(0x0000000F,0xF001C290,"Memory");
__writeMemory32(0x0000FFFF,0xF001C250,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C214,"Memory"); // SLAVE 5
__writeMemory32(0x0000000F,0xF001C294,"Memory");
__writeMemory32(0x0000FFFF,0xF001C254,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C218,"Memory"); // SLAVE 6
__writeMemory32(0x0000000F,0xF001C298,"Memory");
__writeMemory32(0x0000FFFF,0xF001C258,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C21C,"Memory"); // SLAVE 7
__writeMemory32(0x0000000F,0xF001C29C,"Memory");
__writeMemory32(0x0000FFFF,0xF001C25C,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C220,"Memory"); // SLAVE 8
__writeMemory32(0x0000000F,0xF001C2A0,"Memory");
__writeMemory32(0x0000FFFF,0xF001C260,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C224,"Memory"); // SLAVE 9
__writeMemory32(0x0000000F,0xF001C2A4,"Memory");
__writeMemory32(0x0000FFFF,0xF001C264,"Memory");
__writeMemory32(0x00FFFFFF,0xF001C228,"Memory"); // SLAVE 10
__writeMemory32(0x0000000F,0xF001C2A8,"Memory");
__writeMemory32(0x0000FFFF,0xF001C268,"Memory");
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA(87);
PMC_SetMckPllaDiv();
PMC_SetMckPrescaler();
PMC_SetMckDivider();
PMC_SwitchMck2Pll();
__message "------------ PLL set to 1056 MHz, MCK set to 176 MHz ------------";
__initDDR2(1); //* Init DDR2 memory
__message "------------ DDR2 is initialized ------------";
}
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFC069040,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* ini() :
* Function description
* Write ARM9 core regsiter to Reset value
*/
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFC068644,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}
/*********************************************************************
*
* PMC_SelectExt12M_Osc()
*
* Function description
* Select external 12MHz oscillator
*/
PMC_SelectExt12M_Osc()
{
// --------- Select_ext_Crystal_32k ---------------
REG_CKGR_MOR = 0xF0018020;
CKGR_MOR_MOSCXTEN = (0x1 << 0); /*(CKGR_MOR) Main Crystal Oscillator Enable */
CKGR_MOR_MOSCXTBY = (0x1 << 1); /*(CKGR_MOR) Main Crystal Oscillator Bypass */
CKGR_MOR_MOSCRCEN = (0x1 << 3); /*(CKGR_MOR) Main On-Chip RC Oscillator Enable */
CKGR_MOR_MOSCSEL = (0x1 << 24); /*(CKGR_MOR) Main Oscillator Selection */
REG_CKGR_MCFR = 0xF0018024; /*(PMC) Main Clock Frequency Register */
CKGR_MCFR_MAINFRDY = (0x1 << 16); /*(CKGR_MCFR) Main Clock Ready */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
PMC_SR_MOSCSELS = (0x1 << 16); /*(PMC_SR) Main Oscillator Selection Status */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
/* enable external OSC 12 MHz */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCXTEN | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait Main CLK Ready */
while(!((__readMemory32(REG_CKGR_MCFR,"Memory")) & CKGR_MCFR_MAINFRDY));
/* disable external OSC 12 MHz bypass */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var = (__tempo_var & ~CKGR_MOR_MOSCXTBY) | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* switch MAIN clock to external OSC 12 MHz*/
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCSEL | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait MAIN clock status change for external OSC 12 MHz selection*/
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MOSCSELS));
/* in case when MCK is running on MAIN CLK */
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__message " -------- PMC_SelectExt12M_Osc ---------- REG_CKGR_MOR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Main()
*
* Function description
* Switch PMC from MCK to main clock.
*/
PMC_SwitchMck2Main()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_PCK_CSS_MAIN_CLK = (0x1 << 0); /*(PMC_PCK[3]) Main Clock is selected */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
/* Select Main Oscillator as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03)| PMC_PCK_CSS_MAIN_CLK ;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Main ----------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetPllA()
*
* Function description
* Configure PLLA Registe.
*/
PMC_SetPllA(pllmul)
{
REG_CKGR_PLLAR = 0xF0018028; /*(PMC) PLLA Register */
REG_PMC_PLLICPR = 0xF0018080; /*(PMC) PLL Charge Pump Current Register */
REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */
PMC_SR_LOCKA = (0x1 << 1); /*(PMC_SR) PLLA Lock Status */
__writeMemory32(((0x1 << 29) | (0x3F << 8) | ( 0 << 14) | ((pllmul) << 18) | 1 ), REG_CKGR_PLLAR,"Memory");
//__writeMemory32((0x03<<8), REG_PMC_PLLICPR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_LOCKA));
__mac_i=__readMemory32(REG_CKGR_PLLAR,"Memory");
__message " --------- PMC_SetPllA ---------------- REG_CKGR_PLLAR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckPllaDiv()
*
* Function description
* Configure MCK PLLA divider.
*/
PMC_SetMckPllaDiv()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_PLLADIV2_DIV2 = (0x1 << 12); /*(PMC_MCKR) PLLA clock frequency is divided by 2. */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
if ((__tempo_var & PMC_MCKR_PLLADIV2_DIV2) != PMC_MCKR_PLLADIV2_DIV2)
{
__tempo_var |= PMC_MCKR_PLLADIV2_DIV2;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
}
}
/*********************************************************************
*
* PMC_SetMckPrescaler()
*
* Function description
* Configure MCK Prescaler.
*/
PMC_SetMckPrescaler()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_PRES_Msk = (0x7 << 4); /*(PMC_MCKR) Master/Processor Clock Prescaler */
PMC_MCKR_PRES_CLOCK = (0x0 << 4); /*(PMC_MCKR) Selected clock */
/* Change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLOCK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckPrescaler -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckDivider()
*
* Function description
* Configure MCK Divider.
*/
PMC_SetMckDivider()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_MDIV_Msk = (0x3 << 8); /*(PMC_MCKR) Master Clock Division */
PMC_MCKR_MDIV_PCK_DIV3 = (0x3 << 8); /*(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
/* change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_MDIV_Msk) | PMC_MCKR_MDIV_PCK_DIV3;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckDivider -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Pll()
*
* Function description
* Switch PMC from MCK to PLL clock.
*/
PMC_SwitchMck2Pll()
{
REG_PMC_MCKR = 0xF0018030; /*(PMC) Master Clock Register */
PMC_MCKR_CSS_PLLA_CLK = (0x2 << 0); /*(PMC_MCKR) PLLACK/PLLADIV2 is selected */
/* Select PLL as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03) | PMC_MCKR_CSS_PLLA_CLK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Pll -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
// ---------------------------------------------------------------------------
// Function Name : __initDDR2
// Object : Set DDR2 memory for working at 176 Mhz
// ---------------------------------------------------------------------------
__initDDR2(type)
{
// ------------------ DDR Controller Registers --------------
// #define REG_MPDDRC_MR (0xF0010000U) /**< \brief (MPDDRC) MPDDRC Mode Register */
// #define REG_MPDDRC_RTR (0xF0010004U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */
// #define REG_MPDDRC_CR (0xF0010008U) /**< \brief (MPDDRC) MPDDRC Configuration Register */
// #define REG_MPDDRC_TPR0 (0xF001000CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */
// #define REG_MPDDRC_TPR1 (0xF0010010U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */
// #define REG_MPDDRC_TPR2 (0xF0010014U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */
// #define REG_MPDDRC_LPR (0xF001001CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */
// #define REG_MPDDRC_MD (0xF0010020U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */
// #define REG_MPDDRC_LPDDR2_LPR (0xF0010028U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */
// #define REG_MPDDRC_LPDDR2_CAL_MR4 (0xF001002CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */
// #define REG_MPDDRC_LPDDR2_TIM_CAL (0xF0010030U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */
// #define REG_MPDDRC_IO_CALIBR (0xF0010034U) /**< \brief (MPDDRC) MPDDRC IO Calibration */
// #define REG_MPDDRC_OCMS (0xF0010038U) /**< \brief (MPDDRC) MPDDRC OCMS Register */
// #define REG_MPDDRC_OCMS_KEY1 (0xF001003CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */
// #define REG_MPDDRC_OCMS_KEY2 (0xF0010040U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */
// #define REG_MPDDRC_CONF_ARBITER (0xF0010044U) /**< \brief (MPDDRC) MPDDRC Configuration Arbiter */
// #define REG_MPDDRC_TIMEOUT (0xF0010048U) /**< \brief (MPDDRC) MPDDRC Time-out Port 0/1/2/3 */
// #define REG_MPDDRC_REQ_PORT_0123 (0xF001004CU) /**< \brief (MPDDRC) MPDDRC Time-out Request Port 0/1/2/3 */
// #define REG_MPDDRC_REQ_PORT_4567 (0xF0010050U) /**< \brief (MPDDRC) MPDDRC Time-out Request Port 4/5/6/7 */
// #define REG_MPDDRC_BDW_PORT_0123 (0xF0010054U) /**< \brief (MPDDRC) MPDDRC Bandwidth Port 0/1/2/3 */
// #define REG_MPDDRC_BDW_PORT_4567 (0xF0010058U) /**< \brief (MPDDRC) MPDDRC Bandwidth Port 4/5/6/7 */
// #define REG_MPDDRC_RD_DATA_PATH (0xF001005CU) /**< \brief (MPDDRC) MPDDRC_READ_DATA_PATH */
// #define REG_MPDDRC_SAW (0xF0010060U) /**< \brief (MPDDRC) MPDDRC Smart Adaptation Wrapper 0 Register */
// #define REG_MPDDRC_WPMR (0xF00100E4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */
// #define REG_MPDDRC_WPSR (0xF00100E8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */
// #define REG_MPDDRC_DLL_OS (0xF0010100U) /**< \brief (MPDDRC) MPDDRC DLL Offset Selection Register */
// #define REG_MPDDRC_DLL_MO (0xF0010104U) /**< \brief (MPDDRC) MPDDRC DLL MASTER Offset Register */
// #define REG_MPDDRC_DLL_SO0 (0xF0010108U) /**< \brief (MPDDRC) MPDDRC DLL SLAVE Offset 0 Register */
// #define REG_MPDDRC_DLL_SO1 (0xF001010CU) /**< \brief (MPDDRC) MPDDRC DLL SLAVE Offset 1 Register */
// #define REG_MPDDRC_DLL_WRO (0xF0010110U) /**< \brief (MPDDRC) MPDDRC DLL CLKWR Offset Register */
// #define REG_MPDDRC_DLL_ADO (0xF0010114U) /**< \brief (MPDDRC) MPDDRC DLL CLKAD Offset Register */
// #define REG_MPDDRC_DLL_SM (0xF0010118U) /**< \brief (MPDDRC) MPDDRC DLL Status MASTER0 Register */
// #define REG_MPDDRC_DLL_SSL (0xF0010128U) /**< \brief (MPDDRC) MPDDRC DLL Status SLAVE0 Register */
// #define REG_MPDDRC_DLL_SWR (0xF0010148U) /**< \brief (MPDDRC) MPDDRC DLL Status CLKWR0 Register */
// #define REG_MPDDRC_DLL_SAD (0xF0010158U) /**< \brief (MPDDRC) MPDDRC DLL Status CLKAD Register */
// -----------------------------------------------
__delay(2);
__writeMemory32(0x00008000,0xFC068644,"Memory"); // Disable Watchdog
__writeMemory32(0x00010000,0xF0018010,"Memory"); // Enable MPDDR controller clock
__writeMemory32(0x00000004,0xF0018000,"Memory"); // System Clock Enable Register : Enable DDR clock
__writeMemory32(0x00000001,0xF001005C,"Memory"); // Read Data Path register : Sampling point is shifted of one cycle
__writeMemory32(0x00870514,0xF0010034,"Memory"); // MPDDRC I/O Calibration Register : RZQ_60_RZQ_50 + enable permanent calibration + TZQIO = 5
__writeMemory32(0x00000006,0xF0010020,"Memory"); // Memory Device Register : 32bit mode - DDR2 mode
__writeMemory32(0x2223A338,0xF001000C,"Memory"); // Timing 0 Register : tras | trcd | twr | trc | trp | trrd | twtr | tmrd
__writeMemory32(0x0b206417,0xF0010010,"Memory"); // Timing 1 Register : trfc | txsnr | txsrd | txp
__writeMemory32(0x00072328,0xF0010014,"Memory"); // Timing 2 Register : txard | tards | trpa | trtp | tfaw
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : row = 14, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength
__writeMemory32(0x00000001,0xF0010000,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1); // wait 1 ms
__writeMemory32(0x00000001,0xF0010000,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xF0010000,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR2 BA0=0 BA1=1
__writeMemory32(0x00000000,0x28000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR3 BA0=1 BA1=1
__writeMemory32(0x00000000,0x2C000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR1 BA0=1 BA1=0 ENABLE DLL
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B000BD,0xF0010008,"Memory"); // Configuration Register : Enable DLL reset
__writeMemory32(0x00000003,0xF0010000,"Memory"); // Mode register : command RESET DLL
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xF0010000,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xF0010000,"Memory"); // Mode register : 2 * command Auto-Refresh
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xF0010000,"Memory"); // Mode register :
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : disable DLL reset
__writeMemory32(0x00000003,0xF0010000,"Memory"); // Mode register : MRS initialize device operation (CAS latency, burst length and disable DLL reset)
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0703D,0xF0010008,"Memory"); // Configuration Register : OCD default value
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : EMRS1 OCD Default values
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0003D,0xF0010008,"Memory"); // Configuration Register : OCD exit
__writeMemory32(0x00000005,0xF0010000,"Memory"); // Mode register : EMRS1 OCD exit
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000000,0xF0010000,"Memory"); // Mode register : command Normal mode
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x000002B0,0xF0010004,"Memory"); // Refresh Timer register
__message "------------------------------- DDR2 memory init for 176 MHz ----------------------------------";
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d3x-ek-sram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
//CheckNoRemap();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0x1D3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
//__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
//CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFC069040,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
__tempo_var = __readMemory32(0x00000000,"Memory");
if (__tempo_var == 0xAA55AA55)
{
__data_test = 0x55AA55AA;
}
else
{
__data_test = 0xAA55AA55;
}
__writeMemory32(__data_test,0x00000000,"Memory");
__dummy_read = __readMemory32(0x00000000,"Memory");
__writeMemory32(__tempo_var,0x00000000,"Memory");
if (__dummy_read == __data_test)
{
__message " ------------------------ The Remap is already done ------------------------";
}
else
{
__message " ------------------------ The Remap is not DONE ------------------------";
__writeMemory32(0x00000001,0x00700000,"Memory");
__delay(50);
__message "------------ The Remap was executed ------------";
}
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFC068644,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_DDRAM_end__ = 0x23FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x21FFFF;
define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x24000000;
define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x24FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x200;
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_fiqstack__ = 0x60;
define symbol __ICFEDIT_size_abtstack__ = 0x60;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x60;
/*-Exports-*/
export symbol __ICFEDIT_region_DDRAM_start__;
export symbol __ICFEDIT_region_DDRAM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_fiqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__];
define region STACK_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ size __ICFEDIT_size_startup__+__ICFEDIT_size_cstack__+__ICFEDIT_size_irqstack__+__ICFEDIT_size_fiqstack__+__ICFEDIT_size_heap__];
define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__+__ICFEDIT_size_cstack__+__ICFEDIT_size_irqstack__+__ICFEDIT_size_fiqstack__+__ICFEDIT_size_heap__ to __ICFEDIT_region_DDRAM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in VEC_region { section .vectors };
place in DDRAM_region { readonly };
place in DDRAM_region { readwrite };
place in DDRAM_region { zeroinit };
place in STACK_region { block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block CSTACK, block HEAP };
place in DMA_BUF_region {section region_dma_nocache };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x21FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_fiqstack__ = 0x60;
define symbol __ICFEDIT_size_abtstack__ = 0x60;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x400;
/*-Exports-*/
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_fiqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing=none { readwrite };
do not initialize { readonly section .noinit };
place in VEC_region { section .vectors };
place in RAM_region { readonly };
place in RAM_region { section .cstartup };
place in RAM_region { readwrite, block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block CSTACK, block HEAP };

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <string.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/// BMP offset for header
#define IMAGE_OFFSET 0x100
/*----------------------------------------------------------------------------
* Internal types
*----------------------------------------------------------------------------*/
/** Describe the BMP palette */
typedef struct _BMPPaletteEntry
{
/** Blue value */
uint8_t b;
/** Green value */
uint8_t g;
/** Red value */
uint8_t r;
/** Filler character value */
uint8_t filler;
} BMPPaletteEntry ;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Test if BMP is valid.
* \param file Buffer holding the file to examinate.
* \return 1 if the header of a BMP file is valid; otherwise returns 0.
*/
uint8_t BMP_IsValid( void *file )
{
return ((BMPHeader*) file)->type == BMP_TYPE ;
}
/**
* \brief Returns the size of a BMP image given at least its header (the file does
* not have to be complete).
* \param file Pointer to the buffer which holds the BMP file.
* \return size of BMP image
*/
uint32_t BMP_GetFileSize( void *file )
{
return ((BMPHeader *) file)->fileSize ;
}
/**
* \brief Write a BMP header
* \param pAddressHeader Begin address of the BMP
* \param bmpHSize BMP heigth size
* \param bmpVSize BMP width size
* \param bmpRgb Type of BMP (YUV or RGB)
* \param nbByte_Pixels Number of byte per pixels
*/
void WriteBMPheader( uint32_t* pAddressHeader, uint32_t bmpHSize, uint32_t bmpVSize, uint8_t bmpRgb, uint8_t nbByte_Pixels )
{
uint32_t i;
uint32_t* fill;
BMPHeader *Header;
bmpRgb = bmpRgb;
fill = pAddressHeader;
for ( i=0 ; i < IMAGE_OFFSET ; i+=4 )
{
*fill++ = 0;
}
Header = (BMPHeader*) pAddressHeader;
Header->type = BMP_TYPE;
Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET;
Header->reserved1 = 0;
Header->reserved2 = 0;
Header->offset = IMAGE_OFFSET;
Header->headerSize = BITMAPINFOHEADER;
Header->width = bmpHSize;
Header->height = bmpVSize;
Header->planes = 1;
Header->bits = nbByte_Pixels * 8;
Header->compression = 0;
Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels;
Header->xresolution = 0;
Header->yresolution = 0;
Header->ncolours = 0;
Header->importantcolours = 0;
}
/**
* \brief Debug function, dislay BMP header
* \param pAddressHeader Address of the BMP
*/
void BMP_displayHeader( uint32_t* pAddressHeader )
{
#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
BMPHeader *header;
header = (BMPHeader*) pAddressHeader;
TRACE_INFO("BMP\n\r");
TRACE_INFO("type 0x%X \n\r", header->type);
TRACE_INFO("fileSize %ld \n\r", header->fileSize);
TRACE_INFO("reserved1 %d \n\r", header->reserved1);
TRACE_INFO("reserved2 %d \n\r", header->reserved2);
TRACE_INFO("offset %ld \n\r", header->offset);
TRACE_INFO("headerSize %ld \n\r", header->headerSize);
TRACE_INFO("width %ld \n\r", header->width);
TRACE_INFO("height %ld \n\r", header->height);
TRACE_INFO("planes %d \n\r", header->planes);
TRACE_INFO("bits %d \n\r", header->bits);
TRACE_INFO("compression %ld \n\r", header->compression);
TRACE_INFO("imageSize %ld \n\r", header->imageSize);
TRACE_INFO("xresolution %ld \n\r", header->xresolution);
TRACE_INFO("yresolution %ld \n\r", header->yresolution);
TRACE_INFO("ncolours %ld \n\r", header->ncolours);
TRACE_INFO("importantcolours %ld\n\r", header->importantcolours);
#else
pAddressHeader = pAddressHeader;
#endif
}
/**
* \brief Loads a BMP image located at the given address, decodes it and stores the
* resulting image inside the provided buffer. Image must have the specified
* width & height.
* If no buffer is provided, this function simply checks if it is able to
* decode the image.
* \param file Buffer which holds the BMP file.
* \param buffer Buffer in which to store the decoded image.
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
* \return 0 if the image has been loaded; otherwise returns an error code.
*/
uint8_t BMP_Decode( void *file, uint8_t *buffer, uint32_t width, uint32_t height, uint8_t bpp )
{
BMPHeader *header;
uint32_t i, j;
uint8_t r, g, b;
uint8_t *image;
// Read header information
header = (BMPHeader*) file;
// Verify that the file is valid
if ( !BMP_IsValid( file ) )
{
TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type);
return 1;
}
// Check that parameters match
if ( (header->compression != 0) || (header->width != width) || (header->height != height))
{
TRACE_ERROR("BMP_Decode: File format not supported\n\r");
TRACE_ERROR(" -> .compression = %u\n\r", (unsigned int)header->compression);
TRACE_ERROR(" -> .width = %u\n\r", (unsigned int)header->width);
TRACE_ERROR(" -> .height = %u\n\r", (unsigned int)header->height);
TRACE_ERROR(" -> .bits = %d\n\r", header->bits);
return 2;
}
// Get image data
image = (uint8_t *) ((uint32_t) file + header->offset);
// Check that the bpp resolution is supported
// Only a 24-bit output & 24- or 8-bit input are supported
if ( bpp != 24 )
{
TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r");
return 3;
}
else
{
if (header->bits == 24)
{
// Decoding is ok
if (!buffer) return 0;
// Get image data (swapping red & blue)
for ( i=0 ; i < height ; i++ )
{
for ( j=0 ; j < width; j++ )
{
r = image[((height - i - 1) * width + j) * 3 + 2];
g = image[((height - i - 1) * width + j) * 3 + 1];
b = image[((height - i - 1) * width + j) * 3];
#if defined(BOARD_LCD_RGB565)
// Interlacing
r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5);
g = (g << 1) & 0xF8;
b = b & 0xF8;
buffer[(i * width + j) * 3] = b;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = r;
#else
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
#endif //#if defined(BOARD_LCD_RGB565)
}
}
}
else
{
if ( header->bits == 8 )
{
// Decoding is ok
if (!buffer) return 0;
// Retrieve palette
BMPPaletteEntry palette[256];
memcpy( palette, (uint8_t *) ((uint32_t) file + sizeof( BMPHeader )), header->offset - sizeof( BMPHeader ) ) ;
// Decode image (reversing row order)
for ( i=0 ; i < height ; i++ )
{
for (j=0; j < width; j++)
{
r = palette[image[(height - i - 1) * width + j]].r;
g = palette[image[(height - i - 1) * width + j]].g;
b = palette[image[(height - i - 1) * width + j]].b;
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
}
}
}
else
{
TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r");
TRACE_INFO("header->bits 0x%X \n\r", header->bits);
return 4 ;
}
}
}
return 0 ;
}
/**
* \brief Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD)
*
* \param fileSource Buffer which holds the RGB file
* \param fileDestination Buffer in which to store the decoded image
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
*/
void RGB565toBGR555( uint8_t *fileSource, uint8_t *fileDestination, uint32_t width, uint32_t height, uint8_t bpp )
{
uint32_t i;
uint32_t j;
uint32_t row;
for (i=0; i < height*(bpp/8); i++)
{
row = (i*width*(bpp/8));
for (j=0; j <= width*(bpp/8); j+=2)
{
fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F)
| (fileSource[row+j]&0xE0);
fileDestination[row+j+1] = (fileSource[row+j+1]&0x03)
| ((fileSource[row+j]&0x1F)<<2);
}
}
}

283
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFC06E000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define SAIC 0xFC068400
#define AIC_FVR 0x14
#define IRQ_STACK_SIZE 8*3*4
#define FIQ_STACK_SIZE 8*3*4
#define MODE_MSK 0x1F
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define I_BIT 0x80
#define F_BIT 0x40
#define REG_SFR_AICREDIR 0xF8028054
#define REG_SFR_UID 0xF8028050
#define AICREDIR_KEY 0x5F67B102
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
.align 4
.arm
/* Exception vectors
*******************/
.section .vectors, "a", %progbits
resetVector:
ldr pc, =resetHandler /* Reset */
undefVector:
b undefVector /* Undefined instruction */
swiVector:
b swiVector /* Software interrupt */
prefetchAbortVector:
b prefetchAbortVector /* Prefetch abort */
dataAbortVector:
b dataAbortVector /* Data abort */
reservedVector:
b reservedVector /* Reserved for future use */
irqVector:
b irqHandler /* Interrupt */
fiqVector:
b fiqHandler /* Fast interrupt */
//------------------------------------------------------------------------------
/// Handles a fast interrupt request by branching to the address defined in the
/// AIC.
//------------------------------------------------------------------------------
fiqHandler:
SUB lr, lr, #4
STMFD sp!, {lr}
/* MRS lr, SPSR */
STMFD sp!, {r0}
/* Write in the IVR to support Protect Mode */
LDR lr, =SAIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
MOV r14, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =SAIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0}
/* MSR SPSR_cxsf, lr*/
LDMIA sp!, {pc}^
//------------------------------------------------------------------------------
/// Handles incoming interrupt requests by branching to the corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//------------------------------------------------------------------------------
irqHandler:
/* Save interrupt context on the stack to allow nesting */
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
//------------------------------------------------------------------------------
/// Initializes the chip and branches to the main() function.
//------------------------------------------------------------------------------
.section .textEntry
.global entry
entry:
resetHandler:
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
//mrc p15, 0, r0, c1, c0, 2
//orr r0, r0, #0xf00000
//mcr p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
//fmrx r0, fpexc
//orr r0, r0, #0x40000000
//fmxr fpexc, r0
/* Useless instruction for referencing the .vectors section */
ldr r0, =resetVector
/* Set pc to actual code location (i.e. not in remap zone) */
ldr pc, =1f
/* Initialize the prerelocate segment */
1:
ldr r0, =_efixed
ldr r1, =_sprerelocate
ldr r2, =_eprerelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Perform low-level initialization of the chip using LowLevelInit() */
ldr sp, =_cstack
stmfd sp!, {r0}
ldr r0, =LowLevelInit
blx r0
/* Initialize the postrelocate segment */
ldmfd sp!, {r0}
ldr r1, =_spostrelocate
ldr r2, =_epostrelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Clear the zero segment */
ldr r0, =_szero
ldr r1, =_ezero
mov r2, #0
1:
cmp r0, r1
strcc r2, [r0], #4
bcc 1b
MRS r0, cpsr
/* Set up the fast interrupt stack pointer.*/
bic r0, r0, #MODE_MSK
orr r0, r0, #ARM_MODE_FIQ
msr cpsr_c, r0
ldr sp, =_fiqstack
bic sp,sp,#0x7
/* Set up the normal interrupt stack pointer.*/
bic r0, r0, #MODE_MSK
orr r0, r0, #ARM_MODE_IRQ
msr cpsr_c, r0
ldr sp, =_irqstack
bic sp,sp,#0x7
/* Set up the stack pointer.*/
bic r0 ,r0, #MODE_MSK
orr r0 ,r0, #ARM_MODE_SYS
msr cpsr_c, r0
ldr sp, =_sysstack
bic sp,sp,#0x7
bic r0 ,r0, #MODE_MSK
orr r0 ,r0, #ARM_MODE_SVC
msr cpsr_c, r0
ldr sp, =_cstack
bic sp,sp,#0x7
// Redirect FIQ to IRQ
LDR r0, =AICREDIR_KEY
LDR r1, = REG_SFR_UID
LDR r2, = REG_SFR_AICREDIR
LDR r3,[r1]
EORS r0, r0, r3
ORRS r0, r0, #0x01
STR r0, [r2]
/*Initialize the C library */
ldr r3, =__libc_init_array
mov lr, pc
bx r3
/* Branch to main()
******************/
ldr r0, =main
blx r0
/* Loop indefinitely when program is finished */
1:
b 1b

313
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_cstartup_iar.s Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
IAR startup file for SAMA5D4X microcontrollers.
*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION FIQ_STACK:DATA:NOROOT(2)
SECTION UND_STACK:DATA:NOROOT(2)
SECTION ABT_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#define __ASSEMBLY__
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFC06E000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define L2CC_CR 0x00A00100
#define REG_SFR_AICREDIR 0xF8028054
#define REG_SFR_UID 0xF8028050
#define AICREDIR_KEY 0x5F67B102
MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define ARM_MODE_UND 0x1B
#define I_BIT 0x80
#define F_BIT 0x40
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)
PUBLIC resetVector
PUBLIC IRQ_Handler
PUBLIC FIQ_Handler
EXTERN Undefined_C_Handler
EXTERN SWI_Handler
EXTERN Prefetch_C_Handler
EXTERN Abort_C_Handler
ARM
__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done
resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR PC,IRQ_Addr ; 0x18 IRQ
LDR PC,FIQ_Addr ; 0x1c FIQ
Undefined_Addr: DCD Undefined_C_Handler
SWI_Addr: DCD SWI_Handler
Abort_Addr: DCD Abort_C_Handler
Prefetch_Addr: DCD Prefetch_C_Handler
IRQ_Addr: DCD IRQ_Handler
FIQ_Addr: DCD FIQ_Handler
/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
IRQ_Handler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)
PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
EXTERN CP15_InvalidateBTB
EXTERN CP15_InvalidateTranslationTable
EXTERN CP15_InvalidateIcache
EXTERN CP15_InvalidateDcacheBySetWay
ARM
resetHandler:
LDR r4, =SFE(CSTACK) ; End of SVC stack
BIC r4,r4,#0x7 ; Make sure SP is 8 aligned
MOV sp, r4
;; Set up the normal interrupt stack pointer.
MSR CPSR_c, #(ARM_MODE_IRQ | F_BIT | I_BIT)
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the fast interrupt stack pointer.
MSR CPSR_c, #(ARM_MODE_FIQ | F_BIT | I_BIT)
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_ABT | F_BIT | I_BIT)
LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_UND | F_BIT | I_BIT)
LDR sp, =SFE(UND_STACK) ; End of UND_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_SYS | F_BIT | I_BIT)
LDR sp, =SFE(CSTACK-0x3000) ; 0x1000 bytes of SYS stack
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
MRC p15, 0, r0, c1, c0, 2
ORR r0, r0, #0xf00000
MCR p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
#ifdef __ARMVFP__
MOV r3, #0x40000000
VMSR FPEXC, r3
#endif
// Redirect FIQ to IRQ
LDR r0, =AICREDIR_KEY
LDR r1, = REG_SFR_UID
LDR r2, = REG_SFR_AICREDIR
LDR r3,[r1]
EORS r0, r0, r3
ORRS r0, r0, #0x01
STR r0, [r2]
/* Perform low-level initialization of the chip using LowLevelInit() */
LDR r0, =LowLevelInit
BLX r0
MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Regsiter into r0
TST r0, #0x1 ; Is the MMU enabled?
BICNE r0, r0, #0x1 ; Clear bit 0
TST r0, #0x4 ; Is the Dcache enabled?
BICNE r0, r0, #0x4 ; Clear bit 2
MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
// Disbale L2 cache
LDR r1,=L2CC_CR
MOV r2,#0
STR r2, [r1]
DMB
BL CP15_InvalidateTranslationTable
BL CP15_InvalidateBTB
BL CP15_InvalidateIcache
BL CP15_InvalidateDcacheBySetWay
DMB
ISB
/* Branch to main() */
LDR r0, =?main
BLX r0
/* Loop indefinitely when program is finished */
loop4:
B loop4
;------------------------------------------------------------------------------
;- Function : FIQ_Handler
;- Treatments : FIQ Controller Interrupt Handler.
;- Called Functions : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
SAIC DEFINE 0xFC068400
AIC_FVR DEFINE 0x14
SECTION .text:CODE:NOROOT(2)
ARM
FIQ_Handler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
/* MRS lr, SPSR */
STMFD sp!, {r0}
/* Write in the IVR to support Protect Mode */
LDR lr, =SAIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
MOV r14, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
/* Acknowledge interrupt */
LDR lr, =SAIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0}
/* MSR SPSR_cxsf, lr */
LDMIA sp!, {pc}^
END

529
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Provides the low-level initialization function that called on chip startup.
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Definiation
*----------------------------------------------------------------------------*/
#define CPSR_MASK_IRQ 0x00000080
#define CPSR_MASK_FIQ 0x00000040
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Array of Max peripheral Frequence support for SAMA5 chip*/
const PeripheralClockMaxFreq periClkMaxFreq[] = {
/* peripheral ID, Max frequency */
{ID_DBGU , (BOARD_MCK >>1) },
{ID_PIT , (BOARD_MCK >>1) },
{ID_WDT , (BOARD_MCK >>1) },
{ID_HSMC , (BOARD_MCK >>1) },
{ID_PIOA , (BOARD_MCK >>1) },
{ID_PIOB , (BOARD_MCK >>1) },
{ID_PIOC , (BOARD_MCK >>1) },
{ID_PIOD , (BOARD_MCK >>1) },
{ID_PIOE , (BOARD_MCK >>1) },
{ID_USART0 , (BOARD_MCK >>1) },
{ID_USART1 , (BOARD_MCK >>1) },
{ID_USART2 , (BOARD_MCK >>1) },
{ID_USART3 , (BOARD_MCK >>1) },
{ID_UART0 , (BOARD_MCK >>1) },
{ID_UART1 , (BOARD_MCK >>1) },
{ID_TWI0 , (BOARD_MCK >>1) },
{ID_TWI1 , (BOARD_MCK >>1) },
{ID_TWI2 , (BOARD_MCK >>1) },
{ID_HSMCI0 , (BOARD_MCK >>1) },
{ID_HSMCI1 , (BOARD_MCK >>1) },
{ID_SPI0 , (BOARD_MCK >>1) },
{ID_SPI1 , (BOARD_MCK >>1) },
{ID_TC0 , (BOARD_MCK >>1) },
{ID_TC1 , (BOARD_MCK >>1) },
{ID_PWM , (BOARD_MCK >>1) },
{ID_ADC , (BOARD_MCK >>1) },
{ID_XDMAC0 , BOARD_MCK },
{ID_XDMAC1 , BOARD_MCK },
{ID_UHPHS , (BOARD_MCK >>1) },
{ID_UDPHS , (BOARD_MCK >>1) },
{ID_GMAC0 , (BOARD_MCK >>1) },
{ID_GMAC1 , (BOARD_MCK >>1) },
{ID_LCDC , BOARD_MCK },
{ID_ISI , BOARD_MCK },
{ID_SSC0 , (BOARD_MCK >>1) },
{ID_SSC1 , (BOARD_MCK >>1) },
{ID_SHA , (BOARD_MCK >>1) },
{ID_AES , (BOARD_MCK >>1) },
{ID_TDES , (BOARD_MCK >>1) },
{ID_TDES , (BOARD_MCK >>1) },
{ID_TRNG , (BOARD_MCK >>1) },
{ID_ICM , (BOARD_MCK >>1) },
{ID_ARM , (BOARD_MCK >>1) },
{ID_IRQ , (BOARD_MCK >>1) },
{ID_SFC , (BOARD_MCK >>1) },
{ID_MPDDRC , BOARD_MCK }
};
static const char* abort_status[][2]=
{
// IFSR status , DFSR status
{"Unknown(reserved status)", "Unknown(reserved status)" },//0
{"Unknown(reserved status)", "Alignment Fault" },//1
{"Debug Event", "Debug Event" },//2
{"Access flag - section", "Access flag - section" },//3
{"Unknown(reserved status)", "Instruction cache maintenance" },//4
{"Translation fault - section", "Translation fault - section" },//5
{"Access flag - Page", "Access flag - Page" },//6
{"Translation fault -Page", "Translation fault -Page" },//7
{"Synchronous external abort", "Synchronous external abort, nontranslation" },//8
{"Domain fault - Section", "Domain fault - Section" },//9
{"Unknown(reserved status)", "Unknown(reserved status)" },//10
{"Domain fault - Page", "Domain fault - Page" },//11
{"Synchronous external abort - L1 Translation", "Synchronous external abort - L1 Translation" },//12
{"Permission fault - Section", "Permission fault - Section" },//13
{"Synchronous external abort - L2 Translation", "Synchronous external abort - L2 Translation" },//14
{"Permission fault - Page", "Permission fault - Page" },//15
{"Unknown(reserved status)", "Unknown(reserved status)" },//16
{"Unknown(reserved status)", "Unknown(reserved status)" },//17
{"Unknown(reserved status)", "Unknown(reserved status)" },//18
{"Unknown(reserved status)", "Unknown(reserved status)" },//19
{"Unknown(reserved status)", "Unknown(reserved status)" },//20
{"Unknown(reserved status)", "Unknown(reserved status)" },//21
{"Unknown(reserved status)", "Asynchronous external abort"}
};
/*----------------------------------------------------------------------------
* Internal functions
*----------------------------------------------------------------------------*/
void v_ARM_ClrCPSR_bits(unsigned int mask);
void NonSecureITInit (void);
void SecureITInit (void);
void Prefetch_C_Handler( void);
void Abort_C_Handler( void);
void Undefined_C_Handler(void);
/**
* \brief Default spurious interrupt handler. Infinite loop.
*/
void defaultSpuriousHandler( void )
{
while (1);
}
void Abort_C_Handler( void)
{
uint32_t v1,v2, dfsr;
v1= 0;
v2= 0;
asm("mrc p15, 0, %0, c5, c0, 0" : : "r"(v1));
asm("mrc p15, 0, %0, c6, c0, 0" : : "r"(v2));
dfsr = ((v1 >> 4) & 0x0F);
printf("\n\r######################################################################\n\r");
printf("Data Abort occured in %x domain\n\r", (unsigned int)dfsr);
dfsr = (((v1 & 0x400) >> 6) | (v1 & 0x0F));
printf("Data abort fault reason is: %s\n\r", (char*)abort_status[dfsr][1]);
printf("Data fault occured at Address = 0x%08x\n\n\r",(unsigned int)v2);
printf("-[Info]-Data fault status register value = 0x%x\n\r",(unsigned int)v1);
while(1);
}
void Prefetch_C_Handler( void)
{
uint32_t v1,v2, ifsr;
v1= 0;
v2= 0;
asm("mrc p15, 0, %0, c5, c0, 1" : : "r"(v1));
asm("mrc p15, 0, %0, c6, c0, 2" : : "r"(v2));
ifsr = (((v1 & 0x400) >> 6) | (v1 & 0x0F));
printf("\n\r######################################################################\n\r");
printf("Instruction prefetch abort reason is: %s\n\r", (char*)abort_status[ifsr][0]);
printf("Instruction prefetch Fault occured at Address = 0x%08x\n\n\r",(unsigned int)v2);
printf("-[INFO]- Prefetch Fault status register value by = 0x%x\n\r",(unsigned int)v1);
while(1);
}
void Undefined_C_Handler( void)
{
printf("Undefined abort \n\r");
while(1);
}
void v_ARM_ClrCPSR_bits(unsigned int mask)
{
asm("MRS R1, CPSR"); // Get current CPSR
asm("MVN R0, R0"); // invert
asm("AND R0, R0, R1"); // Calculate new CPSR value
asm("MSR CPSR_c,R0"); // Set new value
asm("bx lr");
}
void Dummy_Handler( void );
void Spurious_Handler( void );
#pragma weak SAIC0_Handler=Dummy_Handler
#pragma weak SYS_IrqHandler=Dummy_Handler
#pragma weak ARM_IrqHandler=Dummy_Handler
#pragma weak PIT_IrqHandler=Dummy_Handler
#pragma weak WDT_IrqHandler=Dummy_Handler
#pragma weak PIOD_IrqHandler=Dummy_Handler
#pragma weak USART0_IrqHandler=Dummy_Handler
#pragma weak USART1_IrqHandler=Dummy_Handler
#pragma weak XDMAC0_IrqHandler=Dummy_Handler
#pragma weak ICM_IrqHandler=Dummy_Handler
#pragma weak PKCC_IrqHandler=Dummy_Handler
#pragma weak SCI_IrqHandler=Dummy_Handler
#pragma weak AES_IrqHandler=Dummy_Handler
#pragma weak AESB_IrqHandler=Dummy_Handler
#pragma weak TDES_IrqHandler=Dummy_Handler
#pragma weak SHA_IrqHandler=Dummy_Handler
#pragma weak MPDDRC_IrqHandler=Dummy_Handler
#pragma weak H32MX_IrqHandler=Dummy_Handler
#pragma weak H64MX_IrqHandler=Dummy_Handler
#pragma weak VDEC_IrqHandler=Dummy_Handler
#pragma weak SECUMOD_IrqHandler=Dummy_Handler
#pragma weak MSADCC_IrqHandler=Dummy_Handler
#pragma weak HSMC_IrqHandler=Dummy_Handler
#pragma weak PIOA_IrqHandler=Dummy_Handler
#pragma weak PIOB_IrqHandler=Dummy_Handler
#pragma weak PIOC_IrqHandler=Dummy_Handler
#pragma weak PIOE_IrqHandler=Dummy_Handler
#pragma weak UART0_IrqHandler=Dummy_Handler
#pragma weak UART1_IrqHandler=Dummy_Handler
#pragma weak USART2_IrqHandler=Dummy_Handler
#pragma weak USART3_IrqHandler=Dummy_Handler
#pragma weak USART4_IrqHandler=Dummy_Handler
#pragma weak TWI0_IrqHandler=Dummy_Handler
#pragma weak TWI1_IrqHandler=Dummy_Handler
#pragma weak TWI2_IrqHandler=Dummy_Handler
#pragma weak HSMCI0_IrqHandler=Dummy_Handler
#pragma weak HSMCI1_IrqHandler=Dummy_Handler
#pragma weak SPI0_IrqHandler=Dummy_Handler
#pragma weak SPI1_IrqHandler=Dummy_Handler
#pragma weak SPI2_IrqHandler=Dummy_Handler
#pragma weak TC0_IrqHandler=Dummy_Handler
#pragma weak TC1_IrqHandler=Dummy_Handler
#pragma weak TC2_IrqHandler=Dummy_Handler
#pragma weak PWM_IrqHandler=Dummy_Handler
#pragma weak ADC_IrqHandler=Dummy_Handler
#pragma weak DBGU_IrqHandler=Dummy_Handler
#pragma weak UHPHS_IrqHandler=Dummy_Handler
#pragma weak UDPHS_IrqHandler=Dummy_Handler
#pragma weak SSC0_IrqHandler=Dummy_Handler
#pragma weak SSC1_IrqHandler=Dummy_Handler
#pragma weak XDMAC1_IrqHandler=Dummy_Handler
#pragma weak LCDC_IrqHandler=Dummy_Handler
#pragma weak ISI_IrqHandler=Dummy_Handler
#pragma weak TRNG_IrqHandler=Dummy_Handler
#pragma weak GMAC0_IrqHandler=Dummy_Handler
#pragma weak GMAC1_IrqHandler=Dummy_Handler
#pragma weak AIC0_IrqHandler=Dummy_Handler
#pragma weak SFC_IrqHandler=Dummy_Handler
#pragma weak SECURAM_IrqHandler=Dummy_Handler
#pragma weak CTB_IrqHandler=Dummy_Handler
#pragma weak SMD_IrqHandler=Dummy_Handler
#pragma weak TWI3_IrqHandler=Dummy_Handler
#pragma weak CATB_IrqHandler=Dummy_Handler
#pragma weak SFR_IrqHandler=Dummy_Handler
#pragma weak AIC1_IrqHandler=Dummy_Handler
#pragma weak SAIC1_IrqHandler=Dummy_Handler
#pragma weak L2CC_IrqHandler=Dummy_Handler
#pragma weak Spurious_handler=Spurious_Handler
/**
* \brief Dummy default handler.
*/
volatile uint32_t ulx = 0;
void Dummy_Handler( void )
{
while ( ulx == 0 )
{
__asm volatile( "NOP" );
}
ulx = 0;
}
void Spurious_Handler( void )
{
while ( ulx == 0 )
{
__asm volatile( "NOP" );
}
ulx = 0;
}
/**
* \brief Non-secure Interupt Init.
*/
void NonSecureITInit (void)
{
uint32_t i;
/* Assign handler addesses */
AIC->AIC_SSR = 0; AIC->AIC_SVR = (unsigned int) SAIC0_Handler;
AIC->AIC_SSR = 1; AIC->AIC_SVR = (unsigned int) SYS_IrqHandler;
AIC->AIC_SSR = 2; AIC->AIC_SVR = (unsigned int) ARM_IrqHandler;
AIC->AIC_SSR = 3; AIC->AIC_SVR = (unsigned int) PIT_IrqHandler;
AIC->AIC_SSR = 4; AIC->AIC_SVR = (unsigned int) WDT_IrqHandler;
AIC->AIC_SSR = 5; AIC->AIC_SVR = (unsigned int) PIOD_IrqHandler;
AIC->AIC_SSR = 6; AIC->AIC_SVR = (unsigned int) USART0_IrqHandler;
AIC->AIC_SSR = 7; AIC->AIC_SVR = (unsigned int) USART1_IrqHandler;
AIC->AIC_SSR = 8; AIC->AIC_SVR = (unsigned int) XDMAC0_IrqHandler;
AIC->AIC_SSR = 9; AIC->AIC_SVR = (unsigned int) ICM_IrqHandler;
AIC->AIC_SSR = 10; AIC->AIC_SVR = (unsigned int) PKCC_IrqHandler;
AIC->AIC_SSR = 11; AIC->AIC_SVR = (unsigned int) SCI_IrqHandler;
AIC->AIC_SSR = 12; AIC->AIC_SVR = (unsigned int) AES_IrqHandler;
AIC->AIC_SSR = 13; AIC->AIC_SVR = (unsigned int) AESB_IrqHandler;
AIC->AIC_SSR = 14; AIC->AIC_SVR = (unsigned int) TDES_IrqHandler;
AIC->AIC_SSR = 15; AIC->AIC_SVR = (unsigned int) SHA_IrqHandler;
AIC->AIC_SSR = 16; AIC->AIC_SVR = (unsigned int) MPDDRC_IrqHandler;
AIC->AIC_SSR = 17; AIC->AIC_SVR = (unsigned int) H32MX_IrqHandler;
AIC->AIC_SSR = 18; AIC->AIC_SVR = (unsigned int) H64MX_IrqHandler;
AIC->AIC_SSR = 19; AIC->AIC_SVR = (unsigned int) VDEC_IrqHandler;
AIC->AIC_SSR = 20; AIC->AIC_SVR = (unsigned int) SECUMOD_IrqHandler;
AIC->AIC_SSR = 21; AIC->AIC_SVR = (unsigned int) MSADCC_IrqHandler;
AIC->AIC_SSR = 22; AIC->AIC_SVR = (unsigned int) HSMC_IrqHandler;
AIC->AIC_SSR = 23; AIC->AIC_SVR = (unsigned int) PIOA_IrqHandler;
AIC->AIC_SSR = 24; AIC->AIC_SVR = (unsigned int) PIOB_IrqHandler;
AIC->AIC_SSR = 25; AIC->AIC_SVR = (unsigned int) PIOC_IrqHandler;
AIC->AIC_SSR = 26; AIC->AIC_SVR = (unsigned int) PIOE_IrqHandler;
AIC->AIC_SSR = 27; AIC->AIC_SVR = (unsigned int) UART0_IrqHandler;
AIC->AIC_SSR = 28; AIC->AIC_SVR = (unsigned int) UART1_IrqHandler;
AIC->AIC_SSR = 29; AIC->AIC_SVR = (unsigned int) USART2_IrqHandler;
AIC->AIC_SSR = 30; AIC->AIC_SVR = (unsigned int) USART3_IrqHandler;
AIC->AIC_SSR = 31; AIC->AIC_SVR = (unsigned int) USART4_IrqHandler;
AIC->AIC_SSR = 32; AIC->AIC_SVR = (unsigned int) TWI0_IrqHandler;
AIC->AIC_SSR = 33; AIC->AIC_SVR = (unsigned int) TWI1_IrqHandler;
AIC->AIC_SSR = 34; AIC->AIC_SVR = (unsigned int) TWI2_IrqHandler;
AIC->AIC_SSR = 35; AIC->AIC_SVR = (unsigned int) HSMCI0_IrqHandler;
AIC->AIC_SSR = 36; AIC->AIC_SVR = (unsigned int) HSMCI1_IrqHandler;
AIC->AIC_SSR = 37; AIC->AIC_SVR = (unsigned int) SPI0_IrqHandler;
AIC->AIC_SSR = 38; AIC->AIC_SVR = (unsigned int) SPI1_IrqHandler;
AIC->AIC_SSR = 39; AIC->AIC_SVR = (unsigned int) SPI2_IrqHandler;
AIC->AIC_SSR = 40; AIC->AIC_SVR = (unsigned int) TC0_IrqHandler;
AIC->AIC_SSR = 41; AIC->AIC_SVR = (unsigned int) TC1_IrqHandler;
AIC->AIC_SSR = 42; AIC->AIC_SVR = (unsigned int) TC2_IrqHandler;
AIC->AIC_SSR = 43; AIC->AIC_SVR = (unsigned int) PWM_IrqHandler;
AIC->AIC_SSR = 44; AIC->AIC_SVR = (unsigned int) ADC_IrqHandler;
AIC->AIC_SSR = 45; AIC->AIC_SVR = (unsigned int) DBGU_IrqHandler;
AIC->AIC_SSR = 46; AIC->AIC_SVR = (unsigned int) UHPHS_IrqHandler;
AIC->AIC_SSR = 47; AIC->AIC_SVR = (unsigned int) UDPHS_IrqHandler;
AIC->AIC_SSR = 48; AIC->AIC_SVR = (unsigned int) SSC0_IrqHandler;
AIC->AIC_SSR = 49; AIC->AIC_SVR = (unsigned int) SSC1_IrqHandler;
AIC->AIC_SSR = 50; AIC->AIC_SVR = (unsigned int) XDMAC1_IrqHandler;
AIC->AIC_SSR = 51; AIC->AIC_SVR = (unsigned int) LCDC_IrqHandler;
AIC->AIC_SSR = 52; AIC->AIC_SVR = (unsigned int) ISI_IrqHandler;
AIC->AIC_SSR = 53; AIC->AIC_SVR = (unsigned int) TRNG_IrqHandler;
AIC->AIC_SSR = 54; AIC->AIC_SVR = (unsigned int) GMAC0_IrqHandler;
AIC->AIC_SSR = 55; AIC->AIC_SVR = (unsigned int) GMAC1_IrqHandler;
AIC->AIC_SSR = 56; AIC->AIC_SVR = (unsigned int) AIC0_IrqHandler;
AIC->AIC_SSR = 57; AIC->AIC_SVR = (unsigned int) SFC_IrqHandler;
AIC->AIC_SSR = 59; AIC->AIC_SVR = (unsigned int) SECURAM_IrqHandler;
AIC->AIC_SSR = 60; AIC->AIC_SVR = (unsigned int) CTB_IrqHandler;
AIC->AIC_SSR = 61; AIC->AIC_SVR = (unsigned int) SMD_IrqHandler;
AIC->AIC_SSR = 62; AIC->AIC_SVR = (unsigned int) TWI3_IrqHandler;
AIC->AIC_SSR = 63; AIC->AIC_SVR = (unsigned int) CATB_IrqHandler;
AIC->AIC_SSR = 64; AIC->AIC_SVR = (unsigned int) SFR_IrqHandler;
AIC->AIC_SSR = 65; AIC->AIC_SVR = (unsigned int) AIC1_IrqHandler;
AIC->AIC_SSR = 66; AIC->AIC_SVR = (unsigned int) SAIC1_IrqHandler;
AIC->AIC_SSR = 67; AIC->AIC_SVR = (unsigned int) L2CC_IrqHandler;
AIC->AIC_SPU = (unsigned int) Spurious_handler;
/* Disable all interrupts */
for (i = 1; i < ID_PERIPH_COUNT; i++){
AIC->AIC_SSR=i;
AIC->AIC_IDCR=AIC_IDCR_INTD;
}
/* Clear All pending interrupts flags */
for (i = 0; i < ID_PERIPH_COUNT; i++){
AIC->AIC_SSR = i;
AIC->AIC_ICCR = AIC_ICCR_INTCLR;
}
/* Perform 8 IT acknoledge (write any value in EOICR) (VPy) */
for (i = 0; i < 8; i++){
AIC->AIC_EOICR = 0;
}
/* Enable IRQ and FIQ at core level */
v_ARM_ClrCPSR_bits(CPSR_MASK_IRQ|CPSR_MASK_FIQ);
}
/**
* \brief Secure Interupt Init.
*/
void SecureITInit (void)
{
uint32_t i;
/* Assign handler addesses */
SAIC->AIC_SSR = 0; SAIC->AIC_SVR = (unsigned int) SAIC0_Handler;
SAIC->AIC_SSR = 1; SAIC->AIC_SVR = (unsigned int) SYS_IrqHandler;
SAIC->AIC_SSR = 2; SAIC->AIC_SVR = (unsigned int) ARM_IrqHandler;
SAIC->AIC_SSR = 3; SAIC->AIC_SVR = (unsigned int) PIT_IrqHandler;
SAIC->AIC_SSR = 4; SAIC->AIC_SVR = (unsigned int) WDT_IrqHandler;
SAIC->AIC_SSR = 5; SAIC->AIC_SVR = (unsigned int) PIOD_IrqHandler;
SAIC->AIC_SSR = 6; SAIC->AIC_SVR = (unsigned int) USART0_IrqHandler;
SAIC->AIC_SSR = 7; SAIC->AIC_SVR = (unsigned int) USART1_IrqHandler;
SAIC->AIC_SSR = 8; SAIC->AIC_SVR = (unsigned int) XDMAC0_IrqHandler;
SAIC->AIC_SSR = 9; SAIC->AIC_SVR = (unsigned int) ICM_IrqHandler;
SAIC->AIC_SSR = 10; SAIC->AIC_SVR = (unsigned int) PKCC_IrqHandler;
SAIC->AIC_SSR = 11; SAIC->AIC_SVR = (unsigned int) SCI_IrqHandler;
SAIC->AIC_SSR = 12; SAIC->AIC_SVR = (unsigned int) AES_IrqHandler;
SAIC->AIC_SSR = 13; SAIC->AIC_SVR = (unsigned int) AESB_IrqHandler;
SAIC->AIC_SSR = 14; SAIC->AIC_SVR = (unsigned int) TDES_IrqHandler;
SAIC->AIC_SSR = 15; SAIC->AIC_SVR = (unsigned int) SHA_IrqHandler;
SAIC->AIC_SSR = 16; SAIC->AIC_SVR = (unsigned int) MPDDRC_IrqHandler;
SAIC->AIC_SSR = 17; SAIC->AIC_SVR = (unsigned int) H32MX_IrqHandler;
SAIC->AIC_SSR = 18; SAIC->AIC_SVR = (unsigned int) H64MX_IrqHandler;
SAIC->AIC_SSR = 19; SAIC->AIC_SVR = (unsigned int) VDEC_IrqHandler;
SAIC->AIC_SSR = 20; SAIC->AIC_SVR = (unsigned int) SECUMOD_IrqHandler;
SAIC->AIC_SSR = 21; SAIC->AIC_SVR = (unsigned int) MSADCC_IrqHandler;
SAIC->AIC_SSR = 22; SAIC->AIC_SVR = (unsigned int) HSMC_IrqHandler;
SAIC->AIC_SSR = 23; SAIC->AIC_SVR = (unsigned int) PIOA_IrqHandler;
SAIC->AIC_SSR = 24; SAIC->AIC_SVR = (unsigned int) PIOB_IrqHandler;
SAIC->AIC_SSR = 25; SAIC->AIC_SVR = (unsigned int) PIOC_IrqHandler;
SAIC->AIC_SSR = 26; SAIC->AIC_SVR = (unsigned int) PIOE_IrqHandler;
SAIC->AIC_SSR = 27; SAIC->AIC_SVR = (unsigned int) UART0_IrqHandler;
SAIC->AIC_SSR = 28; SAIC->AIC_SVR = (unsigned int) UART1_IrqHandler;
SAIC->AIC_SSR = 29; SAIC->AIC_SVR = (unsigned int) USART2_IrqHandler;
SAIC->AIC_SSR = 30; SAIC->AIC_SVR = (unsigned int) USART3_IrqHandler;
SAIC->AIC_SSR = 31; SAIC->AIC_SVR = (unsigned int) USART4_IrqHandler;
SAIC->AIC_SSR = 32; SAIC->AIC_SVR = (unsigned int) TWI0_IrqHandler;
SAIC->AIC_SSR = 33; SAIC->AIC_SVR = (unsigned int) TWI1_IrqHandler;
SAIC->AIC_SSR = 34; SAIC->AIC_SVR = (unsigned int) TWI2_IrqHandler;
SAIC->AIC_SSR = 35; SAIC->AIC_SVR = (unsigned int) HSMCI0_IrqHandler;
SAIC->AIC_SSR = 36; SAIC->AIC_SVR = (unsigned int) HSMCI1_IrqHandler;
SAIC->AIC_SSR = 37; SAIC->AIC_SVR = (unsigned int) SPI0_IrqHandler;
SAIC->AIC_SSR = 38; SAIC->AIC_SVR = (unsigned int) SPI1_IrqHandler;
SAIC->AIC_SSR = 39; SAIC->AIC_SVR = (unsigned int) SPI2_IrqHandler;
SAIC->AIC_SSR = 40; SAIC->AIC_SVR = (unsigned int) TC0_IrqHandler;
SAIC->AIC_SSR = 41; SAIC->AIC_SVR = (unsigned int) TC1_IrqHandler;
SAIC->AIC_SSR = 42; SAIC->AIC_SVR = (unsigned int) TC2_IrqHandler;
SAIC->AIC_SSR = 43; SAIC->AIC_SVR = (unsigned int) PWM_IrqHandler;
SAIC->AIC_SSR = 44; SAIC->AIC_SVR = (unsigned int) ADC_IrqHandler;
SAIC->AIC_SSR = 45; SAIC->AIC_SVR = (unsigned int) DBGU_IrqHandler;
SAIC->AIC_SSR = 46; SAIC->AIC_SVR = (unsigned int) UHPHS_IrqHandler;
SAIC->AIC_SSR = 47; SAIC->AIC_SVR = (unsigned int) UDPHS_IrqHandler;
SAIC->AIC_SSR = 48; SAIC->AIC_SVR = (unsigned int) SSC0_IrqHandler;
SAIC->AIC_SSR = 49; SAIC->AIC_SVR = (unsigned int) SSC1_IrqHandler;
SAIC->AIC_SSR = 50; SAIC->AIC_SVR = (unsigned int) XDMAC1_IrqHandler;
SAIC->AIC_SSR = 51; SAIC->AIC_SVR = (unsigned int) LCDC_IrqHandler;
SAIC->AIC_SSR = 52; SAIC->AIC_SVR = (unsigned int) ISI_IrqHandler;
SAIC->AIC_SSR = 53; SAIC->AIC_SVR = (unsigned int) TRNG_IrqHandler;
SAIC->AIC_SSR = 54; SAIC->AIC_SVR = (unsigned int) GMAC0_IrqHandler;
SAIC->AIC_SSR = 55; SAIC->AIC_SVR = (unsigned int) GMAC1_IrqHandler;
SAIC->AIC_SSR = 56; SAIC->AIC_SVR = (unsigned int) AIC0_IrqHandler;
SAIC->AIC_SSR = 57; SAIC->AIC_SVR = (unsigned int) SFC_IrqHandler;
SAIC->AIC_SSR = 59; SAIC->AIC_SVR = (unsigned int) SECURAM_IrqHandler;
SAIC->AIC_SSR = 60; SAIC->AIC_SVR = (unsigned int) CTB_IrqHandler;
SAIC->AIC_SSR = 61; SAIC->AIC_SVR = (unsigned int) SMD_IrqHandler;
SAIC->AIC_SSR = 62; SAIC->AIC_SVR = (unsigned int) TWI3_IrqHandler;
SAIC->AIC_SSR = 63; SAIC->AIC_SVR = (unsigned int) CATB_IrqHandler;
SAIC->AIC_SSR = 64; SAIC->AIC_SVR = (unsigned int) SFR_IrqHandler;
SAIC->AIC_SSR = 65; SAIC->AIC_SVR = (unsigned int) AIC1_IrqHandler;
SAIC->AIC_SSR = 66; SAIC->AIC_SVR = (unsigned int) SAIC1_IrqHandler;
SAIC->AIC_SSR = 67; SAIC->AIC_SVR = (unsigned int) L2CC_IrqHandler;
SAIC->AIC_SPU = (unsigned int) Spurious_handler;
/* Disable all interrupts */
for (i = 1; i < ID_PERIPH_COUNT; i++){
SAIC->AIC_SSR=i;
SAIC->AIC_IDCR=AIC_IDCR_INTD;
}
/* Clear All pending interrupts flags */
for (i = 0; i < ID_PERIPH_COUNT; i++){
SAIC->AIC_SSR = i;
SAIC->AIC_ICCR = AIC_ICCR_INTCLR;
}
/* Perform 8 IT acknoledge (write any value in EOICR) (VPy) */
for (i = 0; i < 8; i++){
SAIC->AIC_EOICR = 0;
}
/* Enable IRQ and FIQ at core level */
v_ARM_ClrCPSR_bits(CPSR_MASK_IRQ|CPSR_MASK_FIQ);
}
/**
* \brief Performs the low-level initialization of the chip.
* It also enable a low level on the pin NRST triggers a user reset.
*/
extern WEAK void LowLevelInit( void )
{
volatile unsigned int * pAicFuse = (volatile unsigned int *) REG_SFR_AICREDIR;
NonSecureITInit();
if(!(*pAicFuse))
{
SecureITInit();
}
if ((uint32_t)LowLevelInit < DDR_CS_ADDR) /* Code not in external mem */ {
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA( CKGR_PLLAR_ONE |
CKGR_PLLAR_PLLACOUNT(0x3F) |
CKGR_PLLAR_OUTA(0x0) |
CKGR_PLLAR_MULA(87) |
1,
PMC_PLLICPR_IPLL_PLLA(0x0));
PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2);
PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK);
PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3);
PMC_SwitchMck2Pll();
}
/* Remap */
BOARD_RemapRam();
}

476
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/board_memories.c Normal file
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@ -0,0 +1,476 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 20143, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup ddrd_module
*
* The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
* four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved
* to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.
*
* \section ddr2 Configures DDR2
*
* The DDR2-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1: Program the memory device type</li>
* <li> Step 2:
* -# Program the features of DDR2-SDRAM device into the Configuration Register.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR. </li>
* <li> Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock. </li>
* <li> Step 4: An NOP command is issued to the DDR2-SDRAM </li>
* <li> Step 5: An all banks precharge command is issued to the DDR2-SDRAM. </li>
* <li> Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.</li>
* <li> Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. </li>
* <li> Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.</li>
* <li> Step 9: Program DLL field into the Configuration Register.</li>
* <li> Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.</li>
* <li> Step 11: An all banks precharge command is issued to the DDR2-SDRAM.</li>
* <li> Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.</li>
* <li> Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).</li>
* <li> Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.</li>
* <li> Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). </li>
* <li> Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.</li>
* <li> Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).</li>
* <li> Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.</li>
* <li> Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.</li>
* <li> Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 or 7.81. </li>
* </ul>
*/
/*@{*/
/*@}*/
/** \addtogroup sdram_module
*
* \section sdram Configures SDRAM
*
* The SDR-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1. Program the memory device type into the Memory Device Register</li>
* <li> Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.</li>
* <li> Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.</li>
* <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
* set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command.
* Now the clock which drives SDR-SDRAM device is enabled.</li>
* <li> Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the
* Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.</li>
* <li> Step 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register.
* Once in the idle state, two AUTO REFRESH cycles must be performed.</li>
* <li> Step 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM
* devices, in particular CAS latency and burst length. </li>
* <li> Step 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The write
* address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0 </li>
* <li> Step 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and perform a write access at any location in the SDRAM to acknowledge this command.</li>
* <li> Step 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register </li>
* </ul>
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of memories configuration on board.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal ROM or the EBI CS0.
*/
void BOARD_RemapRom( void )
{
AXIMX->AXIMX_REMAP = 0;
}
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal RAM.
*/
void BOARD_RemapRam( void )
{
AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0;
}
/**
* \brief Initialize Vdd EBI drive
* \param 0: 1.8V 1: 3.3V
*/
void BOARD_ConfigureVddMemSel( uint8_t VddMemSel )
{
}
#define DDR2_BA0(r) (1 << (26 + r))
#define DDR2_BA1(r) (1 << (27 + r))
#define H64MX_DDR_SLAVE_PORT0 3
static void matrix_configure_slave_ddr(void)
{
int ddr_port;
/* Disable write protection */
MATRIX0->MATRIX_WPMR = MPDDRC_WPMR_WPKEY_PASSWD;
/* Partition internal SRAM */
MATRIX0->MATRIX_SSR[11] = 0;
MATRIX0->MATRIX_SRTSR[11] = 0x05;
MATRIX0->MATRIX_SASSR[11] = 0x04;
ddr_port = 1;
/* Partition external DDR */
/* DDR port 0 not used from NWd */
for (ddr_port = 1 ; ddr_port < 8 ; ddr_port++) {
MATRIX0->MATRIX_SSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x00FFFFFF;
MATRIX0->MATRIX_SRTSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000000F;
MATRIX0->MATRIX_SASSR[H64MX_DDR_SLAVE_PORT0 + ddr_port] = 0x0000FFFF;
}
}
#define MATRIX_KEY_VAL (0x4D4154u)
static void matrix_configure_slave_nand(void)
{
/* Disable write protection */
MATRIX0->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
MATRIX1->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_KEY_VAL);
/* Partition internal SRAM */
MATRIX0->MATRIX_SSR[11] = 0x00010101;
MATRIX0->MATRIX_SRTSR[11] = 0x05;
MATRIX0->MATRIX_SASSR[11] = 0x05;
MATRIX1->MATRIX_SRTSR[3] = 0xBBBBBBBB;
MATRIX1->MATRIX_SSR[3] = 0x00FFFFFF;
MATRIX1->MATRIX_SASSR[3] = 0xBBBBBBBB;
MATRIX1->MATRIX_SRTSR[4] = 0x01;
MATRIX1->MATRIX_SSR[4] = 0x00FFFFFF;
MATRIX1->MATRIX_SASSR[4] = 0x01;
MATRIX1->MATRIX_MEIER = 0x3FF;
}
/**
* \brief Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
MT47H64M16HR : 8 Meg x 16 x 8 banks
Refresh count: 8K
Row address: A[12:0] (8K)
Column address A[9:0] (1K)
Bank address BA[2:0] a(24,25) (8)
*/
void BOARD_ConfigureDdram( void )
{
volatile uint8_t *pDdr = (uint8_t *) DDR_CS_ADDR;
volatile uint32_t i;
volatile uint32_t dummy_value;
matrix_configure_slave_ddr();
/* Enable DDR2 clock x2 in PMC */
PMC->PMC_PCER0 = (1 << (ID_MPDDRC));
PMC->PMC_SCER |= PMC_SCER_DDRCK;
/* MPDDRC I/O Calibration Register */
dummy_value = MPDDRC->MPDDRC_IO_CALIBR;
dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;
dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;
dummy_value |= MPDDRC_IO_CALIBR_CALCODEP(7);
dummy_value |= MPDDRC_IO_CALIBR_CALCODEN(8);
dummy_value |= MPDDRC_IO_CALIBR_RDIV_RZQ_60_RZQ_50;
dummy_value |= MPDDRC_IO_CALIBR_TZQIO(5);
dummy_value |= MPDDRC_IO_CALIBR_EN_CALIB_ENABLE_CALIBRATION;
MPDDRC->MPDDRC_IO_CALIBR = dummy_value;
/* Step 1: Program the memory device type */
/* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM | MPDDRC_MD_DBW_DBW_32_BITS;
MPDDRC->MPDDRC_RD_DATA_PATH = MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE;
/* Step 2: Program the features of DDR2-SDRAM device into the Timing Register.*/
MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_14_ROW_BITS |
MPDDRC_CR_NC_10_COL_BITS |
MPDDRC_CR_CAS_DDR_CAS3 |
MPDDRC_CR_DLL_RESET_DISABLED |
MPDDRC_CR_DQMS_NOT_SHARED |
MPDDRC_CR_ENRDM_OFF |
MPDDRC_CR_NB_8_BANKS |
MPDDRC_CR_NDQS_DISABLED |
MPDDRC_CR_UNAL_SUPPORTED |
MPDDRC_CR_OCD_DDR2_EXITCALIB;
MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(8) // 40 ns
| MPDDRC_TPR0_TRCD(3) // 12.5 ns
| MPDDRC_TPR0_TWR(3) // 15 ns
| MPDDRC_TPR0_TRC(10) // 55 ns
| MPDDRC_TPR0_TRP(3) // 12.5 ns
| MPDDRC_TPR0_TRRD(2) // 8 ns
| MPDDRC_TPR0_TWTR(2) // 2 clock cycle
| MPDDRC_TPR0_TMRD(2); // 2 clock cycles
MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(23)
| MPDDRC_TPR1_TXSNR(25)
| MPDDRC_TPR1_TXSRD(200)
| MPDDRC_TPR1_TXP(2);
MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8)
| MPDDRC_TPR2_TXARDS(2)
| MPDDRC_TPR2_TRPA(3)
| MPDDRC_TPR2_TRTP(2)
| MPDDRC_TPR2_TFAW(7);
/* DDRSDRC Low-power Register */
for (i = 0; i < 13300; i++) {
asm("nop");
}
/* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register, the application must set MODE to 1 in the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
*pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/
/* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */
for (i = 0; i < 13300; i++) {
asm("nop");
}
/* Step 4: An NOP command is issued to the DDR2-SDRAM */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0; /* Now CKE is driven high.*/
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0;
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(0) + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. */
/* An additional 200 cycles of clock are required for locking DLL */
for (i = 0; i < 10000; i++) {
asm("nop");
}
/* Step 9: Program DLL field into the Configuration Register.*/
MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
/* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] bits are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Configure 2nd CBR. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */
MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED;
/* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). */
MPDDRC->MPDDRC_CR |= MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB;
/* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit). */
MPDDRC->MPDDRC_CR &= ~(MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB);
/* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.*/
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(0))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;
*(pDdr) = 0;
/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.
With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */
/* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average
refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */
/* ((64 x 10(^-3))/8192) x133 x (10^6) */
MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(0x2b0); /* Set Refresh timer 7.8125 us*/
/* OK now we are ready to work on the DDRSDR */
/* wait for end of calibration */
for (i = 0; i < 500; i++) {
asm(" nop");
}
}
/**
* \brief Configures the EBI for Sdram (LPSDR Micron MT48H8M16) access.
*/
void BOARD_ConfigureSdram( void )
{
}
/** \brief Configures the EBI for NandFlash access at 133Mhz.
*/
void BOARD_ConfigureNandFlash( uint8_t busWidth )
{
PMC_EnablePeripheral(ID_HSMC);
matrix_configure_slave_nand();
HSMC->HSMC_CS_NUMBER[3].HSMC_SETUP = 0
| HSMC_SETUP_NWE_SETUP(2)
| HSMC_SETUP_NCS_WR_SETUP(2)
| HSMC_SETUP_NRD_SETUP(2)
| HSMC_SETUP_NCS_RD_SETUP(2);
HSMC->HSMC_CS_NUMBER[3].HSMC_PULSE = 0
| HSMC_PULSE_NWE_PULSE(7)
| HSMC_PULSE_NCS_WR_PULSE(7)
| HSMC_PULSE_NRD_PULSE(7)
| HSMC_PULSE_NCS_RD_PULSE(7);
HSMC->HSMC_CS_NUMBER[3].HSMC_CYCLE = 0
| HSMC_CYCLE_NWE_CYCLE(13)
| HSMC_CYCLE_NRD_CYCLE(13);
HSMC->HSMC_CS_NUMBER[3].HSMC_TIMINGS = HSMC_TIMINGS_TCLR(3)
| HSMC_TIMINGS_TADL(27)
| HSMC_TIMINGS_TAR(3)
| HSMC_TIMINGS_TRR(6)
| HSMC_TIMINGS_TWB(5)
| HSMC_TIMINGS_RBNSEL(3)
|(HSMC_TIMINGS_NFSEL);
HSMC->HSMC_CS_NUMBER[3].HSMC_MODE = HSMC_MODE_READ_MODE |
HSMC_MODE_WRITE_MODE |
((busWidth == 8 )? HSMC_MODE_DBW_BIT_8 :HSMC_MODE_DBW_BIT_16) |
HSMC_MODE_TDF_CYCLES(1);
}
void BOARD_ConfigureNorFlash( uint8_t busWidth )
{
uint32_t dbw;
PMC_EnablePeripheral(ID_HSMC);
if (busWidth == 8)
{
dbw = HSMC_MODE_DBW_BIT_8;
}
else {
dbw = HSMC_MODE_DBW_BIT_16;
}
/* Configure SMC, NCS0 is assigned to a norflash */
HSMC->HSMC_CS_NUMBER[0].HSMC_SETUP = 0x00020001;
HSMC->HSMC_CS_NUMBER[0].HSMC_PULSE = 0x0B0B0A0A;
HSMC->HSMC_CS_NUMBER[0].HSMC_CYCLE = 0x000E000B;
HSMC->HSMC_CS_NUMBER[0].HSMC_TIMINGS = 0x00000000;
HSMC->HSMC_CS_NUMBER[0].HSMC_MODE = HSMC_MODE_WRITE_MODE
| HSMC_MODE_READ_MODE
| dbw
| HSMC_MODE_EXNW_MODE_DISABLED
| HSMC_MODE_TDF_CYCLES(1);
}

315
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* Implement simple DBGU usage as stream receiver.
*/
/*-------------------------------
* Headers
*-------------------------------*/
#include <board.h>
/*-------------------------------
* Defines
*-------------------------------*/
/** Data RX timeout in binary start up */
#define TIMEOUT_RX_START (1000*20)
/** Data RX timeout default value */
#define TIMEOUT_RX (200)
/* ASCII Character Codes */
#define SOH 0x01
#define STX 0x02
#define EOT 0x04
#define CTRL_D 0x04 /**< Transfer Done */
#define ACK 0x06
#define NAK 0x15
#define CAN 0x18 /**< Cancel transfer */
#define CTRL_X 0x24
/* 1K XMODEM Parameters */
#define SOH_LENGTH 128
#define STX_LENGTH 1024
#define SOH_TIMEOUT 1000
/*-------------------------------
* Local functions
*-------------------------------*/
/**
* \brief Compute the CRC
*/
static uint16_t _GetCRC(uint8_t bByte, uint16_t wCrc)
{
int32_t cnt;
uint8_t newBit;
for (cnt = 7; cnt >= 0; cnt --)
{
newBit = ((wCrc >> 15) & 0x1) ^ ((bByte >> cnt) & 0x1);
wCrc <<= 1;
if (newBit) wCrc ^= (0x1021);
}
return wCrc;
}
/*-------------------------------
* Exported functions
*-------------------------------*/
/**
* \brief Receives byte with timeout.
* \param pByte pointer to locate received byte, can be NULL
* to discard data.
* \param timeOut timeout setting, in number of ticks.
*/
uint8_t DbgReceiveByte(uint8_t* pByte, uint32_t timeOut)
{
uint32_t tick;
uint32_t delay;
tick = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
uint8_t tmp = DBGU_GetChar();
if (pByte) *pByte = tmp;
return 1;
}
if (timeOut == 0)
{ /* Never timeout */
}
else
{
delay = GetDelayInTicks(tick, GetTickCount());
if (delay > timeOut)
{
return 0;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
* \param bStart 1 to start a new data stream.
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceiveBinary(uint8_t bStart, uint32_t address, uint32_t maxSize)
{
volatile uint32_t tick0;
uint32_t delay;
uint8_t *pBuffer = (uint8_t*)address;
uint8_t xSign = 0;
uint32_t rxCnt = 0;
if (maxSize == 0) return 0;
if (bStart)
{
printf("\n\r-- Please start binary data in %d seconds:\n\r",
TIMEOUT_RX_START / 1000);
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
DBGU_PutChar(' ');
break;
}
else
{
delay = GetDelayInTicks(tick0, GetTickCount());
if ((delay % 1000) == 0)
{
if (xSign == 0)
{
DBGU_PutChar('*');
xSign = 1;
}
}
else if (xSign)
{
xSign = 0;
}
if (delay > TIMEOUT_RX_START)
{
printf("\n\rRX timeout!\n\r");
return rxCnt;
}
}
}
}
/* Get data */
while(1)
{
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
if ((rxCnt % (10*1024)) == 0)
{
DBGU_PutChar('.');
}
if (rxCnt >= maxSize)
{
/* Wait until file transfer finished */
return rxCnt;
}
break;
}
delay = GetDelayInTicks(tick0, GetTickCount());
if (delay > TIMEOUT_RX)
{
return rxCnt;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
*
* \note When "CCC..", uses Ctrl + D to exit.
*
* \param pktBuffer 1K size packet buffer
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceive1KXModem(uint8_t* pktBuffer,
uint32_t address,
uint32_t maxSize)
{
uint8_t inChar;
uint32_t i, index = 0, pktLen = 0;
uint8_t pktNum = 0, prevPktNum = 0;
uint32_t error = 0;
uint16_t inCrc, myCrc;
uint8_t inCheckSum = 0xFF, checkSum = 0;
uint8_t *pBuffer = (uint8_t*)address;
uint32_t totalLen = 0;
DBGU_PutChar('C');
while (1)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT))
{
DBGU_PutChar('C');
continue;
}
/* Done */
if (EOT == inChar)
{
error = 0;
DBGU_PutChar(ACK);
break;
}
else if (CAN == inChar)
{
error = 2;
}
else if (CTRL_X == inChar)
{
error = 3;
}
else if (SOH == inChar)
{
pktLen = SOH_LENGTH;
}
else if (STX == inChar)
{
pktLen = STX_LENGTH;
}
else continue;
/* Get Packet Number */
if (!DbgReceiveByte(&pktNum, SOH_TIMEOUT)) error = 4;
/* Get 1's complement of packet number */
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 5;
/* Get 1 packet of information. */
checkSum = 0; myCrc = 0; index = 0;
for (i = 0; i < pktLen; i ++)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 6;
checkSum += inChar;
myCrc = _GetCRC(inChar, myCrc);
if (pktNum != prevPktNum)
{
pktBuffer[index ++] = inChar;
}
}
/* Get CRC bytes */
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc = inCheckSum << 8;
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc += inCheckSum;
/* If CRC error, NAK */
if (error || (inCrc != myCrc))
{
DBGU_PutChar(NAK);
error = 0;
}
/* Save packet, ACK and next */
else
{
prevPktNum = pktNum;
/* Buffer full? */
if (totalLen + pktLen > maxSize)
{
/* Copy until buffer full? */
/* Stop transfer */
DBGU_PutChar(CAN);
return totalLen;
}
/* Copy the packet */
for (i = 0; i < pktLen; i ++)
{
pBuffer[totalLen + i] = pktBuffer[i];
}
totalLen += pktLen;
DBGU_PutChar(ACK);
}
}
return totalLen;
}

475
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/dbgu_console.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implements DBGU console.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdio.h>
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** The Pheripheral has no HW ID */
#define ID_NOTUSED 0xFF
/** Usart Hw ID (ID_USART0) */
#define CONSOLE_ID (pDbgPort->bID)
/** Usart Hw interface used by the console (USART0). */
#define CONSOLE_DBGU ((Dbgu*)pDbgPort->pHw)
/** Pins description list */
#define CONSOLE_PINLIST (pDbgPort->pPioList)
/** Pins description list size */
#define CONSOLE_PINLISTSIZE (pDbgPort->bPioListSize)
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/**
* Debug port struct
*/
typedef struct _DbgPort {
const void* pHw;
const Pin* pPioList;
const uint8_t bPioListSize;
const uint8_t bID;
} sDbgPort;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
/** Pins for DBGU */
static const Pin pinsDbgu[] = {PINS_DBGU};
/** Pins for USART0 */
static const Pin pinsUs0[] = {PIN_USART0_TXD, PIN_USART0_RXD};
/** Pins for USART1 */
static const Pin pinsUs1[] = {PIN_USART1_TXD, PIN_USART1_RXD};
/** Pins for USART3 */
static const Pin pinsUs3[] = {PIN_USART3_TXD, PIN_USART3_RXD};
/** Uses DBGU as debug port */
static sDbgPort dbgpDbgu =
{
DBGU,
pinsDbgu, PIO_LISTSIZE(pinsDbgu),
ID_DBGU
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs0 =
{
USART0,
pinsUs0, PIO_LISTSIZE(pinsUs0),
ID_USART0
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs1 =
{
USART1,
pinsUs1, PIO_LISTSIZE(pinsUs1),
ID_USART1
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs3 =
{
USART3,
pinsUs3, PIO_LISTSIZE(pinsUs3),
ID_USART3
};
/** Current used debug port */
static sDbgPort *pDbgPort = &dbgpUs3;
/** Console initialize status */
uint8_t _bConsoleIsInitialized = 0;
/**
* \brief Select USART0 as DBGU port.
*/
void DBGU_ConsoleUseUSART0(void)
{
pDbgPort = &dbgpUs0;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select USART1 as DBGU port.
*/
void DBGU_ConsoleUseUSART1(void)
{
pDbgPort = &dbgpUs1;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select USART3 as DBGU port.
*/
void DBGU_ConsoleUseUSART3(void)
{
pDbgPort = &dbgpUs3;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select DBGU as DBGU port.
*/
void DBGU_ConsoleUseDBGU(void)
{
pDbgPort = &dbgpDbgu;
_bConsoleIsInitialized = 0;
}
/**
* \brief Configures an DBGU peripheral with the specified parameters.
*
* \param baudrate Baudrate at which the DBGU should operate (in Hz).
* \param masterClock Frequency of the system master clock (in Hz).
*/
extern void DBGU_Configure( uint32_t baudrate, uint32_t masterClock)
{
/* Configure PIO */
PIO_Configure(CONSOLE_PINLIST, CONSOLE_PINLISTSIZE);
if ( ID_NOTUSED != CONSOLE_ID )
{
//PMC_SetPeriMaxClock(CONSOLE_ID, BOARD_MCK);
PMC_EnablePeripheral(CONSOLE_ID);
}
/* Configure mode register */
if (CONSOLE_DBGU!= DBGU ) {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE | US_MR_CHRL_8_BIT;
}
else {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE;
}
/* Reset and disable receiver & transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RSTRX | DBGU_CR_RSTTX;
CONSOLE_DBGU->DBGU_IDR = 0xFFFFFFFF;
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXDIS | DBGU_CR_TXDIS;
/* Configure baudrate */
CONSOLE_DBGU->DBGU_BRGR = (masterClock/2 / baudrate) / 16;
/* Enable receiver and transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXEN | DBGU_CR_TXEN;
_bConsoleIsInitialized = 1 ;
#if defined(__GNUC__)
setvbuf(stdout, (char*)NULL, _IONBF, 0);
#endif
}
/**
* \brief Outputs a character on the DBGU line.
*
* \note This function is synchronous (i.e. uses polling).
* \param c Character to send.
*/
extern void DBGU_PutChar( uint8_t c )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
/* Wait for the transmitter to be ready */
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_TXEMPTY) == 0 ) ;
/* Send character */
CONSOLE_DBGU->DBGU_THR=c ;
}
/**
* \brief Input a character from the DBGU line.
*
* \note This function is synchronous
* \return character received.
*/
extern uint32_t DBGU_GetChar( void )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) == 0 ) ;
return CONSOLE_DBGU->DBGU_RHR ;
}
/**
* \brief Check if there is Input from DBGU line.
*
* \return true if there is Input.
*/
extern uint32_t DBGU_IsRxReady( void )
{
if ( !_bConsoleIsInitialized )
{
//DBGU_Configure( CONSOLE_BAUDRATE, BOARD_MCK ) ;
}
return (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) > 0 ;
}
/**
* Displays the content of the given frame on the DBGU.
*
* \param pucFrame Pointer to the frame to dump.
* \param dwSize Buffer size in bytes.
*/
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize )
{
uint32_t dw ;
for ( dw=0 ; dw < dwSize ; dw++ )
{
printf( "%02X ", pucFrame[dw] ) ;
}
printf( "\n\r" ) ;
}
/**
* Displays the content of the given buffer on the DBGU.
*
* \param pucBuffer Pointer to the buffer to dump.
* \param dwSize Buffer size in bytes.
* \param dwAddress Start address to display
*/
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress )
{
uint32_t i ;
uint32_t j ;
uint32_t dwLastLineStart ;
uint8_t* pucTmp ;
for ( i=0 ; i < (dwSize / 16) ; i++ )
{
printf( "0x%08X: ", (unsigned int )(dwAddress + ( i * 16) )) ;
pucTmp = (uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 4 ; j++ )
{
printf( "%02X%02X%02X%02X ", pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3] ) ;
pucTmp += 4 ;
}
pucTmp=(uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 16 ; j++ )
{
DBGU_PutChar( *pucTmp++ ) ;
}
printf( "\n\r" ) ;
}
if ( (dwSize%16) != 0 )
{
dwLastLineStart=dwSize - (dwSize%16) ;
printf( "0x%08X: ", (unsigned int ) (dwAddress + dwLastLineStart )) ;
for ( j=dwLastLineStart ; j < dwLastLineStart+16 ; j++ )
{
if ( (j!=dwLastLineStart) && (j%4 == 0) )
{
printf( " " ) ;
}
if ( j < dwSize )
{
printf( "%02X", pucBuffer[j] ) ;
}
else
{
printf(" ") ;
}
}
printf( " " ) ;
for ( j=dwLastLineStart ; j < dwSize ; j++ )
{
DBGU_PutChar( pucBuffer[j] ) ;
}
printf( "\n\r" ) ;
}
}
/**
* Reads an integer
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint8_t ucNbNb=0 ;
uint32_t dwValue=0 ;
while ( 1 )
{
ucKey=DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 10) + (ucKey - '0');
ucNbNb++ ;
}
else
{
if ( ucKey == 0x0D || ucKey == ' ' )
{
if ( ucNbNb == 0 )
{
printf( "\n\rWrite a number and press ENTER or SPACE!\n\r" ) ;
return 0 ;
}
else
{
printf( "\n\r" ) ;
*pdwValue=dwValue ;
return 1 ;
}
}
else
{
printf( "\n\r'%c' not a number!\n\r", ucKey ) ;
return 0 ;
}
}
}
}
/**
* Reads an integer and check the value
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
* \param dwMin Minimum value
* \param dwMax Maximum value
*/
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax )
{
uint32_t dwValue=0 ;
if ( DBGU_GetInteger( &dwValue ) == 0 )
{
return 0 ;
}
if ( dwValue < dwMin || dwValue > dwMax )
{
printf( "\n\rThe number have to be between %u and %u\n\r", (unsigned int)dwMin, (unsigned int)dwMax ) ;
return 0 ;
}
printf( "\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
/**
* Reads an hexadecimal number
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint32_t dw = 0 ;
uint32_t dwValue = 0 ;
for ( dw=0 ; dw < 8 ; dw++ )
{
ucKey = DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 16) + (ucKey - '0') ;
}
else
{
if ( ucKey >= 'A' && ucKey <= 'F' )
{
dwValue = (dwValue * 16) + (ucKey - 'A' + 10) ;
}
else
{
if ( ucKey >= 'a' && ucKey <= 'f' )
{
dwValue = (dwValue * 16) + (ucKey - 'a' + 10) ;
}
else
{
printf( "\n\rIt is not a hexa character!\n\r" ) ;
return 0 ;
}
}
}
}
printf("\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
#if defined __ICCARM__ /* IAR Ewarm 5.41+ */
/**
* \brief Outputs a character on the DBGU.
*
* \param c Character to output.
*
* \return The character that was output.
*/
extern WEAK signed int putchar( signed int c )
{
DBGU_PutChar( c ) ;
return c ;
}
#endif // defined __ICCARM__

516
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/gmacb.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** Default max retry count */
#define GMACB_RETRY_MAX 300000
/** Default max retry count */
#define GACB_RETRY_MAX 1000000
/*---------------------------------------------------------------------------
* Local functions
*---------------------------------------------------------------------------*/
/**
* Wait PHY operation complete.
* Return 1 if the operation completed successfully.
* May be need to re-implemented to reduce CPU load.
* \param retry: the retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_WaitPhy( Gmac *pHw, uint32_t retry )
{
volatile uint32_t retry_count = 0;
while (!GMAC_IsIdle(pHw))
{
if(retry == 0) continue;
retry_count ++;
if (retry_count >= retry)
{
return 0;
}
}
return 1;
}
/**
* Read PHY register.
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param pValue Pointer to a 32 bit location to store read data
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_ReadPhy(Gmac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t *pValue,
uint32_t retry)
{
GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0);
if ( GMACB_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut GMACB_ReadPhy\n\r");
return 0;
}
*pValue = GMAC_PHYData(pHw);
return 1;
}
/**
* Write PHY register
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param Value Data to write ( Actually 16 bit data )
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_WritePhy(Gmac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t Value,
uint32_t retry)
{
GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value);
if ( GMACB_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut GMACB_WritePhy\n\r");
return 0;
}
return 1;
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* \brief Find a valid PHY Address ( from 0 to 31 ).
* \param pMacb Pointer to the MACB instance
* \return 0xFF when no valid PHY Address found.
*/
static uint8_t GMACB_FindValidPhy(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value=0;
uint8_t rc;
uint8_t phyAddress;
uint8_t cnt;
TRACE_DEBUG("GMACB_FindValidPhy\n\r");
GMAC_EnableMdio(pHw);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
/* Check current phyAddress */
rc = phyAddress;
if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) == 0 ) {
TRACE_ERROR("GMACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
/* Find another one */
if (value != GMII_OUI_MSB) {
rc = 0xFF;
for(cnt = 0; cnt < 32; cnt ++) {
phyAddress = (phyAddress + 1) & 0x1F;
if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) == 0 ) {
TRACE_ERROR("MACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
if (value == GMII_OUI_MSB) {
rc = phyAddress;
break;
}
}
}
if (rc != 0xFF) {
TRACE_INFO("** Valid PHY Found: %d\n\r", rc);
GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax);
TRACE_DEBUG("_PHYID1R : 0x%X, addr: %d\n\r", value, phyAddress);
GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID2R, &value, retryMax);
TRACE_DEBUG("_EMSR : 0x%X, addr: %d\n\r", value, phyAddress);
}
GMAC_DisableMdio(pHw);
return rc;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Dump all the useful registers.
* \param pMacb Pointer to the MACB instance
*/
void GMACB_DumpRegisters(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint8_t phyAddress;
uint32_t retryMax;
uint32_t value;
TRACE_INFO("GMACB_DumpRegisters\n\r");
GMAC_EnableMdio(pHw);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
TRACE_INFO("GMII MACB @%d) Registers:\n\r", phyAddress);
GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);
TRACE_INFO(" _BMCR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);
TRACE_INFO(" _BMSR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &value, retryMax);
TRACE_INFO(" _ANAR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &value, retryMax);
TRACE_INFO(" _ANLPAR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANER, &value, retryMax);
TRACE_INFO(" _ANER : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANNPR, &value, retryMax);
TRACE_INFO(" _ANNPR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPNPAR, &value, retryMax);
TRACE_INFO(" _ANLPNPAR : 0x%X\n\r", value);
TRACE_INFO(" \n\r");
GMACB_ReadPhy(pHw, phyAddress, GMII_RXERCR, &value, retryMax);
TRACE_INFO(" _RXERCR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ICSR, &value, retryMax);
TRACE_INFO(" _ICSR : 0x%X\n\r", value);
TRACE_INFO(" \n\r");
GMAC_DisableMdio(pHw);
}
/**
* \brief Setup the maximum timeout count of the driver.
* \param pMacb Pointer to the MACB instance
* \param toMax Timeout maxmum count.
*/
void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax)
{
pMacb->retryMax = toMax;
}
/**
* \brief Initialize the MACB instance.
* \param pMacb Pointer to the MACB instance
* \param phyAddress The PHY address used to access the PHY
*/
void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress)
{
pMacb->pGmacd = pGmacd;
pMacb->phyAddress = phyAddress;
/* Initialize timeout by default */
pMacb->retryMax = GMACB_RETRY_MAX;
}
/**
* \brief Issue a SW reset to reset all registers of the PHY.
* \param pMacb Pointer to the MACB instance
* \return 1 if successfully, 0 if timeout.
*/
uint8_t GMACB_ResetPhy(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t bmcr = GMII_RESET;
uint8_t phyAddress;
uint32_t timeout = 10;
uint8_t ret = 1;
TRACE_INFO(" GMACB_ResetPhy\n\r");
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
GMAC_EnableMdio(pHw);
bmcr = GMII_RESET;
GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, bmcr, retryMax);
do {
GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &bmcr, retryMax);
timeout--;
} while ((bmcr & GMII_RESET) && timeout);
GMAC_DisableMdio(pHw);
if (!timeout) {
ret = 0;
}
return( ret );
}
/**
* \brief Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs
* This should be called only once to initialize the PHY pre-settings.
* The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups).
* The COL pin is used to select MII mode on reset (pulled up for Reduced MII)
* The RXDV pin is used to select test mode on reset (pulled up for test mode)
* The above pins should be predefined for corresponding settings in resetPins
* The GMAC peripheral pins are configured after the reset done.
* \param pMacb Pointer to the MACB instance
* \param mck Main clock setting to initialize clock
* \param resetPins Pointer to list of PIOs to configure before HW RESET
* (for PHY power on reset configuration latch)
* \param nbResetPins Number of PIO items that should be configured
* \param emacPins Pointer to list of PIOs for the EMAC interface
* \param nbEmacPins Number of PIO items that should be configured
* \return 1 if RESET OK, 0 if timeout.
*/
uint8_t GMACB_InitPhy(GMacb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pGmacPins,
uint32_t nbGmacPins)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint8_t rc = 1;
uint8_t phy;
/* Perform RESET */
TRACE_DEBUG("RESET PHY\n\r");
if (pResetPins) {
/* Configure PINS */
PIO_Configure(pResetPins, nbResetPins);
}
/* Configure GMAC runtime pins */
if (rc) {
PIO_Configure(pGmacPins, nbGmacPins);
rc = GMAC_SetMdcClock(pHw, mck );
if (!rc) {
TRACE_ERROR("No Valid MDC clock\n\r");
return 0;
}
/* Check PHY Address */
phy = GMACB_FindValidPhy(pMacb);
if (phy == 0xFF) {
TRACE_ERROR("PHY Access fail\n\r");
return 0;
}
if(phy != pMacb->phyAddress) {
pMacb->phyAddress = phy;
GMACB_ResetPhy(pMacb);
}
}
else {
TRACE_ERROR("PHY Reset Timeout\n\r");
}
return rc;
}
/**
* \brief Issue a Auto Negotiation of the PHY
* \param pMacb Pointer to the MACB instance
* \return 1 if successfully, 0 if timeout.
*/
uint8_t GMACB_AutoNegotiate(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value;
uint32_t phyAnar;
uint32_t phyAnalpar;
uint32_t retryCount= 0;
uint8_t phyAddress;
uint8_t rc = 1;
uint32_t duplex, speed;
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
GMAC_EnableMdio(pHw);
if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID1R, &value, retryMax))
{
TRACE_ERROR("Pb GEMAC_ReadPhy Id1\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress);
if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID2R, &phyAnar, retryMax))
{
TRACE_ERROR("Pb GMACB_ReadPhy Id2\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar);
if( ( value == GMII_OUI_MSB )
&& ( ((phyAnar)&(~GMII_LSB_MASK)) == GMII_OUI_LSB ) )
{
TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F));
TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0xF));
}
else
{
TRACE_ERROR("Problem OUI value\n\r");
}
/* Set the Auto_negotiation Advertisement Register, MII advertising for Next page
100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &phyAnar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
phyAnar = GMII_TX_FDX | GMII_TX_HDX |
GMII_10_FDX | GMII_10_HDX | GMII_AN_IEEE_802_3;
rc = GMACB_WritePhy(pHw,phyAddress, GMII_ANAR, phyAnar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Read & modify control register */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Check AutoNegotiate complete */
value |= GMII_AUTONEG | GMII_RESTART_AUTONEG;
rc = GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
TRACE_DEBUG(" _BMCR: 0x%X\n\r", value);
// Check AutoNegotiate complete
while (1)
{
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);
if (rc == 0)
{
TRACE_ERROR("rc==0\n\r");
goto AutoNegotiateExit;
}
/* Done successfully */
if (value & GMII_AUTONEG_COMP)
{
printf("AutoNegotiate complete\n\r");
break;
}
/* Timeout check */
if (retryMax)
{
if (++ retryCount >= retryMax)
{
GMACB_DumpRegisters(pMacb);
TRACE_ERROR("TimeOut\n\r");
rc = 0;
goto AutoNegotiateExit;
}
}
}
/*Set local link mode */
while(1)
{
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &phyAnalpar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Setup the GMAC link speed */
if ((phyAnar & phyAnalpar) & GMII_TX_FDX)
{
/* set RGMII for 1000BaseTX and Full Duplex */
duplex = GMAC_DUPLEX_FULL;
speed = GMAC_SPEED_100M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_10_FDX)
{
/* set RGMII for 1000BaseT and Half Duplex*/
duplex = GMAC_DUPLEX_FULL;
speed = GMAC_SPEED_10M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_TX_HDX)
{
/* set RGMII for 100BaseTX and half Duplex */
duplex = GMAC_DUPLEX_HALF;
speed = GMAC_SPEED_100M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_10_HDX)
{
// set RGMII for 10BaseT and half Duplex
duplex = GMAC_DUPLEX_HALF;
speed = GMAC_SPEED_10M;
break;
}
}
TRACE_INFO("-I- GMAC_EnableRGMII duplex %d, speed %d\n\r",duplex,speed);
/* Setup GMAC mode */
GMAC_EnableRGMII(pHw, duplex, speed);
AutoNegotiateExit:
GMAC_DisableMdio(pHw);
return rc;
}

711
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/gmacd.c Normal file
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@ -0,0 +1,711 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
#include <string.h>
/** \addtogroup gmacd_defines
@{*/
/*----------------------------------------------------------------------------
* Macro
*----------------------------------------------------------------------------*/
/** Return count in buffer */
#define GCIRC_CNT(head,tail,size) (((head) - (tail)) % (size))
/** Return space available, 0..size-1. always leave one free char as a completely full buffer
has head == tail, which is the same as empty */
#define GCIRC_SPACE(head,tail,size) GCIRC_CNT((tail),((head)+1),(size))
/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once,
so they can change underneath us without returning inconsistent results */
#define GCIRC_CNT_TO_END(head,tail,size) \
({int end = (size) - (tail); \
int n = ((head) + end) % (size); \
n < end ? n : end;})
/** Return space available up to the end of the buffer */
#define GCIRC_SPACE_TO_END(head,tail,size) \
({int end = (size) - 1 - (head); \
int n = (end + (tail)) % (size); \
n <= end ? n : end+1;})
/** Increment head or tail */
#define GCIRC_INC(headortail,size) \
headortail++; \
if(headortail >= size) { \
headortail = 0; \
}
/** Circular buffer is empty ? */
#define GCIRC_EMPTY(head, tail) (head == tail)
/** Clear circular buffer */
#define GCIRC_CLEAR(head, tail) (head = tail = 0)
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
/// The buffer addresses written into the descriptors must be aligned so the
/// last few bits are zero. These bits have special meaning for the GMAC
/// peripheral and cannot be used as part of the address.
#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)
#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask
// receive buffer descriptor bits
#define GMAC_RX_OWNERSHIP_BIT (1 << 0)
#define GMAC_RX_WRAP_BIT (1 << 1)
#define GMAC_RX_SOF_BIT (1 << 14)
#define GMAC_RX_EOF_BIT (1 << 15)
// Transmit buffer descriptor bits
#define GMAC_TX_LAST_BUFFER_BIT (1 << 15)
#define GMAC_TX_WRAP_BIT (1 << 30)
#define GMAC_TX_USED_BIT (1 << 31)
#define GMAC_TX_RLE_BIT (1 << 29) /// Retry Limit Exceeded
#define GMAC_TX_UND_BIT (1 << 28) /// Tx Buffer Underrun
#define GMAC_TX_ERR_BIT (1 << 27) /// Exhausted in mid-frame
#define GMAC_TX_ERR_BITS \
(GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
/*---------------------------------------------------------------------------
* Local functions
*---------------------------------------------------------------------------*/
/**
* \brief Disable TX & reset registers and descriptor list
* \param pDrv Pointer to GMAC Driver instance.
*/
static void GMACD_ResetTx(sGmacd *pDrv )
{
Gmac *pHw = pDrv->pHw;
uint8_t *pTxBuffer = pDrv->pTxBuffer;
sGmacTxDescriptor *pTd = pDrv->pTxD;
uint32_t Index;
uint32_t Address;
/* Disable TX */
GMAC_TransmitEnable(pHw, 0);
/* Setup the TX descriptors. */
GCIRC_CLEAR(pDrv->wTxHead, pDrv->wTxTail);
for(Index = 0; Index < pDrv->wTxListSize; Index++) {
Address = (uint32_t)(&(pTxBuffer[Index * GMAC_TX_UNITSIZE]));
pTd[Index].addr = Address;
pTd[Index].status.val = (uint32_t)GMAC_TX_USED_BIT;
}
pTd[pDrv->wTxListSize - 1].status.val = GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT;
/* Transmit Buffer Queue Pointer Register */
GMAC_SetTxQueue(pHw, (uint32_t)pTd);
}
/**
* \brief Disable RX & reset registers and descriptor list
* \param pDrv Pointer to GMAC Driver instance.
*/
static void GMACD_ResetRx(sGmacd *pDrv )
{
Gmac *pHw = pDrv->pHw;
uint8_t *pRxBuffer = pDrv->pRxBuffer;
sGmacRxDescriptor *pRd = pDrv->pRxD;
uint32_t Index;
uint32_t Address;
/* Disable RX */
GMAC_ReceiveEnable(pHw, 0);
/* Setup the RX descriptors. */
pDrv->wRxI = 0;
for(Index = 0; Index < pDrv->wRxListSize; Index++)
{
Address = (uint32_t)(&(pRxBuffer[Index * GMAC_RX_UNITSIZE]));
/* Remove GMAC_RXD_bmOWNERSHIP and GMAC_RXD_bmWRAP */
pRd[Index].addr.val = Address & GMAC_ADDRESS_MASK;
pRd[Index].status.val = 0;
}
pRd[pDrv->wRxListSize - 1].addr.val |= GMAC_RX_WRAP_BIT;
/* Receive Buffer Queue Pointer Register */
GMAC_SetRxQueue(pHw, (uint32_t) pRd);
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* \brief GMAC Interrupt handler
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Handler(sGmacd *pGmacd )
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
fGmacdTransferCallback *pTxCb = NULL;
uint32_t isr;
uint32_t rsr;
uint32_t tsr;
uint32_t rxStatusFlag;
uint32_t txStatusFlag;
isr = GMAC_GetItStatus(pHw);
rsr = GMAC_GetRxStatus(pHw);
tsr = GMAC_GetTxStatus(pHw);
isr &= ~(GMAC_GetItMask(pHw)| 0xF8030300);
/* RX packet */
if ((isr & GMAC_ISR_RCOMP) || (rsr & GMAC_RSR_REC)) {
asm("nop");
rxStatusFlag = GMAC_RSR_REC;
/* Frame received */
/* Check OVR */
if (rsr & GMAC_RSR_RXOVR) {
rxStatusFlag |= GMAC_RSR_RXOVR;
}
/* Check BNA */
if (rsr & GMAC_RSR_BNA) {
rxStatusFlag |= GMAC_RSR_BNA;
}
/* Check HNO */
if (rsr & GMAC_RSR_HNO) {
rxStatusFlag |= GMAC_RSR_HNO;
}
/* Clear status */
GMAC_ClearRxStatus(pHw, rxStatusFlag);
/* Invoke callbacks */
if (pGmacd->fRxCb)
{
pGmacd->fRxCb(rxStatusFlag);
}
}
/* TX packet */
if ((isr & GMAC_ISR_TCOMP) || (tsr & GMAC_TSR_TXCOMP)) {
asm("nop");
txStatusFlag = GMAC_TSR_TXCOMP;
/* A frame transmitted Check RLE */
if (tsr & GMAC_TSR_RLE) {
/* Status RLE & Number of discarded buffers */
txStatusFlag = GMAC_TSR_RLE
| GCIRC_CNT(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize);
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
GMACD_ResetTx(pGmacd);
TRACE_INFO("Tx RLE!!\n\r");
GMAC_TransmitEnable(pHw, 1);
}
/* Check COL */
if (tsr & GMAC_TSR_COL) {
txStatusFlag |= GMAC_TSR_COL;
}
/* Check TFC */
if (tsr & GMAC_TSR_TFC) {
txStatusFlag |= GMAC_TSR_TFC;
}
/* Check UND */
if (tsr & GMAC_TSR_UND) {
txStatusFlag |= GMAC_TSR_UND;
}
/* Check HRESP */
if (tsr & GMAC_TSR_HRESP) {
txStatusFlag |= GMAC_TSR_HRESP;
}
/* Clear status */
GMAC_ClearTxStatus(pHw, txStatusFlag);
if (!GCIRC_EMPTY(pGmacd->wTxHead, pGmacd->wTxTail))
{
/* Check the buffers */
do {
pTxTd = &pGmacd->pTxD[pGmacd->wTxTail];
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
/* Exit if buffer has not been sent yet */
if ((pTxTd->status.val & (uint32_t)GMAC_TX_USED_BIT) == 0) {
break;
}
/* Notify upper layer that a packet has been sent */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
GCIRC_INC( pGmacd->wTxTail, pGmacd->wTxListSize );
} while (GCIRC_CNT(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize));
}
if (tsr & GMAC_TSR_RLE) {
/* Notify upper layer RLE */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
}
/* If a wakeup has been scheduled, notify upper layer that it can
send other packets, send will be successfull. */
if((GCIRC_SPACE(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize) >= pGmacd->bWakeupThreshold) && pGmacd->fWakupCb)
{
pGmacd->fWakupCb();
}
}
/* PAUSE Frame */
if (isr & GMAC_ISR_PFNZ) TRACE_INFO("Pause!\n\r");
if (isr & GMAC_ISR_PTZ) TRACE_INFO("Pause TO!\n\r");
}
/**
* \brief Initialize the GMAC with the Gmac controller address
* \param pGmacd Pointer to GMAC Driver instance.
* \param pHw Pointer to HW address for registers.
* \param bID HW ID for power management
* \param enableCAF Enable/Disable CopyAllFrame.
* \param enableNBC Enable/Disable NoBroadCast.
*/
void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC )
{
uint32_t dwNcfgr;
/* Check parameters */
assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);
TRACE_DEBUG("GMAC_Init\n\r");
/* Initialize struct */
pGmacd->pHw = pHw;
pGmacd->bId = bID;
/* Power ON */
PMC_EnablePeripheral(bID);
/* Disable TX & RX and more */
GMAC_NetworkControl(pHw, 0);
GMAC_DisableIt(pHw, ~0u);
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_UND | GMAC_TSR_HRESP );
/* Clear interrupts */
GMAC_GetItStatus(pHw);
/* Enable the copy of data into the buffers
ignore broadcasts, and don't copy FCS. */
dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW_DBW32 | GMAC_NCFGR_CLK_MCK_64;
if( enableCAF ) {
dwNcfgr |= GMAC_NCFGR_CAF;
}
if( enableNBC ) {
dwNcfgr |= GMAC_NCFGR_NBC;
}
GMAC_Configure(pHw, dwNcfgr);
}
/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* GMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* GMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,
uint16_t wTxSize)
{
Gmac *pHw = pGmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) )
{
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pGmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pGmacd->pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pGmacd->wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) )
{
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pGmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pGmacd->pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pGmacd->wTxListSize = wTxSize;
pGmacd->fTxCbList = pTxCb;
/* Reset TX & RX */
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
/* Enable Rx and Tx, plus the stats register. */
GMAC_TransmitEnable(pHw, 1);
GMAC_ReceiveEnable(pHw, 1);
GMAC_StatisticsWriteEnable(pHw, 1);
/* Setup the interrupts for TX (and errors) */
GMAC_EnableIt(pHw, GMAC_IER_MFS
|GMAC_IER_RCOMP
|GMAC_IER_RXUBR
|GMAC_IER_TXUBR
|GMAC_IER_TUR
|GMAC_IER_RLEX
|GMAC_IER_TFC
|GMAC_IER_TCOMP
|GMAC_IER_ROVR
|GMAC_IER_HRESP
|GMAC_IER_PFNZ
|GMAC_IER_PTZ
|GMAC_IER_PFTR
|GMAC_IER_EXINT
|GMAC_IER_DRQFR
|GMAC_IER_SFR
|GMAC_IER_DRQFT
|GMAC_IER_SFT
|GMAC_IER_PDRQFR
|GMAC_IER_PDRSFR
|GMAC_IER_PDRQFT
|GMAC_IER_PDRSFT);
//0x03FCFCFF
return GMACD_OK;
}
/**
* Reset TX & RX queue & statistics
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Reset(sGmacd *pGmacd)
{
Gmac *pHw = pGmacd->pHw;
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
//memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats));
GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN
| GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
}
/**
* \brief Send a packet with GMAC. If the packet size is larger than transfer buffer size
* error returned. If packet transfer status is monitored, specify callback for each packet.
* \param pGmacd Pointer to GMAC Driver instance.
* \param buffer The buffer to be send
* \param size The size of buffer to be send
* \param fGMAC_TxCallback Threshold Wakeup callback
* \param fWakeUpCb TX Wakeup
* \return OK, Busy or invalid packet
*/
uint8_t GMACD_Send(sGmacd *pGmacd,
void *pBuffer,
uint32_t size,
fGmacdTransferCallback fTxCb )
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
volatile fGmacdTransferCallback *pfTxCb;
TRACE_DEBUG("GMAC_Send\n\r");
/* Check parameter */
if (size > GMAC_TX_UNITSIZE) {
TRACE_ERROR("GMAC driver does not split send packets.");
return GMACD_PARAM;
}
/* Pointers to the current TxTd */
pTxTd = &pGmacd->pTxD[pGmacd->wTxHead];
/* If no free TxTd, buffer can't be sent */
if( GCIRC_SPACE(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize) == 0)
return GMACD_TX_BUSY;
/* Pointers to the current Tx Callback */
pfTxCb = &pGmacd->fTxCbList[pGmacd->wTxHead];
/* Sanity check */
/* Setup/Copy data to transmition buffer */
if (pBuffer && size) {
// Driver manage the ring buffer
memcpy((void *)pTxTd->addr, pBuffer, size);
}
/* Tx Callback */
*pfTxCb = fTxCb;
/* Update TD status. The buffer size defined is length of ethernet frame
so it's always the last buffer of the frame. */
if (pGmacd->wTxHead == pGmacd->wTxListSize-1) {
pTxTd->status.val =
(size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT | GMAC_TX_WRAP_BIT;
}
else {
pTxTd->status.val = (size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT;
}
GCIRC_INC(pGmacd->wTxHead, pGmacd->wTxListSize);
//CP15_flush_dcache_for_dma ((uint32_t)(pTxTd), ((uint32_t)(pTxTd) + sizeof(pTxTd)));
/* Tx packets count */
/* Now start to transmit if it is not already done */
GMAC_TransmissionStart(pHw);
return GMACD_OK;
}
/**
* Return current load of TX.
* \param pGmacd Pointer to GMAC Driver instance.
*/
uint32_t GMACD_TxLoad(sGmacd *pGmacd)
{
uint16_t head = pGmacd->wTxHead;
uint16_t tail = pGmacd->wTxTail;
return GCIRC_CNT(head, tail, pGmacd->wTxListSize);
}
/**
* \brief Receive a packet with GMAC.
* If not enough buffer for the packet, the remaining data is lost but right
* frame length is returned.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pFrame Buffer to store the frame
* \param frameSize Size of the frame
* \param pRcvSize Received size
* \return OK, no data, or frame too small
*/
uint8_t GMACD_Poll(sGmacd * pGmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize)
{
uint16_t bufferLength;
uint32_t tmpFrameSize = 0;
uint8_t *pTmpFrame = 0;
uint32_t tmpIdx = pGmacd->wRxI;
volatile sGmacRxDescriptor *pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
uint8_t isFrame = 0;
if (pFrame == NULL) return GMACD_PARAM;
/* Set the default return value */
*pRcvSize = 0;
/* Process received RxTd */
while ((pRxTd->addr.val & GMAC_RX_OWNERSHIP_BIT) == GMAC_RX_OWNERSHIP_BIT)
{
/* A start of frame has been received, discard previous fragments */
if ((pRxTd->status.val & GMAC_RX_SOF_BIT) == GMAC_RX_SOF_BIT)
{
/* Skip previous fragment */
while (tmpIdx != pGmacd->wRxI)
{
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
}
pTmpFrame = pFrame;
tmpFrameSize = 0;
/* Start to gather buffers in a frame */
isFrame = 1;
}
/* Increment the pointer */
GCIRC_INC(tmpIdx, pGmacd->wRxListSize);
asm("nop");
/* Copy data in the frame buffer */
if (isFrame) {
if (tmpIdx == pGmacd->wRxI)
{
TRACE_INFO("no EOF (Invalid of buffers too small)\n\r");
do {
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
} while(tmpIdx != pGmacd->wRxI);
return GMACD_RX_NULL;
}
/* Copy the buffer into the application frame */
bufferLength = GMAC_RX_UNITSIZE;
if ((tmpFrameSize + bufferLength) > frameSize)
{
bufferLength = frameSize - tmpFrameSize;
}
memcpy(pTmpFrame, (void*)(pRxTd->addr.val & GMAC_ADDRESS_MASK), bufferLength);
pTmpFrame += bufferLength;
tmpFrameSize += bufferLength;
/* An end of frame has been received, return the data */
if ((pRxTd->status.val & GMAC_RX_EOF_BIT) == GMAC_RX_EOF_BIT)
{
/* Frame size from the GMAC */
*pRcvSize = (pRxTd->status.val & GMAC_LENGTH_FRAME);
/* Application frame buffer is too small all data have not been copied */
if (tmpFrameSize < *pRcvSize) {
return GMACD_SIZE_TOO_SMALL;
}
TRACE_DEBUG("packet %d-%d (%d)\n\r", pGmacd->wRxI, tmpIdx, *pRcvSize);
/* All data have been copied in the application frame buffer => release TD */
while (pGmacd->wRxI != tmpIdx)
{
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
}
return GMACD_OK;
}
}
/* SOF has not been detected, skip the fragment */
else {
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
pGmacd->wRxI = tmpIdx;
}
/* Process the next buffer */
pRxTd = &pGmacd->pRxD[tmpIdx];
}
return GMACD_RX_NULL;
}
/**
* \brief Registers pRxCb callback. Callback will be invoked after the next received
* frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task call GMAC_Set_RxCb()
* to register pRxCb() callback and enters suspend state. The callback is in charge
* to resume the task once a new frame has been received. The next time GMAC_Poll()
* is called, it will be successfull.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxCb Pointer to callback function
* \return OK, no data, or frame too small
*/
void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb)
{
Gmac *pHw = pGmacd->pHw;
if (fRxCb == NULL)
{
GMAC_DisableIt(pHw, GMAC_IDR_RCOMP);
pGmacd->fRxCb = NULL;
}
else
{
pGmacd->fRxCb = fRxCb;
GMAC_EnableIt(pHw, GMAC_IER_RCOMP);
}
}
/**
* Register/Clear TX wakeup callback.
*
* When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application
* task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and
* enters suspend state. The callback is in charge to resume the task once
* several TD have been released. The next time GMACD_Send() will be called,
* it shall be successfull.
*
* This function is usually invoked with NULL callback from the TX wakeup
* callback itself, to unregister. Once the callback has resumed the
* application task, there is no need to invoke the callback again.
*
* \param pGmacd Pointer to GMAC Driver instance.
* \param fWakeup Wakeup callback.
* \param bThreshould Number of free TD before wakeup callback invoked.
* \return GMACD_OK, GMACD_PARAM on parameter error.
*/
uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,
fGmacdWakeupCallback fWakeup,
uint8_t bThreshold)
{
if (fWakeup == NULL)
{
pGmacd->fWakupCb = NULL;
}
else
{
if (bThreshold <= pGmacd->wTxListSize)
{
pGmacd->fWakupCb = fWakeup;
pGmacd->bWakeupThreshold = bThreshold;
}
else
{
return GMACD_PARAM;
}
}
return GMACD_OK;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Internal function
*----------------------------------------------------------------------------*/
/**
* Counts and return the number of bits set to '1' in the given byte.
* \param byte Byte to count.
*/
static uint8_t CountBitsInByte(uint8_t byte)
{
uint8_t count = 0;
while (byte > 0)
{
if (byte & 1)
{
count++;
}
byte >>= 1;
}
return count;
}
/**
* Counts and return the number of bits set to '1' in the given hamming code.
* \param code Hamming code.
*/
static uint8_t CountBitsInCode256(uint8_t *code)
{
return CountBitsInByte(code[0]) + CountBitsInByte(code[1]) + CountBitsInByte(code[2]);
}
/**
* Calculates the 22-bit hamming code for a 256-bytes block of data.
* \param data Data buffer to calculate code for.
* \param code Pointer to a buffer where the code should be stored.
*/
static void Compute256(const uint8_t *data, uint8_t *code)
{
uint32_t i;
uint8_t columnSum = 0;
uint8_t evenLineCode = 0;
uint8_t oddLineCode = 0;
uint8_t evenColumnCode = 0;
uint8_t oddColumnCode = 0;
// Xor all bytes together to get the column sum;
// At the same time, calculate the even and odd line codes
for (i=0; i < 256; i++)
{
columnSum ^= data[i];
// If the xor sum of the byte is 0, then this byte has no incidence on
// the computed code; so check if the sum is 1.
if ((CountBitsInByte(data[i]) & 1) == 1)
{
// Parity groups are formed by forcing a particular index bit to 0
// (even) or 1 (odd).
// Example on one byte:
//
// bits (dec) 7 6 5 4 3 2 1 0
// (bin) 111 110 101 100 011 010 001 000
// '---'---'---'----------.
// |
// groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |
// P2' ooooooo eeeeeee ooooooo eeeeeee P2 |
// P1' ooo eee ooo eee ooo eee ooo eee P1 |
// |
// We can see that: |
// - P4 -> bit 2 of index is 0 --------------------'
// - P4' -> bit 2 of index is 1.
// - P2 -> bit 1 of index if 0.
// - etc...
// We deduce that a bit position has an impact on all even Px if
// the log2(x)nth bit of its index is 0
// ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
// and on all odd Px' if the log2(x)nth bit of its index is 1
// ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
//
// As such, we calculate all the possible Px and Px' values at the
// same time in two variables, evenLineCode and oddLineCode, such as
// evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1
// oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1'
//
evenLineCode ^= (255 - i);
oddLineCode ^= i;
}
}
// At this point, we have the line parities, and the column sum. First, We
// must caculate the parity group values on the column sum.
for (i=0; i < 8; i++)
{
if (columnSum & 1)
{
evenColumnCode ^= (7 - i);
oddColumnCode ^= i;
}
columnSum >>= 1;
}
// Now, we must interleave the parity values, to obtain the following layout:
// Code[0] = Line1
// Code[1] = Line2
// Code[2] = Column
// Line = Px' Px P(x-1)- P(x-1) ...
// Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
code[0] = 0;
code[1] = 0;
code[2] = 0;
for (i=0; i < 4; i++)
{
code[0] <<= 2;
code[1] <<= 2;
code[2] <<= 2;
// Line 1
if ((oddLineCode & 0x80) != 0)
{
code[0] |= 2;
}
if ((evenLineCode & 0x80) != 0)
{
code[0] |= 1;
}
// Line 2
if ((oddLineCode & 0x08) != 0)
{
code[1] |= 2;
}
if ((evenLineCode & 0x08) != 0)
{
code[1] |= 1;
}
// Column
if ((oddColumnCode & 0x04) != 0)
{
code[2] |= 2;
}
if ((evenColumnCode & 0x04) != 0)
{
code[2] |= 1;
}
oddLineCode <<= 1;
evenLineCode <<= 1;
oddColumnCode <<= 1;
evenColumnCode <<= 1;
}
// Invert codes (linux compatibility)
code[0] = (~(uint32_t)code[0]);
code[1] = (~(uint32_t)code[1]);
code[2] = (~(uint32_t)code[2]);
TRACE_DEBUG("Computed code = %02X %02X %02X\n\r",
code[0], code[1], code[2]);
}
/**
* Verifies and corrects a 256-bytes block of data using the given 22-bits
* hamming code.
*
* \param data Data buffer to check.
* \param originalCode Hamming code to use for verifying the data.
*
* \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.
*/
static uint8_t Verify256( uint8_t* pucData, const uint8_t* pucOriginalCode )
{
/* Calculate new code */
uint8_t computedCode[3] ;
uint8_t correctionCode[3] ;
Compute256( pucData, computedCode ) ;
/* Xor both codes together */
correctionCode[0] = computedCode[0] ^ pucOriginalCode[0] ;
correctionCode[1] = computedCode[1] ^ pucOriginalCode[1] ;
correctionCode[2] = computedCode[2] ^ pucOriginalCode[2] ;
TRACE_DEBUG( "Correction code = %02X %02X %02X\n\r", correctionCode[0], correctionCode[1], correctionCode[2] ) ;
// If all bytes are 0, there is no error
if ( (correctionCode[0] == 0) && (correctionCode[1] == 0) && (correctionCode[2] == 0) )
{
return 0 ;
}
/* If there is a single bit error, there are 11 bits set to 1 */
if ( CountBitsInCode256( correctionCode ) == 11 )
{
// Get byte and bit indexes
uint8_t byte = correctionCode[0] & 0x80;
byte |= (correctionCode[0] << 1) & 0x40;
byte |= (correctionCode[0] << 2) & 0x20;
byte |= (correctionCode[0] << 3) & 0x10;
byte |= (correctionCode[1] >> 4) & 0x08;
byte |= (correctionCode[1] >> 3) & 0x04;
byte |= (correctionCode[1] >> 2) & 0x02;
byte |= (correctionCode[1] >> 1) & 0x01;
uint8_t bit = (correctionCode[2] >> 5) & 0x04;
bit |= (correctionCode[2] >> 4) & 0x02;
bit |= (correctionCode[2] >> 3) & 0x01;
/* Correct bit */
printf("Correcting byte #%d at bit %d\n\r", byte, bit ) ;
pucData[byte] ^= (1 << bit) ;
return Hamming_ERROR_SINGLEBIT ;
}
/* Check if ECC has been corrupted */
if ( CountBitsInCode256( correctionCode ) == 1 )
{
return Hamming_ERROR_ECC ;
}
/* Otherwise, this is a multi-bit error */
else
{
return Hamming_ERROR_MULTIPLEBITS ;
}
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Computes 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256 bytes block gets its own code.
* \param data Data to compute code for.
* \param size Data size in bytes.
* \param code Codes buffer.
*/
void Hamming_Compute256x( const uint8_t *pucData, uint32_t dwSize, uint8_t* puCode )
{
TRACE_DEBUG("Hamming_Compute256x()\n\r");
while ( dwSize > 0 )
{
Compute256( pucData, puCode ) ;
pucData += 256;
puCode += 3;
dwSize -= 256;
}
}
/**
* Verifies 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256-bytes block is verified with its own code.
*
* \return 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more
* block(s) have had a single bit corrected, or either Hamming_ERROR_ECC
* or Hamming_ERROR_MULTIPLEBITS.
*
* \param data Data buffer to verify.
* \param size Size of the data in bytes.
* \param code Original codes.
*/
uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode )
{
uint8_t error ;
uint8_t result = 0 ;
TRACE_DEBUG( "Hamming_Verify256x()\n\r" ) ;
while ( dwSize > 0 )
{
error = Verify256( pucData, pucCode ) ;
if ( error == Hamming_ERROR_SINGLEBIT )
{
result = Hamming_ERROR_SINGLEBIT ;
}
else
{
if ( error )
{
return error ;
}
}
pucData += 256;
pucCode += 3;
dwSize -= 256;
}
return result ;
}

614
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/iso7816_4.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* ISO 7816 driver
*
* \section Usage
*
* Explanation on the usage of the code made available through the header file.
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Definitions
*------------------------------------------------------------------------------*/
/** Case for APDU commands*/
#define CASE1 1
#define CASE2 2
#define CASE3 3
/** Flip flop for send and receive char */
#define USART_SEND 0
#define USART_RCV 1
#if !defined(BOARD_ISO7816_BASE_USART)
#define BOARD_ISO7816_BASE_USART USART1
#define BOARD_ISO7816_ID_USART ID_USART1
#endif
/*-----------------------------------------------------------------------------
* Internal variables
*-----------------------------------------------------------------------------*/
/** Variable for state of send and receive froom USART */
static uint8_t StateUsartGlobal = USART_RCV;
/** Pin reset master card */
static Pin st_pinIso7816RstMC;
static uint32_t maxMck;
/*----------------------------------------------------------------------------
* Internal functions
*----------------------------------------------------------------------------*/
/**
* Get a character from ISO7816
* \param pCharToReceive Pointer for store the received char
* \return 0: if timeout else status of US_CSR
*/
static uint32_t ISO7816_GetChar( uint8_t *pCharToReceive )
{
uint32_t status;
uint32_t timeout=0;
if( StateUsartGlobal == USART_SEND ) {
while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXEMPTY) == 0) {}
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
StateUsartGlobal = USART_RCV;
}
/* Wait USART ready for reception */
while( ((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_RXRDY) == 0) ) {
if(timeout++ > 12000 * (BOARD_MCK/1000000)) {
TRACE_DEBUG("TimeOut\n\r");
return( 0 );
}
}
TRACE_DEBUG("T: %u\n\r", timeout);
/* At least one complete character has been received and US_RHR has not yet been read. */
/* Get a char */
*pCharToReceive = ((BOARD_ISO7816_BASE_USART->US_RHR) & 0xFF);
status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME|
US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK|
(1<<10)));
if (status != 0 ) {
/* TRACE_DEBUG("R:0x%X\n\r", status); */
TRACE_DEBUG("R:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR);
TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER );
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA;
}
/* Return status */
return( status );
}
/**
* Send a char to ISO7816
* \param CharToSend char to be send
* \return status of US_CSR
*/
static uint32_t ISO7816_SendChar( uint8_t CharToSend )
{
uint32_t status;
if( StateUsartGlobal == USART_RCV ) {
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
StateUsartGlobal = USART_SEND;
}
/* Wait USART ready for transmit */
while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXRDY) == 0) {}
/* There is no character in the US_THR */
/* Transmit a char */
BOARD_ISO7816_BASE_USART->US_THR = CharToSend;
status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME|
US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK|
(1<<10)));
if (status != 0 ) {
TRACE_DEBUG("E:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR);
TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER );
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA;
}
/* Return status */
return( status );
}
/**
* Iso 7816 ICC power on
*/
static void ISO7816_IccPowerOn( void )
{
/* Set RESET Master Card */
PIO_Set(&st_pinIso7816RstMC);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Iso 7816 ICC power off
*/
void ISO7816_IccPowerOff( void )
{
/* Clear RESET Master Card */
PIO_Clear(&st_pinIso7816RstMC);
}
/**
* Transfert Block TPDU T=0
* \param pAPDU APDU buffer
* \param pMessage Message buffer
* \param wLength Block length
* \return Message index
*/
uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU,
uint8_t *pMessage,
uint16_t wLength )
{
uint16_t NeNc;
uint16_t indexApdu = 4;
uint16_t indexMessage = 0;
uint8_t SW1 = 0;
uint8_t procByte;
uint8_t cmdCase;
uint8_t ins;
TRACE_DEBUG("pAPDU[0]=0x%X\n\r",pAPDU[0]);
TRACE_DEBUG("pAPDU[1]=0x%X\n\r",pAPDU[1]);
TRACE_DEBUG("pAPDU[2]=0x%X\n\r",pAPDU[2]);
TRACE_DEBUG("pAPDU[3]=0x%X\n\r",pAPDU[3]);
TRACE_DEBUG("pAPDU[4]=0x%X\n\r",pAPDU[4]);
TRACE_DEBUG("pAPDU[5]=0x%X\n\r",pAPDU[5]);
TRACE_DEBUG("wlength=%d\n\r",wLength);
ISO7816_SendChar( pAPDU[0] ); /* CLA */
ISO7816_SendChar( pAPDU[1] ); /* INS */
ISO7816_SendChar( pAPDU[2] ); /* P1 */
ISO7816_SendChar( pAPDU[3] ); /* P2 */
ISO7816_SendChar( pAPDU[4] ); /* P3 */
/* Handle the four structures of command APDU */
indexApdu = 4;
if( wLength == 4 ) {
cmdCase = CASE1;
NeNc = 0;
}
else if( wLength == 5) {
cmdCase = CASE2;
NeNc = pAPDU[4]; /* C5 */
if (NeNc == 0) {
NeNc = 256;
}
}
else if( wLength == 6) {
NeNc = pAPDU[4]; /* C5 */
cmdCase = CASE3;
}
else if( wLength == 7) {
NeNc = pAPDU[4]; /* C5 */
if( NeNc == 0 ) {
cmdCase = CASE2;
NeNc = (pAPDU[5]<<8)+pAPDU[6];
}
else {
cmdCase = CASE3;
}
}
else {
NeNc = pAPDU[4]; /* C5 */
if( NeNc == 0 ) {
cmdCase = CASE3;
NeNc = (pAPDU[5]<<8)+pAPDU[6];
}
else {
cmdCase = CASE3;
}
}
TRACE_DEBUG("CASE=0x%X NeNc=0x%X\n\r", cmdCase, NeNc);
/* Handle Procedure Bytes */
do {
ISO7816_GetChar(&procByte);
ins = procByte ^ 0xff;
/* Handle NULL */
if ( procByte == ISO_NULL_VAL ) {
TRACE_DEBUG("INS\n\r");
continue;
}
/* Handle SW1 */
else if ( ((procByte & 0xF0) ==0x60) || ((procByte & 0xF0) ==0x90) ) {
TRACE_DEBUG("SW1\n\r");
SW1 = 1;
}
/* Handle INS */
else if ( pAPDU[1] == procByte) {
TRACE_DEBUG("HdlINS\n\r");
if (cmdCase == CASE2) {
/* receive data from card */
do {
ISO7816_GetChar(&pMessage[indexMessage++]);
} while( 0 != --NeNc );
}
else {
/* Send data */
do {
ISO7816_SendChar(pAPDU[indexApdu++]);
} while( 0 != --NeNc );
}
}
/* Handle INS ^ 0xff */
else if ( pAPDU[1] == ins) {
TRACE_DEBUG("HdlINS+\n\r");
if (cmdCase == CASE2) {
/* receive data from card */
ISO7816_GetChar(&pMessage[indexMessage++]);
}
else {
ISO7816_SendChar(pAPDU[indexApdu++]);
}
NeNc--;
}
else {
/* ?? */
TRACE_DEBUG("procByte=0x%X\n\r", procByte);
break;
}
} while (NeNc != 0);
/* Status Bytes */
if (SW1 == 0) {
ISO7816_GetChar(&pMessage[indexMessage++]); /* SW1 */
}
else {
pMessage[indexMessage++] = procByte;
}
ISO7816_GetChar(&pMessage[indexMessage++]); /* SW2 */
return( indexMessage );
}
/**
* Escape ISO7816
*/
void ISO7816_Escape( void )
{
TRACE_DEBUG("For user, if needed\n\r");
}
/**
* Restart clock ISO7816
*/
void ISO7816_RestartClock( void )
{
TRACE_DEBUG("ISO7816_RestartClock\n\r");
BOARD_ISO7816_BASE_USART->US_BRGR = 13;
}
/**
* Stop clock ISO7816
*/
void ISO7816_StopClock( void )
{
TRACE_DEBUG("ISO7816_StopClock\n\r");
BOARD_ISO7816_BASE_USART->US_BRGR = 0;
}
/**
* T0 APDU
*/
void ISO7816_toAPDU( void )
{
TRACE_DEBUG("ISO7816_toAPDU\n\r");
TRACE_DEBUG("Not supported at this time\n\r");
}
/**
* Answer To Reset (ATR)
* \param pAtr ATR buffer
* \param pLength Pointer for store the ATR length
*/
void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength )
{
uint32_t i;
uint32_t j;
uint32_t y;
*pLength = 0;
/* Read ATR TS */
ISO7816_GetChar(&pAtr[0]);
/* Read ATR T0 */
ISO7816_GetChar(&pAtr[1]);
y = pAtr[1] & 0xF0;
i = 2;
/* Read ATR Ti */
while (y) {
if (y & 0x10) { /* TA[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x20) { /* TB[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x40) { /* TC[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x80) { /* TD[i] */
ISO7816_GetChar(&pAtr[i]);
y = pAtr[i++] & 0xF0;
}
else {
y = 0;
}
}
/* Historical Bytes */
y = pAtr[1] & 0x0F;
for( j=0; j < y; j++ ) {
ISO7816_GetChar(&pAtr[i++]);
}
*pLength = i;
}
/**
* Set data rate and clock frequency
* \param dwClockFrequency ICC clock frequency in KHz.
* \param dwDataRate ICC data rate in bpd
*/
void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate )
{
uint8_t ClockFrequency;
/* Define the baud rate divisor register */
/* CD = MCK / SCK */
/* SCK = FIDI x BAUD = 372 x 9600 */
/* BOARD_MCK */
/* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */
BOARD_ISO7816_BASE_USART->US_BRGR = maxMck / (dwClockFrequency*1000);
ClockFrequency = maxMck / BOARD_ISO7816_BASE_USART->US_BRGR;
BOARD_ISO7816_BASE_USART->US_FIDI = (ClockFrequency)/dwDataRate;
}
/**
* Pin status for ISO7816 RESET
* \return 1 if the Pin RstMC is high; otherwise 0.
*/
uint8_t ISO7816_StatusReset( void )
{
return PIO_Get(&st_pinIso7816RstMC);
}
/**
* cold reset
*/
void ISO7816_cold_reset( void )
{
volatile uint32_t i;
/* tb: wait 400 cycles*/
for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) {
}
BOARD_ISO7816_BASE_USART->US_RHR;
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
ISO7816_IccPowerOn();
}
/**
* Warm reset
*/
void ISO7816_warm_reset( void )
{
volatile uint32_t i;
ISO7816_IccPowerOff();
/* tb: wait 400 cycles */
for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) {
}
BOARD_ISO7816_BASE_USART->US_RHR;
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
ISO7816_IccPowerOn();
}
/**
* Decode ATR trace
* \param pAtr pointer on ATR buffer
*/
void ISO7816_Decode_ATR( uint8_t* pAtr )
{
uint32_t i;
uint32_t j;
uint32_t y;
uint8_t offset;
printf("\n\r");
printf("ATR: Answer To Reset:\n\r");
printf("TS = 0x%X Initial character ",pAtr[0]);
if( pAtr[0] == 0x3B ) {
printf("Direct Convention\n\r");
}
else {
if( pAtr[0] == 0x3F ) {
printf("Inverse Convention\n\r");
}
else {
printf("BAD Convention\n\r");
}
}
printf("T0 = 0x%X Format caracter\n\r",pAtr[1]);
printf(" Number of historical bytes: K = %d\n\r", pAtr[1]&0x0F);
printf(" Presence further interface byte:\n\r");
if( pAtr[1]&0x80 ) {
printf("TA ");
}
if( pAtr[1]&0x40 ) {
printf("TB ");
}
if( pAtr[1]&0x20 ) {
printf("TC ");
}
if( pAtr[1]&0x10 ) {
printf("TD ");
}
if( pAtr[1] != 0 ) {
printf(" present\n\r");
}
i = 2;
y = pAtr[1] & 0xF0;
/* Read ATR Ti */
offset = 1;
while (y) {
if (y & 0x10) { /* TA[i] */
printf("TA[%d] = 0x%X ", offset, pAtr[i]);
if( offset == 1 ) {
printf("FI = %d ", (pAtr[i]>>8));
printf("DI = %d", (pAtr[i]&0x0F));
}
printf("\n\r");
i++;
}
if (y & 0x20) { /* TB[i] */
printf("TB[%d] = 0x%X\n\r", offset, pAtr[i]);
i++;
}
if (y & 0x40) { /* TC[i] */
printf("TC[%d] = 0x%X ", offset, pAtr[i]);
if( offset == 1 ) {
printf("Extra Guard Time: N = %d", pAtr[i]);
}
printf("\n\r");
i++;
}
if (y & 0x80) { /* TD[i] */
printf("TD[%d] = 0x%X\n\r", offset, pAtr[i]);
y = pAtr[i++] & 0xF0;
}
else {
y = 0;
}
offset++;
}
/* Historical Bytes */
printf("Historical bytes:\n\r");
y = pAtr[1] & 0x0F;
for( j=0; j < y; j++ ) {
printf(" 0x%X", pAtr[i]);
if( (pAtr[i] > 0x21) && (pAtr[i] < 0x7D) ) { /* ASCII */
printf("(%c) ", pAtr[i]);
}
i++;
}
printf("\n\r\n\r");
}
/** Initializes a ISO driver
* \param pPinIso7816RstMC Pin ISO 7816 Rst MC
*/
void ISO7816_Init( const Pin pPinIso7816RstMC )
{
TRACE_DEBUG("ISO_Init\n\r");
/* Pin ISO7816 initialize */
st_pinIso7816RstMC = pPinIso7816RstMC;
USART_Configure( BOARD_ISO7816_BASE_USART,
US_MR_USART_MODE_IS07816_T_0
| US_MR_USCLKS_MCK
| US_MR_NBSTOP_1_BIT
| US_MR_PAR_EVEN
| US_MR_CHRL_8_BIT
| US_MR_CLKO
| (3<<24), /* MAX_ITERATION */
1,
0);
/* Configure USART */
//PMC_EnablePeripheral(BOARD_ISO7816_ID_USART);
maxMck = PMC_SetPeriMaxClock(BOARD_ISO7816_ID_USART, BOARD_MCK);
/* Disable interrupts */
BOARD_ISO7816_BASE_USART->US_IDR = (uint32_t) -1;
BOARD_ISO7816_BASE_USART->US_FIDI = 372; /* by default */
/* Define the baud rate divisor register */
/* CD = MCK / SCK */
/* SCK = FIDI x BAUD = 372 x 9600 */
/* BOARD_MCK */
/* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */
BOARD_ISO7816_BASE_USART->US_BRGR = maxMck / (372*9600);
/* Write the Timeguard Register */
BOARD_ISO7816_BASE_USART->US_TTGR = 5;
USART_SetTransmitterEnabled(BOARD_ISO7816_BASE_USART, 1);
USART_SetReceiverEnabled(BOARD_ISO7816_BASE_USART, 1);
}

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/lcd_draw.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup lcdd_draw
*
* Implementation of draw function on LCD, Include draw text, image
* and basic shapes (line, rectangle, circle).
*
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
#include <string.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Local variable
*----------------------------------------------------------------------------*/
/** Front color cache */
static uint32_t dwFrontColor;
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* Hide canvas layer
*/
static void _HideCanvas(void)
{
//LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 0);
}
/**
* Update canvas
*/
static void _ShowCanvas(void)
{
//LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 1);
}
/**
* Set front color
* \param dwColor Pixel color.
*/
static void _SetFrontColor(uint32_t dwColor)
{
dwFrontColor = dwColor;
}
/**
* \brief Draw a pixel on LCD of front color.
*
* \param dwX X-coordinate of pixel.
* \param dwY Y-coordinate of pixel.
*/
static void _DrawPixel( uint32_t dwX, uint32_t dwY )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint8_t* buffer = pDisp->pBuffer;
uint16_t w = pDisp->wImgW;
//uint16_t h = pDisp->wImgH;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
//uint8_t r, g, b;
uint8_t *pPix;
if (buffer == NULL)
return;
if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */
pPix = &buffer[dwY * rw + cw * dwX];
switch (pDisp->bMode)
{
case 16: /* TRGB 1555 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
break;
case 24: /* RGB 888 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
pPix[2] = (dwFrontColor >> 16) & 0xFF;
break;
case 32: /* ARGB 8888 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
pPix[2] = (dwFrontColor >> 16) & 0xFF;
pPix[3] = (dwFrontColor >> 24) & 0xFF;
break;
}
}
/**
* \brief Fill rectangle with front color.
* \param dwX1 X-coordinate of top left.
* \param dwY1 Y-coordinate of top left.
* \param dwX2 X-coordinate of bottom right.
* \param dwY1 Y-coordinate of bottom right.
*/
static void _FillRect( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint16_t w = pDisp->wImgW;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
uint8_t *base = pDisp->pBuffer;
uint8_t *buffer = pDisp->pBuffer;
uint32_t fillStart, fillEnd;
uint32_t i;
if (buffer == NULL) return;
/* 4-byte aligned rows */
if (rw & 0x3) rw = (rw | 0x3) + 1;
/* Buffer address for the starting row */
base = &buffer[dwY1*rw];
fillStart = dwX1 * cw;
fillEnd = dwX2 * cw;
#if 1 /* Memcopy pixel */
buffer = base;
for (; dwY1 <= dwY2; dwY1 ++)
{
for (i = fillStart; i <= fillEnd; i += cw)
{
memcpy(&buffer[i], &dwFrontColor, cw);
}
buffer = &buffer[rw];
}
#endif
#if 0 /* Pixel by pixel */
for (; dwY1 <= dwY2; dwY1 ++)
{
for (i = dwX1; i <= dwX2; i ++)
{
_DrawPixel(i, dwY1);
}
}
#endif
#if 0 /* Optimized */
/* First row */
for (i = fillStart; i <= fillEnd; i += cw)
{
memcpy(&base[i], &dwFrontColor, cw);
}
/* Next rows, copy first */
buffer = &base[rw + fillStart];
for (i = dwY1 + 1; i <= dwY2; i ++)
{
memcpy(buffer, &base[fillStart], fillEnd - fillStart + cw);
buffer = &buffer[rw];
}
#endif
}
/**
* \brief Draw a line on LCD, which is not horizontal or vertical.
*
* \param dwX1 X-coordinate of line start.
* \param dwY1 Y-coordinate of line start.
* \param dwX2 X-coordinate of line end.
* \param dwY2 Y-coordinate of line end.
*/
static uint32_t _DrawLineBresenham( uint32_t dwX1, uint32_t dwY1,
uint32_t dwX2, uint32_t dwY2 )
{
int dx, dy ;
int i ;
int xinc, yinc, cumul ;
int x, y ;
x = dwX1 ;
y = dwY1 ;
dx = dwX2 - dwX1 ;
dy = dwY2 - dwY1 ;
xinc = ( dx > 0 ) ? 1 : -1 ;
yinc = ( dy > 0 ) ? 1 : -1 ;
dx = ( dx > 0 ) ? dx : -dx ;
dy = ( dy > 0 ) ? dy : -dy ;
_DrawPixel( x, y ) ;
if ( dx > dy )
{
cumul = dx / 2 ;
for ( i = 1 ; i <= dx ; i++ )
{
x += xinc ;
cumul += dy ;
if ( cumul >= dx )
{
cumul -= dx ;
y += yinc ;
}
_DrawPixel( x, y ) ;
}
}
else
{
cumul = dy / 2 ;
for ( i = 1 ; i <= dy ; i++ )
{
y += yinc ;
cumul += dx ;
if ( cumul >= dy )
{
cumul -= dy ;
x += xinc ;
}
_DrawPixel( x, y ) ;
}
}
return 0 ;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Fills the given LCD buffer with a particular color.
*
* \param color Fill color.
*/
void LCDD_Fill( uint32_t dwColor )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect( 0, 0, pDisp->wImgW, pDisp->wImgH );
_ShowCanvas();
}
void LCDD_Fill0(void)
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
_HideCanvas();
_SetFrontColor(0xFF0000);
_FillRect( 0, 0, pDisp->wImgW/3, pDisp->wImgH );
_SetFrontColor(0x00FF00);
_FillRect( pDisp->wImgW/3, 0, pDisp->wImgW/3+pDisp->wImgW/3, pDisp->wImgH );
_SetFrontColor(0x0000FF);
_FillRect( pDisp->wImgW/3+pDisp->wImgW/3, 0, pDisp->wImgW, pDisp->wImgH );
_ShowCanvas();
}
/**
* \brief Draw a pixel on LCD of given color.
*
* \param x X-coordinate of pixel.
* \param y Y-coordinate of pixel.
* \param color Pixel color.
*/
extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t color )
{
_SetFrontColor(color);
_HideCanvas();
_DrawPixel(x, y);
_ShowCanvas();
}
/**
* \brief Read a pixel from LCD.
*
* \param x X-coordinate of pixel.
* \param y Y-coordinate of pixel.
*
* \return color Readed pixel color.
*/
extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint8_t* buffer = pDisp->pBuffer;
uint16_t w = pDisp->wImgW;
//uint16_t h = pDisp->wImgH;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
uint8_t *pPix;
uint32_t color = 0;
if (buffer == NULL) return 0;
if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */
pPix = &buffer[x * rw + cw * y];
switch (pDisp->bMode)
{
case 16: /* TRGB 1555 */
color = pPix[0] | (pPix[1] << 8);
break;
case 24: /* RGB 888 */
color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16);
break;
case 32: /* ARGB 8888 */
color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16) | (pPix[3] << 24);
break;
}
return color;
}
/**
* \brief Draw a line on LCD, horizontal and vertical line are supported.
*
* \param x1 X-coordinate of line start.
* \param y1 Y-coordinate of line start.
* \param x2 X-coordinate of line end.
* \param y2 Y-coordinate of line end.
* \param color Pixel color.
*/
extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color )
{
_SetFrontColor(color);
if ( (x1 == x2) || (y1 == y2) )
{
LCDD_DrawFilledRectangle(x1, y1, x2, y2, color);
}
else
{
_HideCanvas();
_DrawLineBresenham(x1, y1, x2, y2);
_ShowCanvas();
}
}
/**
* \brief Draws a rectangle on LCD, at the given coordinates.
*
* \param x X-coordinate of upper-left rectangle corner.
* \param y Y-coordinate of upper-left rectangle corner.
* \param width Rectangle width in pixels.
* \param height Rectangle height in pixels.
* \param color Rectangle color.
*/
extern void LCDD_DrawRectangle( uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t color )
{
uint32_t x1 = x + width - 1;
uint32_t y1 = y + height - 1;
_SetFrontColor(color);
_HideCanvas();
_FillRect(x , y , x1, y );
_FillRect(x1, y , x1, y1);
_FillRect(x , y , x , y1);
_FillRect(x , y1, x1, y1);
_ShowCanvas();
}
/**
* \brief Draws a rectangle with fill inside on LCD, at the given coordinates.
*
* \param dwX1 X-coordinate of upper-left rectangle corner.
* \param dwY1 Y-coordinate of upper-left rectangle corner.
* \param dwX2 X-coordinate of down-right rectangle corner.
* \param dwY2 Y-coordinate of down-right rectangle corner.
* \param color Rectangle color.
*/
extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1,
uint32_t dwX2, uint32_t dwY2,
uint32_t dwColor )
{
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect(dwX1, dwY1, dwX2, dwY2);
_ShowCanvas();
}
/**
* \brief Draws a circle on LCD, at the given coordinates.
*
* \param dwX X-coordinate of circle center.
* \param dwY Y-coordinate of circle center.
* \param dwR circle radius.
* \param dwColor circle color.
*/
extern void LCDD_DrawCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor )
{
int32_t d; /* Decision Variable */
uint32_t curX; /* Current X Value */
uint32_t curY; /* Current Y Value */
if (dwR == 0) return;
_SetFrontColor(dwColor);
d = 3 - (dwR << 1);
curX = 0;
curY = dwR;
_HideCanvas();
while (curX <= curY)
{
_DrawPixel(dwX + curX, dwY + curY);
_DrawPixel(dwX + curX, dwY - curY);
_DrawPixel(dwX - curX, dwY + curY);
_DrawPixel(dwX - curX, dwY - curY);
_DrawPixel(dwX + curY, dwY + curX);
_DrawPixel(dwX + curY, dwY - curX);
_DrawPixel(dwX - curY, dwY + curX);
_DrawPixel(dwX - curY, dwY - curX);
if (d < 0) {
d += (curX << 2) + 6;
}
else {
d += ((curX - curY) << 2) + 10;
curY--;
}
curX++;
}
_ShowCanvas();
}
/**
* \brief Draws a filled circle on LCD, at the given coordinates.
*
* \param dwX X-coordinate of circle center.
* \param dwY Y-coordinate of circle center.
* \param dwR circle radius.
* \param dwColor circle color.
*/
void LCDD_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor )
{
signed int d ; // Decision Variable
uint32_t dwCurX ; // Current X Value
uint32_t dwCurY ; // Current Y Value
uint32_t dwXmin, dwYmin;
if (dwR == 0) return;
_SetFrontColor(dwColor);
d = 3 - (dwR << 1) ;
dwCurX = 0 ;
dwCurY = dwR ;
_HideCanvas();
while ( dwCurX <= dwCurY )
{
dwXmin = (dwCurX > dwX) ? 0 : dwX-dwCurX;
dwYmin = (dwCurY > dwY) ? 0 : dwY-dwCurY;
_FillRect( dwXmin, dwYmin, dwX+dwCurX, dwYmin ) ;
_FillRect( dwXmin, dwY+dwCurY, dwX+dwCurX, dwY+dwCurY ) ;
dwXmin = (dwCurY > dwX) ? 0 : dwX-dwCurY;
dwYmin = (dwCurX > dwY) ? 0 : dwY-dwCurX;
_FillRect( dwXmin, dwYmin, dwX+dwCurY, dwYmin ) ;
_FillRect( dwXmin, dwY+dwCurX, dwX+dwCurY, dwY+dwCurX ) ;
if ( d < 0 )
{
d += (dwCurX << 2) + 6 ;
}
else
{
d += ((dwCurX - dwCurY) << 2) + 10;
dwCurY-- ;
}
dwCurX++ ;
}
_ShowCanvas();
}
/**
* \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks
* will be honored.
*
* \param x X-coordinate of string top-left corner.
* \param y Y-coordinate of string top-left corner.
* \param pString String to display.
* \param color String color.
*/
extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color )
{
uint32_t xorg = x;
while (*pString)
{
if (*pString == '\n')
{
y += gFont.height + 2; x = xorg;
}
else
{
LCDD_DrawChar(x, y, *pString, color);
x += gFont.width + 2;
}
pString ++;
}
}
/**
* \brief Draws a string inside a LCD buffer, at the given coordinates
* with given background color. Line breaks will be honored.
*
* \param x X-coordinate of string top-left corner.
* \param y Y-coordinate of string top-left corner.
* \param pString String to display.
* \param fontColor String color.
* \param bgColor Background color.
*/
extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor )
{
uint32_t xorg = x;
while (*pString)
{
if (*pString == '\n')
{
y += gFont.height + 2; x = xorg;
}
else
{
LCDD_DrawCharWithBGColor(x, y, *pString, fontColor, bgColor);
x += gFont.width + 2;
}
pString ++;
}
}
/**
* \brief Returns the width & height in pixels that a string will occupy on the screen
* if drawn using LCDD_DrawString.
*
* \param pString String.
* \param pWidth Pointer for storing the string width (optional).
* \param pHeight Pointer for storing the string height (optional).
*
* \return String width in pixels.
*/
extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight )
{
uint32_t width = 0;
uint32_t height = gFont.height;
while (*pString)
{
if (*pString == '\n') height += gFont.height + 2;
else width += gFont.height + 2;
pString ++;
}
if (width > 0) width -= 2;
if (pWidth) *pWidth = width;
if (pHeight)*pHeight = height;
}
/**
* \brief Draw a raw image at given position on LCD.
*
* \param x X-coordinate of image start.
* \param y Y-coordinate of image start.
* \param pImage Image buffer.
* \param width Image width.
* \param height Image height.
*/
void LCDD_DrawImage( uint32_t dwX, uint32_t dwY, const uint8_t *pImage, uint32_t dwWidth, uint32_t dwHeight )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = pDisp->wImgW * cw; /* Row width in bytes */
uint32_t rws = dwWidth * cw; /* Source Row Width */
uint32_t rl = (rw & 0x3) ? ((rw | 0x3) + 1) : rw; /* Aligned length*/
uint32_t rls = (rws & 0x3) ? ((rws | 0x3) + 1) : rws; /* Aligned length */
uint8_t *pSrc, *pDst;
uint32_t i;
pSrc = (uint8_t*)pImage;
pDst = pDisp->pBuffer;
pDst = &pDst[dwX*cw + dwY*rl];
for (i = 0; i < dwHeight; i ++)
{
memcpy(pDst, pSrc, rws);
pSrc = &pSrc[rls];
pDst = &pDst[rl];
}
}
/**
* \brief Clear a window with an color.
*
* \param dwX X-coordinate of the window.
* \param dwY Y-coordinate of the window.
* \param dwWidth window width.
* \param dwHeight window height.
* \param dwColor background color
*/
extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor )
{
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect(0, 0, dwX + dwWidth - 1, dwY + dwHeight - 1);
_ShowCanvas();
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file
*
* Implementation of draw font on LCD.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Global variable describing the font being instancied. */
const Font gFont = {10, 14};
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Draws an ASCII character on LCD.
*
* \param x X-coordinate of character upper-left corner.
* \param y Y-coordinate of character upper-left corner.
* \param c Character to output.
* \param color Character color.
*/
extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color )
{
uint32_t row, col ;
assert( (c >= 0x20) && (c <= 0x7F) ) ;
for ( col = 0 ; col < 10 ; col++ )
{
for ( row = 0 ; row < 8 ; row++ )
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row, color ) ;
}
}
for (row = 0; row < 6; row++ )
{
if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1)
{
LCDD_DrawPixel( x+col, y+row+8, color ) ;
}
}
}
}
/**
* \brief Draws an ASCII character on LCD with given background color.
*
* \param x X-coordinate of character upper-left corner.
* \param y Y-coordinate of character upper-left corner.
* \param c Character to output.
* \param fontColor Character color.
* \param bgColor Background color.
*/
extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor )
{
uint32_t row, col ;
assert( (c >= 0x20) && (c <= 0x7F) ) ;
for (col = 0; col < 10; col++)
{
for (row = 0 ; row < 8 ; row++)
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row, fontColor ) ;
}
else
{
LCDD_DrawPixel( x+col, y+row, bgColor ) ;
}
}
for ( row = 0 ; row < 6 ; row++ )
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row+8, fontColor ) ;
}
else
{
LCDD_DrawPixel( x+col, y+row+8, bgColor ) ;
}
}
}
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Font 10x14 table definition.
*
*/
/** \addtogroup font_10x14
*@{
*/
#include "board.h"
/** Char set of font 10x14 */
const uint8_t pCharset10x14[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,
0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,
0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,
0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,
0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,
0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,
0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,
0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,
0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,
0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,
0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,
0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,
0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,
0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,
0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,
0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,
0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,
0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,
0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,
0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,
0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,
0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,
0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,
0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,
0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,
0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,
0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,
0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,
0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,
0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,
0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,
0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,
0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,
0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,
0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,
0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,
0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,
0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,
0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,
0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,
0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,
0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,
0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,
0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,
0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,
0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,
0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,
0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,
0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,
0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,
0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,
0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,
0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,
0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,
0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,
0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,
0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,
0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,
0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,
0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,
0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,
0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,
0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,
0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,
0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,
0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,
0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,
0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,
0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,
0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,
0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,
0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,
0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,
0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,
0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,
0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,
0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,
0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,
0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,
0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,
0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,
0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,
0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC
} ;
/**@}*/

1590
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/lcdd.c Normal file
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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/led.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
#ifdef PINS_LEDS
static const Pin pinsLeds[] = { PINS_LEDS } ;
static const uint32_t numLeds = PIO_LISTSIZE( pinsLeds ) ;
#endif
/*------------------------------------------------------------------------------
* Global Functions
*------------------------------------------------------------------------------*/
/**
* Configures the pin associated with the given LED number. If the LED does
* not exist on the board, the function does nothing.
* \param led Number of the LED to configure.
* \return 1 if the LED exists and has been configured; otherwise 0.
*/
extern uint32_t LED_Configure( uint32_t dwLed )
{
#ifdef PINS_LEDS
// Check that LED exists
if ( dwLed >= numLeds)
{
return 0;
}
// Configure LED
return ( PIO_Configure( &pinsLeds[dwLed], 1 ) ) ;
#else
return 0 ;
#endif
}
/**
* Turns the given LED on if it exists; otherwise does nothing.
* \param led Number of the LED to turn on.
* \return 1 if the LED has been turned on; 0 otherwise.
*/
extern uint32_t LED_Set( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Turn LED on */
if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}
/**
* Turns a LED off.
*
* \param led Number of the LED to turn off.
* \return 1 if the LED has been turned off; 0 otherwise.
*/
extern uint32_t LED_Clear( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Turn LED off */
if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}
/**
* Toggles the current state of a LED.
*
* \param led Number of the LED to toggle.
* \return 1 if the LED has been toggled; otherwise 0.
*/
extern uint32_t LED_Toggle( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Toggle LED */
if ( PIO_GetOutputDataStatus( &pinsLeds[dwLed] ) )
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}

97
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/math.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
/**
* Returns the minimum value between two integers.
*
* \param a First integer to compare.
* \param b Second integer to compare.
*/
extern uint32_t min( uint32_t dwA, uint32_t dwB )
{
if ( dwA < dwB )
{
return dwA ;
}
else
{
return dwB ;
}
}
/*------------------------------------------------------------------------------
* Returns the absolute value of an integer.
*
* \param value Integer value.
*
* \note Do not call this function "abs", problem with gcc !
*/
extern uint32_t absv( int32_t lValue )
{
if ( lValue < 0 )
{
return -lValue ;
}
else
{
return lValue ;
}
}
/*------------------------------------------------------------------------------
* Computes and returns x power of y.
*
* \param x Value.
* \param y Power.
*/
extern uint32_t power( uint32_t dwX, uint32_t dwY )
{
uint32_t dwResult = 1 ;
while ( dwY > 0 )
{
dwResult *= dwX ;
dwY-- ;
}
return dwResult ;
}

953
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/mcid_dma.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file
*
* Implement for SD/MMC low level commands.
*
* \sa \ref hsmci_module, \ref sdmmc_module
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include "libsdmmc.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local constants
*----------------------------------------------------------------------------*/
/** \addtorgoup mcid_defines
* @{*/
/** Enable MCI */
#define MCI_ENABLE(pMciHw) HSMCI_Enable(pMciHw)
/** Disable MCI */
#define MCI_DISABLE(pMciHw) HSMCI_Disable(pMciHw)
/** Reset MCI */
#define MCI_RESET(pMciHw) HSMCI_Reset(pMciHw, 0)
/** Return halfword(16-bit) count from byte count */
#define toHWCOUNT(byteCnt) (((byteCnt)&0x1) ? (((byteCnt)/2)+1) : ((byteCnt)/2))
/** Return word(32-bit) count from byte count */
#define toWCOUNT(byteCnt) (((byteCnt)&0x3) ? (((byteCnt)/4)+1) : ((byteCnt)/4))
/** Bit mask for status register errors. */
#define STATUS_ERRORS ((uint32_t)(HSMCI_SR_UNRE \
| HSMCI_SR_OVRE \
| HSMCI_SR_ACKRCVE \
| HSMCI_SR_CSTOE \
| HSMCI_SR_DTOE \
| HSMCI_SR_DCRCE \
| HSMCI_SR_RTOE \
| HSMCI_SR_RENDE \
| HSMCI_SR_RCRCE \
| HSMCI_SR_RDIRE \
| HSMCI_SR_RINDE))
/** Bit mask for response errors */
#define STATUS_ERRORS_RESP ((uint32_t)(HSMCI_SR_CSTOE \
| HSMCI_SR_RTOE \
| HSMCI_SR_RENDE \
| HSMCI_SR_RCRCE \
| HSMCI_SR_RDIRE \
| HSMCI_SR_RINDE))
/** Bit mask for data errors */
#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \
| HSMCI_SR_OVRE \
| HSMCI_SR_DTOE \
| HSMCI_SR_DCRCE))
/** Max DMA size in a single transfer */
#define MAX_DMA_SIZE (XDMAC_MAX_BT_SIZE & 0xFFFFFF00)
/** SD/MMC memory Single block */
#define _CMDR_SDMEM_SINGLE \
(HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_SINGLE)
/** SD/MMC memory Multi block */
#define _CMDR_SDMEM_MULTI \
(HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_MULTIPLE)
/** SDIO byte transfer */
#define _CMDR_SDIO_BYTE \
(HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BYTE)
/** SDIO block transfer */
#define _CMDR_SDIO_BLOCK \
(HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BLOCK)
/** @}*/
/*---------------------------------------------------------------------------
* Local types
*---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Local variable
*----------------------------------------------------------------------------*/
//#define MCID_DBG 0
//static uint8_t bMcidDBG = 0;
/** HAL for SD/MMC bus mode (MCI interface) */
static sSdHalFunctions sdHal = {
(fSdmmcLock)MCID_Lock,
(fSdmmcRelease)MCID_Release,
(fSdmmcSendCommand)MCID_SendCmd,
(fSdmmcIOCtrl)MCID_IOCtrl
};
/*---------------------------------------------------------------------------
* Internal functions
*---------------------------------------------------------------------------*/
/** \addtogroup mcid_functions
*@{
*/
/**
* Enable MCI peripheral access clock
*/
static uint8_t _PeripheralEnable(uint32_t id)
{
if (PMC_IsPeriphEnabled(id)) return 0;
PMC_EnablePeripheral(id);
return 1;
}
/**
* HSMCI DMA R/W prepare
*/
static uint32_t _MciDMAPrepare(sMcid *pMcid, uint8_t bRd)
{
sXdmad *pXdmad = pMcid->pXdmad;
/* Allocate a channel */
if (bRd){
pMcid->dwDmaCh = XDMAD_AllocateChannel(pXdmad, pMcid->bID, XDMAD_TRANSFER_MEMORY);
}
else {
pMcid->dwDmaCh = XDMAD_AllocateChannel(pXdmad, XDMAD_TRANSFER_MEMORY, pMcid->bID);
}
if (pMcid->dwDmaCh == XDMAD_ALLOC_FAILED)
{
return SDMMC_ERROR_BUSY;
}
XDMAD_SetCallback(pXdmad, pMcid->dwDmaCh, NULL, NULL);
XDMAD_PrepareChannel( pXdmad, pMcid->dwDmaCh );
return SDMMC_SUCCESS;
}
/**
* HSMCI DMA R/W
* \return 1 if DMA started.
*/
/* Linked lists for multi transfer buffer chaining structure instance. */
#if defined ( __ICCARM__ ) /* IAR Ewarm */
#pragma location = "region_dma_nocache"
#elif defined ( __GNUC__ ) /* GCC CS3 */
__attribute__((__section__(".region_dma_nocache")))
#endif
static LinkedListDescriporView1 dmaLinkList[256];
static uint32_t _MciDMA(sMcid *pMcid, uint32_t bFByte, uint8_t bRd)
{
Hsmci *pHw = pMcid->pMciHw;
sXdmad *pXdmad = pMcid->pXdmad;
sSdmmcCommand *pCmd = pMcid->pCmd;
sXdmadCfg xdmadRxCfg,xdmadTxCfg;
uint32_t xdmaCndc;
uint32_t hsmciId;
uint8_t i;
uint32_t totalSize = pCmd->wNbBlocks * pCmd->wBlockSize;
uint32_t maxXSize;
uint32_t memAddress;
uint8_t bMByte;
if (pMcid->dwXfrNdx >= totalSize) return 0;
/* Prepare DMA transfer */
if(pCmd->wBlockSize != 1){
pMcid->dwXSize = totalSize - pMcid->dwXfrNdx;
hsmciId = ((unsigned int)pHw == (unsigned int)HSMCI0 )? ID_HSMCI0: ID_HSMCI1;
if (bRd){
//printf("_MciDMA read %d,%d \n\r",pCmd->wBlockSize, pCmd->bCmd );
for ( i = 0; i < pCmd->wNbBlocks; i++){
dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
| (( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)
| XDMA_UBC_NDEN_UPDATED
| pCmd->wBlockSize /4 ;
dmaLinkList[i].mbr_sa = (uint32_t)&(pHw->HSMCI_FIFO[i]);
dmaLinkList[i].mbr_da = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize];
if ( i == pCmd->wNbBlocks - 1)
dmaLinkList[i].mbr_nda = 0;
else
dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ];
}
xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
| XDMAC_CC_MBSIZE_SINGLE
| XDMAC_CC_DSYNC_PER2MEM
| XDMAC_CC_CSIZE_CHK_1
| XDMAC_CC_DWIDTH_WORD
| XDMAC_CC_SIF_AHB_IF1
| XDMAC_CC_DIF_AHB_IF0
| XDMAC_CC_SAM_FIXED_AM
| XDMAC_CC_DAM_INCREMENTED_AM
| XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( 0, hsmciId, XDMAD_TRANSFER_RX ));
xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
| XDMAC_CNDC_NDE_DSCR_FETCH_EN
| XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
| XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;
if (XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadRxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0])) {
return 0;
}
if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) {
return 0;
}
//Write
} else {
//printf("_MciDMA write %d,%d \n\r",pCmd->wBlockSize, pCmd->bCmd );
for ( i = 0; i < pCmd->wNbBlocks; i++){
dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
|(( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)
| XDMA_UBC_NDEN_UPDATED
| pCmd->wBlockSize /4 ;
dmaLinkList[i].mbr_sa = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize];
dmaLinkList[i].mbr_da = (uint32_t)&(pHw->HSMCI_FIFO[i]);
if ( i == pCmd->wNbBlocks - 1) dmaLinkList[i].mbr_nda = 0;
else dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ];
}
xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
| XDMAC_CC_MBSIZE_SINGLE
| XDMAC_CC_DSYNC_MEM2PER
| XDMAC_CC_CSIZE_CHK_1
| XDMAC_CC_DWIDTH_WORD
| XDMAC_CC_SIF_AHB_IF0
| XDMAC_CC_DIF_AHB_IF1
| XDMAC_CC_SAM_INCREMENTED_AM
| XDMAC_CC_DAM_FIXED_AM
| XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( 0, hsmciId, XDMAD_TRANSFER_TX ));
xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
| XDMAC_CNDC_NDE_DSCR_FETCH_EN
| XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
| XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;
if(XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadTxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0])){
return 0;
}
if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) {
return 0;
}
}
} else {
/* Memory address and alignment */
memAddress = (uint32_t)&pCmd->pData[pMcid->dwXfrNdx];
bMByte = bFByte ? 1 : (((memAddress & 0x3) || (totalSize & 0x3)));
/* P to M: Max size is P size */
if (bRd)
{
maxXSize = bFByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4);
}
/* M to P: Max size is M size */
else
{
maxXSize = bMByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4);
}
/* Update index */
pMcid->dwXSize = totalSize - pMcid->dwXfrNdx;
if (pMcid->dwXSize > maxXSize)
{
pMcid->dwXSize = maxXSize;
}
/* Prepare DMA transfer */
if (bRd)
{
xdmadRxCfg.mbr_ubc = bFByte ? pMcid->dwXSize : toWCOUNT(pMcid->dwXSize);
xdmadRxCfg.mbr_sa = (uint32_t)&(pHw->HSMCI_RDR);
xdmadRxCfg.mbr_da = (uint32_t)memAddress;
xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MEMSET_NORMAL_MODE |
XDMAC_CC_DSYNC_PER2MEM|
XDMAC_CC_CSIZE_CHK_1 |
(bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) |
XDMAC_CC_SIF_AHB_IF1 |
XDMAC_CC_DIF_AHB_IF0 |
XDMAC_CC_SAM_FIXED_AM |
XDMAC_CC_DAM_INCREMENTED_AM;
xdmadRxCfg.mbr_bc = 0;
XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadRxCfg, 0, 0);
//CP15_coherent_dcache_for_dma ((uint32_t)memAddress, ((uint32_t)memAddress + (pMcid->dwXSize)));
}
else
{
xdmadTxCfg.mbr_ubc = toWCOUNT(pMcid->dwXSize);
xdmadTxCfg.mbr_sa = (uint32_t)memAddress;
xdmadTxCfg.mbr_da = (uint32_t)&(pHw->HSMCI_TDR);
xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MEMSET_NORMAL_MODE |
XDMAC_CC_DSYNC_MEM2PER |
XDMAC_CC_CSIZE_CHK_1 |
(bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) |
XDMAC_CC_SIF_AHB_IF0 |
XDMAC_CC_DIF_AHB_IF1 |
XDMAC_CC_SAM_INCREMENTED_AM |
XDMAC_CC_DAM_FIXED_AM;
xdmadTxCfg.mbr_bc = 0;
XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadTxCfg, 0, 0);
}
XDMAD_StartTransfer(pXdmad, pMcid->dwDmaCh);
}
return 1;
}
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* Reset MCI HW interface and disable it.
* \param keepSettings Keep old register settings, including
* _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG.
*/
static void MCI_Reset(sMcid *pMci, uint8_t keepSettings)
{
Hsmci *pMciHw = pMci->pMciHw;
assert(pMci);
assert(pMci->pMciHw);
HSMCI_Reset( pMciHw, keepSettings );
}
/**
* Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is
* MCK/2 and corresponds to CLKDIV = 0
* \param pMci Pointer to the low level MCI driver.
* \param mciSpeed MCI clock speed in Hz, 0 will not change current speed.
* \param mck MCK to generate MCI Clock, in Hz
* \return The actual speed used, 0 for fail.
*/
static uint32_t MCI_SetSpeed( sMcid* pMci, uint32_t mciSpeed, uint32_t mck )
{
Hsmci *pMciHw = pMci->pMciHw;
uint32_t clkdiv;
assert(pMci);
assert(pMciHw);
if((mck % mciSpeed) == 0)
{
clkdiv = mck /mciSpeed;
}
else
{
clkdiv = ((mck + mciSpeed)/mciSpeed);
}
mciSpeed = mck / clkdiv;
/* Modify MR */
HSMCI_DivCtrl( pMciHw, clkdiv, 0x7);
return (mciSpeed);
}
/**
*/
static void _FinishCmd( sMcid* pMcid, uint8_t bStatus )
{
sSdmmcCommand *pCmd = pMcid->pCmd;
sXdmad *pXdmad = pMcid->pXdmad;
//uint32_t memAddress;
/* Release DMA channel (if used) */
if (pMcid->dwDmaCh != XDMAD_ALLOC_FAILED)
{
if (XDMAD_FreeChannel(pXdmad, pMcid->dwDmaCh)) printf("-E- Can't free channel \n\r");
pMcid->dwDmaCh = XDMAD_ALLOC_FAILED;
}
/* Release command */
pMcid->pCmd = NULL;
pMcid->bState = MCID_LOCKED;
pCmd->bStatus = bStatus;
/* Invoke callback */
if (pCmd->fCallback)
{
(pCmd->fCallback)(pCmd->bStatus, pCmd->pArg);
}
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* Select MCI slot.
*/
void MCID_SetSlot(Hsmci *pMci, uint8_t slot)
{
HSMCI_SetSlot(pMci, slot);
}
/**
* Initialize MCI driver.
*/
void MCID_Init(sMcid *pMcid,
Hsmci *pMci, uint8_t bID, uint32_t dwMck,
sXdmad *pXdmad,
uint8_t bPolling)
{
uint16_t clkDiv;
assert(pMcid);
assert(pMci);
/* Initialize driver struct */
pMcid->pMciHw = pMci;
pMcid->pCmd = NULL;
pMcid->pXdmad = pXdmad;
pMcid->dwDmaCh = XDMAD_ALLOC_FAILED;
pMcid->dwXfrNdx = 0;
pMcid->dwMck = dwMck;
pMcid->bID = bID;
pMcid->bPolling = bPolling;
pMcid->bState = MCID_IDLE;
_PeripheralEnable( bID );
MCI_RESET( pMci );
MCI_DISABLE ( pMci );
HSMCI_DisableIt( pMci, 0xFFFFFFFF );
HSMCI_ConfigureDataTO( pMci, HSMCI_DTOR_DTOCYC(0xFF)
|HSMCI_DTOR_DTOMUL_1048576 );
HSMCI_ConfigureCompletionTO( pMci , HSMCI_CSTOR_CSTOCYC(0xFF)
|HSMCI_CSTOR_CSTOMUL_1048576 );
/* Set the Mode Register: 400KHz */
clkDiv = (dwMck / (MCI_INITIAL_SPEED << 1)) - 1;
HSMCI_ConfigureMode( pMci, (clkDiv | HSMCI_MR_PWSDIV(0x7)) );
HSMCI_Enable( pMci );
HSMCI_Configure( pMci, HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL );
/* Enable DMA */
HSMCI_EnableDma( pMci, 1 );
//_PeripheralDisable( bID );
}
/**
* Lock the MCI driver for slot N access
*/
uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot)
{
Hsmci *pHw = pMcid->pMciHw;
uint32_t sdcr;
assert(pMcid);
assert(pMcid->pMciHw);
if (bSlot > 0)
{
return SDMMC_ERROR_PARAM;
}
if (pMcid->bState >= MCID_LOCKED)
{
return SDMMC_ERROR_LOCKED;
}
pMcid->bState = MCID_LOCKED;
sdcr = pHw->HSMCI_SDCR & ~(uint32_t)HSMCI_SDCR_SDCSEL_Msk;
pHw->HSMCI_SDCR = sdcr | (bSlot << HSMCI_SDCR_SDCSEL_Pos);
return SDMMC_OK;
}
/**
* Release the driver.
*/
uint32_t MCID_Release(sMcid *pMcid)
{
assert(pMcid);
if (pMcid->bState >= MCID_CMD)
{
return SDMMC_ERROR_BUSY;
}
pMcid->bState = MCID_IDLE;
return SDMMC_OK;
}
/**
* SD/MMC command.
*/
uint32_t MCID_SendCmd(sMcid *pMcid, void *pCommand)
{
Hsmci *pHw = pMcid->pMciHw;
sSdmmcCommand *pCmd = pCommand;
uint32_t mr, ier;
uint32_t cmdr;
assert(pMcid);
assert(pMcid->pMciHw);
assert(pCmd);
//printf("cmd = %d \n\r",pCmd->bCmd);
if (!MCID_IsCmdCompleted(pMcid))
{
return SDMMC_ERROR_BUSY;
}
pMcid->bState = MCID_CMD;
pMcid->pCmd = pCmd;
//_PeripheralEnable(pMcid->bID);
MCI_DISABLE(pHw);
mr = HSMCI_GetMode(pHw) & (~(uint32_t)(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF |HSMCI_MR_FBYTE));
/* Special: PowerON Init */
if (pCmd->cmdOp.wVal == SDMMC_CMD_POWERONINIT){
HSMCI_ConfigureMode(pHw, mr);
ier = HSMCI_IER_XFRDONE;
}
/* Normal command: idle the bus */
else if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR)
{
HSMCI_ConfigureMode(pHw, mr);
ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP;
}
/* No data transfer */
else if ((pCmd->cmdOp.wVal & SDMMC_CMD_CNODATA(0xF)) == SDMMC_CMD_CNODATA(0))
{
ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP;
/* R3 response, no CRC */
if (pCmd->cmdOp.bmBits.respType == 3)
{
ier &= ~(uint32_t)HSMCI_IER_RCRCE;
}
}
/* Data command but no following */
else if (pCmd->wNbBlocks == 0 || pCmd->pData == 0)
{
HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF
| HSMCI_MR_RDPROOF);
HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks);
ier = HSMCI_IER_CMDRDY | STATUS_ERRORS_RESP;
}
/* Command with data */
else
{
/* Setup block size */
if (pCmd->cmdOp.bmBits.sendCmd)
{
HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks);
}
/* Block size is 0, force byte */
if (pCmd->wBlockSize == 0)
pCmd->wBlockSize = 1;
/* Force byte transfer */
if (pCmd->wBlockSize & 0x3)
{
mr |= HSMCI_MR_FBYTE;
}
/* Set block size & MR */
HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF
| HSMCI_MR_RDPROOF
| (pCmd->wBlockSize << 16));
/* DMA write */
if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX)
{
if (_MciDMAPrepare(pMcid, 0))
{
_FinishCmd(pMcid, SDMMC_ERROR_BUSY);
return SDMMC_ERROR_BUSY;
}
_MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),0);
ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA;
if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY;
}
else
{
if (_MciDMAPrepare(pMcid, 1))
{
_FinishCmd(pMcid, SDMMC_ERROR_BUSY);
return SDMMC_ERROR_BUSY;
}
_MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),1);
ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA;
if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY;
}
}
MCI_ENABLE(pHw);
if (pCmd->cmdOp.wVal & (SDMMC_CMD_bmPOWERON | SDMMC_CMD_bmCOMMAND))
{
cmdr = pCmd->bCmd;
if (pCmd->cmdOp.bmBits.powerON)
{
cmdr |= (HSMCI_CMDR_OPDCMD | HSMCI_CMDR_SPCMD_INIT);
}
if (pCmd->cmdOp.bmBits.odON)
{
cmdr |= HSMCI_CMDR_OPDCMD;
}
if (pCmd->cmdOp.bmBits.sendCmd)
{
cmdr |= HSMCI_CMDR_MAXLAT;
}
switch(pCmd->cmdOp.bmBits.xfrData)
{
case SDMMC_CMD_TX:
if (pCmd->cmdOp.bmBits.ioCmd)
{
cmdr |= (pCmd->wBlockSize == 1) ?
_CMDR_SDIO_BYTE :
_CMDR_SDIO_BLOCK;
}
else
{
cmdr |= (pCmd->wNbBlocks == 1) ?
_CMDR_SDMEM_SINGLE :
_CMDR_SDMEM_MULTI;
}
break;
case SDMMC_CMD_RX:
if (pCmd->cmdOp.bmBits.ioCmd)
{
cmdr |= HSMCI_CMDR_TRDIR_READ
|((pCmd->wBlockSize == 1) ?
_CMDR_SDIO_BYTE :
_CMDR_SDIO_BLOCK)
;
}
else
{
cmdr |= HSMCI_CMDR_TRDIR_READ
|((pCmd->wNbBlocks == 1) ?
_CMDR_SDMEM_SINGLE :
_CMDR_SDMEM_MULTI)
;
}
break;
case SDMMC_CMD_STOPXFR:
cmdr |= HSMCI_CMDR_TRCMD_STOP_DATA;
break;
}
switch(pCmd->cmdOp.bmBits.respType)
{
case 3: case 4:
/* ignore CRC error */
ier &= ~(uint32_t)HSMCI_IER_RCRCE;
case 1: case 5: case 6: case 7:
cmdr |= HSMCI_CMDR_RSPTYP_48_BIT;
break;
case 2:
cmdr |= HSMCI_CMDR_RSPTYP_136_BIT;
break;
/* No response, ignore RTOE */
default:
ier &= ~(uint32_t)HSMCI_IER_RTOE;
}
pHw->HSMCI_ARGR = pCmd->dwArg;
pHw->HSMCI_CMDR = cmdr;
}
/* Ignore CRC error for R3 & R4 */
if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR)
{
ier &= ~STATUS_ERRORS_DATA;
}
/* Enable status flags */
HSMCI_EnableIt(pHw, ier);
return SDMMC_OK;
}
static uint32_t dwMsk;
/**
* Process pending events on the given MCI driver.
*/
void MCID_Handler(sMcid *pMcid)
{
Hsmci *pHw = pMcid->pMciHw;
sSdmmcCommand *pCmd = pMcid->pCmd;
//uint32_t dwSr, dwMsk, dwMaskedSr;
uint32_t dwSr, dwMaskedSr;
assert(pMcid);
assert(pMcid->pMciHw);
/* Do nothing if no pending command */
if (pCmd == NULL)
{
if (pMcid->bState >= MCID_CMD)
{
pMcid->bState = MCID_LOCKED;
}
return;
}
/* Read status */
dwSr = HSMCI_GetStatus(pHw);
dwMsk = HSMCI_GetItMask(pHw);
dwMaskedSr = dwSr & dwMsk;
/* Check errors */
if (dwMaskedSr & STATUS_ERRORS)
{
if (dwMaskedSr & HSMCI_SR_RTOE)
{
pCmd->bStatus = SDMMC_ERROR_NORESPONSE;
}
if (pCmd->bCmd != 12) pMcid->bState = MCID_ERROR;
//pMcid->bState = MCID_ERROR;
}
dwMsk &= ~STATUS_ERRORS;
/* Check command complete */
if (dwMaskedSr & HSMCI_SR_CMDRDY)
{
//printf("HSMCI_SR_CMDRDY \n\r");
HSMCI_DisableIt(pHw, HSMCI_IDR_CMDRDY);
dwMsk &= ~(uint32_t)HSMCI_IMR_CMDRDY;
}
/* Check if not busy */
if (dwMaskedSr & HSMCI_SR_NOTBUSY)
{
//printf("NOTBUSY ");
HSMCI_DisableIt(pHw, HSMCI_IDR_NOTBUSY);
dwMsk &= ~(uint32_t)HSMCI_IMR_NOTBUSY;
}
/* Check if TX ready */
if (dwMaskedSr & HSMCI_SR_TXRDY)
{
// printf("TXRDY ");
dwMsk &= ~(uint32_t)HSMCI_IMR_TXRDY;
}
/* Check if FIFO empty (all data sent) */
if (dwMaskedSr & HSMCI_SR_FIFOEMPTY)
{
/* Disable FIFO empty */
HSMCI_DisableIt(pHw, HSMCI_IDR_FIFOEMPTY);
dwMsk &= ~(uint32_t)HSMCI_IMR_FIFOEMPTY;
//printf("FIFOEMPTY %x \n\r",dwMsk);
}
/* Check if DMA finished */
if (dwMaskedSr & HSMCI_SR_XFRDONE)
{
HSMCI_DisableIt(pHw, HSMCI_IDR_XFRDONE);
dwMsk &= ~(uint32_t)HSMCI_IMR_XFRDONE;
//printf("HSMCI_SR_XFRDONE %x \n\r",dwMsk);
}
/* All none error mask done, complete the command */
if (0 == dwMsk || pMcid->bState == MCID_ERROR)
{
/* Error reset */
if (pMcid->bState == MCID_ERROR)
{
MCI_Reset(pMcid, 1);
}
else
{
pCmd->bStatus = SDMMC_SUCCESS;
if (pCmd->pResp)
{
uint8_t bRspSize, i;
switch(pCmd->cmdOp.bmBits.respType)
{
case 1: case 3: case 4: case 5: case 6: case 7:
bRspSize = 1;
break;
case 2:
bRspSize = 4;
break;
default:
bRspSize = 0;
}
for (i = 0; i < bRspSize; i ++)
{
pCmd->pResp[i] = HSMCI_GetResponse(pHw);
}
}
}
/* Disable interrupts */
HSMCI_DisableIt(pHw, HSMCI_GetItMask(pHw));
/* Disable peripheral */
//_PeripheralDisable(pMcid->bID);
/* Command is finished */
_FinishCmd(pMcid, pCmd->bStatus);
}
}
/**
* Cancel pending SD/MMC command.
*/
uint32_t MCID_CancelCmd(sMcid *pMcid)
{
if (pMcid->bState == MCID_IDLE)
{
return SDMMC_ERROR_STATE;
}
if (pMcid->bState == MCID_CMD)
{
/* Cancel ... */
MCI_Reset(pMcid, 1);
/* Command is finished */
_FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL);
}
return SDMMC_OK;
}
/**
* Reset MCID and disable HW
*/
void MCID_Reset(sMcid * pMcid)
{
Hsmci *pHw = pMcid->pMciHw;
MCID_CancelCmd(pMcid);
//_PeripheralEnable(pMcid->bID);
/* Disable */
MCI_DISABLE(pHw);
/* MR reset */
HSMCI_ConfigureMode(pHw, HSMCI_GetMode(pHw) & (HSMCI_MR_CLKDIV_Msk
| HSMCI_MR_PWSDIV_Msk));
/* BLKR reset */
HSMCI_ConfigureTransfer(pHw, 0, 0);
/* Cancel ... */
MCI_Reset(pMcid, 1);
//_PeripheralDisable(pMcid->bID);
if (pMcid->bState == MCID_CMD)
{
/* Command is finished */
_FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL);
}
}
/**
* Check if the command is finished
*/
uint32_t MCID_IsCmdCompleted(sMcid *pMcid)
{
sSdmmcCommand *pCmd = pMcid->pCmd;
if (pMcid->bPolling)
{
MCID_Handler(pMcid);
}
if (pMcid->bState == MCID_CMD)
{
return 0;
}
if (pCmd)
{
return 0;
}
return 1;
}
/**
* IO control functions
*/
uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param)
{
Hsmci *pMciHw = pMcid->pMciHw;
assert(pMcid);
assert(pMcid->pMciHw);
//mciDis = _PeripheralEnable(pMcid->bID);
switch (bCtl)
{
case SDMMC_IOCTL_BUSY_CHECK:
*(uint32_t*)param = !MCID_IsCmdCompleted(pMcid);
break;
case SDMMC_IOCTL_POWER:
return SDMMC_ERROR_NOT_SUPPORT;
case SDMMC_IOCTL_RESET:
MCID_Reset(pMcid);
return SDMMC_SUCCESS;
case SDMMC_IOCTL_CANCEL_CMD:
return MCID_CancelCmd(pMcid);
case SDMMC_IOCTL_SET_CLOCK:
*(uint32_t*)param = MCI_SetSpeed(pMcid,
*(uint32_t*)param,
pMcid->dwMck);
break;
case SDMMC_IOCTL_SET_HSMODE:
HSMCI_HsEnable( pMciHw, *(uint32_t*)param );
*(uint32_t*)param = HSMCI_IsHsEnabled( pMciHw );
break;
case SDMMC_IOCTL_SET_BUSMODE:
HSMCI_SetBusWidth( pMciHw, *(uint32_t*)param );
break;
case SDMMC_IOCTL_GET_BUSMODE:
//*(uint32_t*)param = 8; /* Max 4-bit bus */
break;
case SDMMC_IOCTL_GET_HSMODE:
*(uint32_t*)param = 1; /* Supported */
break;
default:
return SDMMC_ERROR_NOT_SUPPORT;
}
return SDMMC_OK;
}
/**
* Initialize the SD/MMC card driver struct for SD/MMC bus mode
* \note defined in SD/MMC bus mode low level (Here uses MCI interface)
*/
void SDD_InitializeSdmmcMode(sSdCard * pSd,void * pDrv,uint8_t bSlot)
{
SDD_Initialize(pSd, pDrv, bSlot, &sdHal);
}
/**@}*/

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** Slave address of OMNIVISION chips. */
#define OV_CAPTOR_ADDRESS_1 0x30
#define OV_CAPTOR_ADDRESS_2 0x21
#define OV_CAPTOR_ADDRESS_3 0x3c
#define OV_CAPTOR_ADDRESS_4 0x10
/** terminating list entry for register in configuration file */
#define OV_REG_TERM 0xFF
#define OV_REG_DELAY 0xFFFF
/** terminating list entry for value in configuration file */
#define OV_VAL_TERM 0xFF
static const Pin pin_ISI_RST= PIN_ISI_RST;
static uint8_t twiSlaveAddr = OV_CAPTOR_ADDRESS_1;
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
static void ov_reset(void)
{
volatile uint32_t i;
PIO_Configure(&pin_ISI_RST, 1);
PIO_Clear(&pin_ISI_RST);
for(i = 0; i < 6000; i++ );
PIO_Set(&pin_ISI_RST);
for(i = 0; i<6000; i++ );
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id8(Twid *pTwid)
{
uint8_t id, ver;
uint8_t status;
// OV_PID
status = ov_read_reg8(pTwid, 0x0A, &id);
if( status != 0 ) return 0;
TRACE_INFO("PID = 0x%X\n\r", id);
// OV_VER
status = ov_read_reg8(pTwid, 0x0B, &ver);
if( status != 0 ) return 0;
TRACE_INFO("VER = 0x%X\n\r", ver);
return((uint16_t)(id <<8) | ver);
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id16(Twid *pTwid)
{
uint8_t id, ver;
// OV_PID
ov_read_reg16(pTwid, 0x300A, &id);
TRACE_INFO("PID = 0x%X\n\r", id);
// OV_VER
ov_read_reg16(pTwid, 0x300B, &ver);
TRACE_INFO("VER = 0x%X\n\r", ver);
return((uint16_t)(id <<8) | ver);
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id(Twid *pTwid)
{
uint16_t id;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
twiSlaveAddr = OV_CAPTOR_ADDRESS_1;
id = ov_id8(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_2;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id8(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_3;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id16(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_4;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id16(pTwid);
}
}
}
return id;
}
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/**
* \brief Read a value from a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be read
* \param isize Internal address size in bytes.
* \param pData Data read
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData)
{
uint8_t status;
status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, &reg, 1, 0);
status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_read_reg pb\n\r");
}
return status;
}
/**
* \brief Read a value from a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be read
* \param pData Data read
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData)
{
uint8_t status;
uint8_t reg8[2];
reg8[0] = reg>>8;
reg8[1] = reg & 0xff;
status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, reg8, 2, 0);
status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_read_reg pb\n\r");
}
return status;
}
/**
* \brief Write a value to a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be writen
* \param pData Data written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val)
{
uint8_t status;
status = TWID_Write(pTwid, twiSlaveAddr, reg, 1, &val, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_write_reg pb\n\r");
}
return status;
}
/**
* \brief Write a value to a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be writen
* \param pData Data written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val)
{
uint8_t status;
status = TWID_Write(pTwid, twiSlaveAddr, reg, 2, &val, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_write_reg pb\n\r");
}
return status;
}
/**
* \brief Initialize a list of OV registers.
* The list of registers is terminated by the pair of values
* \param pTwid TWI interface
* \param pReglist Register list to be written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist)
{
uint32_t err;
uint32_t size=0;
const struct ov_reg *pNext = pReglist;
volatile uint32_t delay;
TRACE_DEBUG("ov_write_regs:");
while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {
err = ov_write_reg8(pTwid, pNext->reg, pNext->val);
size++;
for(delay=0;delay<=10000;delay++);
if (err == TWID_ERROR_BUSY){
TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");
return err;
}
//printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);
pNext++;
}
TRACE_DEBUG_WP("\n\r");
return 0;
}
/**
* \brief Initialize a list of OV registers.
* The list of registers is terminated by the pair of values
* \param pTwid TWI interface
* \param pReglist Register list to be written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist)
{
uint32_t err = 0;
uint32_t size = 0;
const struct ov_reg *pNext = pReglist;
volatile uint32_t delay;
TRACE_DEBUG("ov_write_regs:");
while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {
err = ov_write_reg16(pTwid, pNext->reg, pNext->val);
size++;
for(delay = 0;delay <= 10000; delay++);
if (err == TWID_ERROR_BUSY){
TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");
return err;
}
//printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);
pNext++;
}
TRACE_DEBUG_WP("\n\r");
return 0;
}
void isOV5640_AF_InitDone(Twid *pTwid)
{
uint8_t value = 0;
while(1){
ov_read_reg16(pTwid, 0x3029, &value);
if (value == 0x70) break;
}
}
/**
* \brief AF for OV 5640
* \param pTwid TWI interface
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_5640_AF_single(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 3);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AF_continue(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3024, 1);
ov_write_reg16(pTwid, 0x3022, 4);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AFPause(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 6);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AFrelease(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 8);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
/**
* \brief Dump all register
* \param pTwid TWI interface
*/
void ov_DumpRegisters8(Twid *pTwid)
{
uint32_t i;
uint8_t value;
TRACE_INFO_WP("Dump all camera register\n\r");
for(i = 0; i <= 0x5C; i++) {
value = 0;
ov_read_reg8(pTwid, i, &value);
TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);
if( ((i+1)%5) == 0 ) {
TRACE_INFO_WP("\n\r");
}
}
TRACE_INFO_WP("\n\r");
}
/**
* \brief Dump all register
* \param pTwid TWI interface
*/
void ov_DumpRegisters16(Twid *pTwid)
{
uint32_t i;
uint8_t value;
TRACE_INFO_WP("Dump all camera register\n\r");
for(i = 3000; i <= 0x305C; i++) {
value = 0;
ov_read_reg16(pTwid, i, &value);
TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);
if( ((i+1)%5) == 0 ) {
TRACE_INFO_WP("\n\r");
}
}
TRACE_INFO_WP("\n\r");
}
/**
* \brief Sequence For correct operation of the sensor
* \param pTwid TWI interface
* \return OV type
*/
uint8_t ov_init(Twid *pTwid)
{
uint16_t id = 0;
uint8_t ovType;
ov_reset();
id = ov_id(pTwid);
switch (id) {
case 0x7740: case 0x7742:
ovType = OV_7740;
break;
case 0x9740: case 0x9742:
ovType = OV_9740;
break;
case 0x2642: case 0x2640:
ovType = OV_2640;
break;
case 0x2643:
ovType = OV_2643;
break;
case 0x5640:
ovType = OV_5640;
break;
default:
ovType = OV_UNKNOWN;
TRACE_ERROR("Can not support product ID %x \n\r", id);
break;
}
return ovType;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
const static struct capture_size ov_sizes[] = {
// {width, height}
/// VGA
{ 320, 240 },
{ 640, 360 },
{ 640, 480 },
// SWVGA
{ 800, 600 },
/// SXGA
{1280, 960 },
{1280, 720 },
/// UXGA
{1600, 1200 },
};
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/**
* \brief Configure the OV for a specified image size, pixel format,
* and frame period.
*/
void ov_configure(Twid *pTwid, uint8_t ovType, uint32_t width, uint32_t heigth)
{
const struct ov_reg *reg_conf;
uint8_t goodCaptureSize = 0;
uint8_t i;
reg_conf = ov5640_yuv_vga;
TRACE_DEBUG("ovxxx_configure\n\r");
for( i = 0; i< sizeof(ov_sizes); i++ ) {
if( ov_sizes[i].width == width ) {
if( ov_sizes[i].height != heigth ) {
TRACE_INFO("ov configure vsize not define\n\r");
}
else {
goodCaptureSize = 1;
break;
}
}
}
if( goodCaptureSize == 0 ) {
TRACE_ERROR("Problem size\n\r");
while(1);
}
switch (ovType){
case OV_2640: {
// Default value
reg_conf = ov2640_yuv_qvga;
// common register initialization
switch(width) {
case 320: //VGA
printf("-I- QVGA 640 x 480\n\r");
reg_conf = ov2640_yuv_qvga;
break;
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov2640_yuv_vga;
break;
default:
TRACE_DEBUG("ov2640_configure problem\n\r");
break;
}
break;
}
case OV_7740: {
// Default value
reg_conf = ov7740_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov7740_yuv_vga;
break;
default:
TRACE_DEBUG("ov7740_configure problem\n\r");
break;
}
break;
}
case OV_9740: {
// Default value
reg_conf = ov9740_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 360\n\r");
reg_conf = ov9740_yuv_vga;
break;
case 1280: //VGA
printf("-I- VGA 1280 x 720\n\r");
reg_conf = ov9740_yuv_sxga;
break;
default:
TRACE_DEBUG("ov9740_configure problem\n\r");
break;
}
break;
}
case OV_2643: {
// Default value
reg_conf = ov2643_yuv_vga;
// common register initialization
switch(width) {
case 1600: //UXGA
printf("-I- UXGA 1600 x 1200 \n\r");
reg_conf = ov2643_yuv_uxga;
break;
case 800: //SWVGA
printf("-I- SWVGA 800 x 600\n\r");
reg_conf = ov2643_yuv_swvga;
break;
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov2643_yuv_vga;
break;
default:
TRACE_DEBUG("ov2643_configure problem\n\r");
break;
}
break;
}
case OV_5640: {
// Default value
reg_conf = ov5640_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov5640_yuv_vga;
break;
case 1280: //SXGA
printf("-I- SXGA 1280 x 720\n\r");
reg_conf = ov5640_yuv_sxga;
break;
default:
TRACE_DEBUG("ov5640_configure problem\n\r");
break;
}
break;
}
}
if ((ovType == OV_5640) || (ovType == OV_9740))
ov_write_regs16(pTwid, reg_conf);
else
ov_write_regs8(pTwid, reg_conf);
}
/**
* \brief Configure the OV 5640 afc fireware.
*/
void ov_5640Afc_Firmware(Twid *pTwid)
{
const struct ov_reg *reg_conf;
reg_conf = ov5640_afc;
ov_write_regs16(pTwid, reg_conf);
}

328
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
/* 320*240 */
const struct ov_reg ov2640_yuv_qvga[]= {
{0xff, 0x01},{0x12, 0x80},
{0xff, 0x00},{0x2c, 0xff},{0x2e, 0xdf},
{0xff, 0x01},{0x3c, 0x32},{0x11, 0x00},{0x09, 0x02},
{0x04, 0x28},{0x13, 0xe5},{0x14, 0x48},{0x2c, 0x0c},{0x33, 0x78},{0x3a, 0x33},{0x3b, 0xfb},{0x3e, 0x00},{0x43, 0x11},
{0x16, 0x10},{0x39, 0x02},{0x35, 0x88},{0x22, 0x0a},{0x37, 0x40},{0x23, 0x00},{0x34, 0xa0},{0x36, 0x1a},{0x06, 0x02},
{0x07, 0xc0},{0x0d, 0xb7},{0x0e, 0x01},{0x4c, 0x00},{0x4a, 0x81},{0x21, 0x99},{0x24, 0x3a},{0x25, 0x32},{0x26, 0x82},
{0x5c, 0x00},{0x63, 0x00},{0x5d, 0x55},{0x5e, 0x7d},{0x5f, 0x7d},{0x60, 0x55},{0x61, 0x70},{0x62, 0x80},{0x7c, 0x05},
{0x20, 0x80},{0x28, 0x30},{0x6c, 0x00},{0x6d, 0x80},{0x6e, 0x00},{0x70, 0x02},{0x71, 0x94},{0x73, 0xc1},{0x3d, 0x34},
{0x5a, 0x57},{0x4f, 0xbb},{0x50, 0x9c},
{0xff, 0x00},{0xe5, 0x7f},{0xf9, 0xc0},{0x41, 0x24},{0xe0, 0x14},{0x76, 0xff},
{0x33, 0xa0},{0x42, 0x20},{0x43, 0x18},{0x4c, 0x00},{0x87, 0xd0},{0x88, 0x3f},{0xd7, 0x03},{0xd9, 0x10},{0xd3, 0x82},
{0xc8, 0x08},{0xc9, 0x80},{0x7c, 0x00},{0x7d, 0x02},{0x7c, 0x03},{0x7d, 0x48},{0x7d, 0x48},{0x7c, 0x08},{0x7d, 0x20},
{0x7d, 0x10},{0x7d, 0x0e},{0x90, 0x00},{0x91, 0x0e},{0x91, 0x1a},{0x91, 0x31},{0x91, 0x5a},{0x91, 0x69},{0x91, 0x75},
{0x91, 0x7e},{0x91, 0x88},{0x91, 0x8f},{0x91, 0x96},{0x91, 0xa3},{0x91, 0xaf},{0x91, 0xc4},{0x91, 0xd7},{0x91, 0xe8},
{0x91, 0x20},{0x92, 0x00},{0x93, 0x06},{0x93, 0xe3},{0x93, 0x05},{0x93, 0x05},{0x93, 0x00},{0x93, 0x02},{0x93, 0x00},
{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x96, 0x00},{0x97, 0x08},{0x97, 0x19},
{0x97, 0x02},{0x97, 0x0c},{0x97, 0x24},{0x97, 0x30},{0x97, 0x28},{0x97, 0x26},{0x97, 0x02},{0x97, 0x98},{0x97, 0x80},
{0x97, 0x00},{0x97, 0x00},{0xc3, 0xed},{0xa4, 0x00},{0xa8, 0x00},{0xc5, 0x11},{0xc6, 0x51},{0xbf, 0x80},{0xc7, 0x10},
{0xb6, 0x66},{0xb8, 0xa5},{0xb7, 0x64},{0xb9, 0x7c},{0xb3, 0xaf},{0xb4, 0x97},{0xb5, 0xff},{0xb0, 0xc5},{0xb1, 0x94},
{0xb2, 0x0f},{0xc4, 0x5c},{0xc0, 0xc8},{0xc1, 0x96},{0x86, 0x1d},{0x50, 0x00},{0x51, 0x90},{0x52, 0x18},{0x53, 0x00},
{0x54, 0x00},{0x55, 0x88},{0x57, 0x00},{0x5a, 0x90},{0x5b, 0x18},{0x5c, 0x05},{0xc3, 0xed},{0x7f, 0x00},{0xda, 0x04},
{0xe5, 0x1f},{0xe1, 0x67},{0xe0, 0x00},{0xdd, 0xff},{0x05, 0x00},
{0xff, 0x01},{0x11, 0x01},
{0xff, 0x01},{0x12, 0x40},
{0x17, 0x11},{0x18, 0x43},{0x19, 0x00},{0x1a, 0x4b},{0x32, 0x09},{0x4f, 0xca},{0x50, 0xa8},{0x5a, 0x23},{0x6d, 0x00},
{0x3d, 0x38},{0x39, 0x12},{0x35, 0xda},{0x22, 0x1a},{0x37, 0xc3},{0x23, 0x00},{0x34, 0xc0},{0x36, 0x1a},{0x06, 0x88},
{0x07, 0xc0},{0x0d, 0x87},{0x0e, 0x41},{0x4c, 0x00},{0x48, 0x00},{0x5B, 0x00},{0x42, 0x03},
{0xff, 0x00},{0xe0, 0x04},
{0xc0, 0x64},{0xc1, 0x4B},{0x8c, 0x00},{0x86, 0x1D},{0xd3, 0x82},{0xe0, 0x00},
{0xff, 0x00},
{0xc0, 0x64},{0xc1, 0x4B},{0x8c, 0x00}, // Xiao: HSIZE 0x64*8 = 800, VSIZE 0x4b*8 = 600
{0x86, 0x3D},
{0x50, 0x89}, // LP_DP, V_DIV 1, H_DIV 1
{0x51, 0xC8},{0x52, 0x96},{0x53, 0x00},{0x54, 0x00},{0x55, 0x00}, // Xiao: HSIZE 0xC8(200)*4 = 800, VSIZE 0x96(150)*4 = 600
{0x5a, 0x50},{0x5b, 0x3C},{0x5c, 0x00}, // Xiao: ZMOW 0x50(80)*4 = 320, ZMOH 0x3C(60)*4 = 240
{0xd3, 0x04},
{0xFF, 0x00},{0xE0, 0x04},{0xE1, 0x67},{0xD7, 0x01},{0xDA, 0x00},{0xD3, 0x82},{0xE0, 0x00},
{0xFF, 0xFF}
};
const struct ov_reg ov2640_yuv_vga[]= {
{0xff, 0x01}, //dsp
{0x12, 0x80}, //reset
{0xff, 0x00}, //sensor
{0x2c, 0xff}, //?
{0x2e, 0xdf}, //ADDVSH, VSYNC msb=223
{0xff, 0x01}, //dsp
{0x3c, 0x32}, //?
{0x11, 0x00}, //clock rate off
{0x09, 0x02}, //2 capablity + standby mode
{0x04, 0x28}, //? ??????????????????????????????????
{0x13, 0xe5}, //
{0x14, 0x48}, //Auto agc
{0x2c, 0x0c}, //?
{0x33, 0x78}, //?
{0x3a, 0x33}, //?
{0x3b, 0xfb}, //?
{0x3e, 0x00}, //?
{0x43, 0x11}, //?
{0x16, 0x10}, //?
{0x39, 0x02}, //?
{0x35, 0x88}, //?
{0x22, 0x0a}, //?
{0x37, 0x40}, //?
{0x23, 0x00}, //?
{0x34, 0xa0}, //startpoint 0
{0x36, 0x1a}, //? XXXXXXXXXXXXXXXX
{0x06, 0x02}, //?
{0x07, 0xc0}, //?
{0x0d, 0xb7}, //?
{0x0e, 0x01}, //?
{0x4c, 0x00}, //?
{0x4a, 0x81}, //?
{0x21, 0x99}, //?
{0x24, 0x3a}, // Luminance high
{0x25, 0x32}, // Luminance low
//{0x24, 0x10}, // Luminance high
//{0x25, 0x03}, // Luminance low
{0x26, 0xF3}, // Fast mode large Step Range Threshold
{0x5c, 0x00}, //?
{0x63, 0x00}, //?
{0x5d, 0x55}, //zone
{0x5e, 0x7d}, //zone
{0x5f, 0x7d}, //zone
{0x60, 0x55}, //zone
{0x61, 0x70}, //Histogram low
{0x62, 0x80}, //Histogram high
{0x7c, 0x05}, //?
{0x20, 0x80}, //?
{0x28, 0x30}, //?
{0x6c, 0x00}, //?
{0x6d, 0x80}, //?
{0x6e, 0x00}, //?
{0x70, 0x02}, //?
{0x71, 0x94}, //?
{0x73, 0xc1}, //?
{0x3d, 0x34}, //?
{0x5a, 0x57}, //?
{0x4f, 0xbb}, //50Hz
{0x50, 0x9c}, //60Hz
{0xff, 0x00}, //dsp
{0xe5, 0x7f}, //?
{0xf9, 0xc0}, //MicroC reset,Boot
{0x41, 0x24}, //?
{0xe0, 0x14}, //JPEG,DVP reset
{0x76, 0xff}, //?
{0x33, 0xa0}, //?
{0x42, 0x20}, //?
{0x43, 0x18}, //?
{0x4c, 0x00}, //?
{0x87, 0xd0}, //Module Enable BPC+WPC 11010000
{0x88, 0x3f}, //?
{0xd7, 0x03}, //?
{0xd9, 0x10}, //?
{0xd3, 0x82}, //Auto mode
{0xc8, 0x08}, //?
{0xc9, 0x80}, //?
{0x7c, 0x00}, //SDE indirect register access: address
{0x7d, 0x02}, //SDE indirect register data
{0x7c, 0x03}, //
{0x7d, 0x48}, //
{0x7d, 0x48}, //
{0x7c, 0x08}, //
{0x7d, 0x20}, //
{0x7d, 0x10}, //
{0x7d, 0x0e}, //
{0x90, 0x00}, //?
{0x91, 0x0e}, //?
{0x91, 0x1a}, //?
{0x91, 0x31}, //?
{0x91, 0x5a}, //?
{0x91, 0x69}, //?
{0x91, 0x75}, //?
{0x91, 0x7e}, //?
{0x91, 0x88}, //?
{0x91, 0x8f}, //?
{0x91, 0x96}, //?
{0x91, 0xa3}, //?
{0x91, 0xaf}, //?
{0x91, 0xc4}, //?
{0x91, 0xd7}, //?
{0x91, 0xe8}, //?
{0x91, 0x20}, //?
{0x92, 0x00}, //?
{0x93, 0x06}, //?
{0x93, 0xe3}, //?
{0x93, 0x05}, //?
{0x93, 0x05}, //?
{0x93, 0x00}, //?
{0x93, 0x02}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x96, 0x00}, //?
{0x97, 0x08}, //?
{0x97, 0x19}, //?
{0x97, 0x02}, //?
{0x97, 0x0c}, //?
{0x97, 0x24}, //?
{0x97, 0x30}, //?
{0x97, 0x28}, //?
{0x97, 0x26}, //?
{0x97, 0x02}, //?
{0x97, 0x98}, //?
{0x97, 0x80}, //?
{0x97, 0x00}, //?
{0x97, 0x00}, //?
{0xc3, 0xed}, //Module enable
{0xa4, 0x00}, //?
{0xa8, 0x00}, //?
{0xc5, 0x11}, //?
{0xc6, 0x51}, //?
{0xbf, 0x80}, //?
{0xc7, 0x10}, //?
{0xb6, 0x66}, //?
{0xb8, 0xa5}, //?
{0xb7, 0x64}, //?
{0xb9, 0x7c}, //?
{0xb3, 0xaf}, //?
{0xb4, 0x97}, //?
{0xb5, 0xff}, //?
{0xb0, 0xc5}, //?
{0xb1, 0x94}, //?
{0xb2, 0x0f}, //?
{0xc4, 0x5c}, //?
{0xc0, 0xc8}, // HSIZE8[7:0] 1600
{0xc1, 0x96}, // VSIZE8[7:0] 1200
{0x86, 0x1d}, //Module enable
{0x50, 0x00}, //?
{0x51, 0x90}, //H_SIZE[7:0] (real/4) 1600
{0x52, 0x18}, //V_SIZE[7:0] (real/4) 1120
{0x53, 0x00}, //OFFSET_X[7:0]
{0x54, 0x00}, //OFFSET_Y[7:0]
{0x55, 0x88}, //V_SIZE[8]=1 H_SIZE[8]
{0x57, 0x00}, //?
{0x5a, 0x90}, //OUTW
{0x5b, 0x18}, //OUTH
{0x5c, 0x05}, //OUTW8 ,OUTH8
{0xc3, 0xed}, //
{0x7f, 0x00}, //?
{0xda, 0x04}, //Image output format select ------ RAW
{0xe5, 0x1f}, //?
{0xe1, 0x67}, //?
{0xe0, 0x00}, //Reset
{0xdd, 0xff}, //?
{0x05, 0x00}, //Bypass DSP no
{0xC2, 0x08 | 0x04 | 0x02 },
{0xff, 0x01}, //Sensor
{0x11, 0x01}, //?
{0xff, 0x01}, //Sensor
{0x12, 0x40}, //Preview mode
{0x17, 0x11}, //?
{0x18, 0x43}, //?
{0x19, 0x00}, //?
{0x1a, 0x4b}, //?
{0x32, 0x09}, //?
{0x4f, 0xca}, //?
{0x50, 0xa8}, //10 101 000 V_DIVDER = 5
{0x5a, 0x23}, // OUTW 23
{0x6d, 0x00}, //?
{0x3d, 0x38}, //?
{0x39, 0x12}, //?
{0x35, 0xda}, //?
{0x22, 0x1a}, //?
{0x37, 0xc3}, //?
{0x23, 0x00}, //?
{0x34, 0xc0}, //?
{0x36, 0x1a}, //?
{0x06, 0x88}, //?
{0x07, 0xc0}, //?
{0x0d, 0x87}, //?
{0x0e, 0x41}, //?
{0x4c, 0x00}, //?
{0x48, 0x00}, //?
{0x5B, 0x00}, //OUTH
{0x42, 0x03}, //?
{0xff, 0x00}, //DSP
{0xe0, 0x04}, //Reset DVP
{0xc0, 0x64}, // HSIZE8[7:0] 400
{0xc1, 0x4B}, // VSIZE8[7:0] 300
{0x8c, 0x00}, //?
{0x86, 0x1D}, //Modle enable
{0xd3, 0x82}, //Auto mode DVP PCLK=2
{0xe0, 0x00}, //Reset
{0xff, 0x00}, //DSP
{0xc0, 0x64}, // HSIZE8[7:0] 400
{0xc1, 0x4B}, // VSIZE8[7:0] 300
{0x8c, 0x00}, //?
{0x86, 0x3D}, //?
{0x50, 0x00}, //?
{0x51, 0xC8}, //H_SIZE[7:0] (real/4) 800
{0x52, 0x96}, //V_SIZE[7:0] (real/4) 600
{0x53, 0x00}, //OFFSET
{0x54, 0x00}, //OFFSET
{0x55, 0x00}, //H_SIZE[8],V_SIZE[8]
{0x5a, 0xA0}, //OUTW[0-7] 160?
{0x5b, 0x78}, //OUTH[0-7] 120?
{0x5c, 0x00}, //OUTW8,OUTH8
{0xd3, 0x04}, //?
{0xFF, 0x00},
{0xE0, 0x04},
{0xE1, 0x67},
{0xD7, 0x01},
{0xDA, 0x00}, //Image output format select ------ YUV422
{0xD3, 0x82},
{0xE0, 0x00},
{0xFF, 0xFF}
};

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/ov2643_config.c Normal file
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@ -0,0 +1,682 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
#define MANUFACTURER_ID 0x7FA2
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov2643_yuv_uxga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb7},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0xFF, 0xFF}
};
const struct ov_reg ov2643_yuv_swvga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x3d, 0x48},
{0x0e, 0xb8},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x21, 0x98},
{0x22, 0x00},
{0x23, 0x06},
{0x24, 0x32},
{0x25, 0x04},
{0x26, 0x25},
{0x27, 0x84},
{0x28, 0x40},
{0x29, 0x04},
{0x2a, 0xce},
{0x2b, 0x02},
{0x2c, 0x8a},
{0x12, 0x09},
{0x39, 0xd0},
{0xcd, 0x13},
{0xde, 0x7c},
{0x3d, 0x08},
{0x15, 0x42},
{0xde, 0x7c},
{0x0f, 0x24},
{0xFF, 0xFF}
};
const struct ov_reg ov2643_yuv_vga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb7},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
//{0x43, 0xC0},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x13, 0x00},
{0x3d, 0x48},
{0x0e, 0xb8},
{0x20, 0x02},
{0x21, 0x18},
{0x22, 0x00},
{0x23, 0x42},
{0x24, 0x28},
{0x25, 0x04},
{0x26, 0x1e},
{0x27, 0x04},
{0x28, 0x40},
{0x29, 0x04},
{0x2a, 0xce},
{0x2b, 0x02},
{0x2c, 0x8a},
//YUV
{0x12, 0x09},
//RGB
//{0x12, 0x05},
{0x39, 0xd0},
{0xcd, 0x13},
{0xde, 0x7c},
{0x3d, 0x08},
{0x13, 0xff},
{0x15, 0x42},
{0xFF, 0xFF}
};

4795
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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/ov7740_config.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov7740_yuv_vga[]= {
{0x12 ,0x80},
//{0x11 ,0x07},
{0x55 ,0x40},
{0x11 ,0x02},
{0x12 ,0x00},
{0xd5 ,0x10},
{0x0c ,0x12},
{0x0d ,0x34},
{0x17 ,0x25},
{0x18 ,0xa0},
{0x19 ,0x03},
{0x1a ,0xf0},
{0x1b ,0x89}, //;was 81
{0x22 ,0x03}, //;new
{0x29 ,0x18}, //;was 17
{0x2b ,0xf8},
{0x2c ,0x01},
{0x31 ,0xa0},
{0x32 ,0xf0},
{0x33 ,0xc4}, //;was44
{0x35 ,0x05}, //;new
{0x36 ,0x3f},
{0x04 ,0x60},
{0x27 ,0x80}, //;delete "42 3a b4"
{0x3d ,0x0f},
{0x3e ,0x80},
{0x3f ,0x40},
{0x40 ,0x7f},
{0x41 ,0x6a},
{0x42 ,0x29},
{0x44 ,0x22}, //;was 11
{0x45 ,0x41},
{0x47 ,0x02},
{0x49 ,0x64},
{0x4a ,0xa1},
{0x4b ,0x40},
{0x4c ,0x1a},
{0x4d ,0x50},
{0x4e ,0x13},
{0x64 ,0x00},
{0x67 ,0x88},
{0x68 ,0x1a},
{0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling
{0x24 ,0x3c},
{0x25 ,0x30},
{0x26 ,0x72},
{0x50 ,0x97},
{0x51 ,0x1f}, //;0fc/7e/3f/1f for 60/30/15/7.5fps, 60Hz
{0x52 ,0x00}, //;[7:6]/[5:4] 2 msb for 60/50Hz
{0x53 ,0x00},
{0x20 ,0x00},
{0x21 ,0xcf}, //;01/23/57/cf for 60/30/15/7.5fps
{0x50, 0x4b}, // ;12e/97/4b/25 for 60/30/15/7.5fps, 50Hz
{0x38 ,0x14},
{0xe9 ,0x00},
{0x56 ,0x55},
{0x57 ,0xff},
{0x58 ,0xff},
{0x59 ,0xff},
{0x5f ,0x04},
{0xec ,0x00},
{0x13 ,0xff},
{0x80 ,0x7f}, //;[6]/[5] for BPC/WPC
{0x81 ,0x3f},
{0x82 ,0x32},
{0x83 ,0x01},
{0x38 ,0x11},
{0x84 ,0x70},
{0x85 ,0x00},
{0x86 ,0x03},
{0x87 ,0x01},
{0x88 ,0x05},
{0x89 ,0x30},
{0x8d ,0x30},
{0x8f ,0x85},
{0x93 ,0x30},
{0x95 ,0x85},
{0x99 ,0x30},
{0x9b ,0x85},
{0x9c ,0x08},
{0x9d ,0x12},
{0x9e ,0x23},
{0x9f ,0x45},
{0xa0 ,0x55},
{0xa1 ,0x64},
{0xa2 ,0x72},
{0xa3 ,0x7f},
{0xa4 ,0x8b},
{0xa5 ,0x95},
{0xa6 ,0xa7},
{0xa7 ,0xb5},
{0xa8 ,0xcb},
{0xa9 ,0xdd},
{0xaa ,0xec},
{0xab ,0x1a},
{0xce ,0x78},
{0xcf ,0x6e},
{0xd0 ,0x0a},
{0xd1 ,0x0c},
{0xd2 ,0x84},
{0xd3 ,0x90},
{0xd4 ,0x1e},
{0x5a ,0x24},
{0x5b ,0x1f},
{0x5c ,0x88},
{0x5d ,0x60},
{0xac ,0x6e},
{0xbe ,0xff},
{0xbf ,0x00},
{0x0f ,0x1d},
{0x0f ,0x1f},
{0xFF, 0xFF}
};

602
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov9740_yuv_vga[]= {
//@@ VGA 640x360 bin YUV DVP 60FPS (Full speed)
{0x0103,0x01},
{0x3026,0x00},
{0x3027,0x00},
{0x3002,0xe8},
{0x3004,0x03},
{0x3005,0xff},
{0x3703,0x42},
{0x3704,0x10},
{0x3705,0x45},
{0x3603,0xaa},
{0x3632,0x27},
{0x3620,0x66},
{0x3621,0xc0},
{0x0202,0x03},
{0x0203,0x43},
{0x3833,0x04},
{0x3835,0x02},
{0x4702,0x04},
{0x4704,0x00},
{0x4706,0x08},
{0x3819,0x6e},
{0x3817,0x94},
{0x3a18,0x00},
{0x3a19,0x7f},
{0x5003,0xa7},
{0x3631,0x5e},
{0x3633,0x50},
{0x3630,0xd2},
{0x3604,0x0c},
{0x3601,0x40},
{0x3602,0x16},
{0x3610,0xa1},
{0x3612,0x24},
{0x034a,0x02},
{0x034b,0xd3},
{0x034c,0x02},
{0x034d,0x80},
{0x034e,0x01},
{0x034f,0x68},
{0x0202,0x01},
{0x0203,0x9e},
{0x381a,0x44},
{0x3707,0x14},
{0x3622,0x9f},
{0x5841,0x04},
{0x4002,0x45},
{0x5000,0x01},
{0x5001,0x00},
{0x3406,0x00},
{0x5000,0xff},
{0x5001,0xef},
{0x5003,0xff},
{0x4005,0x18},
{0x3503,0x10},
{0x3a11,0xa0},
{0x3a1b,0x50},
{0x3a0f,0x50},
{0x3a10,0x4c},
{0x3a1e,0x4c},
{0x3a1f,0x26},
{0x3104,0x20},
{0x0305,0x03},
{0x0307,0x5f},
{0x0303,0x01},
{0x0301,0x0a},
{0x3010,0x01},
{0x300c,0x02},
{0x0340,0x02},
{0x0341,0x08},
{0x0342,0x04},
{0x0343,0xc0},
{0x0101,0x01},
{0x3a08,0x01},
{0x3a09,0x38},
{0x3a0e,0x01},
{0x3a14,0x09},
{0x3a15,0xc0},
{0x3a0a,0x01},
{0x3a0b,0x02},
{0x3a0d,0x02},
{0x3a02,0x10},
{0x3a03,0x30},
{0x3c0a,0x9c},
{0x3c0b,0x3f},
{0x529a,0x1 },
{0x529b,0x2 },
{0x529c,0x3 },
{0x529d,0x5 },
{0x529e,0x5 },
{0x529f,0x28},
{0x52a0,0x32},
{0x52a2,0x0 },
{0x52a3,0x2 },
{0x52a4,0x0 },
{0x52a5,0x4 },
{0x52a6,0x0 },
{0x52a7,0x8 },
{0x52a8,0x0 },
{0x52a9,0x10},
{0x52aa,0x0 },
{0x52ab,0x38},
{0x52ac,0x0 },
{0x52ad,0x3c},
{0x52ae,0x0 },
{0x52af,0x4c},
{0x5842,0x02},
{0x5843,0x5e},
{0x5844,0x04},
{0x5845,0x32},
{0x5846,0x03},
{0x5847,0x29},
{0x5848,0x02},
{0x5849,0xcc},
{0x5800,0x22},
{0x5801,0x1e},
{0x5802,0x1a},
{0x5803,0x1a},
{0x5804,0x1f},
{0x5805,0x26},
{0x5806,0xe },
{0x5807,0x9 },
{0x5808,0x7 },
{0x5809,0x8 },
{0x580a,0xb },
{0x580b,0x11},
{0x580c,0x5 },
{0x580d,0x2 },
{0x580e,0x0 },
{0x580f,0x0 },
{0x5810,0x3 },
{0x5811,0x7 },
{0x5812,0x4 },
{0x5813,0x1 },
{0x5814,0x0 },
{0x5815,0x0 },
{0x5816,0x3 },
{0x5817,0x7 },
{0x5818,0xc },
{0x5819,0x8 },
{0x581a,0x6 },
{0x581b,0x6 },
{0x581c,0x9 },
{0x581d,0x10},
{0x581e,0x20},
{0x581f,0x1b},
{0x5820,0x17},
{0x5821,0x18},
{0x5822,0x1d},
{0x5823,0x23},
{0x5824,0x5b},
{0x5825,0x6e},
{0x5826,0x6e},
{0x5827,0x7e},
{0x5828,0xab},
{0x5829,0x5e},
{0x582a,0x8a},
{0x582b,0x8a},
{0x582c,0x8a},
{0x582d,0x9d},
{0x582e,0x5b},
{0x582f,0x88},
{0x5830,0x88},
{0x5831,0x98},
{0x5832,0x9a},
{0x5833,0x4e},
{0x5834,0x8a},
{0x5835,0x79},
{0x5836,0x7a},
{0x5837,0xad},
{0x5838,0x9b},
{0x5839,0x9d},
{0x583a,0xad},
{0x583b,0x8e},
{0x583c,0x5c},
{0x583e,0x08},
{0x583f,0x04},
{0x5840,0x10},
{0x5480,0x07},
{0x5481,0x16},
{0x5482,0x2c},
{0x5483,0x4d},
{0x5484,0x59},
{0x5485,0x64},
{0x5486,0x6e},
{0x5487,0x76},
{0x5488,0x7f},
{0x5489,0x86},
{0x548a,0x94},
{0x548b,0xa3},
{0x548c,0xba},
{0x548d,0xd2},
{0x548e,0xe9},
{0x548f,0x1e},
{0x5490,0x0f},
{0x5491,0xff},
{0x5492,0x0e},
{0x5493,0x34},
{0x5494,0x07},
{0x5495,0x1a},
{0x5496,0x04},
{0x5497,0x0e},
{0x5498,0x03},
{0x5499,0x82},
{0x549a,0x03},
{0x549b,0x20},
{0x549c,0x02},
{0x549d,0xd7},
{0x549e,0x02},
{0x549f,0xa5},
{0x54a0,0x02},
{0x54a1,0x75},
{0x54a2,0x02},
{0x54a3,0x55},
{0x54a4,0x02},
{0x54a5,0x1c},
{0x54a6,0x01},
{0x54a7,0xea},
{0x54a8,0x01},
{0x54a9,0xae},
{0x54aa,0x01},
{0x54ab,0x7c},
{0x54ac,0x01},
{0x54ad,0x57},
{0x5180,0xf0},
{0x5181,0x00},
{0x5182,0x41},
{0x5183,0x42},
{0x5184,0x8f},
{0x5185,0x63},
{0x5186,0xce},
{0x5187,0xa8},
{0x5188,0x17},
{0x5189,0x1f},
{0x518a,0x27},
{0x518b,0x41},
{0x518c,0x34},
{0x518d,0xf0},
{0x518e,0x10},
{0x518f,0xff},
{0x5190,0x00},
{0x5191,0xff},
{0x5192,0x00},
{0x5193,0xff},
{0x5194,0x00},
{0x5380,0x1 },
{0x5381,0x0 },
{0x5382,0x0 },
{0x5383,0x17},
{0x5384,0x0 },
{0x5385,0x1 },
{0x5386,0x0 },
{0x5387,0x0 },
{0x5388,0x0 },
{0x5389,0xad},
{0x538a,0x0 },
{0x538b,0x11},
{0x538c,0x0 },
{0x538d,0x0 },
{0x538e,0x0 },
{0x538f,0x7 },
{0x5390,0x0 },
{0x5391,0x80},
{0x5392,0x0 },
{0x5393,0xa0},
{0x5394,0x18},
{0x3c0a,0x9c},
{0x3c0b,0x3f},
{0x5501,0x14},
{0x5502,0x00},
{0x5503,0x40},
{0x5504,0x00},
{0x5505,0x80},
{0x0100,0x01},
{0xFF, 0xFF}
};
const struct ov_reg ov9740_yuv_sxga[]= {
//@@ WXGA 1280x720 YUV DVP 15FPS for card reader
{0x0103, 0x01},
{0x3026, 0x00},
{0x3027, 0x00},
{0x3002, 0xe8},
{0x3004, 0x03},
{0x3005, 0xff},
{0x3406, 0x00},
{0x3603, 0xaa},
{0x3632, 0x27},
{0x3620, 0x66},
{0x3621, 0xc0},
{0x3631, 0x5e},
{0x3633, 0x50},
{0x3630, 0xd2},
{0x3604, 0x0c},
{0x3601, 0x40},
{0x3602, 0x16},
{0x3610, 0xa1},
{0x3612, 0x24},
{0x3622, 0x9f},
{0x3703, 0x42},
{0x3704, 0x10},
{0x3705, 0x45},
{0x3707, 0x14},
{0x3833, 0x04},
{0x3835, 0x03},
{0x3819, 0x6e},
{0x3817, 0x94},
{0x3503, 0x10},
{0x3a18, 0x00},
{0x3a19, 0x7f},
{0x3a11, 0xa0},
{0x3a1a, 0x05},
{0x3a1b, 0x50},
{0x3a0f, 0x50},
{0x3a10, 0x4c},
{0x3a1e, 0x4c},
{0x3a1f, 0x26},
{0x4002, 0x45},
{0x4005, 0x18},
{0x4702, 0x04},
{0x4704, 0x00},
{0x4706, 0x08},
{0x5000, 0xff},
{0x5001, 0xef},
{0x5003, 0xff},
{0x3104,0x20},
{0x0305,0x03},
{0x0307,0x4c},
{0x0303,0x01},
{0x0301,0x08},
{0x3010,0x01},
{0x300c,0x03},
{0x0340, 0x03},
{0x0341, 0x07},
{0x0342, 0x06},
{0x0343, 0x62},
{0x034b, 0xd1},
{0x034c, 0x05},
{0x034d, 0x00},
{0x034e, 0x02},
{0x034f, 0xd0},
{0x0101, 0x01},
{0x3a08, 0x00},
{0x3a09, 0xe8},
{0x3a0e, 0x03},
{0x3a14, 0x15},
{0x3a15, 0xc6},
{0x3a0a, 0x00},
{0x3a0b, 0xc0},
{0x3a0d, 0x04},
{0x3a02, 0x18},
{0x3a03, 0x20},
{0x3c0a, 0x9c},
{0x3c0b, 0x3f},
{0x529a, 0x1 },
{0x529b, 0x2 },
{0x529c, 0x3 },
{0x529d, 0x5 },
{0x529e, 0x5 },
{0x529f, 0x28},
{0x52a0, 0x32},
{0x52a2, 0x0 },
{0x52a3, 0x2 },
{0x52a4, 0x0 },
{0x52a5, 0x4 },
{0x52a6, 0x0 },
{0x52a7, 0x8 },
{0x52a8, 0x0 },
{0x52a9, 0x10},
{0x52aa, 0x0 },
{0x52ab, 0x38},
{0x52ac, 0x0 },
{0x52ad, 0x3c},
{0x52ae, 0x0 },
{0x52af, 0x4c},
{0x5842, 0x02},
{0x5843, 0x5e},
{0x5844, 0x04},
{0x5845, 0x32},
{0x5846, 0x03},
{0x5847, 0x29},
{0x5848, 0x02},
{0x5849, 0xcc},
{0x5800, 0x22},
{0x5801, 0x1e},
{0x5802, 0x1a},
{0x5803, 0x1a},
{0x5804, 0x1f},
{0x5805, 0x26},
{0x5806, 0xe },
{0x5807, 0x9 },
{0x5808, 0x7 },
{0x5809, 0x8 },
{0x580a, 0xb },
{0x580b, 0x11},
{0x580c, 0x5 },
{0x580d, 0x2 },
{0x580e, 0x0 },
{0x580f, 0x0 },
{0x5810, 0x3 },
{0x5811, 0x7 },
{0x5812, 0x4 },
{0x5813, 0x1 },
{0x5814, 0x0 },
{0x5815, 0x0 },
{0x5816, 0x3 },
{0x5817, 0x7 },
{0x5818, 0xc },
{0x5819, 0x8 },
{0x581a, 0x6 },
{0x581b, 0x6 },
{0x581c, 0x9 },
{0x581d, 0x10},
{0x581e, 0x20},
{0x581f, 0x1b},
{0x5820, 0x17},
{0x5821, 0x18},
{0x5822, 0x1d},
{0x5823, 0x23},
{0x5824, 0x5b},
{0x5825, 0x6e},
{0x5826, 0x6e},
{0x5827, 0x7e},
{0x5828, 0xab},
{0x5829, 0x5e},
{0x582a, 0x8a},
{0x582b, 0x8a},
{0x582c, 0x8a},
{0x582d, 0x9d},
{0x582e, 0x5b},
{0x582f, 0x88},
{0x5830, 0x88},
{0x5831, 0x98},
{0x5832, 0x9a},
{0x5833, 0x4e},
{0x5834, 0x8a},
{0x5835, 0x79},
{0x5836, 0x7a},
{0x5837, 0xad},
{0x5838, 0x9b},
{0x5839, 0x9d},
{0x583a, 0xad},
{0x583b, 0x8e},
{0x583c, 0x5c},
{0x583e, 0x08},
{0x583f, 0x04},
{0x5840, 0x10},
{0x5480, 0x07},
{0x5481, 0x16},
{0x5482, 0x2c},
{0x5483, 0x4d},
{0x5484, 0x59},
{0x5485, 0x64},
{0x5486, 0x6e},
{0x5487, 0x76},
{0x5488, 0x7f},
{0x5489, 0x86},
{0x548a, 0x94},
{0x548b, 0xa3},
{0x548c, 0xba},
{0x548d, 0xd2},
{0x548e, 0xe9},
{0x548f, 0x1e},
{0x5490, 0x0f},
{0x5491, 0xff},
{0x5492, 0x0e},
{0x5493, 0x34},
{0x5494, 0x07},
{0x5495, 0x1a},
{0x5496, 0x04},
{0x5497, 0x0e},
{0x5498, 0x03},
{0x5499, 0x82},
{0x549a, 0x03},
{0x549b, 0x20},
{0x549c, 0x02},
{0x549d, 0xd7},
{0x549e, 0x02},
{0x549f, 0xa5},
{0x54a0, 0x02},
{0x54a1, 0x75},
{0x54a2, 0x02},
{0x54a3, 0x55},
{0x54a4, 0x02},
{0x54a5, 0x1c},
{0x54a6, 0x01},
{0x54a7, 0xea},
{0x54a8, 0x01},
{0x54a9, 0xae},
{0x54aa, 0x01},
{0x54ab, 0x7c},
{0x54ac, 0x01},
{0x54ad, 0x57},
{0x5180, 0xf0},
{0x5181, 0x00},
{0x5182, 0x41},
{0x5183, 0x42},
{0x5184, 0x8f},
{0x5185, 0x63},
{0x5186, 0xce},
{0x5187, 0xa8},
{0x5188, 0x17},
{0x5189, 0x1f},
{0x518a, 0x27},
{0x518b, 0x41},
{0x518c, 0x34},
{0x518d, 0xf0},
{0x518e, 0x10},
{0x518f, 0xff},
{0x5190, 0x00},
{0x5191, 0xff},
{0x5192, 0x00},
{0x5193, 0xff},
{0x5194, 0x00},
{0x5380, 0x1 },
{0x5381, 0x0 },
{0x5382, 0x0 },
{0x5383, 0x17},
{0x5384, 0x0 },
{0x5385, 0x1 },
{0x5386, 0x0 },
{0x5387, 0x0 },
{0x5388, 0x0 },
{0x5389, 0xad},
{0x538a, 0x0 },
{0x538b, 0x11},
{0x538c, 0x0 },
{0x538d, 0x0 },
{0x538e, 0x0 },
{0x538f, 0x7 },
{0x5390, 0x0 },
{0x5391, 0x80},
{0x5392, 0x0 },
{0x5393, 0xa0},
{0x5394, 0x18},
{0x3c0a, 0x9c},
{0x3c0b, 0x3f},
{0x5501, 0x14},
{0x5502, 0x00},
{0x5503, 0x40},
{0x5504, 0x00},
{0x5505, 0x80},
{0x5308, 0x40},
{0x5309, 0x60},
{0x3a11, 0xd0},
{0x3a1b, 0x78},
{0x3a0f, 0x78},
{0x3a10, 0x68},
{0x3a1e, 0x68},
{0x3a1f, 0x40},
{0x0100, 0x01},
{0xFF, 0xFF}
};

224
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/qt1070.c Normal file
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@ -0,0 +1,224 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation QT1070 driver.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* \brief Read one byte of data from QT1070 Register.
*
* \param pTwid Pointer to twi driver structure.
* \param regAddr Register address to read.
* \return value in the given register.
*/
static uint8_t QT1070_ReadReg(Twid *pTwid, uint8_t regAddr)
{
uint8_t data;
TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, &regAddr, 1, 0);
TWID_Read(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, &data, 1, 0);
return data;
}
/**
* \brief Write one byte of data to QT1070 Register.
*
* \param pTwid Pointer to twi driver structure.
* \param regAddr Register address to write.
* \param data Data to write.
*/
static void QT1070_WriteReg(Twid *pTwid, uint32_t regAddr, uint8_t data)
{
TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, regAddr, 1, &data, 1, 0);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Get qt1070 chip ID.
*
* \param pTwid Pointer to twi driver structure.
* \return Chip Id
*/
uint8_t QT1070_GetChipId(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_CHIP_ID);
}
/**
* \brief Get qt1070 firmware version number.
*
* \param pTwid Pointer to twi driver structure.
* \return Firmware version number.
*/
uint8_t QT1070_GetFirmwareVersion(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_FIRMWARE_VERSION);
}
/**
* \brief Get qt1070 detection status.
*
* \param pTwid Pointer to twi driver structure.
* \return Dectection status.
*/
uint8_t QT1070_GetDetection_Status(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_DETECTION_STATUS);
}
/**
* \brief Get qt1070 Key status.
*
* \param pTwid Pointer to twi driver structure.
* \return Key status.
*/
uint8_t QT1070_GetKey_Status(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_KEY_STATUS);
}
/**
* \brief Get qt1070 key signal value in the given Key. These are the key's
* of 16-bit key signals which are accessed as two 8-bit bytes,stored MSB first
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \return Key signal value.
*/
uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key)
{
uint8_t data[2];
data[0] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_MSB + key * 2);
data[1] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_LSB + key * 2);
return (data[0] << 8) | data[1];
}
/**
* \brief Get qt1070 key reference data in the given Key. These are the key's
* of 16-bit key reference data which are accessed as two 8-bit bytes, stored MSB first
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \return Key reference data.
*/
uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key)
{
uint8_t data[2];
data[0] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_MSB + key * 2);
data[1] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_LSB + key * 2);
return (data[0] << 8) | data[1];
}
/**
* \brief Set the threshold value for the given Key.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param threshold Threshold value.
*/
void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold)
{
// Do not use a setting of 0 as this causes a key to go into detection
// when its signal is equal to its reference.
if ( threshold )
{
QT1070_WriteReg(pTwid, QT1070_REG_NTHR_KEY0 + key, threshold);
}
}
/**
* \brief Set Averaging factor and adjacent key suppression for the given Key.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param Ave Averaging factor.
* \param Aks AKS group index.
*/
void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks)
{
QT1070_WriteReg(pTwid, QT1070_REG_AVEAKS_KEY0 + key, (Ave << 3) | Aks );
}
/**
* \brief Set DI level for the given Key. This 8-bit value controls the number
* of consecutive measurement that must be confirmed as having passed the key threshold
* before that key is registered as being in detect.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param di DI level.
*/
void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di)
{
QT1070_WriteReg(pTwid, QT1070_REG_DI_KEY0 + key, di);
}
/**
* \brief Start a calibration cycle, the CALIBTATE flag in the detection status
* register is set when the calibration begins and clears when the calibration
* has finished.
*
* \param pTwid Pointer to twi driver structure.
*/
void QT1070_StartCalibrate(Twid *pTwid)
{
QT1070_WriteReg(pTwid, QT1070_REG_CALIRATE , 1);
}
/**
* \brief Reset the qt1070 device.
*
* \param pTwid Pointer to twi driver structure.
*/
void QT1070_StartReset(Twid *pTwid)
{
QT1070_WriteReg(pTwid, QT1070_REG_RESET , 1);
}

67
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/rand.c Normal file
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@ -0,0 +1,67 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Header
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Global Variables
*------------------------------------------------------------------------------*/
static uint32_t _dwRandNext=1 ;
/*------------------------------------------------------------------------------
* Exported Functions
*------------------------------------------------------------------------------*/
/**
* Initialize the seed for rand generator.
*
* \param seed rand initiation seed
*/
extern void srand( uint32_t dwSeed )
{
_dwRandNext = dwSeed ;
}
/**
* Return a random number, maxinum assumed to be 65536
*/
extern uint32_t rand( void )
{
_dwRandNext = _dwRandNext * 1103515245 + 12345 ;
return (uint32_t)(_dwRandNext/131072) % 65536 ;
}

194
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for Real Time Clock calibration (RTC) .
*
*/
#include "board.h"
const RTC_PPMLookup PPM_Lookup[] =
{
{-40, -168 ,0, 1 ,22 },
{-39, -163 ,0, 1 ,23 },
{-38, -158 ,0, 1 ,24 },
{-37, -153 ,0, 1 ,25 },
{-36, -148 ,0, 1 ,25 },
{-35, -143 ,0, 1 ,26 },
{-34, -138 ,0, 1 ,27 },
{-33, -134 ,0, 1 ,28 },
{-32, -129 ,0, 1 ,29 },
{-31, -124 ,0, 1 ,31 },
{-30, -120 ,0, 1 ,32 },
{-29, -116 ,0, 1 ,33 },
{-28, -111 ,0, 1 ,34 },
{-27, -107 ,0, 1 ,36 },
{-26, -103 ,0, 1 ,37 },
{-25, -99, 0, 1 ,38 },
{-24, -95, 0, 1 ,40 },
{-23, -91, 0, 1 ,42 },
{-22, -87, 0, 1 ,44 },
{-21, -84, 0, 1 ,45 },
{-20, -80, 0, 1 ,48 },
{-19, -76, 0, 1 ,50 },
{-18, -73, 0, 1 ,53 },
{-17, -70, 0, 1 ,55 },
{-16, -66, 0, 1 ,58 },
{-15, -63, 0, 1 ,61 },
{-14, -60, 0, 1 ,64 },
{-13, -57, 0, 1 ,68 },
{-12, -54, 0, 1 ,71 },
{-11, -51, 0, 1 ,76 },
{-10, -48, 0, 1 ,80 },
{-9 ,-45 , 0, 1 ,86 },
{-8 ,-43 , 0, 1 ,90 },
{-7 ,-40 , 0, 1 ,97 },
{-6 ,-37 , 0, 1 ,105},
{-5 ,-35 , 0, 1 ,111},
{-4 ,-33 , 0, 1 ,117},
{-3 ,-30 , 0, 0 ,6 },
{-2 ,-28 , 0, 0 ,6 },
{-1 ,-26 , 0, 0 ,7 },
{0 ,-24 , 0, 0 ,7 },
{1 ,-22 , 0, 0 ,8 },
{2 ,-20 , 0, 0 ,9 },
{3 ,-18 , 0, 0 ,10 },
{4 ,-17 , 0, 0 ,10 },
{5 ,-15 , 0, 0 ,12 },
{6 ,-13 , 0, 0 ,14 },
{7 ,-12 , 0, 0 ,15 },
{8 ,-11 , 0, 0 ,17 },
{9 ,-9 , 0, 0 ,21 },
{10 ,-8 , 0, 0 ,23 },
{11 ,-7 , 0, 0 ,27 },
{12 ,-6 , 0, 0 ,32 },
{13 ,-5 , 0, 0 ,38 },
{14 ,-4 , 0, 0 ,48 },
{15 ,-3 , 0, 0 ,64 },
{16 ,-2 , 0, 0 ,97 },
{17 ,-2 , 0, 0 ,97 },
{18 ,-1 , 0, 0 ,127},
{19 ,0, 1, 0 ,0 },
{20 ,0, 1, 0 ,0 },
{21 ,0, 1, 0 ,0 },
{22 ,1, 1, 0 ,127},
{23 ,1, 1, 0 ,127},
{24 ,1, 1, 0 ,127},
{25 ,1, 1, 0 ,127},
{26 ,1, 1, 0 ,127},
{27 ,1, 1, 0 ,127},
{28 ,1, 1, 0 ,127},
{29 ,0, 1, 0 ,0 },
{30 ,0, 1, 0 ,0 },
{31 ,0, 1, 0 ,0 },
{32 ,-1, 0, 0 ,127},
{33 ,-2, 0, 0 ,97 },
{34 ,-2, 0, 0 ,97 },
{35 ,-3, 0, 0 ,64 },
{36 ,-4, 0, 0 ,48 },
{37 ,-5, 0, 0 ,38 },
{38 ,-6, 0, 0 ,32 },
{39 ,-7, 0, 0 ,27 },
{40 ,-8, 0, 0 ,23 },
{41 ,-9, 0, 0 ,21 },
{42 ,-11 , 0, 0 ,17 },
{43 ,-12 , 0, 0 ,15 },
{44 ,-13 , 0, 0 ,14 },
{45 ,-15 , 0, 0 ,12 },
{46 ,-17 , 0, 0 ,10 },
{47 ,-18 , 0, 0 ,10 },
{48 ,-20 , 0, 0 ,9 },
{49 ,-22 , 0, 0 ,8 },
{50 ,-24 , 0, 0 ,7 },
{51 ,-26 , 0, 0 ,7 },
{52 ,-28 , 0, 0 ,6 },
{53 ,-30 , 0, 0 ,6 },
{54 ,-33 , 0, 1 ,117},
{55 ,-35 , 0, 1 ,111},
{56 ,-37 , 0, 1 ,105},
{57 ,-40 , 0, 1 ,97 },
{58 ,-43 , 0, 1 ,90 },
{59 ,-45 , 0, 1 ,86 },
{60 ,-48 , 0, 1 ,80 },
{61 ,-51 , 0, 1 ,76 },
{62 ,-54 , 0, 1 ,71 },
{63 ,-57 , 0, 1 ,68 },
{64 ,-60 , 0, 1 ,64 },
{65 ,-63 , 0, 1 ,61 },
{66 ,-66 , 0, 1 ,58 },
{67 ,-70 , 0, 1 ,55 },
{68 ,-73 , 0, 1 ,53 },
{69 ,-76 , 0, 1 ,50 },
{70 ,-80 , 0, 1 ,48 },
{71 ,-84 , 0, 1 ,45 },
{72 ,-87 , 0, 1 ,44 },
{73 ,-91 , 0, 1 ,42 },
{74 ,-95 , 0, 1 ,40 },
{75 ,-99 , 0, 1 ,38 },
{76 ,-103 , 0, 1 ,37 },
{77 ,-107 , 0, 1 ,36 },
{78 ,-111 , 0, 1 ,34 },
{79 ,-116 , 0, 1 ,33 },
{80 ,-120 , 0, 1 ,32 },
{81 ,-124 , 0, 1 ,31 },
{82 ,-129 , 0, 1 ,29 },
{83 ,-134 , 0, 1 ,28 },
{84 ,-138 , 0, 1 ,27 },
{85 ,-143 , 0, 1 ,26 }
} ;
/**
* \brief RTC calibration for Temperature or PPM drift
*/
extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr)
{
uint16_t i;
uint32_t MR_Reg, Size;
Size = sizeof(PPM_Lookup);
MR_Reg =0;
for(i=0; i< Size; i++)
{
if(PPM_Lookup[i].Tempr == CurrentTempr)
{
MR_Reg |= RTC_MR_CORRECTION(PPM_Lookup[i].CORRECTION);
MR_Reg |= (PPM_Lookup[i].HIGHPPM << 15);
MR_Reg |= (PPM_Lookup[i].NEGPPM << 4);
pRtc->RTC_MR = MR_Reg; // update the calibration value
break;
}
}
}

132
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/timetick.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* Implement simple PIT usage as system tick.
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Tick Counter united by ms */
static volatile uint32_t _dwTickCount = 0 ;
/*----------------------------------------------------------------------------
* Exported Functions
*----------------------------------------------------------------------------*/
/**
* \brief Handler for Sytem Tick interrupt.
*/
extern void TimeTick_Increment( uint32_t dwInc )
{
_dwTickCount += dwInc;
}
/**
* \brief Configures the PIT & reset tickCount.
* Systick interrupt handler will generates 1ms interrupt and increase a
* tickCount.
* \note IRQ handler must be configured before invoking this function.
* \note PIT is enabled automatically in this function.
* \param new_mck Current master clock.
*/
extern uint32_t TimeTick_Configure( uint32_t new_mck )
{
_dwTickCount = 0 ;
PIT_Init( 1000, new_mck / 1000000 );
PIT_EnableIT();
PIT_Enable();
return 0;
}
/**
* Get Delayed number of tick
* \param startTick Start tick point.
* \param endTick End tick point.
*/
extern uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick)
{
if (endTick >= startTick) return (endTick - startTick);
return (endTick + (0xFFFFFFFF - startTick) + 1);
}
/**
* \brief Get current Tick Count, in ms.
*/
extern uint32_t GetTickCount( void )
{
return _dwTickCount ;
}
/**
* \brief Sync Wait for several ms
*/
extern void Wait( volatile uint32_t dwMs )
{
uint32_t dwStart ;
uint32_t dwCurrent ;
dwStart = _dwTickCount ;
do
{
dwCurrent = _dwTickCount ;
} while ( dwCurrent - dwStart < dwMs ) ;
}
/**
* \brief Sync Sleep for several ms
*/
extern void Sleep( volatile uint32_t dwMs )
{
uint32_t dwStart ;
uint32_t dwCurrent ;
__ASM("CPSIE I");
dwStart = _dwTickCount ;
do
{
dwCurrent = _dwTickCount ;
if ( dwCurrent - dwStart > dwMs )
{
break ;
}
__ASM("WFI");
} while( 1 ) ;
}

60
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Internal variables
*------------------------------------------------------------------------------*/
/** Trace level can be set at applet initialization */
#if !defined(NOTRACE) && (DYN_TRACES == 1)
uint32_t dwTraceLevel = TRACE_LEVEL ;
#endif
/**
* Initializes the DBGU Console
*
* \param dwBaudRate U(S)ART baudrate.
* \param dwMCk Master clock frequency.
*/
extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk )
{
const Pin pinsDBUG[] = { PINS_DBGU } ;
PIO_Configure( pinsDBUG, PIO_LISTSIZE( pinsDBUG ) ) ;
DBGU_Configure( dwBaudRate, dwMCk ) ;
}

384
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/tsd_com.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
/** \addtogroup tsd_module
*@{
*/
#include <board.h>
#include <string.h>
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/** Size in pixels of calibration points. */
#define POINTS_SIZE 4
/** Maximum difference in pixels between the test point and the measured point.
*/
#define POINTS_MAX_XERROR 10
/** Maximum difference in pixels between the test point and the measured point.
*/
#define POINTS_MAX_YERROR 8
/** Delay at the end of calibartion for result display (positive or negative) */
#define DELAY_RESULT_DISPLAY 4000000
/** Clear Strings on LCD */
#if 1
#define CLEAR_STRING() LCDD_Fill(COLOR_WHITE)
#else
#define CLEAR_STRING() \
LCDD_DrawFilledRectangle(strX - 3*strW, strY, \
strX + 20*strW, strY + 6*strH, COLOR_WHITE)
#endif
/*----------------------------------------------------------------------------
* Local types
*----------------------------------------------------------------------------*/
/**
* Point used during the touchscreen calibration process.
*/
typedef struct _CalibrationPoint {
/** Coordinate of point along the X-axis of the screen. */
uint32_t x;
/** Coordinate of point along the Y-axis of the screen. */
uint32_t y;
/** Calibration data of point. */
uint32_t data[2];
} CalibrationPoint;
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Calibration display title */
static const char* strTitle = "LCD Calibration";
/** indicates if the touch screen has been calibrated.
If not, Callback functions are not called */
static volatile uint8_t bCalibrationOk = 0;
/** Slope for interpoling touchscreen measurements along the X-axis. */
static int32_t xSlope;
/** Slope for interpoling touchscreen measurements along the Y-axis. */
static int32_t ySlope;
/** Calibration points */
static CalibrationPoint calibrationPoints[] = {
/* Top-left corner calibration point */
{
BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Top-right corner calibration point */
{
BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Bottom-right corner calibration point */
{
BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Bottom-left corner calibration point */
{
BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
{0, 0}
}
};
/** Test point */
static const CalibrationPoint testPoint = {
BOARD_LCD_WIDTH / 2,
BOARD_LCD_HEIGHT / 2,
{0, 0}
};
/*----------------------------------------------------------------------------
* External functions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* Display a calibration point on the given buffer.
* \param pPoint Calibration point to display.
*/
static void DrawCalibrationPoint(
const CalibrationPoint *pPoint)
{
LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE / 2,
pPoint->y - POINTS_SIZE / 2,
pPoint->x + POINTS_SIZE,
pPoint->y + POINTS_SIZE,
COLOR_RED);
}
/**
* Clears a calibration point from the given buffer.
* \param pLcdBuffer LCD buffer to draw on.
* \param pPoint Calibration point to clear.
*/
static void ClearCalibrationPoint(
const CalibrationPoint *pPoint)
{
LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE,
pPoint->y - POINTS_SIZE,
pPoint->x + POINTS_SIZE,
pPoint->y + POINTS_SIZE,
COLOR_WHITE);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Indicates if the calibration of the touch screen is Ok
* \return 1 calibration Ok, 0 if not
*/
uint8_t TSDCom_IsCalibrationOk(void)
{
return bCalibrationOk;
}
/**
* Interpolates the provided raw measurements using the previously calculated
* slope. The resulting x and y coordinates are stored in an array.
* \param pData Raw measurement data, as returned by TSD_GetRawMeasurement().
* \param pPoint Array in which x and y will be stored.
*/
void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint)
{
pPoint[0] = calibrationPoints[0].x
- (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024)
/ xSlope;
pPoint[1] = calibrationPoints[0].y
- (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024)
/ ySlope;
/* Is pPoint[0] negative ? */
if(pPoint[0] & 0x80000000) pPoint[0] = 0;
/* Is pPoint[0] bigger than the LCD width ? */
if(pPoint[0] > BOARD_LCD_WIDTH) pPoint[0] = BOARD_LCD_WIDTH;
/* Is pPoint[1] negative ? */
if(pPoint[1] & 0x80000000) pPoint[1] = 0;
/* Is pPoint[1] bigger than the LCD width ? */
if(pPoint[1] > BOARD_LCD_HEIGHT) pPoint[1] = BOARD_LCD_HEIGHT;
}
/**
* Performs the calibration process using the provided buffer to display
* information.
* \param pLcdBuffer LCD buffer to display.
* \return True if calibration was successful; otherwise false.
*/
uint8_t TSDCom_Calibrate(void)
{
uint32_t i; // to keep the tempo with gcc code optimisation
int32_t slope1, slope2;
CalibrationPoint measuredPoint;
uint8_t xOk, yOk;
int32_t xDiff, yDiff;
uint32_t strX = BOARD_LCD_WIDTH / 2 - 75, strY = 60;
uint32_t strW, strH;
LCDD_GetStringSize("P", &strW, &strH);
/* Calibration setup */
LCDD_Fill(COLOR_WHITE);
LCDD_Flush_CurrentCanvas();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_Flush_CurrentCanvas();
LCDD_DrawString(strX - 2*strW, strY + 3*strH,
" Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE);
LCDD_Flush_CurrentCanvas();
/* Calibration points */
for (i = 0; i < 4; i++) {
DrawCalibrationPoint(&calibrationPoints[i]);
LCDD_Flush_CurrentCanvas();
/* Wait for touch & end of conversion */
TSD_WaitPenPressed();
TSD_GetRawMeasurement(calibrationPoints[i].data);
ClearCalibrationPoint(&calibrationPoints[i]);
LCDD_Flush_CurrentCanvas();
/* Wait for contact loss */
TSD_WaitPenReleased();
printf("P%d: (%d,%d)\n\r", (unsigned int)i, (unsigned int)calibrationPoints[i].data[0], (unsigned int)calibrationPoints[i].data[1]);
}
/* Calculate slopes using the calibration data
* Theory behind those calculations:
* - We suppose the touchscreen measurements are linear, so the following equations are true (simple
* linear regression) for any two 'a' and 'b' points of the screen:
* dx = (a.data[0] - b.data[0]) / (a.x - b.x)
* dy = (a.data[1] - b.data[1]) / (a.y - b.y)
*
* - We calculate dx and dy (called xslope and yslope here) using the calibration points.
*
* - We can then use dx and dy to infer the position of a point 'p' given the measurements performed
* by the touchscreen ('c' is any of the calibration points):
* dx = (p.data[0] - c.data[0]) / (p.x - c.x)
* dy = (p.data[1] - c.data[1]) / (p.y - c.y)
* Thus:
* p.x = c.x - (p.data[0] - c.data[0]) / dx
* p.y = c.y - (p.data[1] - c.data[1]) / dy
*
* - Since there are four calibration points, dx and dy can be calculated twice, so we average
* the two values.
*/
slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]);
slope1 *= 1024;
slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x);
slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]);
slope2 *= 1024;
slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x);
xSlope = (slope1 + slope2) / 2;
slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]);
slope1 *= 1024;
slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y);
slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]);
slope2 *= 1024;
slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y);
ySlope = (slope1 + slope2) / 2;
printf("Slope: %d, %d\n\r", (unsigned int)xSlope, (unsigned int)ySlope);
/* Test point */
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX - 2*strW, strY + 3*strH,
" Touch the point to\nvalidate calibration", COLOR_DARKBLUE);
LCDD_Flush_CurrentCanvas();
DrawCalibrationPoint(&testPoint);
LCDD_Flush_CurrentCanvas();
/* Wait for touch & end of conversion */
TSD_WaitPenPressed();
TSD_GetRawMeasurement(measuredPoint.data);
TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint);
DrawCalibrationPoint(&measuredPoint);
LCDD_Flush_CurrentCanvas();
/* Check resulting x and y */
xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x;
yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y;
xOk = (xDiff >= -POINTS_MAX_XERROR) && (xDiff <= POINTS_MAX_XERROR);
yOk = (yDiff >= -POINTS_MAX_YERROR) && (yDiff <= POINTS_MAX_YERROR);
/* Wait for contact loss */
TSD_WaitPenReleased();
printf("TP: %d, %d -> %d, %d\n\r",
(unsigned int)measuredPoint.data[0], (unsigned int)measuredPoint.data[1],
(unsigned int)measuredPoint.x, (unsigned int)measuredPoint.y);
/* Check calibration result */
if (xOk && yOk) {
bCalibrationOk = 1;
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX + 3*strW, strY + 2*strH, "Success !", COLOR_GREEN);
LCDD_Flush_CurrentCanvas();
}
else {
bCalibrationOk = 0;
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX + strW, strY + 2*strH, "Error too big", COLOR_RED);
LCDD_Flush_CurrentCanvas();
TRACE_WARNING("X %u, Y %u; Diff %d, %d\n\r",
(unsigned int)(measuredPoint.x), (unsigned int)(measuredPoint.y), (unsigned int)xDiff, (unsigned int)yDiff);
}
/* Slight delay */
for (i = 0; i < DELAY_RESULT_DISPLAY; i++);
LCDD_Flush_CurrentCanvas();
return (xOk && yOk);
}
/**
* Read calibrate data to buffer.
* \param pBuffer Data buffer.
* \param size Size of data buffer in bytes.
*/
void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size)
{
uint8_t *pDest = (uint8_t *)pBuffer;
memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk));
pDest += sizeof(bCalibrationOk);
memcpy(pDest, &xSlope, sizeof(xSlope));
pDest += sizeof(xSlope);
memcpy(pDest, &ySlope, sizeof(ySlope));
pDest += sizeof(ySlope);
memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data));
pDest += sizeof(calibrationPoints[0].data);
}
/**
* Restore calibrate data with buffer data.
* \param pBuffer Data buffer.
* \param size Size of data buffer in bytes.
*/
void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size)
{
uint8_t *pSrc = (uint8_t *)pBuffer;
memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk));
pSrc += sizeof(bCalibrationOk);
memcpy(&xSlope, pSrc, sizeof(xSlope));
pSrc += sizeof(xSlope);
memcpy(&ySlope, pSrc, sizeof(ySlope));
pSrc += sizeof(ySlope);
memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data));
pSrc += sizeof(calibrationPoints[0].data);
}
/**@}*/

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <board.h>
#include <string.h>
#ifdef REG_ADC_TSMR
/** \addtogroup tsd_module
*@{
*/
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/** SWAP X & Y */
#define TS_XY_SWAP
/** Status that used for touchscreen */
#define TS_STATUSES ( ADC_ISR_PENS | ADC_ISR_PEN | ADC_ISR_NOPEN \
| ADC_ISR_XRDY | ADC_ISR_YRDY | ADC_ISR_PRDY )
/*----------------------------------------------------------------------------
* Local types
*----------------------------------------------------------------------------*/
/** X value is ready */
#define TS_X_RDY (1 << 0)
/** Y value is ready */
#define TS_Y_RDY (1 << 1)
/** Pressure value is ready */
#define TS_P_RDY (1 << 2)
/** Pen status */
#define TS_PEN_STAT (1 << 7)
/** All data is ready (X,Y & P) */
#define TS_DATA_RDY (TS_X_RDY|TS_Y_RDY|TS_P_RDY)
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Raw register value */
static uint32_t dwRaw[3];
/** Touchscreen data sampling results */
static uint32_t dwTsData[3];
/** Last Touchscreen sampling results */
static uint32_t dwLastTsData[3];
/** Touchscreen data ready */
static uint8_t bTsFlags = 0;
/*----------------------------------------------------------------------------
* External functions
*----------------------------------------------------------------------------*/
extern uint32_t TSD_GetRaw(uint32_t i);
/**
* Return raw register value.
*/
uint32_t TSD_GetRaw(uint32_t i)
{
return dwRaw[i];
}
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/**
* Interrupt handler for the TouchScreen.
* Handles pen press, pen move and pen release events
* by invoking three callback functions.
*/
void TSD_Handler(uint32_t dwAdcStatus)
{
Adc *pAdc = ADC;
uint32_t status;
/* TSADC status */
status = dwAdcStatus;
status &= /*ADC_GetItMask(pAdc) &*/ TS_STATUSES;
if (status == 0) return;
/* Pen released */
if (status & ADC_ISR_NOPEN)
{
if ((bTsFlags & TS_PEN_STAT) == 0)
{
/* Register last data */
memcpy(dwLastTsData, dwTsData, sizeof(dwTsData));
/* Invoke PenReleased callback */
if (TSDCom_IsCalibrationOk())
TSD_PenReleased(dwTsData[0], dwTsData[1]);
}
bTsFlags = 0;
/* Stop periodic trigger & enable pen */
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE);
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
/* Disable pen release detect */
ADC_DisableIt(pAdc, ADC_IDR_NOPEN);
/* Enable pen press detect */
ADC_EnableIt(pAdc, ADC_IER_PEN);
}
/* Pen pressed */
else if (status & ADC_ISR_PEN)
{
bTsFlags |= TS_PEN_STAT;
/* Configure for peripdic trigger */
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_AVG8CONV);
ADC_SetTsDebounce(pAdc, 300); /* 300ns */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PERIOD_TRIG);
/* Disable pen press detect */
ADC_DisableIt(pAdc, ADC_IDR_PEN);
/* Enable pen release detect */
ADC_EnableIt(pAdc, ADC_IER_NOPEN|ADC_IER_XRDY|ADC_IER_YRDY|ADC_IER_PRDY);
}
else if (status & ADC_ISR_PENS)
{
/* X */
if (status & ADC_ISR_XRDY)
{
bTsFlags |= TS_X_RDY;
}
/* Y */
if (status & ADC_ISR_YRDY)
{
bTsFlags |= TS_Y_RDY;
}
/* P: (X/1024)*[(Z2/Z1)-1] */
if (status & ADC_ISR_PRDY)
{
bTsFlags |= TS_P_RDY;
}
}
/* X,Y,P are ready */
if ((bTsFlags & TS_DATA_RDY) == TS_DATA_RDY)
{
uint32_t xpos, z2, z1;
bTsFlags &= ~TS_DATA_RDY;
/* Get X,Y */
TSD_GetRawMeasurement(dwRaw);
/* Interprate X,Y */
TSDCom_InterpolateMeasurement(dwRaw, dwTsData);
/* Get P: Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1] */
dwRaw[2] = ADC_GetTsPressure(pAdc);
#ifdef TS_XY_SWAP
xpos = (dwRaw[1]);
#else
xpos = (dwRaw[0]);
#endif
xpos = (xpos & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos;
z2 = (dwRaw[2] & ADC_PRESSR_Z2_Msk) >> ADC_PRESSR_Z2_Pos;
z1 = (dwRaw[2] & ADC_PRESSR_Z1_Msk) >> ADC_PRESSR_Z1_Pos;
dwTsData[2] = (xpos) * (z2 - z1) / z1;
/* PenPress */
if (bTsFlags & TS_PEN_STAT)
{
bTsFlags &= ~TS_PEN_STAT;
/* Invoke PenPress callback */
if (TSDCom_IsCalibrationOk())
TSD_PenPressed(dwTsData[0], dwTsData[1], dwTsData[2]);
}
/* Periodic if data change invoke callback */
if (dwTsData[0] != dwLastTsData[0]
|| dwTsData[1] != dwLastTsData[1]
|| dwTsData[2] != dwLastTsData[2] )
{
/* Register last data */
memcpy(dwLastTsData, dwTsData, sizeof(dwTsData));
/* Invoke PenMoved callback */
if (TSDCom_IsCalibrationOk())
TSD_PenMoved(dwTsData[0], dwTsData[1], dwTsData[2]);
}
}
}
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* Reads and store a touchscreen measurement in the provided array.
* The value stored are:
* - data[0] = XPOS * 1024 / XSCALE
* - data[1] = YPOS * 1024 / YSCALE
* \param pData Array where the measurements will be stored
*/
void TSD_GetRawMeasurement(uint32_t *pData)
{
Adc *pAdc = ADC;
uint32_t xr, yr;
#ifdef TS_XY_SWAP
yr = ADC_GetTsXPosition(pAdc);
xr = ADC_GetTsYPosition(pAdc);
#else
xr = ADC_GetTsXPosition(pAdc);
yr = ADC_GetTsYPosition(pAdc);
#endif
pData[0] = ((xr & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos) * 1024 ;
pData[0] /= ((xr & ADC_XPOSR_XSCALE_Msk) >> ADC_XPOSR_XSCALE_Pos);
pData[1] = ((yr & ADC_YPOSR_YPOS_Msk) >> ADC_YPOSR_YPOS_Pos) * 1024 ;
pData[1] /= ((yr & ADC_YPOSR_YSCALE_Msk) >> ADC_YPOSR_YSCALE_Pos);
}
/**
* Wait pen pressed
*/
void TSD_WaitPenPressed(void)
{
Adc *pAdc = ADC;
uint8_t bFlags = 0;
uint32_t dwStatus;
/* Wait for touch & end of conversion */
while (1)
{
dwStatus = ADC_GetStatus(pAdc);
if (dwStatus & ADC_ISR_PEN) bFlags |= 8;
if (dwStatus & ADC_ISR_XRDY)bFlags |= 1;
if (dwStatus & ADC_ISR_YRDY)bFlags |= 2;
if (dwStatus & ADC_ISR_PRDY)bFlags |= 4;
if (bFlags == 0xF) break;
}
}
/**
* Wait pen released
*/
void TSD_WaitPenReleased(void)
{
Adc *pAdc = ADC;
/* Wait for contact loss */
while((ADC_GetStatus(pAdc) & ADC_ISR_NOPEN) == 0);
}
/**
* Initializes the touchscreen driver and starts the calibration process. When
* finished, the touchscreen is operational.
* The configuration is taken from the board.h of the device being compiled.
* Important: the LCD driver must have been initialized prior to calling this
* function.
*/
void TSD_Initialize(void)
{
Adc *pAdc = ADC;
bTsFlags = 0;
/* Configuration */
PMC_EnablePeripheral(ID_ADC);
ADC_SetClock(pAdc, BOARD_TOUCHSCREEN_ADCCLK, BOARD_MCK);
ADC_SetStartupTime(pAdc, BOARD_TOUCHSCREEN_STARTUP);
ADC_SetTrackingTime(pAdc, BOARD_TOUCHSCREEN_SHTIM);
ADC_SetTriggerPeriod(pAdc, 20000000); /* 20ms */
ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_4_WIRE);
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_SetTsPenDetect(pAdc, 1);
ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE);
}
/**
* Enable/Disable TSD capturing
*/
void TSD_Enable(uint8_t bEnDis)
{
Adc *pAdc = ADC;
if (bEnDis)
{
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_TsCalibration(pAdc);
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
ADC_EnableIt(pAdc, ADC_IER_PEN);
}
else
{
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER);
ADC_DisableIt(pAdc, TS_STATUSES);
ADC_GetStatus(pAdc);
ADC_GetTsXPosition(pAdc);
ADC_GetTsYPosition(pAdc);
ADC_GetTsPressure(pAdc);
}
}
/**
* Do touchscreen calibration
* \param pLcdBuffer LCD buffer to use for displaying the calibration info.
* \return 1 if calibration is Ok, 0 else
*/
uint8_t TSD_Calibrate(void)
{
Adc *pAdc = ADC;
uint8_t ret = 0;
/* Calibration is done only once */
if(TSDCom_IsCalibrationOk()) return 1;
/* Disable touch */
TSD_Enable(0);
/* Enable capturing */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
/* Do calibration */
ret = TSDCom_Calibrate();
/* Configure interrupt generation
Do it only if the calibration is Ok. */
TSD_Enable(ret);
return ret;
}
/**
* Reset/stop the touchscreen
*/
void TSD_DeInitialize(void)
{
Adc *pAdc = ADC;
/* Disable TS related interrupts */
ADC_DisableIt(pAdc, TS_STATUSES);
/* Disable Trigger */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER);
/* Disable TS mode */
ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_NONE);
bTsFlags = 0;
}
/**@}*/
#endif /* #ifdef REG_ADC_TSMR */

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/twid.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
#define TWITIMEOUTMAX 0xfffff
static sXdmad twi_dma;
static sXdmadCfg twi_dmaCfg;
static uint32_t dmaWriteChannel,dmaReadChannel;
static LinkedListDescriporView1 dmaWriteLinkList[1];
static LinkedListDescriporView1 dmaReadLinkList[1];
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** TWI driver callback function.*/
typedef void (*TwiCallback)(Async *);
/** \brief TWI asynchronous transfer descriptor.*/
typedef struct _AsyncTwi {
/** Asynchronous transfer status. */
volatile uint32_t status;
// Callback function to invoke when transfer completes or fails.*/
TwiCallback callback;
/** Pointer to the data buffer.*/
uint8_t *pData;
/** Total number of bytes to transfer.*/
uint32_t num;
/** Number of already transferred bytes.*/
uint32_t transferred;
} AsyncTwi;
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Initializes a TWI DMA Read channel.
*/
static void TWID_DmaInitializeRead(uint8_t TWI_ID)
{
/* Allocate a XDMA channel, Read accesses into TWI_THR */
dmaReadChannel = XDMAD_AllocateChannel( &twi_dma, TWI_ID, XDMAD_TRANSFER_MEMORY);
if ( dmaReadChannel == XDMAD_ALLOC_FAILED )
{
printf("-E- Can't allocate XDMA channel\n\r");
}
XDMAD_PrepareChannel(&twi_dma, dmaReadChannel );
}
/**
* \brief Initializes a TWI DMA write channel.
*/
static void TWID_DmaInitializeWrite(uint8_t TWI_ID)
{
/* Allocate a XDMA channel, Write accesses into TWI_THR */
dmaWriteChannel = XDMAD_AllocateChannel( &twi_dma, XDMAD_TRANSFER_MEMORY, TWI_ID);
if ( dmaWriteChannel == XDMAD_ALLOC_FAILED )
{
printf("-E- Can't allocate XDMA channel\n\r");
}
XDMAD_PrepareChannel(&twi_dma, dmaWriteChannel );
}
/**
* \brief Initializes a TWI driver instance, using the given TWI peripheral.
* \note The peripheral must have been initialized properly before calling this function.
* \param pTwid Pointer to the Twid instance to initialize.
* \param pTwi Pointer to the TWI peripheral to use.
*/
void TWID_Initialize(Twid *pTwid, Twi *pTwi)
{
TRACE_DEBUG( "TWID_Initialize()\n\r" ) ;
assert( pTwid != NULL ) ;
assert( pTwi != NULL ) ;
/* Initialize driver. */
pTwid->pTwi = pTwi;
pTwid->pTransfer = 0;
/* Initialize XDMA driver instance with polling mode */
XDMAD_Initialize( &twi_dma, 1 );
}
/**
* \brief Configure xDMA write linker list for TWI transfer.
*/
static void _xdma_configure_write(uint8_t *buf, uint32_t len, uint8_t TWI_ID)
{
uint32_t i;
uint32_t xdmaCndc, Thr;
Thr = (uint32_t)&(TWI0->TWI_THR);
if(TWI_ID==ID_TWI1)
{
Thr = (uint32_t)&(TWI1->TWI_THR);
}
if(TWI_ID==ID_TWI2)
{
Thr = (uint32_t)&(TWI2->TWI_THR);
}
for ( i = 0; i < 1; i++){
dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
|(( i == len - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)
| len ;
dmaWriteLinkList[i].mbr_sa = (uint32_t)&buf[i];
dmaWriteLinkList[i].mbr_da = Thr;
if ( i == len - 1) dmaWriteLinkList[i].mbr_nda = 0;
else dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[ i + 1 ];
}
twi_dmaCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
| XDMAC_CC_MBSIZE_SINGLE
| XDMAC_CC_DSYNC_MEM2PER
| XDMAC_CC_CSIZE_CHK_1
| XDMAC_CC_DWIDTH_BYTE
| XDMAC_CC_SIF_AHB_IF0
| XDMAC_CC_DIF_AHB_IF1
| XDMAC_CC_SAM_INCREMENTED_AM
| XDMAC_CC_DAM_FIXED_AM
| XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( 0, TWI_ID, XDMAD_TRANSFER_TX ));
xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
| XDMAC_CNDC_NDE_DSCR_FETCH_EN
| XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
| XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED ;
CP15_coherent_dcache_for_dma((uint32_t)&dmaWriteLinkList, ((uint32_t)&dmaWriteLinkList + sizeof(LinkedListDescriporView1) * len));
XDMAD_ConfigureTransfer( &twi_dma, dmaWriteChannel, &twi_dmaCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0]);
}
/**
* \brief Configure xDMA read linker list for TWI transfer.
*/
static void _xdma_configure_read(uint8_t *buf, uint32_t len, uint8_t TWI_ID)
{
uint32_t i;
uint32_t xdmaCndc, Rhr;
Rhr = (uint32_t)&(TWI0->TWI_RHR);
if(TWI_ID==ID_TWI1)
{
Rhr = (uint32_t)&(TWI1->TWI_RHR);
}
if(TWI_ID==ID_TWI2)
{
Rhr = (uint32_t)&(TWI2->TWI_RHR);
}
for ( i = 0; i < 1; i++){
dmaReadLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
| (( i == len - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)
| len ;
dmaReadLinkList[i].mbr_sa = Rhr;
dmaReadLinkList[i].mbr_da = (uint32_t)&buf[i];
if ( i == len - 1)
dmaReadLinkList[i].mbr_nda = 0;
else
dmaReadLinkList[i].mbr_nda = (uint32_t)&dmaReadLinkList[ i + 1 ];
}
twi_dmaCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
| XDMAC_CC_MBSIZE_SINGLE
| XDMAC_CC_DSYNC_PER2MEM
| XDMAC_CC_CSIZE_CHK_1
| XDMAC_CC_DWIDTH_BYTE
| XDMAC_CC_SIF_AHB_IF1
| XDMAC_CC_DIF_AHB_IF0
| XDMAC_CC_SAM_FIXED_AM
| XDMAC_CC_DAM_INCREMENTED_AM
| XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( 0, TWI_ID, XDMAD_TRANSFER_RX ));
xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
| XDMAC_CNDC_NDE_DSCR_FETCH_EN
| XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
| XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;
CP15_coherent_dcache_for_dma((uint32_t)&dmaReadLinkList, ((uint32_t)&dmaReadLinkList + sizeof(LinkedListDescriporView1) * len));
XDMAD_ConfigureTransfer( &twi_dma, dmaReadChannel, &twi_dmaCfg, xdmaCndc, (uint32_t)&dmaReadLinkList[0]);
}
/**
* \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer
* occuring on the bus. This function MUST be called by the interrupt service
* routine of the TWI peripheral if asynchronous read/write are needed.
* \param pTwid Pointer to a Twid instance.
*/
void TWID_Handler( Twid *pTwid )
{
uint32_t status;
AsyncTwi *pTransfer ;
Twi *pTwi ;
assert( pTwid != NULL ) ;
pTransfer = (AsyncTwi*)pTwid->pTransfer ;
assert( pTransfer != NULL ) ;
pTwi = pTwid->pTwi ;
assert( pTwi != NULL ) ;
/* Retrieve interrupt status */
status = TWI_GetMaskedStatus(pTwi);
/* Byte received */
if (TWI_STATUS_RXRDY(status)) {
pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi);
pTransfer->transferred++;
/* check for transfer finish */
if (pTransfer->transferred == pTransfer->num) {
TWI_DisableIt(pTwi, TWI_IDR_RXRDY);
TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
}
/* Last byte? */
else if (pTransfer->transferred == (pTransfer->num - 1)) {
TWI_Stop(pTwi);
}
}
/* Byte sent*/
else if (TWI_STATUS_TXRDY(status)) {
/* Transfer finished ? */
if (pTransfer->transferred == pTransfer->num) {
TWI_DisableIt(pTwi, TWI_IDR_TXRDY);
TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
TWI_SendSTOPCondition(pTwi);
}
/* Bytes remaining */
else {
TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]);
pTransfer->transferred++;
}
}
/* Transfer complete*/
else if (TWI_STATUS_TXCOMP(status)) {
TWI_DisableIt(pTwi, TWI_IDR_TXCOMP);
pTransfer->status = 0;
if (pTransfer->callback) {
pTransfer->callback((Async *)(void*) pTransfer);
}
pTwid->pTransfer = 0;
}
}
/**
* \brief Asynchronously reads data from a slave on the TWI bus. An optional
* callback function is triggered when the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Internal address size in bytes.
* \param pData Data buffer for storing received bytes.
* \param num Number of bytes to read.
* \param pAsync Asynchronous transfer descriptor.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_Read(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync)
{
Twi *pTwi;
AsyncTwi *pTransfer;
uint32_t timeout = 0;
uint32_t i = 0;
uint32_t status;
assert( pTwid != NULL ) ;
pTwi = pTwid->pTwi;
pTransfer = (AsyncTwi *) pTwid->pTransfer;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
/* Check that no transfer is already pending*/
if (pTransfer) {
TRACE_ERROR("TWID_Read: A transfer is already pending\n\r");
return TWID_ERROR_BUSY;
}
/* Asynchronous transfer*/
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 0;
/* Enable read interrupt and start the transfer */
TWI_EnableIt(pTwi, TWI_IER_RXRDY);
TWI_StartRead(pTwi, address, iaddress, isize);
}
/* Synchronous transfer*/
else {
/* Start read*/
TWI_StartRead(pTwi, address, iaddress, isize);
if (num != 1)
{
status = TWI_GetStatus(pTwi);
if(status & TWI_SR_NACK)
TRACE_ERROR("TWID NACK error\n\r");
timeout = 0;
while( ! (status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX))
{
status = TWI_GetStatus(pTwi);
//TRACE_ERROR("TWID status %x\n\r",TWI_GetStatus(pTwi));
}
pData[0] = TWI_ReadByte(pTwi);
for( i = 1; i < num - 1; i++)
{
status = TWI_GetStatus(pTwi);
if(status & TWI_SR_NACK)
TRACE_ERROR("TWID NACK error\n\r");
timeout = 0;
while( ! (status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX))
{
status = TWI_GetStatus(pTwi);
//TRACE_ERROR("TWID status %x\n\r",TWI_GetStatus(pTwi));
}
pData[i] = TWI_ReadByte(pTwi);
}
}
TWI_Stop(pTwi);
status = TWI_GetStatus(pTwi);
if(status & TWI_SR_NACK)
TRACE_ERROR("TWID NACK error\n\r");
timeout = 0;
while( ! (status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX))
{
status = TWI_GetStatus(pTwi);
//TRACE_ERROR("TWID status %x\n\r",TWI_GetStatus(pTwi));
}
pData[i] = TWI_ReadByte(pTwi);
timeout = 0;
status = TWI_GetStatus(pTwi);
while( !(status & TWI_SR_TXCOMP) && (++timeout<TWITIMEOUTMAX))
{
status = TWI_GetStatus(pTwi);
//TRACE_ERROR("TWID status %x\n\r",TWI_GetStatus(pTwi));
}
#if 0
/* Read all bytes, setting STOP before the last byte*/
while (num > 0) {
/* Last byte ?*/
if (num == 1) {
TWI_Stop(pTwi);
}
/* Wait for byte then read and store it*/
timeout = 0;
while( !TWI_ByteReceived(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout BR\n\r");
}
*pData++ = TWI_ReadByte(pTwi);
num--;
}
/* Wait for transfer to be complete */
timeout = 0;
while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout TC\n\r");
}
#endif
}
return 0;
}
/**
* \brief Asynchronously reads data from a slave on the TWI bus. An optional
* callback function is triggered when the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Internal address size in bytes.
* \param pData Data buffer for storing received bytes.
* \param num Number of bytes to read.
* \param pAsync Asynchronous transfer descriptor.
* \param TWI_ID TWI ID for TWI0, TWI1, TWI2.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_DmaRead(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID)
{
Twi *pTwi;
AsyncTwi *pTransfer;
uint32_t timeout = 0;
uint32_t status;
assert( pTwid != NULL ) ;
pTwi = pTwid->pTwi;
pTransfer = (AsyncTwi *) pTwid->pTransfer;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
/* Check that no transfer is already pending*/
if (pTransfer) {
TRACE_ERROR("TWID_Read: A transfer is already pending\n\r");
return TWID_ERROR_BUSY;
}
/* Asynchronous transfer*/
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 0;
/* Enable read interrupt and start the transfer */
TWI_EnableIt(pTwi, TWI_IER_RXRDY);
TWI_StartRead(pTwi, address, iaddress, isize);
}
/* Synchronous transfer*/
else {
TWID_DmaInitializeRead(TWI_ID);
_xdma_configure_read(pData, num, TWI_ID);
/* Start read*/
XDMAD_StartTransfer( &twi_dma, dmaReadChannel );
TWI_StartRead(pTwi, address, iaddress, isize);
while((XDMAD_IsTransferDone(&twi_dma, dmaReadChannel)) && (++timeout<TWITIMEOUTMAX));
XDMAD_StopTransfer( &twi_dma, dmaReadChannel );
status = TWI_GetStatus(pTwi);
timeout=0;
while( !(status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX));
TWI_Stop(pTwi);
TWI_ReadByte(pTwi);
status = TWI_GetStatus(pTwi);
timeout=0;
while( !(status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX));
TWI_ReadByte(pTwi);
status = TWI_GetStatus(pTwi);
timeout=0;
while( !(status & TWI_SR_TXCOMP) && (++timeout<TWITIMEOUTMAX));
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout Read\n\r");
}
XDMAD_FreeChannel(&twi_dma, dmaReadChannel);
}
return 0;
}
/**
* \brief Asynchronously sends data to a slave on the TWI bus. An optional callback
* function is invoked whenever the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Number of internal address bytes.
* \param pData Data buffer for storing received bytes.
* \param num Data buffer to send.
* \param pAsync Asynchronous transfer descriptor.
* \param TWI_ID TWI ID for TWI0, TWI1, TWI2.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_DmaWrite(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync,
uint8_t TWI_ID)
{
Twi *pTwi = pTwid->pTwi;
AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
uint32_t timeout = 0;
uint32_t status;
//uint8_t singleTransfer = 0;
assert( pTwi != NULL ) ;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
// if(num == 1) singleTransfer = 1;
/* Check that no transfer is already pending */
if (pTransfer) {
TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");
return TWID_ERROR_BUSY;
}
/* Asynchronous transfer */
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 1;
/* Enable write interrupt and start the transfer */
TWI_StartWrite(pTwi, address, iaddress, isize, *pData);
TWI_EnableIt(pTwi, TWI_IER_TXRDY);
}
/* Synchronous transfer*/
else {
CP15_coherent_dcache_for_dma ( (uint32_t)pData, (uint32_t)pData );
TWID_DmaInitializeWrite(TWI_ID);
_xdma_configure_write(pData, num, TWI_ID);
/* Set slave address and number of internal address bytes. */
pTwi->TWI_MMR = 0;
pTwi->TWI_MMR = (isize << 8) | (address << 16);
/* Set internal address bytes. */
pTwi->TWI_IADR = 0;
pTwi->TWI_IADR = iaddress;
XDMAD_StartTransfer( &twi_dma, dmaWriteChannel );
while(XDMAD_IsTransferDone(&twi_dma, dmaWriteChannel));
XDMAD_StopTransfer( &twi_dma, dmaWriteChannel );
status = TWI_GetStatus(pTwi);
timeout = 0;
while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) )
{
status = TWI_GetStatus(pTwi);
}
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout TXRDY\n\r");
}
/* Send a STOP condition */
TWI_Stop(pTwi);
status = TWI_GetStatus(pTwi);
timeout = 0;
while( !(status & TWI_SR_TXCOMP) && (++timeout<TWITIMEOUTMAX))
{
status = TWI_GetStatus(pTwi);
}
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout Write\n\r");
}
CP15_invalidate_dcache_for_dma ( (uint32_t)pData, (uint32_t)(pData) );
XDMAD_FreeChannel(&twi_dma, dmaWriteChannel);
}
return 0;
}
/**
* \brief Asynchronously sends data to a slave on the TWI bus. An optional callback
* function is invoked whenever the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Number of internal address bytes.
* \param pData Data buffer for storing received bytes.
* \param num Data buffer to send.
* \param pAsync Asynchronous transfer descriptor.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_Write(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync)
{
Twi *pTwi = pTwid->pTwi;
AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
uint32_t timeout = 0;
uint32_t status;
uint8_t singleTransfer = 0;
assert( pTwi != NULL ) ;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
if(num == 1) singleTransfer = 1;
/* Check that no transfer is already pending */
if (pTransfer) {
TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");
return TWID_ERROR_BUSY;
}
/* Asynchronous transfer */
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 1;
/* Enable write interrupt and start the transfer */
TWI_StartWrite(pTwi, address, iaddress, isize, *pData);
TWI_EnableIt(pTwi, TWI_IER_TXRDY);
}
/* Synchronous transfer*/
else {
// Start write
TWI_StartWrite(pTwi, address, iaddress, isize, *pData++);
num--;
if (singleTransfer) {
/* Send a STOP condition */
TWI_SendSTOPCondition(pTwi);
}
status = TWI_GetStatus(pTwi);
if(status & TWI_SR_NACK)
TRACE_ERROR("TWID NACK error\n\r");
while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) )
{
status = TWI_GetStatus(pTwi);
}
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout BS\n\r");
}
timeout = 0;
/* Send all bytes */
while (num > 0) {
/* Wait before sending the next byte */
timeout = 0;
TWI_WriteByte(pTwi, *pData++);
status = TWI_GetStatus(pTwi);
if(status & TWI_SR_NACK)
TRACE_ERROR("TWID NACK error\n\r");
while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) )
{
status = TWI_GetStatus(pTwi);
}
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout BS\n\r");
}
num--;
}
/* Wait for actual end of transfer */
timeout = 0;
if (!singleTransfer) {
/* Send a STOP condition */
TWI_SendSTOPCondition(pTwi);
}
while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
TRACE_ERROR("TWID Timeout TC2\n\r");
}
}
return 0;
}

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FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/wav.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdio.h>
/*----------------------------------------------------------------------------
* Definiation
*----------------------------------------------------------------------------*/
/* WAV letters "RIFF" */
#define WAV_CHUNKID 0x46464952
/* WAV letters "WAVE"*/
#define WAV_FORMAT 0x45564157
/* WAV letters "fmt "*/
#define WAV_SUBCHUNKID 0x20746D66
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Check if the header of a Wav file is valid ot not.
*
* \param file Buffer holding the file to examinate.
* \return 1 if the header of a Wav file is valid; otherwise returns 0.
*/
unsigned char WAV_IsValid(const WavHeader *header)
{
return ((header->chunkID == WAV_CHUNKID)
&& (header->format == WAV_FORMAT)
&& (header->subchunk1Size == 0x10));
}
/**
* \brief Display the information of the WAV file (sample rate, stereo/mono
* and frame size).
*
* \param header Wav head information.
*/
void WAV_DisplayInfo(const WavHeader *header)
{
printf( "Wave file header information\n\r");
printf( "--------------------------------\n\r");
printf( " - Chunk ID = 0x%08X\n\r", header->chunkID);
printf( " - Chunk Size = %u\n\r", header->chunkSize);
printf( " - Format = 0x%08X\n\r", header->format);
printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID);
printf( " - Subchunk1 Size = %u\n\r", header->subchunk1Size);
printf( " - Audio Format = 0x%04X\n\r", header->audioFormat);
printf( " - Num. Channels = %d\n\r", header->numChannels);
printf( " - Sample Rate = %u\n\r", header->sampleRate);
printf( " - Byte Rate = %u\n\r", header->byteRate);
printf( " - Block Align = %d\n\r", header->blockAlign);
printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample);
printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID);
printf( " - Subchunk2 Size = %u\n\r", header->subchunk2Size);
}

484
FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libboard_sama5d4x-ek/source/wm8904.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation WM8904 driver.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Type
*----------------------------------------------------------------------------*/
typedef struct {
uint16_t value;
uint8_t address;
}WM8904_PARA;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Read data from WM8904 Register.
*
* \param pTwid Pointer to twi driver structure
* \param device Twi slave address.
* \param regAddr Register address to read.
* \return value in the given register.
*/
uint16_t WM8904_Read(Twid *pTwid,
uint32_t device,
uint32_t regAddr)
{
uint16_t bitsDataRegister;
uint8_t Tdata[2]={0,0};
TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0);
bitsDataRegister = (Tdata[0] << 8) | Tdata[1];
return bitsDataRegister;
}
/**
* \brief Write data to WM8904 Register.
*
* \param pTwid Pointer to twi driver structure
* \param device Twi slave address.
* \param regAddr Register address to read.
* \param data Data to write
*/
void WM8904_Write(Twid *pTwid,
uint32_t device,
uint32_t regAddr,
uint16_t data)
{
uint8_t tmpData[2];
tmpData[0] = (data & 0xff00) >> 8;
tmpData[1] = data & 0xff;
TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0);
}
static WM8904_PARA wm8904_access_slow[]=
{
{ 0x0000, 0}, /** R0 - SW Reset and ID */
{ 0x001A, 4}, /** R4 - Bias Control 0 */
{ 0x0047, 5}, /** R5 - VMID Control 0 */ /*insert_delay_ms 5*/
{ 0x0043, 5}, /** R5 - VMID Control 0 */
{ 0x000B, 4}, /** R4 - Bias Control 0 */
{ 0x0003, 0x0C}, /** R12 - Power Management 0 CC */
{ 0x0003, 0x0E}, /** R14 - Power Management 2 */
{ 0x000C, 0x12}, /** R18 - Power Management 6 */
{ 0x0000, 0x21}, /** R33 - DAC Digital 1 */
{ 0x0000, 0x3D}, /** R61 - Analogue OUT12 ZC */
{ 0x0001, 0x62}, /** R98 - Charge Pump 0 */
{ 0x0005, 0x68}, /** R104 - Class W 0 */
//FLL setting,32.768KHZ MCLK input,12.288M output.
{ 0x0000, 0x74}, /** R116 - FLL Control 1 */
{ 0x0704, 0x75}, /** R117 - FLL Control 2 */
{ 0x8000, 0x76}, /** R118 - FLL Control 3 */
{ 0x1760, 0x77}, /** R119 - FLL Control 4 */
{ 0x0005, 0x74}, /** R116 - FLL Control 1 */ /*insert_delay_ms 5*/
{ 0x0C05, 0x15}, /** R21 - Clock Rates 1 */
{ 0x845E, 0x14}, /** R20 - Clock Rates 0 */
{ 0x4006, 0x16}, /** R22 - Clock Rates 2 */
////////////////WM8904 IIS master
//BCLK=12.288MHz/8=1.536MHz
//LRCK=1.536MHz/32=48KHz
//{ 0x0042, 0x18}, /** R24 - Audio Interface 0 */
{ 0x0042, 0x19}, /** R25 - Audio Interface 1 */
{ 0x00E8, 0x1A}, /** R26 - Audio Interface 2 */
{ 0x0820, 0x1B}, /** R27 - Audio Interface 3 */
////////////////ADC
{ 0x0003, 0x0C}, /** R12 - Power Management 0 */
{ 0x000F, 0x12}, /** R18 - Power Management 6 */ /*insert_delay_ms 5*/
{ 0x0010, 0x2C}, /** R44 - Analogue Left Input 0 */
{ 0x0010, 0x2D}, /** R45 - Analogue Right Input 0 */
{ 0x0004, 0x2E}, /** R46 - Analogue Left Input 1 */
{ 0x0004, 0x2F}, /** R47 - Analogue Right Input 1 */
{ 0x0011, 0x5A}, /** R90 - Analogue HP 0 */
{ 0x0033, 0x5A}, /** R90 - Analogue HP 0 */
{ 0x000F, 0x43}, /** R67 - DC Servo 0 */
{ 0x00F0, 0x44}, /** R68 - DC Servo 1 */ /*insert_delay_ms 100*/
//{ 0x0000, 0xFF}, /** end */
{ 0x0077, 0x5A}, /** R90 - Analogue HP 0 */
{ 0x00FF, 0x5A}, /** R90 - Analogue HP 0 */
{ 0x00B9, 0x39}, /** R57 - Analogue OUT1 Left */
{ 0x00B9, 0x3A}, /** R58 - Analogue OUT1 Right */
//{ 0x0150, 0x18} ;Loopback
};
static WM8904_PARA wm8904_access_main[] =
{
//{ 0x8904, 0}, /** R0 - SW Reset and ID */
//{ 0x0000, 1}, /** R1 - Revision */
//{ 0x0000, 2}, /** R2 */
//{ 0x0000, 3}, /** R3 */
{ 0x0019, 4}, /** R4 - Bias Control 0 */
{ 0x0043, 5}, /** R5 - VMID Control 0 */
//{ 0x0003, 6}, /** R6 - Mic Bias Control 0 */
//{ 0xC000, 7}, /** R7 - Mic Bias Control 1 */
//{ 0x001E, 8}, /** R8 - Analogue DAC 0 */
//{ 0xFFFF, 9}, /** R9 - mic Filter Control */
//{ 0x0001, 10}, /** R10 - Analogue ADC 0 */
//{ 0x0000, 11}, /** R11 */
{ 0x0003, 12}, /** R12 - Power Management 0 */
//{ 0x0000, 13}, /** R13 */
{ 0x0003, 14}, /** R14 - Power Management 2 */
//{ 0x0003, 15}, /** R15 - Power Management 3 */
//{ 0x0000, 16}, /** R16 */
//{ 0x0000, 17}, /** R17 */
{ 0x000F, 18}, /** R18 - Power Management 6 */
//{ 0x0000, 19}, /** R19 */
{ 0x845E, 20}, /** R20 - Clock Rates 0 */
//{ 0x3C07, 21}, /** R21 - Clock Rates 1 */
{ 0x0006, 22}, /** R22 - Clock Rates 2 */
//{ 0x0000, 23}, /** R23 */
//{ 0x1FFF, 24}, /** R24 - Audio Interface 0 */
{ 0x404A, 25}, /** R25 - Audio Interface 1 */
//{ 0x0004, 26}, /** R26 - Audio Interface 2 */
{ 0x0840, 27}, /** R27 - Audio Interface 3 */
//{ 0x0000, 28}, /** R28 */
//{ 0x0000, 29}, /** R29 */
//{ 0x00FF, 30}, /** R30 - DAC Digital Volume Left */
//{ 0x00FF, 31}, /** R31 - DAC Digital Volume Right */
//{ 0x0FFF, 32}, /** R32 - DAC Digital 0 */
{ 0x0000, 33}, /** R33 - DAC Digital 1 */
//{ 0x0000, 34}, /** R34 */
//{ 0x0000, 35}, /** R35 */
//{ 0x00FF, 36}, /** R36 - ADC Digital Volume Left */
//{ 0x00FF, 37}, /** R37 - ADC Digital Volume Right */
//{ 0x0073, 38}, /** R38 - ADC Digital 0 */
//{ 0x1800, 39}, /** R39 - Digital Microphone 0 */
//{ 0xDFEF, 40}, /** R40 - DRC 0 */
//{ 0xFFFF, 41}, /** R41 - DRC 1 */
//{ 0x003F, 42}, /** R42 - DRC 2 */
//{ 0x07FF, 43}, /** R43 - DRC 3 */
{ 0x0005, 44}, /** R44 - Analogue Left Input 0 */
{ 0x0005, 45}, /** R45 - Analogue Right Input 0 */
{ 0x0000, 46}, /** R46 - Analogue Left Input 1 */
{ 0x0000, 47}, /** R47 - Analogue Right Input 1 */
//{ 0x0000, 48}, /** R48 */
//{ 0x0000, 49}, /** R49 */
//{ 0x0000, 50}, /** R50 */
//{ 0x0000, 51}, /** R51 */
//{ 0x0000, 52}, /** R52 */
//{ 0x0000, 53}, /** R53 */
//{ 0x0000, 54}, /** R54 */
//{ 0x0000, 55}, /** R55 */
//{ 0x0000, 56}, /** R56 */
//{ 0x017F, 57}, /** R57 - Analogue OUT1 Left */
{ 0x00AD, 58}, /** R58 - Analogue OUT1 Right */
//{ 0x017F, 59}, /** R59 - Analogue OUT2 Left */
//{ 0x017F, 60}, /** R60 - Analogue OUT2 Right */
//{ 0x000F, 61}, /** R61 - Analogue OUT12 ZC */
//{ 0x0000, 62}, /** R62 */
//{ 0x0000, 63}, /** R63 */
//{ 0x0000, 64}, /** R64 */
//{ 0x0000, 65}, /** R65 */
//{ 0x0000, 66}, /** R66 */
{ 0x0003, 67}, /** R67 - DC Servo 0 */
//{ 0xFFFF, 68}, /** R68 - DC Servo 1 */
//{ 0x0F0F, 69}, /** R69 - DC Servo 2 */
//{ 0x0000, 70}, /** R70 */
//{ 0x007F, 71}, /** R71 - DC Servo 4 */
//{ 0x007F, 72}, /** R72 - DC Servo 5 */
//{ 0x00FF, 73}, /** R73 - DC Servo 6 */
//{ 0x00FF, 74}, /** R74 - DC Servo 7 */
//{ 0x00FF, 75}, /** R75 - DC Servo 8 */
//{ 0x00FF, 76}, /** R76 - DC Servo 9 */
//{ 0x0FFF, 77}, /** R77 - DC Servo Readback 0 */
//{ 0x0000, 78}, /** R78 */
//{ 0x0000, 79}, /** R79 */
//{ 0x0000, 80}, /** R80 */
//{ 0x0000, 81}, /** R81 */
//{ 0x0000, 82}, /** R82 */
//{ 0x0000, 83}, /** R83 */
//{ 0x0000, 84}, /** R84 */
//{ 0x0000, 85}, /** R85 */
//{ 0x0000, 86}, /** R86 */
//{ 0x0000, 87}, /** R87 */
//{ 0x0000, 88}, /** R88 */
//{ 0x0000, 89}, /** R89 */
{ 0x00FF, 90}, /** R90 - Analogue HP 0 */
//{ 0x0000, 91}, /** R91 */
//{ 0x0000, 92}, /** R92 */
//{ 0x0000, 93}, /** R93 */
//{ 0x00FF, 94}, /** R94 - Analogue Lineout 0 */
//{ 0x0000, 95}, /** R95 */
//{ 0x0000, 96}, /** R96 */
//{ 0x0000, 97}, /** R97 */
{ 0x0001, 98}, /** R98 - Charge Pump 0 */
//{ 0x0000, 99}, /** R99 */
//{ 0x0000, 100}, /** R100 */
//{ 0x0000, 101}, /** R101 */
//{ 0x0000, 102}, /** R102 */
//{ 0x0000, 103}, /** R103 */
{ 0x0005, 104}, /** R104 - Class W 0 */
//{ 0x0000, 105}, /** R105 */
//{ 0x0000, 106}, /** R106 */
//{ 0x0000, 107}, /** R107 */
//{ 0x011F, 108}, /** R108 - Write Sequencer 0 */
//{ 0x7FFF, 109}, /** R109 - Write Sequencer 1 */
//{ 0x4FFF, 110}, /** R110 - Write Sequencer 2 */
//{ 0x003F, 111}, /** R111 - Write Sequencer 3 */
//{ 0x03F1, 112}, /** R112 - Write Sequencer 4 */
//{ 0x0000, 113}, /** R113 */
//{ 0x0000, 114}, /** R114 */
//{ 0x0000, 115}, /** R115 */
{ 0x0004, 116}, /** R116 - FLL Control 1 */
{ 0x0704, 117}, /** R117 - FLL Control 2 */
{ 0x8000, 118}, /** R118 - FLL Control 3 */
{ 0x1760, 119}, /** R119 - FLL Control 4 */
//{ 0x001B, 120}, /** R120 - FLL Control 5 */
//{ 0x0014, 121}, /** R121 - GPIO Control 1 */
//{ 0x0010, 122}, /** R122 - GPIO Control 2 */
//{ 0x0010, 123}, /** R123 - GPIO Control 3 */
//{ 0x0000, 124}, /** R124 - GPIO Control 4 */
//{ 0x0000, 125}, /** R125 */
//{ 0x000A, 126}, /** R126 - Digital Pulls */
//{ 0x07FF, 127}, /** R127 - Interrupt Status */
//{ 0x03FF, 128}, /** R128 - Interrupt Status Mask */
//{ 0x03FF, 129}, /** R129 - Interrupt Polarity */
//{ 0x03FF, 130}, /** R130 - Interrupt Debounce */
//{ 0x0000, 131}, /** R131 */
//{ 0x0000, 132}, /** R132 */
//{ 0x0000, 133}, /** R133 */
//{ 0x0001, 134}, /** R134 - EQ1 */
//{ 0x001F, 135}, /** R135 - EQ2 */
//{ 0x001F, 136}, /** R136 - EQ3 */
//{ 0x001F, 137}, /** R137 - EQ4 */
//{ 0x001F, 138}, /** R138 - EQ5 */
//{ 0x001F, 139}, /** R139 - EQ6 */
//{ 0xFFFF, 140}, /** R140 - EQ7 */
//{ 0xFFFF, 141}, /** R141 - EQ8 */
//{ 0xFFFF, 142}, /** R142 - EQ9 */
//{ 0xFFFF, 143}, /** R143 - EQ10 */
//{ 0xFFFF, 144}, /** R144 - EQ11 */
//{ 0xFFFF, 145}, /** R145 - EQ12 */
//{ 0xFFFF, 146}, /** R146 - EQ13 */
//{ 0xFFFF, 147}, /** R147 - EQ14 */
//{ 0xFFFF, 148}, /** R148 - EQ15 */
//{ 0xFFFF, 149}, /** R149 - EQ16 */
//{ 0xFFFF, 150}, /** R150 - EQ17 */
//{ 0xFFFF, 151}, /** R151wm8523_dai - EQ18 */
//{ 0xFFFF, 152}, /** R152 - EQ19 */
//{ 0xFFFF, 153}, /** R153 - EQ20 */
//{ 0xFFFF, 154}, /** R154 - EQ21 */
//{ 0xFFFF, 155}, /** R155 - EQ22 */
//{ 0xFFFF, 156}, /** R156 - EQ23 */
//{ 0xFFFF, 157}, /** R157 - EQ24 */
//{ 0x0000, 158}, /** R158 */
//{ 0x0000, 159}, /** R159 */
//{ 0x0000, 160}, /** R160 */
//{ 0x0002, 161}, /** R161 - Control Interface Test 1 */
//{ 0x0000, 162}, /** R162 */
//{ 0x0000, 163}, /** R163 */
//{ 0x0000, 164}, /** R164 */
//{ 0x0000, 165}, /** R165 */
//{ 0x0000, 166}, /** R166 */
//{ 0x0000, 167}, /** R167 */
//{ 0x0000, 168}, /** R168 */
//{ 0x0000, 169}, /** R169 */
//{ 0x0000, 170}, /** R170 */
//{ 0x0000, 171}, /** R171 */
//{ 0x0000, 172}, /** R172 */
//{ 0x0000, 173}, /** R173 */
//{ 0x0000, 174}, /** R174 */
//{ 0x0000, 175}, /** R175 */
//{ 0x0000, 176}, /** R176 */
//{ 0x0000, 177}, /** R177 */
//{ 0x0000, 178}, /** R178 */
//{ 0x0000, 179}, /** R179 */
//{ 0x0000, 180}, /** R180 */
//{ 0x0000, 181}, /** R181 */
//{ 0x0000, 182}, /** R182 */
//{ 0x0000, 183}, /** R183 */
//{ 0x0000, 184}, /** R184 */
//{ 0x0000, 185}, /** R185 */
//{ 0x0000, 186}, /** R186 */
//{ 0x0000, 187}, /** R187 */
//{ 0x0000, 188}, /** R188 */
//{ 0x0000, 189}, /** R189 */
//{ 0x0000, 190}, /** R190 */
//{ 0x0000, 191}, /** R191 */
//{ 0x0000, 192}, /** R192 */
//{ 0x0000, 193}, /** R193 */
//{ 0x0000, 194}, /** R194 */
//{ 0x0000, 195}, /** R195 */
//{ 0x0000, 196}, /** R196 */
//{ 0x0000, 197}, /** R197 */
//{ 0x0000, 198}, /** R198 */
//{ 0x0000, 199}, /** R199 */
//{ 0x0000, 200}, /** R200 */
//{ 0x0000, 201}, /** R201 */
//{ 0x0000, 202}, /** R202 */
//{ 0x0000, 203}, /** R203 */
//{ 0x0070, 204}, /** R204 - Analogue Output Bias 0 */
//{ 0x0000, 205}, /** R205 */
//{ 0x0000, 206}, /** R206 */
//{ 0x0000, 207}, /** R207 */
//{ 0x0000, 208}, /** R208 */
//{ 0x0000, 209}, /** R209 */
//{ 0x0000, 210}, /** R210 */
//{ 0x0000, 211}, /** R211 */
//{ 0x0000, 212}, /** R212 */
//{ 0x0000, 213}, /** R213 */
//{ 0x0000, 214}, /** R214 */
//{ 0x0000, 215}, /** R215 */
//{ 0x0000, 216}, /** R216 */
//{ 0x0000, 217}, /** R217 */
//{ 0x0000, 218}, /** R218 */
//{ 0x0000, 219}, /** R219 */
//{ 0x0000, 220}, /** R220 */
//{ 0x0000, 221}, /** R221 */
//{ 0x0000, 222}, /** R222 */
//{ 0x0000, 223}, /** R223 */
//{ 0x0000, 224}, /** R224 */
//{ 0x0000, 225}, /** R225 */
//{ 0x0000, 226}, /** R226 */
//{ 0x0000, 227}, /** R227 */
//{ 0x0000, 228}, /** R228 */
//{ 0x0000, 229}, /** R229 */
//{ 0x0000, 230}, /** R230 */
//{ 0x0000, 231}, /** R231 */
//{ 0x0000, 232}, /** R232 */
//{ 0x0000, 233}, /** R233 */
//{ 0x0000, 234}, /** R234 */
//{ 0x0000, 235}, /** R235 */
//{ 0x0000, 236}, /** R236 */
//{ 0x0000, 237}, /** R237 */
//{ 0x0000, 238}, /** R238 */
//{ 0x0000, 239}, /** R239 */
//{ 0x0000, 240}, /** R240 */
//{ 0x0000, 241}, /** R241 */
//{ 0x0000, 242}, /** R242 */
//{ 0x0000, 243}, /** R243 */
//{ 0x0000, 244}, /** R244 */
//{ 0x0000, 245}, /** R245 */
//{ 0x0000, 246}, /** R246 */
//{ 0x0000, 247}, /** R247 - FLL NCO Test 0 */
//{ 0x0019, 248}, /** R248 - FLL NCO Test 1 */
{ 0x55AA, 255} /** end */
};
static void DelayMS(signed int delay)
{
uint32_t count;
for(;delay>0;delay--)
for(count=0;count<(BOARD_MCK/1000000);count++);
}
uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK)
{
uint8_t count, size;
uint16_t data = 0;
// Reset (write Reg@0x0 to reset)
WM8904_Write(pTwid, device, 0, 0xFFFF);
for(data=0;data<1000;data++);
//wait ready
while(data!=0x8904)
data=WM8904_Read(pTwid, device, 0);
if (PMC_MCKR_CSS_SLOW_CLK == PCK)
{
{
size = sizeof(wm8904_access_slow)/4+1;
for(count=0; count<size; count++)
{
WM8904_Write(pTwid, device, wm8904_access_slow[count].address, wm8904_access_slow[count].value);
if(((wm8904_access_slow[count].address==0x05)&&(wm8904_access_slow[count].value==0x0047))
||((wm8904_access_slow[count].address==0x74)&&(wm8904_access_slow[count].value==0x0005))
||((wm8904_access_slow[count].address==0x12)&&(wm8904_access_slow[count].value==0x000F)))
{
DelayMS(5);
}
if (((wm8904_access_slow[count].address==0x44)&&(wm8904_access_slow[count].value==0x00F0))
||((wm8904_access_slow[count].address==0x3A)&&(wm8904_access_slow[count].value==0x00B9)))
{
DelayMS(100);
}
}
}
}
else if (PMC_MCKR_CSS_MAIN_CLK == PCK)
{
for(count=0;count<255;count++)
{
if(wm8904_access_main[count].address<255)
{
WM8904_Write(pTwid, device, wm8904_access_main[count].address, wm8904_access_main[count].value);
}
else
{
break;
}
}
}
else
{
printf("W: PCK not supported! \n\r");
while(1);
}
return 0;
}
void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device)
{
//{ 0x0005, 44}, /** R44 - Analogue Left Input 0 */
//{ 0x0005, 45}, /** R45 - Analogue Right Input 0 */
//{ 0x0000, 46}, /** R46 - Analogue Left Input 1 */
//{ 0x0010, 47}, /** R47 - Analogue Right Input 1 */
WM8904_Write(pTwid, device, 0x2C, 0x0008);
WM8904_Write(pTwid, device, 0x2D, 0x0005);
WM8904_Write(pTwid, device, 0x2E, 0x0000);
WM8904_Write(pTwid, device, 0x2F, 0x0010);
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup dmad_module
*
* \section DmaHw Dma Hardware Interface Usage
* <ul>
* <li> The DMA controller can handle the transfer between peripherals and memory
* and so receives the triggers from the peripherals. The hardware interface number
* are getting from DMAIF_Get_ChannelNumber().</li>
* <li> DMAIF_IsValidatedPeripherOnDma() helps to check if the given DMAC has associated
* peripheral identifier coded by the given peripheral.</li>
*
* </ul>
*/
/*@{*/
/*@}*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <board.h>
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Array of DMA Channel definition for SAMA5 chip*/
static const XdmaHardwareInterface xdmaHwIf[] = {
/* dmac, peripheral, T/R, Channel Number*/
{0, ID_HSMCI0, 0, 0},
{0, ID_HSMCI0, 1, 0},
{0, ID_HSMCI1, 0, 1},
{0, ID_HSMCI1, 1, 1},
{0, ID_TWI0, 0, 2},
{0, ID_TWI0, 1, 3},
{0, ID_TWI1, 0, 4},
{0, ID_TWI1, 1, 5},
{0, ID_TWI2, 0, 6},
{0, ID_TWI2, 1, 7},
{0, ID_TWI3, 0, 8},
{0, ID_TWI3, 1, 9},
{0, ID_SPI0, 0, 10},
{0, ID_SPI0, 1, 11},
{0, ID_SPI1, 0, 12},
{0, ID_SPI1, 1, 13},
{0, ID_SPI2, 0, 14},
{0, ID_SPI2, 1, 15},
{0, ID_USART2, 0, 16},
{0, ID_USART2, 1, 17},
{0, ID_USART3, 0, 18},
{0, ID_USART3, 1, 19},
{0, ID_USART4, 0, 20},
{0, ID_USART4, 1, 21},
{0, ID_UART0, 0, 22},
{0, ID_UART0, 1, 23},
{0, ID_UART1, 0, 24},
{0, ID_UART1, 1, 25},
{0, ID_SSC0, 0, 26},
{0, ID_SSC0, 1, 27},
{0, ID_SSC1, 0, 28},
{0, ID_SSC1, 1, 29},
{0, ID_DBGU, 0, 30},
{0, ID_DBGU, 1, 31},
{0, ID_ADC, 1, 32},
{0, ID_SMD, 1, 33},
{0, ID_SMD, 1, 34},
{0, ID_MSADCC, 1, 35},
{0, ID_USART0, 0, 36},
{0, ID_USART0, 1, 37},
{0, ID_USART1, 0, 38},
{0, ID_USART1, 1, 39},
{0, ID_AES, 1, 40},
{0, ID_AES, 0, 41},
{0, ID_TDES, 0, 42},
{0, ID_TDES, 1, 43},
{0, ID_SHA, 0, 44},
// {0, ID_CTB, 1, 45},
{0, ID_CATB, 0, 46},
{0, ID_CATB, 1, 47},
/* dmac 1 */
{1, ID_HSMCI0, 0, 0},
{1, ID_HSMCI0, 1, 0},
{1, ID_HSMCI1, 0, 1},
{1, ID_HSMCI1, 1, 1},
{1, ID_TWI0, 0, 2},
{1, ID_TWI0, 1, 3},
{1, ID_TWI1, 0, 4},
{1, ID_TWI1, 1, 5},
{1, ID_TWI2, 0, 6},
{1, ID_TWI2, 1, 7},
{1, ID_TWI3, 0, 8},
{1, ID_TWI3, 1, 9},
{1, ID_SPI0, 0, 10},
{1, ID_SPI0, 1, 11},
{1, ID_SPI1, 0, 12},
{1, ID_SPI1, 1, 13},
{1, ID_SPI2, 0, 14},
{1, ID_SPI2, 1, 15},
{1, ID_USART2, 0, 16},
{1, ID_USART2, 1, 17},
{1, ID_USART3, 0, 18},
{1, ID_USART3, 1, 19},
{1, ID_USART4, 0, 20},
{1, ID_USART4, 1, 21},
{1, ID_UART0, 0, 22},
{1, ID_UART0, 1, 23},
{1, ID_UART1, 0, 24},
{1, ID_UART1, 1, 25},
{1, ID_SSC0, 0, 26},
{1, ID_SSC0, 1, 27},
{1, ID_SSC1, 0, 28},
{1, ID_SSC1, 1, 29},
{1, ID_DBGU, 0, 30},
{1, ID_DBGU, 1, 31},
{1, ID_ADC, 1, 32},
{1, ID_SMD, 1, 33},
{1, ID_SMD, 1, 34},
};
/*----------------------------------------------------------------------------
* Consts
*----------------------------------------------------------------------------*/
/** Number of recognized peripheral identifier code for DMA0/1. */
#define NUMPERIPHERAL (sizeof(xdmaHwIf) / sizeof (XdmaHardwareInterface))
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Get peripheral identifier coded for hardware handshaking interface
*
* \param bDmac DMA Controller number.
* \param bPeriphID Peripheral ID.
* \param bTransfer Transfer type 0: Tx, 1 :Rx.
* \return 0-15 peripheral identifier coded.
* 0xff : no associated peripheral identifier coded.
*/
uint8_t XDMAIF_Get_ChannelNumber (uint8_t bXdmac,
uint8_t bPeriphID,
uint8_t bTransfer)
{
uint8_t i;
for (i = 0; i < NUMPERIPHERAL; i++)
{
if ((xdmaHwIf[i].bXdmac == bXdmac) && (xdmaHwIf[i].bPeriphID == bPeriphID) && (xdmaHwIf[i].bTransfer == bTransfer))
{
return xdmaHwIf[i].bIfID;
}
}
return 0xff;
}
/**
* \brief Check if the given DMAC has associated peripheral identifier coded by
* the given peripheral.
*
* \param bDmac DMA Controller number.
* \param bPeriphID Peripheral ID (0xff : memory only).
* \return 1: Is a validated peripher. 0: no associated peripheral identifier coded.
*/
uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bXdmac, uint8_t bPeriphID)
{
uint8_t i;
/* It is always validated when transfer to memory */
if (bPeriphID == 0xFF) {
return 1;
}
for (i = 0; i < NUMPERIPHERAL; i++)
{
if ((xdmaHwIf[i].bXdmac == bXdmac) && (xdmaHwIf[i].bPeriphID == bPeriphID))
{
return 1;
}
}
return 0;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup xdmad_module
*
* \section Xdma xDma Configuration Usage
*
* To configure a XDMA channel, the user has to follow these few steps :
* <ul>
* <li> Initialize a XDMA driver instance by XDMAD_Initialize().</li>
* <li> choose an available (disabled) channel using XDMAD_AllocateChannel().</li>
* <li> After the XDMAC selected channel has been programmed, XDMAD_PrepareChannel() is to enable
* clock and dma peripheral of the DMA, and set Configuration register to set up the transfer type
* (memory or non-memory peripheral for source and destination) and flow control device.</li>
* <li> Invoke XDMAD_StartTransfer() to start DMA transfer or XDMAD_StopTransfer() to force stop DMA transfer.</li>
* <li> Once the buffer of data is transferred, XDMAD_IsTransferDone() checks if DMA transfer is finished.</li>
* <li> XDMAD_Handler() handles XDMA interrupt, and invoking XDMAD_SetCallback() if provided.</li>
* </ul>
*
* Related files:\n
* \ref xdmad.h\n
* \ref xdmad.c.\n
*/
/** \file */
/** \addtogroup dmad_functions
@{*/
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* \brief Try to allocate a DMA channel for on given controller.
* \param pDmad Pointer to DMA driver instance.
* \param bXdmac xDMA controller ID (0 ~ 1).
* \param bSrcID Source peripheral ID, 0xFF for memory.
* \param bDstID Destination peripheral ID, 0xFF for memory.
* \return Channel number if allocation sucessful, return
* DMAD_ALLOC_FAILED if allocation failed.
*/
static uint32_t XDMAD_AllocateXdmacChannel( sXdmad *pXdmad,
uint8_t bXdmac,
uint8_t bSrcID,
uint8_t bDstID)
{
uint32_t i;
/* Can't support peripheral to peripheral */
if ((( bSrcID != XDMAD_TRANSFER_MEMORY ) && ( bDstID != XDMAD_TRANSFER_MEMORY )))
{
return XDMAD_ALLOC_FAILED;
}
/* dma transfer from peripheral to memory */
if ( bDstID == XDMAD_TRANSFER_MEMORY)
{
if( (!XDMAIF_IsValidatedPeripherOnDma(bXdmac, bSrcID)) )
{
return XDMAD_ALLOC_FAILED;
}
}
/* dma transfer from memory to peripheral */
if ( bSrcID == XDMAD_TRANSFER_MEMORY )
{
if( (!XDMAIF_IsValidatedPeripherOnDma(bXdmac, bDstID)) )
{
return XDMAD_ALLOC_FAILED;
}
}
for (i = 0; i < pXdmad->numChannels; i ++)
{
if ( pXdmad->XdmaChannels[bXdmac][i].state == XDMAD_STATE_FREE )
{
/* Allocate the channel */
pXdmad->XdmaChannels[bXdmac][i].state = XDMAD_STATE_ALLOCATED;
/* Get general informations */
pXdmad->XdmaChannels[bXdmac][i].bSrcPeriphID = bSrcID;
pXdmad->XdmaChannels[bXdmac][i].bDstPeriphID = bDstID;
pXdmad->XdmaChannels[bXdmac][i].bSrcTxIfID =
XDMAIF_Get_ChannelNumber(bXdmac, bSrcID, 0);
pXdmad->XdmaChannels[bXdmac][i].bSrcRxIfID =
XDMAIF_Get_ChannelNumber(bXdmac, bSrcID, 1);
pXdmad->XdmaChannels[bXdmac][i].bDstTxIfID =
XDMAIF_Get_ChannelNumber(bXdmac, bDstID, 0);
pXdmad->XdmaChannels[bXdmac][i].bDstTxIfID =
XDMAIF_Get_ChannelNumber(bXdmac, bDstID, 1);
return ((bXdmac << 8)) | ((i) & 0xFF);
}
}
return XDMAD_ALLOC_FAILED;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Initialize xDMA driver instance.
* \param pXdmad Pointer to xDMA driver instance.
* \param bPollingMode Polling DMA transfer:
* 1. Via XDMAD_IsTransferDone(); or
* 2. Via XDMAD_Handler().
*/
void XDMAD_Initialize( sXdmad *pXdmad, uint8_t bPollingMode )
{
uint32_t i, j;
assert( pXdmad != NULL ) ;
pXdmad->pXdmacs[0] = XDMAC0;
pXdmad->pXdmacs[1] = XDMAC1;
pXdmad->pollingMode = bPollingMode;
pXdmad->numControllers = XDMAC_CONTROLLER_NUM;
pXdmad->numChannels = XDMAC_CHANNEL_NUM;
for (i = 0; i < pXdmad->numControllers; i ++)
{
for (j = 0; j < pXdmad->numChannels; j ++)
{
pXdmad->XdmaChannels[i][j].fCallback = 0;
pXdmad->XdmaChannels[i][j].pArg = 0;
pXdmad->XdmaChannels[i][j].bIrqOwner = 0;
pXdmad->XdmaChannels[i][j].bSrcPeriphID = 0;
pXdmad->XdmaChannels[i][j].bDstPeriphID = 0;
pXdmad->XdmaChannels[i][j].bSrcTxIfID = 0;
pXdmad->XdmaChannels[i][j].bSrcRxIfID = 0;
pXdmad->XdmaChannels[i][j].bDstTxIfID = 0;
pXdmad->XdmaChannels[i][j].bDstRxIfID = 0;
pXdmad->XdmaChannels[i][j].state = XDMAD_STATE_FREE;
}
}
}
/**
* \brief Allocate a XDMA channel for upper layer.
* \param pXdmad Pointer to xDMA driver instance.
* \param bSrcID Source peripheral ID, 0xFF for memory.
* \param bDstID Destination peripheral ID, 0xFF for memory.
* \return Channel number if allocation sucessful, return
* XDMAD_ALLOC_FAILED if allocation failed.
*/
uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,
uint8_t bSrcID,
uint8_t bDstID)
{
uint32_t _iController;
uint32_t dwChannel = XDMAD_ALLOC_FAILED;
for ( _iController = 0; _iController < pXdmad->numControllers; _iController ++)
{
dwChannel = XDMAD_AllocateXdmacChannel( pXdmad, _iController, bSrcID, bDstID );
if (dwChannel != XDMAD_ALLOC_FAILED)
break;
}
return dwChannel;
}
/**
* \brief Free the specified xDMA channel.
* \param pXdmad Pointer to xDMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad,
uint32_t dwChannel )
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
assert( pXdmad != NULL ) ;
switch ( pXdmad->XdmaChannels[_iController][iChannel].state )
{
case XDMAD_STATE_START:
return XDMAD_BUSY;
case XDMAD_STATE_ALLOCATED: case XDMAD_STATE_DONE:
pXdmad->XdmaChannels[_iController][iChannel].state = XDMAD_STATE_FREE;
break;
}
return XDMAD_OK;
}
/**
* \brief Set the callback function for xDMA channel transfer.
* \param pXdmad Pointer to xDMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
* \param fCallback Pointer to callback function.
* \param pArg Pointer to optional argument for callback.
*/
eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad,
uint32_t dwChannel,
XdmadTransferCallback fCallback,
void* pArg )
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
assert( pXdmad != NULL ) ;
if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_FREE )
return XDMAD_ERROR;
else if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_START )
return XDMAD_BUSY;
pXdmad->XdmaChannels[_iController][iChannel].fCallback = fCallback;
pXdmad->XdmaChannels[_iController][iChannel].pArg = pArg;
return XDMAD_OK;
}
/**
* \brief Enable clock of the xDMA peripheral, Enable the dma peripheral,
* configure configuration register for xDMA transfer.
* \param pXdmad Pointer to xDMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
* \param dwCfg Configuration value.
*/
eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel)
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
uint32_t _dwdmaId;
assert( pXdmad != NULL ) ;
Xdmac *pXdmac = pXdmad->pXdmacs[_iController];
if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_FREE )
return XDMAD_ERROR;
else if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_START )
return XDMAD_BUSY;
/* Clear dummy status */
XDMAC_GetGlobalChStatus( pXdmac );
XDMAC_GetGIsr (pXdmac);
_dwdmaId = (_iController == 0) ? ID_XDMAC0 : ID_XDMAC1;
/* Enable clock of the DMA peripheral */
if (!PMC_IsPeriphEnabled( _dwdmaId ))
{
PMC_EnablePeripheral( _dwdmaId );
}
/* Clear dummy status */
XDMAC_GetChannelIsr( pXdmac,iChannel );
/* Disables XDMAC interrupt for the given channel. */
XDMAC_DisableGIt (pXdmac, -1);
XDMAC_DisableChannelIt (pXdmac, iChannel, -1);
/* Disable the given dma channel. */
XDMAC_DisableChannel( pXdmac, iChannel );
XDMAC_SetSourceAddr(pXdmac, iChannel, 0);
XDMAC_SetDestinationAddr(pXdmac, iChannel, 0);
XDMAC_SetBlockControl(pXdmac, iChannel, 0);
XDMAC_SetChannelConfig( pXdmac, iChannel, 0x20);
XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0);
XDMAC_SetDescriptorControl(pXdmac, iChannel, 0);
return XDMAD_OK;
}
/**
* \brief xDMA interrupt handler
* \param pxDmad Pointer to DMA driver instance.
*/
void XDMAD_Handler( sXdmad *pDmad)
{
Xdmac *pXdmac;
sXdmadChannel *pCh;
uint32_t xdmaChannelIntStatus, xdmaGlobaIntStatus,xdmaGlobalChStatus;
uint8_t bExec = 0;
uint8_t _iController, _iChannel;
assert( pDmad != NULL ) ;
for (_iController = 0; _iController < pDmad->numControllers; _iController ++)
{
pXdmac = pDmad->pXdmacs[_iController];
xdmaGlobaIntStatus = XDMAC_GetGIsr(pXdmac);
if ((xdmaGlobaIntStatus & 0xFFFF) == 0) continue;
xdmaGlobalChStatus = XDMAC_GetGlobalChStatus(pXdmac);
for (_iChannel = 0; _iChannel < pDmad->numChannels; _iChannel ++)
{
if (!(xdmaGlobaIntStatus & (1<<_iChannel))) continue;
pCh = &pDmad->XdmaChannels[_iController][_iChannel];
if ( pCh->state == XDMAD_STATE_FREE) return ;
if ((xdmaGlobalChStatus & ( XDMAC_GS_ST0 << _iChannel)) == 0)
{
bExec = 0;
xdmaChannelIntStatus = XDMAC_GetChannelIsr( pXdmac, _iChannel);
if (xdmaChannelIntStatus & XDMAC_CIS_BIS) {
if((XDMAC_GetChannelItMask(pXdmac, _iChannel) & XDMAC_CIM_LIM) == 0 ) {
pCh->state = XDMAD_STATE_DONE ;
bExec = 1;
}
//printf("XDMAC_CIS_BIS\n\r");
}
if (xdmaChannelIntStatus & XDMAC_CIS_FIS) {
// printf("XDMAC_CIS_FIS\n\r");
}
if (xdmaChannelIntStatus & XDMAC_CIS_RBEIS) {
//printf("XDMAC_CIS_RBEIS\n\r");
}
if (xdmaChannelIntStatus & XDMAC_CIS_WBEIS) {
// printf("XDMAC_CIS_WBEIS\n\r");
}
if (xdmaChannelIntStatus & XDMAC_CIS_ROIS) {
// printf("XDMAC_CIS_ROIS\n\r");
}
if (xdmaChannelIntStatus & XDMAC_CIS_LIS) {
//printf("XDMAC_CIS_LIS\n\r");
pCh->state = XDMAD_STATE_DONE ;
bExec = 1;
}
if (xdmaChannelIntStatus & XDMAC_CIS_DIS )
{
pCh->state = XDMAD_STATE_DONE ;
bExec = 1;
}
}
// printf("bExec =%d, _iChannel=%d \n\r",bExec,_iChannel);
/* Execute callback */
if (bExec && pCh->fCallback) {
//XDMAC_DisableGIt( pXdmac,1 << _iChannel);
pCh->fCallback(_iChannel, pCh->pArg);
}
}
}
}
/**
* \brief Check if DMA transfer is finished.
* In polling mode XDMAD_Handler() is polled.
* \param pDmad Pointer to DMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel )
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
uint8_t state;
state = pXdmad->XdmaChannels[_iController][iChannel].state;
assert( pXdmad != NULL ) ;
if ( state == XDMAD_STATE_ALLOCATED ) return XDMAD_OK;
if ( state == XDMAD_STATE_FREE )
return XDMAD_ERROR;
else if ( state != XDMAD_STATE_DONE )
{
if(pXdmad->pollingMode) XDMAD_Handler( pXdmad);
return XDMAD_BUSY;
}
return XDMAD_OK;
}
/**
* \brief Configure DMA for a single transfer.
* \param pXdmad Pointer to xDMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,
uint32_t dwChannel,
sXdmadCfg *pXdmaParam,
uint32_t dwXdmaDescCfg,
uint32_t dwXdmaDescAddr)
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
Xdmac *pXdmac = pXdmad->pXdmacs[_iController];
XDMAC_GetGIsr(pXdmac);
XDMAC_GetChannelIsr( pXdmac, iChannel);
if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_FREE )
return XDMAD_ERROR;
if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_START )
return XDMAD_BUSY;
/* Linked List is enabled */
if ((dwXdmaDescCfg & XDMAC_CNDC_NDE) == XDMAC_CNDC_NDE_DSCR_FETCH_EN)
{
if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV0) {
XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );
XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa);
XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da);
}
if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV1) {
XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );
}
XDMAC_SetDescriptorAddr(pXdmac, iChannel, dwXdmaDescAddr, 0);
XDMAC_SetDescriptorControl(pXdmac, iChannel, dwXdmaDescCfg);
XDMAC_DisableChannelIt (pXdmac, iChannel, -1);
XDMAC_EnableChannelIt (pXdmac,iChannel, XDMAC_CIE_LIE );
}
/* LLI is disabled. */
else
{
XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa);
XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da);
XDMAC_SetMicroblockControl(pXdmac, iChannel, pXdmaParam->mbr_ubc);
XDMAC_SetBlockControl(pXdmac, iChannel, pXdmaParam->mbr_bc);
XDMAC_SetDataStride_MemPattern(pXdmac, iChannel, pXdmaParam->mbr_ds);
XDMAC_SetSourceMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_sus);
XDMAC_SetDestinationMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_dus);
XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );
XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0);
XDMAC_SetDescriptorControl(pXdmac, iChannel, 0);
XDMAC_EnableChannelIt (pXdmac,
iChannel,
XDMAC_CIE_BIE |
XDMAC_CIE_DIE |
XDMAC_CIE_FIE |
XDMAC_CIE_RBIE |
XDMAC_CIE_WBIE |
XDMAC_CIE_ROIE);
}
return XDMAD_OK;
}
/**
* \brief Start xDMA transfer.
* \param pXdmad Pointer to XDMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel )
{
uint8_t _iController = (dwChannel >> 8);
uint8_t iChannel = (dwChannel) & 0xFF;
Xdmac *pXdmac = pXdmad->pXdmacs[_iController];
if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_FREE )
{
printf("-E- XDMAD_STATE_FREE \n\r");
return XDMAD_ERROR;
}
else if ( pXdmad->XdmaChannels[_iController][iChannel].state == XDMAD_STATE_START )
{
printf("-E- XDMAD_STATE_START \n\r");
return XDMAD_BUSY;
}
/* Change state to transferring */
pXdmad->XdmaChannels[_iController][iChannel].state = XDMAD_STATE_START;
XDMAC_EnableChannel(pXdmac, iChannel);
if ( pXdmad->pollingMode == 0 )
{
XDMAC_EnableGIt( pXdmac,1 << iChannel);
}
return XDMAD_OK;
}
/**
* \brief Stop DMA transfer.
* \param pDmad Pointer to DMA driver instance.
* \param dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel )
{
uint8_t _iController = (dwChannel >> 8);
uint8_t _iChannel = (dwChannel) & 0xFF;
Xdmac *pXdmac = pXdmad->pXdmacs[_iController];
pXdmad->XdmaChannels[_iController][_iChannel].state = XDMAD_STATE_ALLOCATED;
/* Disable channel */
XDMAC_DisableChannel(pXdmac, _iChannel);
/* Disable interrupts */
XDMAC_DisableChannelIt(pXdmac, _iChannel, -1);
/* Clear pending status */
XDMAC_GetChannelIsr( pXdmac, _iChannel);
XDMAC_GetGlobalChStatus(pXdmac);
return XDMAD_OK;
}
/**@}*/

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#ifndef _LIB_CHIP_sama5d4_
#define _LIB_CHIP_sama5d4_
/*
* Peripherals registers definitions
*/
#if defined sama5d4x
#include "include/sama5d4.h"
#else
#warning Library does not support the specified chip, specifying sama5d4x
#define sama5d4x
#include "include/sama5d4.h"
#endif
/* Define attribute */
#if defined ( __CC_ARM ) /* Keil µVision 4 */
#define WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
#define WEAK __weak
#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
#define WEAK __attribute__ ((weak))
#endif
/* Define NO_INIT attribute and compiler specific symbols */
#if defined ( __CC_ARM )
#define NO_INIT
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define NO_INIT __no_init
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define NO_INIT
#endif
#define CP15_PRESENT
/*
* Peripherals
*/
#include "include/adc.h"
#include "include/async.h"
#include "include/mmu.h"
#include "cp15/cp15.h"
#include "cp15/cp15_pmu.h"
#include "tz/mon_macros.h"
#include "tz/mon.h"
#include "include/l2cc.h"
#include "include/aic.h"
#include "include/pio.h"
#include "include/pio_it.h"
#include "include/pmc.h"
#include "include/pwmc.h"
#include "include/usart.h"
#include "include/xdmac.h"
#include "include/spi.h"
#include "include/pit.h"
#include "include/wdt.h"
#include "include/tc.h"
#include "include/smcNfc.h"
#include "include/twi.h"
#include "include/trace.h"
#include "include/hsmci.h"
#include "include/trng.h"
#include "include/tdes.h"
#include "include/aes.h"
#include "include/aesb.h"
#include "include/sha.h"
#include "include/icm.h"
#include "include/gmac.h"
#include "include/catb.h"
#include "include/udphs.h"
#include "include/video.h"
#include "include/isi.h"
#include "include/ssc.h"
#include "include/rtc.h"
#include "include/rstc.h"
#endif /* _LIB_CHIP_sama5d4_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
// core list
//-------------------
// arm7tdmi
// arm926ej_s
// arm1176jzf_s
// cortexm3
#ifndef _CORE_H
#define _CORE_H
#define cortex_a5
#endif // #ifndef _CORE_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//-----------------------------------------------------------------------------
// Reg Reads Writes
//----------------------------------------------------------------------------
// 0 ID code Unpredictable
// 0 cache type Unpredictable
// 0 TCM status Unpredictable
// 1 Control Control
// 2 Translation table base Translation table base
// 3 Domain access control Domain access control
// 4 (Reserved)
// 5 Data fault status Data fault status
// 5 Instruction fault status Instruction fault status
// 6 Fault address Fault address
// 7 cache operations cache operations
// 8 Unpredictable TLB operations
// 9 cache lockdown cache lockdown
// 9 TCM region TCM region
// 10 TLB lockdown TLB lockdown
// 11 (Reserved)
// 12 (Reserved)
// 13 FCSE PID FCSE PID
// 13 Context ID Context ID
// 14 (Reserved)
// 15 Test configuration Test configuration
//-----------------------------------------------------------------------------
/** \page cp15_f CP15 Functions.
*
* \section CP15 function Usage
*
* Methods to manage the Coprocessor 15. Coprocessor 15, or System Control
* Coprocessor CP15, is used to configure and control all the items in the
* list below:
* <ul>
* <li> ARM core
* <li> caches (Icache, Dcache and write buffer)
* <li> TCM
* <li> MMU
* <li> Other system options
* </ul>
* \section Usage
*
* -# Enable or disable D cache with Enable_D_cache and Disable_D_cache
* -# Enable or disable I cache with Enable_I_cache and Disable_I_cache
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15.c.\n
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#if defined(__ICCARM__)
#include <intrinsics.h>
#endif
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Check Instruction cache
* \return 0 if I_cache disable, 1 if I_cache enable
*/
unsigned int CP15_IsIcacheEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & (1 << CP15_I_BIT)) != 0);
}
/**
* \brief Enable Instruction cache
*/
void CP15_EnableIcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is disabled
if ((control & (1 << CP15_I_BIT)) == 0) {
control |= (1 << CP15_I_BIT);
CP15_WriteControl(control);
TRACE_INFO("I cache enabled.\n\r");
}
else {
TRACE_INFO("I cache is already enabled.\n\r");
}
}
/**
* \brief Disable Instruction cache
*/
void CP15_DisableIcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is enabled
if ((control & (1 << CP15_I_BIT)) != 0) {
control &= ~(1ul << CP15_I_BIT);
CP15_WriteControl(control);
TRACE_INFO("I cache disabled.\n\r");
}
else {
TRACE_INFO("I cache is already disabled.\n\r");
}
}
/**
* \brief Check MMU
* \return 0 if MMU disable, 1 if MMU enable
*/
unsigned int CP15_IsMMUEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & (1 << CP15_M_BIT)) != 0);
}
/**
* \brief Enable MMU
*/
void CP15_EnableMMU(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if MMU is disabled
if ((control & (1 << CP15_M_BIT)) == 0) {
control |= (1 << CP15_M_BIT);
CP15_WriteControl(control);
TRACE_INFO("MMU enabled.\n\r");
}
else {
TRACE_INFO("MMU is already enabled.\n\r");
}
}
/**
* \brief Disable MMU
*/
void CP15_DisableMMU(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if MMU is enabled
if ((control & (1 << CP15_M_BIT)) != 0) {
control &= ~(1ul << CP15_M_BIT);
control &= ~(1ul << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("MMU disabled.\n\r");
}
else {
TRACE_INFO("MMU is already disabled.\n\r");
}
}
/**
* \brief Check D_cache
* \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course)
*/
unsigned int CP15_IsDcacheEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);
}
/**
* \brief Enable Data cache
*/
void CP15_EnableDcache(void)
{
unsigned int control;
control = CP15_ReadControl();
if( !CP15_IsMMUEnabled() ) {
TRACE_ERROR("Do nothing: MMU not enabled\n\r");
}
else {
// Check if cache is disabled
if ((control & (1 << CP15_C_BIT)) == 0) {
control |= (1 << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("D cache enabled.\n\r");
}
else {
TRACE_INFO("D cache is already enabled.\n\r");
}
}
}
/**
* \brief Disable Data cache
*/
void CP15_DisableDcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is enabled
if ((control & (1 << CP15_C_BIT)) != 0) {
control &= ~(1ul << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("D cache disabled.\n\r");
}
else {
TRACE_INFO("D cache is already disabled.\n\r");
}
}
/**
* \brief Invalidate TLB
*/
void CP15_InvalidateTLB(void)
{
asm("MCR p15, 0, %0, c8, c3, 0" : : "r"(1));
asm("DSB");
}
/**
* \brief Clean Data cache
*/
void CP15_CacheClean(uint8_t CacheType)
{
assert(!CacheType);
CP15_SelectDCache();
CP15_CleanDCacheBySetWay();
asm("DSB");
}
/**
* \brief Invalidate D/Icache
*/
void CP15_CacheInvalidate(uint8_t CacheType)
{
if(CacheType)
{
CP15_SelectICache();
CP15_InvalidateIcacheInnerSharable();
asm("DSB");
asm("ISB");
}
else
{
CP15_SelectDCache();
CP15_InvalidateDcacheBySetWay();
asm("DSB");
asm("ISB");
}
}
/**
* \brief Flush(Clean and invalidate) Data cache
*/
void CP15_CacheFlush(uint8_t CacheType)
{
assert(!CacheType);
CP15_SelectDCache();
CP15_CleanInvalidateDCacheBySetWay();
asm("DSB");
}
/**
* \brief Invalidate Data cache by address
*/
void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add)
{
CP15_SelectDCache();
CP15_InvalidateDcacheByMva(S_Add, E_Add);
}
/**
* \brief Clean Data cache by address
*/
void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add)
{
CP15_SelectDCache();
CP15_CleanDCacheByMva(S_Add, E_Add);
}
/**
* \brief Flush Data cache by address
*/
void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add)
{
CP15_SelectDCache();
CP15_CleanInvalidateDcacheByMva(S_Add, E_Add);
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _CP15_H
#define _CP15_H
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions
// change the PC:
// 0 = loads to PC set the T bit
// 1 = loads to PC do not set T bit
#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache:
// 0 = Random replacement
// 1 = Round-robin replacement.
#define CP15_V_BIT 13 // V bit Location of exception vectors:
// 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C
// 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C
#define CP15_I_BIT 12 // I bit Icache enable/disable:
// 0 = Icache disabled
// 1 = Icache enabled
#define CP15_R_BIT 9 // R bit ROM protection
#define CP15_S_BIT 8 // S bit System protection
#define CP15_B_BIT 7 // B bit Endianness:
// 0 = Little-endian operation
// 1 = Big-endian operation.
#define CP15_C_BIT 2 // C bit Dcache enable/disable:
// 0 = cache disabled
// 1 = cache enabled
#define CP15_A_BIT 1 // A bit Alignment fault enable/disable:
// 0 = Data address alignment fault checking disabled
// 1 = Data address alignment fault checking enabled
#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.
// 0 = disabled
// 1 = enabled
/** No access Any access generates a domain fault. */
#define CP15_DOMAIN_NO_ACCESS 0x00
/** Client Accesses are checked against the access permission bits in the section or page descriptor. */
#define CP15_DOMAIN_CLIENT_ACCESS 0x01
/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */
#define CP15_DOMAIN_MANAGER_ACCESS 0x03
#define CP15_ICache 1
#define CP15_DCache 0
#define CP15_PMCNTENSET_ENABLE 31
#define CP15_PMCR_DIVIDER 3
#define CP15_PMCR_RESET 2
#define CP15_PMCR_ENABLE 0
/*------------------------------------------------------------------------------ */
/* Exported functions */
/*------------------------------------------------------------------------------ */
extern unsigned int CP15_ReadID(void);
extern unsigned int CP15_ReadControl(void);
extern void CP15_ExclusiveCache(void);
extern void CP15_NonExclusiveCache(void);
extern void CP15_ISB(void);
extern void CP15_DSB(void);
extern void CP15_DMB(void);
extern void CP15_SelectDCache(void);
extern void CP15_SelectICache(void);
extern void CP15_WriteControl(unsigned int value);
extern void CP15_WriteTTB(unsigned int value);
extern void CP15_WriteDomainAccessControl(unsigned int value);
extern void CP15_InvalidateIcacheInnerSharable(void);
extern void CP15_InvalidateBTBinnerSharable(void);
extern void CP15_InvalidateIcache(void);
extern void CP15_InvalidateIcacheByMva(void);
extern void CP15_InvalidateBTB(void);
extern void CP15_InvalidateBTBbyMva(uint32_t VA_Addr);
extern void CP15_InvalidateDcacheBySetWay(void);
extern void CP15_CleanDCacheBySetWay(void);
extern void CP15_CleanInvalidateDCacheBySetWay(void);
extern void CP15_InvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr );
extern void CP15_CleanDCacheByMva(uint32_t startAddr, uint32_t endAddr );
extern void CP15_CleanInvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr );
extern void CP15_CleanDCacheUMva(void);
extern void CP15_InvalidateTranslationTable(void);
extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size );
/*------------------------------------------------------------------------------ */
/* Exported functions from CP15.c */
/*------------------------------------------------------------------------------ */
/** MMU (Status/Enable/Disable) */
extern unsigned int CP15_IsMMUEnabled(void);
extern void CP15_EnableMMU(void);
extern void CP15_DisableMMU(void);
/** I cache (Status/Enable/Disable) */
extern unsigned int CP15_IsIcacheEnabled(void);
extern void CP15_EnableIcache(void);
extern void CP15_DisableIcache(void);
/** D cache (Status/Enable/Disable) */
extern unsigned int CP15_IsDcacheEnabled(void);
extern void CP15_EnableDcache(void);
extern void CP15_DisableDcache(void);
extern void CP15_InvalidateTLB(void);
extern void CP15_CacheClean(uint8_t CacheType);
extern void CP15_CacheInvalidate(uint8_t CacheType);
extern void CP15_CacheFlush(uint8_t CacheType);
extern void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add);
extern void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add);
extern void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add);
#endif // #ifndef _CP15_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA,
* OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup cp15_cache Cache Operations
*
* \section Usage
*
* They are performed as MCR instructions and only operate on a level 1 cache associated with
* ATM v7 processor.
* The supported operations are:
* <ul>
* <li> Any of these operations can be applied to
* -# any data cache
* -# any unified cache.
* <li> Invalidate by MVA
* Performs an invalidate of a data or unified cache line based on the address it contains.
* <li> Invalidate by set/way
* Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean by MVA
* Performs a clean of a data or unified cache line based on the address it contains.
* <li> Clean by set/way
* Performs a clean of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean and Invalidate by MVA
* Performs a clean and invalidate of a data or unified cache line based on the address it contains.
* <li> Clean and Invalidate by set/way
* Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy.
* </ul>
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15_arm_gnu.S \n
*/
/*----------------------------------------------------------------------------
* Functions to access CP15 coprocessor register
*----------------------------------------------------------------------------*/
.global CP15_ReadID
.global CP15_ExclusiveCache
.global CP15_NonExclusiveCache
.global CP15_ISB
.global CP15_DSB
.global CP15_DMB
.global CP15_SelectICache
.global CP15_SelectDCache
.global CP15_ReadControl
.global CP15_WriteControl
.global CP15_WriteDomainAccessControl
.global CP15_WriteTTB
.global CP15_InvalidateIcacheInnerSharable
.global CP15_InvalidateBTBinnerSharable
.global CP15_InvalidateIcache
.global CP15_InvalidateIcacheByMva
.global CP15_InvalidateBTB
.global CP15_InvalidateBTBbyMva
.global CP15_InvalidateDcacheBySetWay
.global CP15_CleanDCacheBySetWay
.global CP15_CleanInvalidateDCacheBySetWay
.global CP15_InvalidateDcacheByMva
.global CP15_CleanDCacheByMva
.global CP15_CleanDCacheUMva
.global CP15_CleanInvalidateDcacheByMva
.global CP15_coherent_dcache_for_dma
.global CP15_invalidate_dcache_for_dma
.global CP15_clean_dcache_for_dma
.global CP15_flush_dcache_for_dma
.global CP15_flush_kern_dcache_for_dma
/**
* \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
* Reading from this register returns the device ID, the cache type, or the TCM status
* depending on the value of Opcode_2 used.
*/
.section .CP15_ReadID
.global CP15_ReadID
CP15_ReadID:
mov r0, #0
mrc p15, 0, r0, c0, c0, 0
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
.section .CP15_ISB
.global CP15_ISB
CP15_ISB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 4
nop
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
.section .CP15_DSB
.global CP15_DSB
CP15_DSB:
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
nop
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
.section .CP15_DMB
.global CP15_DMB
CP15_DMB:
mov r0, #0
mcr p15, 0, r0, c7, c10, 5
nop
bx lr
/**
* \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
.section .CP15_ExclusiveCache
.global CP15_ExclusiveCache
CP15_ExclusiveCache:
mov r0, #0
mrc p15, 0, r0, c1, c0, 1 // Read ACTLR
orr r0, r0, #0x00000080
mcr p15, 0, r0, c1, c0, 1 // Write ACTLR
nop
bx lr
/**
* \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
.section .CP15_NonExclusiveCache
.global CP15_NonExclusiveCache
CP15_NonExclusiveCache:
mov r0, #0
mrc p15, 0, r0, c1, c0, 1 // Read ACTLR
bic r0, r0, #0x00000080
mcr p15, 0, r0, c1, c0, 1 // Write ACTLR
nop
bx lr
/**
* \brief Register c1 accesses the CSSELR Register, to select ICache
*/
.section .CP15_SelectICache
.global CP15_SelectICache
CP15_SelectICache:
mrc p15, 2, r0, c0, c0, 0 // Read CSSELR
orr r0, r0, #0x1 // Change 0th bit to ICache
mcr p15, 2, r0, c0, c0, 0 // Write CSSELR
nop
bx lr
/**
* \brief Register c1 accesses the CSSELR Register, to select DCache
*/
.section .CP15_SelectDCache
.global CP15_SelectDCache
CP15_SelectDCache:
mrc p15, 2, r0, c0, c0, 0 // Read CSSELR
and r0, r0, #0xFFFFFFFE // Change 0th bit to ICache
mcr p15, 2, r0, c0, c0, 0 // Write CSSELR
nop
bx lr
/**
* \brief Register c1 is the Control Register for the ARM926EJ-S processor.
* This register specifies the configuration used to enable and disable the
* caches and MMU. It is recommended that you access this register using a
* read-modify-write sequence
*/
.section .CP15_ReadControl
.global CP15_ReadControl
CP15_ReadControl:
mov r0, #0
mrc p15, 0, r0, c1, c0, 0
bx lr
.section .CP15_WriteControl
.global CP15_WriteControl
CP15_WriteControl:
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.section .CP15_WriteDomainAccessControl
.global CP15_WriteDomainAccessControl
CP15_WriteDomainAccessControl:
mcr p15, 0, r0, c3, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief ARMv7A architecture supports two translation tables
* Configure translation table base (TTB) control register cp15,c2
* to a value of all zeros, indicates we are using TTB register 0.
* write the address of our page table base to TTB register 0.
*/
.section .CP15_WriteTTB
.global CP15_WriteTTB
CP15_WriteTTB:
mcr p15, 0, r0, c2, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief Invalidate I cache predictor array inner Sharable
*/
.section .CP15_InvalidateIcacheInnerSharable
.global CP15_InvalidateIcacheInnerSharable
CP15_InvalidateIcacheInnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 0
bx lr
/**
* \brief Invalidate entire branch predictor array inner Sharable
*/
.section .CP15_InvalidateBTBinnerSharable
.global CP15_InvalidateBTBinnerSharable
CP15_InvalidateBTBinnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
bx lr
/**
* \brief Invalidate all instruction caches to PoU, also flushes branch target cache
*/
.section .CP15_InvalidateIcache
.global CP15_InvalidateIcache
CP15_InvalidateIcache:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
bx lr
/**
* \brief Invalidate instruction caches by VA to PoU
*/
.section .CP15_InvalidateIcacheByMva
.global CP15_InvalidateIcacheByMva
CP15_InvalidateIcacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 1
bx lr
/**
* \brief Invalidate entire branch predictor array
*/
.section .CP15_InvalidateBTB
.global CP15_InvalidateBTB
CP15_InvalidateBTB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 6
bx lr
/**
* \brief Invalidate branch predictor array entry by MVA
*/
.section .CP15_InvalidateBTBbyMva
.global CP15_InvalidateBTBbyMva
CP15_InvalidateBTBbyMva:
mcr p15, 0, r0, c7, c5, 7
bx lr
/***********************************************************
*
* ===Data Cache related maintenance functions===
*
**************************************************************/
// ===Data Cache maintenance by SetWay ===
/**
* \brief Invalidate entire data cache by set/way
*/
.section .CP15_InvalidateDcacheBySetWay
.global CP15_InvalidateDcacheBySetWay
CP15_InvalidateDcacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 // Num of ways
and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 // Num of stes
and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB
mov r0, #0 // 0:SHL:5
inv_way_loop:
lsl r4, r1, #30
sub r1, r1, #1 //
mov r3, r2
inv_line_loop:
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c6, 2
sub r3, r3, #1 // 1:SHL:30
cmp r3, #0
bpl inv_line_loop
cmp r1, #-1
bne inv_way_loop
nop
bx lr
/**
* \brief Clean entire data cache by set/way
*/
.section .CP15_CleanDCacheBySetWay
.global CP15_CleanDCacheBySetWay
CP15_CleanDCacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 // Num of ways
and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 // Num of stes
and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB
mov r0, #0 // 0:SHL:5
clean_way_loop:
lsl r4, r1, #30
sub r1, r1, #1 //
mov r3, r2
clean_line_loop:
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c10, 2
sub r3, r3, #1 // 1:SHL:30
cmp r3, #0
bpl clean_line_loop
cmp r1, #-1
bne clean_way_loop
nop
bx lr
/**
* \brief Clean and Invalidate entire data cache by set/way
*/
.section .CP15_CleanInvalidateDCacheBySetWay
.global CP15_CleanInvalidateDCacheBySetWay
CP15_CleanInvalidateDCacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 // Num of ways
and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 // Num of stes
and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB
mov r0, #0 // 0:SHL:5
clinv_way_loop:
lsl r4, r1, #30
sub r1, r1, #1 //
mov r3, r2
clinv_line_loop:
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c10, 2
sub r3, r3, #1 // 1:SHL:30
cmp r3, #0
bpl clinv_line_loop
cmp r1, #-1
bne clinv_way_loop
nop
bx lr
// ===Data Cache maintenance by VA ===
/**
* \brief Invalidate data cache by VA to Poc
*/
.section .CP15_InvalidateDcacheByMva
.global CP15_InvalidateDcacheByMva
CP15_InvalidateDcacheByMva:
mov r2, #0x20 //Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
inv_loop:
mcr p15, 0, r0, c7, c6, 1
add r3, r3, r2
cmp r3, r1
bls inv_loop
bx lr
/**
* \brief Clean data cache by MVA
*/
.section .CP15_CleanDCacheByMva
.global CP15_CleanDCacheByMva
CP15_CleanDCacheByMva:
mov r2, #0x20 //Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
clean_loop:
mcr p15, 0, r0, c7, c10, 1
add r3, r3, r2
cmp r3, r1
bls clean_loop
bx lr
/**
* \brief Clean unified cache by MVA
*/
.section .CP15_CleanDCacheUMva
.global CP15_CleanDCacheUMva
CP15_CleanDCacheUMva:
mov r0, #0
mcr p15, 0, r0, c7, c11, 1
bx lr
/**
* \brief Clean and invalidate data cache by VA to PoC
*/
.section .CP15_CleanInvalidateDcacheByMva
.global CP15_CleanInvalidateDcacheByMva
CP15_CleanInvalidateDcacheByMva:
mov r2, #0x20 //Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
clinv_loop:
mcr p15, 0, r0, c7, c14, 1
add r3, r3, r2
cmp r3, r1
bls clinv_loop
bx lr
/**
* \brief Ensure that the I and D caches are coherent within specified
* region. This is typically used when code has been written to
* a memory region, and will be executed.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_coherent_dcache_for_dma
.global CP15_coherent_dcache_for_dma
CP15_coherent_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r12, r0, r3
1:
mcr p15, 0, r12, c7, c11, 1
add r12, r12, r2
cmp r12, r1
blo 1b
dsb
mrc p15, 0, r3, c0, c0, 1
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r12, r0, r3
2:
mcr p15, 0, r12, c7, c5, 1
add r12, r12, r2
cmp r12, r1
blo 2b
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
mcr p15, 0, r0, c7, c5, 6
dsb
isb
bx lr
/**
* \brief Invalidate the data cache within the specified region; we will
* be performing a DMA operation in this region and we want to
* purge old data in the cache.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_invalidate_dcache_for_dma
.global CP15_invalidate_dcache_for_dma
CP15_invalidate_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
tst r0, r3
bic r0, r0, r3
mcrne p15, 0, r0, c7, c14, 1
tst r1, r3
bic r1, r1, r3
mcrne p15, 0, r1, c7, c14, 1
3:
mcr p15, 0, r0, c7, c6, 1
add r0, r0, r2
cmp r0, r1
blo 3b
dsb
bx lr
/**
* \brief Clean the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_clean_dcache_for_dma
.global CP15_clean_dcache_for_dma
CP15_clean_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r0, r0, r3
4:
mcr p15, 0, r0, c7, c10, 1
add r0, r0, r2
cmp r0, r1
blo 4b
dsb
bx lr
/**
* \brief Flush the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_flush_dcache_for_dma
.global CP15_flush_dcache_for_dma
CP15_flush_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r0, r0, r3
5:
mcr p15, 0, r0, c7, c14, 1
add r0, r0, r2
cmp r0, r1
blo 5b
dsb
bx lr
/**
* \brief CP15_flush_kern_dcache_for_dma
* Ensure that the data held in the page kaddr is written back to the page in question.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_flush_kern_dcache_for_dma
.global CP15_flush_kern_dcache_for_dma
CP15_flush_kern_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
add r1, r0, r1
sub r3, r2, #1
bic r0, r0, r3
mcr p15, 0, r0, c7, c14, 1
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
bx lr

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA,
* OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup cp15_cache Cache Operations
*
* \section Usage
*
* They are performed as MCR instructions and only operate on a level 1 cache associated with
* ATM v7 processor.
* The supported operations are:
* <ul>
* <li> Any of these operations can be applied to
* -# any data cache
* -# any unified cache.
* <li> Invalidate by MVA
* Performs an invalidate of a data or unified cache line based on the address it contains.
* <li> Invalidate by set/way
* Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean by MVA
* Performs a clean of a data or unified cache line based on the address it contains.
* <li> Clean by set/way
* Performs a clean of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean and Invalidate by MVA
* Performs a clean and invalidate of a data or unified cache line based on the address it contains.
* <li> Clean and Invalidate by set/way
* Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy.
* </ul>
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15_arm_iar.s \n
*/
MODULE ?cp15
//// Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#define __ASSEMBLY__
/*----------------------------------------------------------------------------
* Functions to access CP15 coprocessor register
*----------------------------------------------------------------------------*/
PUBLIC CP15_ReadID
PUBLIC CP15_ExclusiveCache
PUBLIC CP15_NonExclusiveCache
PUBLIC CP15_ISB
PUBLIC CP15_DSB
PUBLIC CP15_DMB
PUBLIC CP15_SelectICache
PUBLIC CP15_SelectDCache
PUBLIC CP15_ReadControl
PUBLIC CP15_WriteControl
PUBLIC CP15_WriteDomainAccessControl
PUBLIC CP15_WriteTTB
PUBLIC CP15_InvalidateIcacheInnerSharable
PUBLIC CP15_InvalidateBTBinnerSharable
PUBLIC CP15_InvalidateIcache
PUBLIC CP15_InvalidateIcacheByMva
PUBLIC CP15_InvalidateBTB
PUBLIC CP15_InvalidateBTBbyMva
PUBLIC CP15_InvalidateDcacheBySetWay
PUBLIC CP15_CleanDCacheBySetWay
PUBLIC CP15_CleanInvalidateDCacheBySetWay
PUBLIC CP15_InvalidateDcacheByMva
PUBLIC CP15_CleanDCacheByMva
PUBLIC CP15_CleanDCacheUMva
PUBLIC CP15_CleanInvalidateDcacheByMva
PUBLIC CP15_InvalidateTranslationTable
PUBLIC CP15_coherent_dcache_for_dma
PUBLIC CP15_invalidate_dcache_for_dma
PUBLIC CP15_clean_dcache_for_dma
PUBLIC CP15_flush_dcache_for_dma
PUBLIC CP15_flush_kern_dcache_for_dma
/**
* \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
* Reading from this register returns the device ID, the cache type, or the TCM status
* depending on the value of Opcode_2 used.
*/
SECTION .CP15_ReadID:DATA:NOROOT(2)
PUBLIC CP15_ReadID
CP15_ReadID:
mov r0, #0
mrc p15, 0, r0, c0, c0, 0
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
SECTION .CP15_ISB:DATA:NOROOT(2)
PUBLIC CP15_ISB
CP15_ISB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 4
nop
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
SECTION .CP15_DSB:DATA:NOROOT(2)
PUBLIC CP15_DSB
CP15_DSB:
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
nop
bx lr
/**
* \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
SECTION .CP15_DMB:DATA:NOROOT(2)
PUBLIC CP15_DMB
CP15_DMB:
mov r0, #0
mcr p15, 0, r0, c7, c10, 5
nop
bx lr
/**
* \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
SECTION .CP15_ExclusiveCache:DATA:NOROOT(2)
PUBLIC CP15_ExclusiveCache
CP15_ExclusiveCache:
mov r0, #0
mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #0x00000080
mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR
nop
bx lr
/**
* \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode
*/
SECTION .CP15_NonExclusiveCache:DATA:NOROOT(2)
PUBLIC CP15_NonExclusiveCache
CP15_NonExclusiveCache:
mov r0, #0
mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
bic r0, r0, #0x00000080
mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR
nop
bx lr
/**
* \brief Register c1 accesses the CSSELR Register, to select ICache
*/
SECTION .CP15_SelectICache:DATA:NOROOT(2)
PUBLIC CP15_SelectICache
CP15_SelectICache:
mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR
orr r0, r0, #0x1 ; Change 0th bit to ICache
mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR
nop
bx lr
/**
* \brief Register c1 accesses the CSSELR Register, to select DCache
*/
SECTION .CP15_SelectDCache:DATA:NOROOT(2)
PUBLIC CP15_SelectDCache
CP15_SelectDCache:
mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR
and r0, r0, #0xFFFFFFFE ; Change 0th bit to ICache
mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR
nop
bx lr
/**
* \brief Register c1 is the Control Register for the ARM926EJ-S processor.
* This register specifies the configuration used to enable and disable the
* caches and MMU. It is recommended that you access this register using a
* read-modify-write sequence
*/
SECTION .CP15_ReadControl:CODE:NOROOT(2)
PUBLIC CP15_ReadControl
CP15_ReadControl:
mov r0, #0
mrc p15, 0, r0, c1, c0, 0
bx lr
SECTION .CP15_WriteControl:CODE:NOROOT(2)
PUBLIC CP15_WriteControl
CP15_WriteControl:
mcr p15, 0, r0, c1, c0, 0
dsb
isb
bx lr
SECTION .CP15_WriteDomainAccessControl:CODE:NOROOT(2)
PUBLIC CP15_WriteDomainAccessControl
CP15_WriteDomainAccessControl:
mcr p15, 0, r0, c3, c0, 0
dsb
isb
bx lr
/**
* \brief ARMv7A architecture supports two translation tables
* Configure translation table base (TTB) control register cp15,c2
* to a value of all zeros, indicates we are using TTB register 0.
* write the address of our page table base to TTB register 0.
*/
SECTION .CP15_WriteTTB:CODE:NOROOT(2)
PUBLIC CP15_WriteTTB
CP15_WriteTTB:
mcr p15, 0, r0, c2, c0, 0
dsb
isb
bx lr
/**
* \brief Invalidate I cache predictor array inner Sharable
*/
SECTION .CP15_InvalidateIcacheInnerSharable:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcacheInnerSharable
CP15_InvalidateIcacheInnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 0
bx lr
/**
* \brief Invalidate entire branch predictor array inner Sharable
*/
SECTION .CP15_InvalidateBTBinnerSharable:CODE:NOROOT(2)
PUBLIC CP15_InvalidateBTBinnerSharable
CP15_InvalidateBTBinnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
bx lr
/**
* \brief Invalidate all instruction caches to PoU, also flushes branch target cache
*/
SECTION .CP15_InvalidateIcache:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcache
CP15_InvalidateIcache:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
isb
bx lr
/**
* \brief Invalidate instruction caches by VA to PoU
*/
SECTION .CP15_InvalidateIcacheByMva:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcacheByMva
CP15_InvalidateIcacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 1
bx lr
/**
* \brief Invalidate entire branch predictor array
*/
SECTION .CP15_InvalidateBTB:CODE:NOROOT(2)
PUBLIC CP15_InvalidateBTB
CP15_InvalidateBTB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 6
dsb
isb
bx lr
/**
* \brief Invalidate branch predictor array entry by MVA
*/
SECTION .CP15_InvalidateBTBbyMva:CODE:NOROOT(2)
PUBLIC CP15_InvalidateBTBbyMva
CP15_InvalidateBTBbyMva:
mcr p15, 0, r0, c7, c5, 7
bx lr
/***********************************************************
*
* ===Data Cache related maintenance functions===
*
**************************************************************/
// ===Data Cache maintenance by SetWay ===
/**
* \brief Invalidate entire data cache by set/way
*/
SECTION .CP15_InvalidateDcacheBySetWay:CODE:NOROOT(2)
PUBLIC CP15_InvalidateDcacheBySetWay
CP15_InvalidateDcacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 ; Num of ways
and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 ; Num of stes
and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB
mov r0, #0 ; 0:SHL:5
inv_way_loop
lsl r4, r1, #30
sub r1, r1, #1 ;
mov r3, r2
inv_line_loop
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c6, 2
sub r3, r3, #1 ; 1:SHL:30
cmp r3, #0
bpl inv_line_loop
cmp r1, #-1
bne inv_way_loop
nop
bx lr
/**
* \brief Clean entire data cache by set/way
*/
SECTION .CP15_CleanDCacheBySetWay:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheBySetWay
CP15_CleanDCacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 ; Num of ways
and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 ; Num of stes
and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB
mov r0, #0 ; 0:SHL:5
clean_way_loop
lsl r4, r1, #30
sub r1, r1, #1 ;
mov r3, r2
clean_line_loop
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c10, 2
sub r3, r3, #1 ; 1:SHL:30
cmp r3, #0
bpl clean_line_loop
cmp r1, #-1
bne clean_way_loop
nop
bx lr
/**
* \brief Clean and Invalidate entire data cache by set/way
*/
SECTION .CP15_CleanInvalidateDCacheBySetWay:CODE:NOROOT(2)
PUBLIC CP15_CleanInvalidateDCacheBySetWay
CP15_CleanInvalidateDCacheBySetWay:
mrc p15, 1, r0, c0, c0, 0
mov r1, r0, lsr #3 ; Num of ways
and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB
mov r2, r0, lsr #13 ; Num of stes
and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB
mov r0, #0 ; 0:SHL:5
clinv_way_loop
lsl r4, r1, #30
sub r1, r1, #1 ;
mov r3, r2
clinv_line_loop
orr r0, r4, r3, lsl #5
mcr p15, 0, r0, c7, c10, 2
sub r3, r3, #1 ; 1:SHL:30
cmp r3, #0
bpl clinv_line_loop
cmp r1, #-1
bne clinv_way_loop
dsb
isb
bx lr
// ===Data Cache maintenance by VA ===
/**
* \brief Invalidate data cache by VA to Poc
*/
SECTION .CP15_InvalidateDcacheByMva:CODE:NOROOT(2)
PUBLIC CP15_InvalidateDcacheByMva
CP15_InvalidateDcacheByMva:
mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
inv_loop
mcr p15, 0, r0, c7, c6, 1
add r3, r3, r2
cmp r3, r1
bls inv_loop
bx lr
/**
* \brief Clean data cache by MVA
*/
SECTION .CP15_CleanDCacheByMva:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheByMva
CP15_CleanDCacheByMva:
mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
clean_loop
mcr p15, 0, r0, c7, c10, 1
add r3, r3, r2
cmp r3, r1
bls clean_loop
bx lr
/**
* \brief Clean unified cache by MVA
*/
SECTION .CP15_CleanDCacheUMva:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheUMva
CP15_CleanDCacheUMva:
mov r0, #0
mcr p15, 0, r0, c7, c11, 1
bx lr
/**
* \brief Clean and invalidate data cache by VA to PoC
*/
SECTION .CP15_CleanInvalidateDcacheByMva:CODE:NOROOT(2)
PUBLIC CP15_CleanInvalidateDcacheByMva
CP15_CleanInvalidateDcacheByMva:
mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes
mov r3, r0
clinv_loop
mcr p15, 0, r0, c7, c14, 1
add r3, r3, r2
cmp r3, r1
bls clinv_loop
bx lr
/**
* \brief Invalidate translation table
*/
SECTION .CP15_InvalidateTranslationTable:CODE:NOROOT(2)
PUBLIC CP15_InvalidateTranslationTable
CP15_InvalidateTranslationTable:
mcr p15, 0, r0, c8, c3, 0
dsb
isb
mcr p15, 0, r0, c8, c7, 0
dsb
isb
bx lr
/**
* \brief flush translation table
*/
SECTION .CP15_FlushTranslationTable:CODE:NOROOT(2)
PUBLIC CP15_FlushTranslationTable
CP15_FlushTranslationTable:
mcr p15, 0, r0, c8, c3, 0
dsb
isb
bx lr
/**
* \brief Ensure that the I and D caches are coherent within specified
* region. This is typically used when code has been written to
* a memory region, and will be executed.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_coherent_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_coherent_dcache_for_dma
CP15_coherent_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r12, r0, r3
loop1:
mcr p15, 0, r12, c7, c11, 1 // clean D line to the point of unification
add r12, r12, r2
cmp r12, r1
blo loop1
dsb
// .macro icache_line_size, reg, tmp
mrc p15, 0, r3, c0, c0, 1 // read ctr
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r12, r0, r3
loop2:
mcr p15, 0, r12, c7, c5, 1 // invalidate I line
add r12, r12, r2
cmp r12, r1
blo loop2
mov r0, #0
mcr p15, 0, r0, c7, c1, 6 //invalidate BTB Inner Shareable
mcr p15, 0, r0, c7, c5, 6 // invalidate BTB
dsb
isb
bx lr
/**
* \brief Invalidate the data cache within the specified region; we will
* be performing a DMA operation in this region and we want to
* purge old data in the cache.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_invalidate_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_invalidate_dcache_for_dma
CP15_invalidate_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
tst r0, r3
bic r0, r0, r3
mcrne p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line
tst r1, r3
bic r1, r1, r3
mcrne p15, 0, r1, c7, c14, 1 // clean & invalidate D / U line
loop3:
mcr p15, 0, r0, c7, c6, 1 // invalidate D / U line
add r0, r0, r2
cmp r0, r1
blo loop3
dsb
bx lr
/**
* \brief Clean the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_clean_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_clean_dcache_for_dma
CP15_clean_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r0, r0, r3
loop4:
mcr p15, 0, r0, c7, c10, 1 // clean D / U line
add r0, r0, r2
cmp r0, r1
blo loop4
dsb
bx lr
/**
* \brief Flush the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_flush_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_flush_dcache_for_dma
CP15_flush_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r0, r0, r3
loop5:
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line
add r0, r0, r2
cmp r0, r1
blo loop5
dsb
bx lr
/**
* \brief CP15_flush_kern_dcache_for_dma
* Ensure that the data held in the page kaddr is written back to the page in question.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_flush_kern_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_flush_kern_dcache_for_dma
CP15_flush_kern_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
add r1, r0, r1
sub r3, r2, #1
bic r0, r0, r3
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D line / unified line
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
bx lr
END

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#if defined(__ICCARM__)
#include <intrinsics.h>
#endif
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Resets the counter and enables/disables all counters including PMCCNTR.
* \param ResetCounterType CounterType: Performance or Cycle counter
*/
static void CP15_PMUControl(uint8_t ResetCounterType, uint8_t EnableCounter)
{
uint32_t PMU_Value=0;
asm("mrc p15, 0, %0, c9, c12, 0" :"=r" (PMU_Value));
PMU_Value |= ((ResetCounterType << 1)| EnableCounter);
asm("mcr p15, 0, %0, c9, c12, 0" : : "r" (PMU_Value));
}
/**
* \brief Select Cycle Count divider
* \param Divider 0 for increment of counter at every single cycle or 1 for at every 64th cycle
*/
static void CP15_CycleCountDivider(uint8_t Divider)
{
uint32_t PMU_Value=0;
assert((Divider>1?0:1));
asm("mrc p15, 0, %0, c9, c12, 0" :"=r" (PMU_Value));
PMU_Value |= (Divider << 3);
asm("mcr p15, 0, %0, c9, c12, 0" : : "r" (PMU_Value));
}
/**
* \brief Enables PMCCNTR.
*/
static void CP15_EnablePMCNT(void)
{
uint32_t CNT_Value=0;
asm("mrc p15, 0, %0, c9, c12, 1" :"=r" (CNT_Value));
CNT_Value |= (uint32_t)((1 << CP15_PMCNTENSET));
asm("mcr p15, 0, %0, c9, c12, 1" : : "r" (CNT_Value));
}
/**
* \brief Enables PMCCNTR.
*/
static void CP15_EnableCounter(uint8_t Counter)
{
uint32_t CNT_Value=0;
asm("mrc p15, 0, %0, c9, c12, 1" :"=r" (CNT_Value));
CNT_Value |= Counter;
asm("mcr p15, 0, %0, c9, c12, 1" : : "r" (CNT_Value));
}
/**
* \brief Disables/clear PMCCNTR.
* \param Counter 0 or 1 to selct counter
*/
static void CP15_ClearPMCNT(void)
{
uint32_t CNT_Value = 0;
asm("mrc p15, 0, %0, c9, c12, 2" :"=r" (CNT_Value));
CNT_Value |= (uint32_t)(1 << CP15_PMCNTENCLEAR);
asm("mcr p15, 0, %0, c9, c12, 2" : : "r" (CNT_Value));
}
/**
* \brief Disables/Enables overflow flag.
* \param Enable Enables or disables the flag option
* \param ClearCounterFlag selects the counter flag to clear
*/
void CP15_OverflowStatus(uint8_t Enable, uint8_t ClearCounterFlag)
{
uint32_t OFW_Value=0;
asm("mrc p15, 0, %0, c9, c12, 3" :"=r" (OFW_Value));
OFW_Value |= ((Enable << 31)| ClearCounterFlag);
asm("mcr p15, 0, %0, c9, c12, 3" : : "r" (OFW_Value));
}
/**
* \brief Disables/Enables overflow flag.
* \param Enable Enables or disables the flag option
* \param ClearCounterFlag selects the counter flag to clear
*/
uint32_t CP15_ReadOverflowStatus(uint8_t EventCounter)
{
uint32_t OFW_Value=0;
asm("mrc p15, 0, %0, c9, c12, 3" :"=r" (OFW_Value));
OFW_Value = ((OFW_Value & EventCounter) >> (EventCounter - 1));
return OFW_Value;
}
/**
* \brief Increments the count of a performance monitor count register.
* \param IncrCounter 0 or 1 counters
*/
void CP15_SoftINCR(uint8_t IncrCounter)
{
uint32_t INRC_Value=0;
asm("mrc p15, 0, %0, c9, c12, 4" :"=r" (INRC_Value));
INRC_Value |= IncrCounter;
asm("mcr p15, 0, %0, c9, c12, 4" : : "r" (INRC_Value));
}
/**
* \brief Increments the count of a performance monitor count register.
* \param EventType Select Event Type
* \param Counter 0 or 1 counters
*/
static void CP15_SelectEvent(PerfEventType EventType, uint8_t Counter)
{
uint32_t CounterSelect=0;
assert((Counter == 1) || (Counter == 2));
CounterSelect = (Counter & 0x1F);
asm("mcr p15, 0, %0, c9, c12, 5" : : "r" (CounterSelect));
CounterSelect = (EventType & 0xFF);
asm("mcr p15, 0, %0, c9, c13, 1" : : "r" (CounterSelect)); // PMXEVTYPER
asm("mrc p15, 0, %0, c9, c13, 1" : "=r" (CounterSelect)); // PMXEVTYPER
}
/**
* \brief Enables USER mode
*/
void CP15_EnableUserMode(void)
{
uint8_t Value = 1;
asm("mcr p15, 0, %0, c9, c14, 0" : : "r" (Value));
}
/**
* \brief Enables Oveflows interrupt
* \param Enable Enables the Interrupt
* \param Counter 0 or 1 counters
*/
void CP15_EnableIT(uint8_t Enable, uint8_t Counter)
{
uint32_t ITE_Value=0;
ITE_Value |= ((Enable << 31)| Counter);
asm("mcr p15, 0, %0, c9, c14, 1" : : "r" (ITE_Value));
}
/**
* \brief Disables Oveflows interrupt
* \param Disable Disables the Interrupt
* \param Counter 0 or 1 counters
*/
void CP15_DisableIT(uint8_t Disable, uint8_t Counter)
{
uint32_t ITE_Value=0;
ITE_Value |= ((Disable << 31)| Counter);
asm("mcr p15, 0, %0, c9, c14, 2" : : "r" (ITE_Value));
}
/**
* \brief Initialize Cycle counter with Divider 64
*/
uint32_t CP15_CycleCounterInit(void)
{
uint32_t value;
CP15_ClearPMCNT();
CP15_EnablePMCNT();
CP15_OverflowStatus(ENABLE, CP15_BothCounter);
CP15_CycleCountDivider(CP15_CountDivider64);
CP15_PMUControl(CP15_ResetCycCounter, ENABLE);
asm("mrc p15, 0, %0, c9, c13, 0" :"=r" (value));
return value;
}
/**
* \brief Initialize Performance monitor counter with Divider 64
* \param Event Event type
* \param Counter 0 or 1 counters
*/
void CP15_PerfCounterInit(PerfEventType Event, uint8_t Counter)
{
CP15_PMUControl(CP15_ResetPerCounter, ENABLE);
CP15_SelectEvent(Event, Counter);
CP15_OverflowStatus(DISABLE, CP15_BothCounter);
CP15_EnableCounter(Counter);
}
/**
* \brief gives total number of event count
* \param Counter 0 or 1 counters
*/
uint32_t CP15_CountEvent(uint8_t Counter)
{
uint32_t value;
asm("mcr p15, 0, %0, c9, c12, 5" : : "r" (Counter));
asm("mrc p15, 0, %0, c9, c13, 2" :"=r" (value)); // PMXEVTYPER
return (value);
}
/**
* \brief gives total number of cycle count
*/
uint32_t CP15_GetCycleCounter(void)
{
uint32_t value;
asm("mrc p15, 0, %0, c9, c13, 0" :"=r" (value));
return value;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _CP15_PMU_H
#define _CP15_PMU_H
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
#define CP15_PMCNTENSET 31
#define CP15_PMCNTENCLEAR 31
#define CP15_PMCR_DIVIDER 3
#define CP15_PMCR_RESET 2
#define CP15_PMCR_ENABLE 0
#define CP15_NoReset 0
#define CP15_ResetPerCounter 1
#define CP15_ResetCycCounter 2
#define CP15_ResetPerCycCounter 3
#define CP15_CountDividerSingle 0
#define CP15_CountDivider64 1
#define CP15_CounterNone 0
#define CP15_Counter0 1
#define CP15_Counter1 2
#define CP15_BothCounter 3
typedef enum
{
L1_IC_FILL, // Level 1 instruction cache refill
L1_ITLB_FILL, // Level 1 instruction TLB refill
L1_DC_FILL, // Level 1 data cache refill
L1_DC_ACC, // Level 1 data cache access
L1_DTLB_FILL, // Level 1 data TLB refill
LOAD, // Load
STORE, // Store
InstArchExec, // Instruction architecturally executed
ExcepetionTaken, // Exception taken
ExcepetionRet, // Exception return
WrCONTEXTIDR, // Write to CONTEXTIDR
SoftPCChange, // Software change of the PC
ImmBr, // Immediate branch
ProcRet, // Procedure return
UnalingedLdStr, // Unaligned load or store
MispredictedBranchExec, // Mispredicted or not predicted branch speculatively executed
PredictedBranchExec, // Predictable branch speculatively executed
DataMemAcc, // Data memory access.
ICAcc, // Instruction Cache access.
DCEviction, // Data cache eviction.
IRQException, // IRQ exception taken.
FIQException, // FIQ exception taken.
ExtMemReq, // External memory request.
NCExtMemReq, // Non-cacheable external memory request
PrefetchLineFill, // Linefill because of prefetch.
PrefetchLineDrop, // Prefetch linefill dropped.
EnteringRAmode, // Entering read allocate mode.
RAmode, // Read allocate mode.
reserved, // Reserved, do not use
DWstallSBFfull // Data Write operation that stalls the pipeline because the store buffer is full.
}PerfEventType;
extern uint32_t CP15_CycleCounterInit(void);
extern uint32_t CP15_GetCycleCounter(void);
extern uint32_t CP15_ReadOverflowStatus(uint8_t EventCounter);
extern void CP15_OverflowStatus(uint8_t Enable, uint8_t ClearCounterFlag);
extern void CP15_SoftINCR(uint8_t IncrCounter);
extern uint32_t CP15_CountEvent(uint8_t Counter);
extern void CP15_EnableUserMode(void);
extern void CP15_EnableIT(uint8_t Enable, uint8_t Counter);
extern void CP15_DisableIT(uint8_t Disable, uint8_t Counter);
extern void CP15_PerfCounterInit(PerfEventType Event, uint8_t Counter);
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* USB Device Framework configurations.
*
*/
#ifndef USBD_CONFIG_H
#define USBD_CONFIG_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** \addtogroup usbd_config
*@{
*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_ids USBD Device IDs
* @{
*/
#define USBD_VID_ATMEL 0x03EB /**< Vendor ID: Atmel */
#define USBD_PID_ENUM 0x0001 /**< Product ID: Enum (Core) */
#define USBD_PID_CDCDSERIAL 0x6119 /**< Product ID: CDC Serial */
#define USBD_PID_HIDKEYBOARD 0x6127 /**< Product ID: HID Keyboard */
#define USBD_PID_AUDIO 0x6128 /**< Product ID: Audio devices */
#define USBD_PID_MSD 0x6129 /**< Product ID: Massstorage */
#define USBD_PID_CDCHID 0x6130 /**< Product ID: composite */
#define USBD_PID_CDCAUDIO 0x6131 /**< Product ID: composite */
#define USBD_PID_CDCMSD 0x6132 /**< Product ID: composite */
#define USBD_PID_CDCCDC 0x6133 /**< Product ID: composite */
#define USBD_PID_HIDAUDIO 0x6134 /**< Product ID: composite */
#define USBD_PID_HIDMSD 0x6135 /**< Product ID: composite */
#define USBD_PID_HIDMOUSE 0x6200 /**< Product ID: HID Mouse */
#define USBD_PID_HIDTRANSFER 0x6201 /**< Product ID: HID Transfer */
#define USBD_PID_CCID 0x6203 /**< Product ID: CCID */
#define USBD_RELEASE_1_00 0x0100 /**< Release: 1.00 */
/** @}*/
/** \addtogroup usbd_general_config USBD General Configure
* @{
* This page lists general configurations for all USB device drivers.
* - \ref USBD_BMATTRIBUTES
*/
/** default USB Device attributes configuration descriptor
* (bus or self powered, remote wakeup) */
#define USBD_BMATTRIBUTES BOARD_USB_BMATTRIBUTES
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Mass storage
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_msdd_config USB MassStorage Configure
* @{
* This page lists the defines used by the Mass Storage driver.
*
* \section msd_ep_addr Endpoint Addresses
* - \ref MSDDriverDescriptors_BULKOUT
* - \ref MSDDriverDescriptors_BULKIN
*/
/** Address of the Mass Storage bulk-out endpoint.*/
#define MSDDriverDescriptors_BULKOUT 1
/** Address of the Mass Storage bulk-in endpoint.*/
#define MSDDriverDescriptors_BULKIN 2
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - CDC Serial
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_cdc_serial_config USB CDC Serial Configure
* @{
* This page lists the defines used by the CDC Serial Device Driver.
*
* \section cdcd_ep_addr Endpoint Addresses
* - \ref CDCDSerialDriverDescriptors_DATAOUT
* - \ref CDCDSerialDriverDescriptors_DATAIN
* - \ref CDCDSerialDriverDescriptors_NOTIFICATION
*/
/** Data OUT endpoint number */
#define CDCDSerialDriverDescriptors_DATAOUT 1
/** Data IN endpoint number */
#define CDCDSerialDriverDescriptors_DATAIN 2
/** Notification endpoint number */
#define CDCDSerialDriverDescriptors_NOTIFICATION 3
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_config USB Audio General Configure
* @{
* This page lists definitions for USB Audio Devices Drivers.
* - \ref
*/
#if defined(at91sam7s) || defined(at91sam9xe)
/** Sample rate in Hz. */
#define AUDDevice_SAMPLERATE 32000UL
/** Number of channels in audio stream. */
#define AUDDevice_NUMCHANNELS 1
/** Number of bytes in one sample. */
#define AUDDevice_BYTESPERSAMPLE 2
#else
/** Sample rate in Hz. */
#define AUDDevice_SAMPLERATE 48000UL
/** Number of channels in audio stream. */
#define AUDDevice_NUMCHANNELS 2
/** Number of bytes in one sample. */
#define AUDDevice_BYTESPERSAMPLE 2
#endif
/** Number of bits in one sample. */
#define AUDDevice_BITSPERSAMPLE (AUDDevice_BYTESPERSAMPLE * 8)
/** Number of bytes in one USB subframe. */
#define AUDDevice_BYTESPERSUBFRAME (AUDDevice_NUMCHANNELS * \
AUDDevice_BYTESPERSAMPLE)
/** Number of samples in one USB frame. */
#define AUDDevice_SAMPLESPERFRAME (AUDDevice_SAMPLERATE / 1000 \
* AUDDevice_NUMCHANNELS)
/** Number of bytes in one USB frame. */
#define AUDDevice_BYTESPERFRAME (AUDDevice_SAMPLESPERFRAME * \
AUDDevice_BYTESPERSAMPLE)
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio - Desktop Speaker
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_speaker_config USB Speaker Configure
* @{
* This page lists the definitions for USB Audio Speaker Device Driver.
* - \ref AUDDSpeakerDriverDescriptors_DATAOUT
* - \ref AUDDSpeakerDriverDescriptors_FS_INTERVAL
* - \ref AUDDSpeakerDriverDescriptors_HS_INTERVAL
*
* \note for UDP, uses IN EPs that support double buffer; for UDPHS, uses
* IN EPs that support DMA and High bandwidth.
*/
/** Data out endpoint number. */
#define AUDDSpeakerDriverDescriptors_DATAOUT 0x02
/** Endpoint polling interval 2^(x-1) * 125us */
#define AUDDSpeakerDriverDescriptors_HS_INTERVAL 0x02
/** Endpoint polling interval 2^(x-1) * ms */
#define AUDDSpeakerDriverDescriptors_FS_INTERVAL 0x01
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio - Speaker Phone
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_speakerphone_config USB Speaker Phone Configure
* @{
* This page lists the definitions for USB Audio Speaker Phone Device Driver.
* - \ref AUDDSpeakerPhoneDriverDescriptors_DATAOUT
* - \ref AUDDSpeakerPhoneDriverDescriptors_DATAIN
* - \ref AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL
* - \ref AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL
*/
#if defined(at91sam7s) || defined(at91sam9xe)
/** Data out endpoint number, size 64B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01
/** Data in endpoint number, size 64B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x02
#elif defined(CHIP_USB_UDP)
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x04
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x05
#elif defined(at91sam9m10ek)
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06
#else
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x05
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06
#endif
/** Endpoint polling interval 2^(x-1) * 125us */
#define AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL 0x04
/** Endpoint polling interval 2^(x-1) * ms */
#define AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL 0x01
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Keyboard
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_keyboard_config USB HID Keyboard Device Configure
* @{
* This page lists the defines used by the HID Keyboard Device Driver.
*
* \section hidd_k_ep_addr Endpoint Addresses
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT
* \section hidd_k_ep_polling Endpoint Polling Rate
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING
*/
/** Interrupt IN endpoint number */
#define HIDDKeyboardDriverDescriptors_INTERRUPTIN 1
/** Interrupt IN endpoint polling rate (in milliseconds) */
#define HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING 10
/** Interrupt OUT endpoint number */
#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT 2
/** Interrupt OUT endpoint polling rate (in milliseconds) */
#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING 10
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Mouse
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_mouse_config USB HID Mouse Device Configure
* @{
* This page lists the defines used by the HID Mouse Device Driver.
*
* \section hidd_m_ep_addr Endpoint Addresses
* - \ref HIDDMouseDriverDescriptors_INTERRUPTIN
* \section hidd_m_ep_polling Endpoint Polling Rate
* - \ref HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING
*/
/** Interrupt IN endpoint number */
#define HIDDMouseDriverDescriptors_INTERRUPTIN 1
/** Interrupt IN endpoint polling rate (in milliseconds) */
#define HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING 10
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Transfer (Customize device)
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_xfr_config USB HID Transfer Device Configure
* @{
* This page lists the defines used by the HID Transfer Device Driver.
*
* \section hidd_t_ep_addr Endpoint Addresses
* - \ref HIDDTransferDriverDescriptors_INTERRUPTIN
* - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT
* \section hidd_t_ep_polling Endpoint Polling Rate
* - \ref HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING
* - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING
*/
/** Interrupt IN endpoint number. */
#define HIDDTransferDriverDescriptors_INTERRUPTIN 1
/** Polling rate in ms */
#define HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING 50
/** Interrupt IN endpoint polling rate (in milliseconds). */
#define HIDDTransferDriverDescriptors_INTERRUPTOUT 2
/** Polling rate in ms */
#define HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING 50
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Composite
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_composite_config USB Composite Device Configure
* @{
*/
/** @}*/
/**@}*/
#endif //#ifndef USBD_CONFIG_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Collection of LEDs for using the USB device controller on AT91
* microcontrollers.
*/
#ifndef USBDLEDS_H
#define USBDLEDS_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** \addtogroup usbd_hal
*@{
*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_leds USB Device LEDs
* @{
* This page lists the LEDs used in the USB %device driver.
*
* - USBD_LEDPOWER
* - USBD_LEDUSB
* - USBD_LEDOTHER
*/
/** LED for indicating that the device is powered. */
#define USBD_LEDPOWER 0
/** LED for indicating USB activity. */
#define USBD_LEDUSB 1
/** LED for custom usage. */
#define USBD_LEDOTHER 2
/** @}*/
/**@}*/
#endif //#ifndef USBDLEDS_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.
*
* \section Usage
*
* -# Configurate the pins for ADC.
* -# Initialize the ADC with ADC_Initialize().
* -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming().
* -# Select the active channel using ADC_EnableChannel().
* -# Start the conversion with ADC_StartConversion().
* -# Wait the end of the conversion by polling status with ADC_GetStatus().
* -# Finally, get the converted data using ADC_GetConvertedData() or ADC_GetLastConvertedData().
*
*/
#ifndef _ADC_
#define _ADC_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <assert.h>
#include <stdint.h>
/*------------------------------------------------------------------------------
* Definitions
*------------------------------------------------------------------------------*/
/* Max. ADC Clock Frequency (Hz) */
#define ADC_CLOCK_MAX 20000000
/* Max. normal ADC startup time (us) */
#define ADC_STARTUP_NORMAL_MAX 40
/* Max. fast ADC startup time (us) */
#define ADC_STARTUP_FAST_MAX 12
/* Definitions for ADC channels */
#define ADC_CHANNEL_0 0
#define ADC_CHANNEL_1 1
#define ADC_CHANNEL_2 2
#define ADC_CHANNEL_3 3
#define ADC_CHANNEL_4 4
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
* Macros function of register access
*------------------------------------------------------------------------------*/
#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR)
#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START)
#define ADC_EnableChannel( pAdc, dwChannel ) {\
(pAdc)->ADC_CHER = (1 << (dwChannel));\
}
#define ADC_DisableChannel(pAdc, dwChannel) {\
(pAdc)->ADC_CHDR = (1 << (dwChannel));\
}
#define ADC_EnableIt(pAdc, dwMode) {\
(pAdc)->ADC_IER = (dwMode);\
}
#define ADC_DisableIt(pAdc, dwMode) {\
(pAdc)->ADC_IDR = (dwMode);\
}
#define ADC_SetChannelGain(pAdc,dwMode) {\
(pAdc)->ADC_CGR = dwMode;\
}
#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY)
#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR)
#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk))
#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR)
#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR)
#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR)
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern void ADC_Initialize( Adc* pAdc, uint32_t dwId );
extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck );
extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling );
extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel );
extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode);
extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis );
extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 );
extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh );
extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis );
extern void ADC_ConfigureExtMode( Adc *pAdc, uint32_t dwMode );
extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ;
extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ;
extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ;
extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ;
extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ;
extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv);
extern uint32_t ADC_GetTsXPosition(Adc *pADC);
extern uint32_t ADC_GetTsYPosition(Adc *pADC);
extern uint32_t ADC_GetTsPressure(Adc *pADC);
extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime);
extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis);
extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs );
extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs );
extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod);
extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode);
extern void ADC_TsCalibration( Adc *pAdc );
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _ADC_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _AES_
#define _AES_
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
/*------------------------------------------------------------------------------*/
/* Definition */
/*------------------------------------------------------------------------------*/
#define AES_MR_CIPHER_ENCRYPT 1
#define AES_MR_CIPHER_DECRYPT 0
/*------------------------------------------------------------------------------*/
/* Exported functions */
/*------------------------------------------------------------------------------*/
extern void AES_Start(void);
extern void AES_SoftReset(void);
extern void AES_Recount(void);
extern void AES_Configure(uint32_t mode);
extern void AES_EnableIt(uint32_t sources);
extern void AES_DisableIt(uint32_t sources);
extern uint32_t AES_GetStatus(void);
extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength);
extern void AES_SetInput(uint32_t *data);
extern void AES_GetOutput(uint32_t *data);
extern void AES_SetVector(const uint32_t *pVector);
extern void AES_SetAadLen(uint32_t len);
extern void AES_SetDataLen(uint32_t len);
extern void AES_SetGcmHash(uint32_t * hash);
extern void AES_GetGcmTag(uint32_t * tag);
extern void AES_GetGcmCounter(uint32_t * counter);
extern void AES_GetGcmH(uint32_t *h);
#endif /* #ifndef _AES_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _AESB_
#define _AESB_
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
/*------------------------------------------------------------------------------*/
/* Definition */
/*------------------------------------------------------------------------------*/
#define AESB_MR_CIPHER_ENCRYPT 1
#define AESB_MR_CIPHER_DECRYPT 0
/*------------------------------------------------------------------------------*/
/* Exported functions */
/*------------------------------------------------------------------------------*/
extern void AESB_Start(void);
extern void AESB_SoftReset(void);
extern void AESB_Recount(void);
extern void AESB_Configure(uint32_t mode);
extern void AESB_EnableIt(uint32_t sources);
extern void AESB_DisableIt(uint32_t sources);
extern uint32_t AESB_GetStatus(void);
extern void AESB_WriteKey(const uint32_t *pKey);
extern void AESB_SetInput(uint32_t *data);
extern void AESB_GetOutput(uint32_t *data);
extern void AESB_SetVector(const uint32_t *pVector);
#endif /* #ifndef _AESB_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Methods and definitions for configuring interrupts.
*
* \section Usage
* -# Enable or disable interrupt generation of a particular source with
* IRQ_EnableIT and IRQ_DisableIT.
* -# Start or stop the timer clock using TC_Start() and TC_Stop().
*/
#ifndef AIC_H
#define AIC_H
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
/*------------------------------------------------------------------------------
* Global functions
*------------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
extern void AIC_EnableIT( uint32_t source);
extern void AIC_DisableIT(uint32_t source);
#ifdef __cplusplus
}
#endif
#endif //#ifndef AIC_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Provide a routine for asynchronous transfer.
*
*/
#ifndef _ASYNC_
#define _ASYNC_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/** Transfer is still pending.*/
#define ASYNC_STATUS_PENDING 0xFF
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Type
*----------------------------------------------------------------------------*/
/** \brief Asynchronous transfer descriptor. */
typedef struct _Async
{
/** Asynchronous transfer status.*/
volatile uint32_t status ;
/** Callback function to invoke when transfer completes or fails.*/
void *callback ;
/** Driver storage area; do not use.*/
uint8_t pStorage[9] ;
} Async ;
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint32_t ASYNC_IsFinished( Async* pAsync ) ;
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _ASYNC_ */

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/*-----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
*-----------------------------------------------------------------------------
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*----------------------------------------------------------------------------
* File Name : catb.h
* Object :
* Creation : DAL 21/Jun/2013
*----------------------------------------------------------------------------
*/
#ifndef _V_CATB_H
#define _V_CATB_H
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief Catb hardware registers */
typedef struct {
__IO uint32_t CATB_CR; /**< \brief (CATB Offset: 0x00) Control Register */
__IO uint32_t CATB_CNTCR; /**< \brief (CATB Offset: 0x04) Counter Control Register */
__IO uint32_t CATB_IDLE; /**< \brief (CATB Offset: 0x08) Sensor Idle Level */
__IO uint32_t CATB_LEVEL; /**< \brief (CATB Offset: 0x0C) Sensor Relative Level */
__IO uint32_t CATB_RAW; /**< \brief (CATB Offset: 0x10) Sensor Raw Value */
__IO uint32_t CATB_TIMING; /**< \brief (CATB Offset: 0x14) Filter Timing Register */
__IO uint32_t CATB_THRESH; /**< \brief (CATB Offset: 0x18) Threshold Register */
__IO uint32_t CATB_PINSEL; /**< \brief (CATB Offset: 0x1C) Pin Selection Register */
__IO uint32_t CATB_DMA; /**< \brief (CATB Offset: 0x20) Direct Memory Access Register */
__IO uint32_t CATB_ISR; /**< \brief (CATB Offset: 0x24) Interrupt Status Register */
__IO uint32_t CATB_IER; /**< \brief (CATB Offset: 0x28) Interrupt Enable Register */
__IO uint32_t CATB_IDR; /**< \brief (CATB Offset: 0x2C) Interrupt Disable Register */
__IO uint32_t CATB_IMR; /**< \brief (CATB Offset: 0x30) Interrupt Mask Register */
__IO uint32_t CATB_SCR; /**< \brief (CATB Offset: 0x34) Status Clear Register */
__I uint32_t Reserved1[2];
__IO uint32_t CATB_INTCHi; /**< \brief (CATB Offset: 0x40) In-Touch Status Register i */
__I uint32_t Reserved2[3];
__IO uint32_t CATB_INTCHCLRn; /**< \brief (CATB Offset: 0x50) In-Touch Status Clear Register n */
__I uint32_t Reserved3[3];
__IO uint32_t CATB_OUTTCHi; /**< \brief (CATB Offset: 0x60) Out-of-Touch Status Register i */
__I uint32_t Reserved4[3];
__IO uint32_t CATB_OUTTCHCLRn; /**< \brief (CATB Offset: 0x70) Out-of-Touch Status Clear Register n */
__I uint32_t Reserved5[33];
__IO uint32_t CATB_PARAMETER; /**< \brief (CATB Offset: 0xF8) Parameter Register */
} Catb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define LENGTH 0x1F
#define TLEVEL 100
#define TIDLE 0
#define CATB_THRESH_RTHRESH 12
#define CATB_THRESH_FTHRESH 0
#define CATB_ISR_INTCH (0x1u << 1) /**< \brief (CATB_ISR_INTCH) In-touch */
#define CATB_ISR_OUTTCH (0x1u<< 2) /**< \brief (CATB_ISR_OUTTCH) Out-touch */
#define CATB_IER_INTCH (0x1u << 1) /**< \brief (CATB_IER_INTCH) In-touch */
#define CATB_IER_OUTTCH (0x1u<< 2) /**< \brief (CATB_IER_OUTTCH) Out-touch */
#define CATB_CR_SWRST (0x1u << 31)
#define CATB_CR_EN ( 1u<<0 )
#define CATB_CR_CHARGET_Pos 16
#define CATB_CR_CHARGET_Msk (0xfu << CATB_CR_CHARGET_Pos) /**< \brief (CATB_CNTCR) Counter Top Value */
#define CATB_CR_CHARGET(value) ((CATB_CR_CHARGET_Msk & ((value) << CATB_CR_CHARGET_Pos)))
#define CATB_CNTCR_TOP 0
#define CATB_SPREAD 24
#define CATB_REPEAT 28
#define CATB_TIMING_TIDLE 16
#define CATB_TIMING_TLEVEL 0
#define CATB_ISR_SAMPLE (1 << 0)
#define CATB_CR_RUN (0x1u << 1)
#define CATB_CR_IIDLE (1<< 2)
#define CATB_CR_DMAEN (1 << 7)
#endif //_V_CATB_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup emac_module
* @{
* Provides the interface to configure and use the EMAC peripheral.
*
* \section emac_usage Usage
* - Configure Emac::EMAC_NCFG with EMAC_Configure(), some of related controls
* are also available, such as:
* - EMAC_SetSpeed(): Setup EMAC working clock.
* - EMAC_FullDuplexEnable(): Working in full duplex or not.
* - EMAC_CpyAllEnable(): Copying all valid frames (\ref EMAC_NCFG_CAF).
* - ...
* - Setup Emac::EMAC_NCR with EMAC_NetworkControl(), more related controls
* can modify with:
* - EMAC_ReceiveEnable(): Enable/Disable Rx.
* - EMAC_TransmitEnable(): Enable/Disable Tx.
* - EMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
* - ...
* - Manage EMAC interrupts with EMAC_EnableIt(), EMAC_DisableIt(),
* EMAC_GetItMask() and EMAC_GetItStatus().
* - Manage EMAC Tx/Rx status with EMAC_GetTxStatus(), EMAC_GetRxStatus()
* EMAC_ClearTxStatus() and EMAC_ClearRxStatus().
* - Manage EMAC Queue with EMAC_SetTxQueue(), EMAC_GetTxQueue(),
* EMAC_SetRxQueue() and EMAC_GetRxQueue(), the queue descriptor can define
* by \ref sEmacRxDescriptor and \ref sEmacTxDescriptor.
* - Manage PHY through EMAC is performed by
* - EMAC_ManagementEnable(): Enable/Disable PHY management.
* - EMAC_PHYMaintain(): Execute PHY management commands.
* - EMAC_PHYData(): Return PHY management data.
* - EMAC_IsIdle(): Check if PHY is idle.
* - Setup EMAC parameters with following functions:
* - EMAC_SetHash(): Set Hash value.
* - EMAC_SetAddress(): Set MAC address.
* - Enable/Disable EMAC transceiver clock via EMAC_TransceiverClockEnable()
* - Switch EMAC MII/RMII mode through EMAC_RMIIEnable()
*
* For more accurate information, please look at the EMAC section of the
* Datasheet.
*
* \sa \ref emacd_module
*
* Related files:\n
* emac.c\n
* emac.h.\n
*
* \defgroup emac_defines EMAC Defines
* \defgroup emac_structs EMAC Data Structs
* \defgroup emac_functions EMAC Functions
*/
/**@}*/
#ifndef _EMAC_H
#define _EMAC_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Defines
*----------------------------------------------------------------------------*/
/** \addtogroup emac_defines
@{*/
/** The buffer addresses written into the descriptors must be aligned so the
last few bits are zero. These bits have special meaning for the EMAC
peripheral and cannot be used as part of the address. */
#define EMAC_RXD_ADDR_MASK 0xFFFFFFFC
#define EMAC_RXD_bmWRAP (1ul << 1) /**< Wrap bit */
#define EMAC_RXD_bmOWNERSHIP (1ul << 0) /**< Ownership bit */
#define EMAC_RXD_bmBROADCAST (1ul << 31) /**< Broadcast detected */
#define EMAC_RXD_bmMULTIHASH (1ul << 30) /**< Multicast hash match */
#define EMAC_RXD_bmUNIHASH (1ul << 29) /**< Unicast hash match */
#define EMAC_RXD_bmEXTADDR (1ul << 28) /**< External address match */
#define EMAC_RXD_bmADDR1 (1ul << 26) /**< Address 1 match */
#define EMAC_RXD_bmADDR2 (1ul << 25) /**< Address 2 match */
#define EMAC_RXD_bmADDR3 (1ul << 24) /**< Address 3 match */
#define EMAC_RXD_bmADDR4 (1ul << 23) /**< Address 4 match */
#define EMAC_RXD_bmTYPE (1ul << 22) /**< Type ID match */
#define EMAC_RXD_bmVLAN (1ul << 21) /**< VLAN tag detected */
#define EMAC_RXD_bmPRIORITY (1ul << 20) /**< Prority tag detected */
#define EMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN prority */
#define EMAC_RXD_bmCFI (1ul << 16) /**< Concatenation Format Indicator
only if bit 21 is set */
#define EMAC_RXD_bmEOF (1ul << 15) /**< End of frame */
#define EMAC_RXD_bmSOF (1ul << 14) /**< Start of frame */
#define EMAC_RXD_OFFSET_MASK /**< Receive buffer offset */
#define EMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS
(if selected) */
#define EMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */
#define EMAC_TXD_bmUSED (1ul << 31) /**< Frame is transmitted */
#define EMAC_TXD_bmWRAP (1ul << 30) /**< Last descriptor */
#define EMAC_TXD_bmERROR (1ul << 29) /**< Retry limit exceed, error */
#define EMAC_TXD_bmUNDERRUN (1ul << 28) /**< Transmit underrun */
#define EMAC_TXD_bmEXHAUSTED (1ul << 27) /**< Buffer exhausted */
#define EMAC_TXD_bmNOCRC (1ul << 16) /**< No CRC */
#define EMAC_TXD_bmLAST (1ul << 15) /**< Last buffer in frame */
#define EMAC_TXD_LEN_MASK (0x7FF) /**< Length of buffer */
/** The MAC can support frame lengths up to 1536 bytes. */
#define EMAC_FRAME_LENTGH_MAX 1536
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup emac_structs
@{*/
#ifdef __ICCARM__ // IAR
#define PACKED_ATTR
#elif defined ( __GNUC__ ) /* GCC CS3 */
#define PACKED_ATTR __attribute__((packed, aligned(8)))
#endif
/** Receive buffer descriptor struct */
typedef struct _EmacRxDescriptor {
union _EmacRxAddr {
uint32_t val;
struct _EmacRxAddrBM {
uint32_t bOwnership:1, /**< User clear, EMAC set this to one once
it has successfully written a frame to
memory */
bWrap:1, /**< Marks last descriptor in receive buffer */
addrDW:30; /**< Address in number of DW */
} bm;
} addr; /**< Address, Wrap & Ownership */
union _EmacRxStatus {
uint32_t val;
struct _EmacRxStatusBM {
uint32_t len:12, /** Length of frame including FCS */
offset:2, /** Receive buffer offset,
bits 13:12 of frame length for jumbo
frame */
bSof:1, /** Start of frame */
bEof:1, /** End of frame */
bCFI:1, /** Concatenation Format Indicator */
vlanPriority:3, /** VLAN priority (if VLAN detected) */
bPriorityDetected:1, /** Priority tag detected */
bVlanDetected:1, /**< VLAN tag detected */
bTypeIDMatch:1, /**< Type ID match */
bAddr4Match:1, /**< Address register 4 match */
bAddr3Match:1, /**< Address register 3 match */
bAddr2Match:1, /**< Address register 2 match */
bAddr1Match:1, /**< Address register 1 match */
reserved:1,
bExtAddrMatch:1, /**< External address match */
bUniHashMatch:1, /**< Unicast hash match */
bMultiHashMatch:1, /**< Multicast hash match */
bBroadcastDetected:1; /**< Global all ones broadcast
address detected */
} bm;
} status;
}PACKED_ATTR sEmacRxDescriptor; /* GCC */
/** Transmit buffer descriptor struct */
typedef struct _EmacTxDescriptor {
uint32_t addr;
union _EmacTxStatus {
uint32_t val;
struct _EmacTxStatusBM {
uint32_t len:11, /**< Length of buffer */
reserved:4,
bLastBuffer:1, /**< Last buffer (in the current frame) */
bNoCRC:1, /**< No CRC */
reserved1:10,
bExhausted:1, /**< Buffer exhausted in mid frame */
bUnderrun:1, /**< Transmit underrun */
bError:1, /**< Retry limit exceeded, error detected */
bWrap:1, /**< Marks last descriptor in TD list */
bUsed:1; /**< User clear, EMAC sets this once a frame
has been successfully transmitted */
} bm;
} status;
} PACKED_ATTR sEmacTxDescriptor; /* GCC */
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup emac_functions
@{*/
extern void EMAC_NetworkControl(Emac *pEmac, uint32_t bmNCR);
extern uint32_t EMAC_GetNetworkControl(Emac * pEmac);
extern void EMAC_ReceiveEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_TransmitEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_ManagementEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_ClearStatistics(Emac * pEmac);
extern void EMAC_IncreaseStatistics(Emac * pEmac);
extern void EMAC_StatisticsWriteEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_BackPressureEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_TransmissionStart(Emac * pEmac);
extern void EMAC_TransmissionHalt(Emac * pEmac);
extern void EMAC_Configure(Emac * pEmac,uint32_t dwCfg);
extern uint32_t EMAC_GetConfigure(Emac * pEmac);
extern void EMAC_SetSpeed(Emac * pEmac,uint8_t bSpeed);
extern void EMAC_FullDuplexEnable(Emac * pEmac,uint8_t bFD);
extern void EMAC_CpyAllEnable(Emac * pEmac,uint8_t bCAF);
extern void EMAC_JumboFrameEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_BroadcastDisable(Emac * pEmac,uint8_t bDisEna);
extern void EMAC_MulticastHashEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_BigFrameEnable(Emac * pEmac,uint8_t bEnaDis);
extern uint8_t EMAC_SetClock(Emac * pEmac,uint32_t dwMck);
extern void EMAC_RetryTestEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_PauseFrameEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_SetRxBufferOffset(Emac * pEmac,uint8_t bOffset);
extern void EMAC_RxLenthCheckEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_DiscardFCSEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_EFRHD(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_IRXFCS(Emac * pEmac,uint8_t bEnaDis);
extern uint32_t EMAC_GetStatus(Emac * pEmac);
extern uint8_t EMAC_GetMDIO(Emac * pEmac);
extern uint8_t EMAC_IsIdle(Emac * pEmac);
extern uint32_t EMAC_GetTxStatus(Emac * pEmac);
extern void EMAC_ClearTxStatus(Emac * pEmac,uint32_t dwStatus);
extern uint32_t EMAC_GetRxStatus(Emac * pEmac);
extern void EMAC_ClearRxStatus(Emac * pEmac,uint32_t dwStatus);
extern void EMAC_SetTxQueue(Emac * pEmac,uint32_t dwAddr);
extern uint32_t EMAC_GetTxQueue(Emac * pEmac);
extern void EMAC_SetRxQueue(Emac * pEmac,uint32_t dwAddr);
extern uint32_t EMAC_GetRxQueue(Emac * pEmac);
extern void EMAC_EnableIt(Emac * pEmac,uint32_t dwSources);
extern void EMAC_DisableIt(Emac * pEmac,uint32_t dwSources);
extern uint32_t EMAC_GetItMask(Emac * pEmac);
extern uint32_t EMAC_GetItStatus(Emac * pEmac);
extern void EMAC_PHYMaintain(Emac * pEmac,
uint8_t bPhyAddr, uint8_t bRegAddr,
uint8_t bRW,
uint16_t wData);
extern uint16_t EMAC_PHYData(Emac * pEmac);
extern void EMAC_SetPauseTime(Emac * pEmac,uint16_t wPTime);
extern void EMAC_SetHash(Emac * pEmac,uint32_t dwHashTop,uint32_t dwHashBottom);
extern void EMAC_SetHash64(Emac * pEmac,uint64_t ddwHash);
extern void EMAC_SetAddress(Emac * pEmac,uint8_t bIndex,uint8_t * pMacAddr);
extern void EMAC_SetAddress32(Emac * pEmac,uint8_t bIndex,
uint32_t dwMacT,uint32_t dwMacB);
extern void EMAC_SetAddress64(Emac * pEmac,uint8_t bIndex,uint64_t ddwMac);
extern void EMAC_SetTypeID(Emac * pEmac,uint16_t wTID);
extern uint16_t EMAC_GetTypeID(Emac * pEmac);
extern void EMAC_RMIIEnable(Emac * pEmac,uint8_t bEnaDis);
extern void EMAC_TransceiverClockEnable(Emac * pEmac,uint8_t bEnaDis);
/** @}*/
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _EMAC_H */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for Synchronous Serial (SSC) controller.
*
*/
#ifndef _FUSE_
#define _FUSE_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint32_t FUSE_Read (uint8_t wordPosition );
extern void FUSE_Write (uint32_t data, uint8_t wordPosition );
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _FUSE_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmac_module
* @{
* Provides the interface to configure and use the GMAC peripheral.
*
* \section gmac_usage Usage
* - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls
* are also available, such as:
* - GMAC_SetSpeed(): Setup GMAC working clock.
* - GMAC_FullDuplexEnable(): Working in full duplex or not.
* - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).
* - ...
* - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls
* can modify with:
* - GMAC_ReceiveEnable(): Enable/Disable Rx.
* - GMAC_TransmitEnable(): Enable/Disable Tx.
* - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
* - ...
* - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),
* GMAC_GetItMask() and GMAC_GetItStatus().
* - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()
* GMAC_ClearTxStatus() and GMAC_ClearRxStatus().
* - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),
* GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define
* by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.
* - Manage PHY through GMAC is performed by
* - GMAC_ManagementEnable(): Enable/Disable PHY management.
* - GMAC_PHYMaintain(): Execute PHY management commands.
* - GMAC_PHYData(): Return PHY management data.
* - GMAC_IsIdle(): Check if PHY is idle.
* - Setup GMAC parameters with following functions:
* - GMAC_SetHash(): Set Hash value.
* - GMAC_SetAddress(): Set MAC address.
* - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()
* - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()
*
* For more accurate information, please look at the GMAC section of the
* Datasheet.
*
* \sa \ref gmacd_module
*
* Related files:\n
* gmac.c\n
* gmac.h.\n
*
* \defgroup gmac_defines GMAC Defines
* \defgroup gmac_structs GMAC Data Structs
* \defgroup gmac_functions GMAC Functions
*/
/**@}*/
#ifndef _GMAC_H
#define _GMAC_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------
* Defines
*----------------------------------------------------------------------------*/
/** \addtogroup gmac_defines
@{*/
/// Board GMAC base address
/// Number of buffer for RX, be carreful: MUST be 2^n
#define GRX_BUFFERS 16
/// Number of buffer for TX, be carreful: MUST be 2^n
#define GTX_BUFFERS 8
/// Buffer Size
#define GMAC_RX_UNITSIZE 128 /// Fixed size for RX buffer
#define GMAC_TX_UNITSIZE 1518 /// Size for ETH frame length
// The MAC can support frame lengths up to 1536 bytes.
#define GMAC_FRAME_LENTGH_MAX 1536
//
#define GMAC_DUPLEX_HALF 0
#define GMAC_DUPLEX_FULL 1
//
#define GMAC_SPEED_10M 0
#define GMAC_SPEED_100M 1
#define GMAC_SPEED_1000M 2
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup gmac_structs
@{*/
/** Receive buffer descriptor struct */
typedef struct _GmacRxDescriptor {
union _GmacRxAddr {
uint32_t val;
struct _GmacRxAddrBM {
uint32_t bOwnership:1, /**< User clear, GMAC set this to one once
it has successfully written a frame to
memory */
bWrap:1, /**< Marks last descriptor in receive buffer */
addrDW:30; /**< Address in number of DW */
} bm;
} addr; /**< Address, Wrap & Ownership */
union _GmacRxStatus {
uint32_t val;
struct _GmacRxStatusBM {
uint32_t len:12, /** Length of frame including FCS */
offset:2, /** Receive buffer offset,
bits 13:12 of frame length for jumbo
frame */
bSof:1, /** Start of frame */
bEof:1, /** End of frame */
bCFI:1, /** Concatenation Format Indicator */
vlanPriority:3, /** VLAN priority (if VLAN detected) */
bPriorityDetected:1, /** Priority tag detected */
bVlanDetected:1, /**< VLAN tag detected */
bTypeIDMatch:1, /**< Type ID match */
bAddr4Match:1, /**< Address register 4 match */
bAddr3Match:1, /**< Address register 3 match */
bAddr2Match:1, /**< Address register 2 match */
bAddr1Match:1, /**< Address register 1 match */
reserved:1,
bExtAddrMatch:1, /**< External address match */
bUniHashMatch:1, /**< Unicast hash match */
bMultiHashMatch:1, /**< Multicast hash match */
bBroadcastDetected:1; /**< Global all ones broadcast
address detected */
} bm;
} status;
} sGmacRxDescriptor; /* GCC */
/** Transmit buffer descriptor struct */
typedef struct _GmacTxDescriptor {
uint32_t addr;
union _GmacTxStatus {
uint32_t val;
struct _GmacTxStatusBM {
uint32_t len:11, /**< Length of buffer */
reserved:4,
bLastBuffer:1, /**< Last buffer (in the current frame) */
bNoCRC:1, /**< No CRC */
reserved1:10,
bExhausted:1, /**< Buffer exhausted in mid frame */
bUnderrun:1, /**< Transmit underrun */
bError:1, /**< Retry limit exceeded, error detected */
bWrap:1, /**< Marks last descriptor in TD list */
bUsed:1; /**< User clear, GMAC sets this once a frame
has been successfully transmitted */
} bm;
} status;
} sGmacTxDescriptor; /* GCC */
/** @}*/
//-----------------------------------------------------------------------------
// PHY Exported functions
//-----------------------------------------------------------------------------
extern uint8_t GMAC_IsIdle(Gmac *pGmac);
extern void GMAC_PHYMaintain(Gmac *pGmac,
uint8_t bPhyAddr,
uint8_t bRegAddr,
uint8_t bRW,
uint16_t wData);
extern uint16_t GMAC_PHYData(Gmac *pGmac);
extern void GMAC_ClearStatistics(Gmac *pGmac);
extern void GMAC_IncreaseStatistics(Gmac *pGmac);
extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck );
extern void GMAC_EnableMdio(Gmac *pGmac );
extern void GMAC_DisableMdio(Gmac *pGmac );
extern void GMAC_EnableMII(Gmac *pGmac );
extern void GMAC_EnableRMII(Gmac *pGmac );
extern void GMAC_EnableGMII( Gmac *pGmac );
extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources);
extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources);
extern uint32_t GMAC_GetItStatus(Gmac *pGmac);
extern uint32_t GMAC_GetItMask(Gmac *pGmac);
extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis);
extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr);
extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
extern uint32_t GMAC_GetRxQueue(Gmac *pGmac);
extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr);
extern uint32_t GMAC_GetTxQueue(Gmac *pGmac);
extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB);
extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
extern void GMAC_TransmissionStart(Gmac *pGmac);
extern void GMAC_TransmissionHalt(Gmac *pGmac);
extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
#endif // #ifndef GMAC_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup hsmci_module Working with HSMCI
* \ingroup mcid_module
*
* \section Purpose
*
* The HSMCI driver provides the interface to configure and use the HSMCI
* peripheral.
*
* \section Usage
*
* -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface.
* -# HSMCI_Reset(): Reset HSMCI interface.
* -# HSMCI_Select(): HSMCI slot and buswidth selection
* (\ref Hsmci::HSMCI_SDCR).
* -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register
* (\ref Hsmci::HSMCI_MR).
* -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus()
* HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR,
* \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR).
* -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer
* (\ref Hsmci::HSMCI_BLKR).
* -# HSMCI_SendCmd(): Send SD/MMC command with argument
* (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR).
* -# HSMCI_GetResponse(): Get SD/MMC response after command finished
* (\ref Hsmci::HSMCI_RSPR).
* -# HSMCI_ConfigureDma(): Configure MCI DMA transfer
* (\ref Hsmci::HSMCI_DMA).
* -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG).
* -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control.
*
* For more accurate information, please look at the HSMCI section of the
* Datasheet.
*
* \sa \ref mcid_module
*
* Related files :\n
* \ref hsmci.h\n
* \ref hsmci.c.\n
*/
#ifndef HSMCID_H
#define HSMCID_H
/** \addtogroup hsmci_module
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup hsmci_functions HSMCI Functions
* @{
*/
extern void HSMCI_Enable(Hsmci* pRMci);
extern void HSMCI_Disable(Hsmci* pRMci);
extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup);
extern void HSMCI_Select(Hsmci * pRMci,uint8_t bSlot,uint8_t bBusWidth);
extern void HSMCI_SetSlot(Hsmci * pRMci,uint8_t bSlot);
extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth);
extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci);
extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode);
extern uint32_t HSMCI_GetMode(Hsmci *pRMci);
extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof);
extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv);
extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn);
extern uint8_t HSMCI_IsFByteEnabled(Hsmci * pRMci);
extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv);
extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources);
extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources);
extern uint32_t HSMCI_GetItMask(Hsmci *pRMci);
extern void HSMCI_ConfigureTransfer(Hsmci * pRMci,uint16_t wBlkLen,uint16_t wCnt);
extern void HSMCI_SetBlockLen(Hsmci * pRMci,uint16_t wBlkSize);
extern void HSMCI_SetBlockCount(Hsmci * pRMci,uint16_t wBlkCnt);
extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure);
extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure);
extern void HSMCI_SendCmd(Hsmci * pRMci,uint32_t dwCmd,uint32_t dwArg);
extern uint32_t HSMCI_GetResponse(Hsmci *pRMci);
extern uint32_t HSMCI_Read(Hsmci *pRMci);
extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize);
extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData);
extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize);
extern uint32_t HSMCI_GetStatus(Hsmci *pRMci);
extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure);
extern void HSMCI_EnableDma(Hsmci * pRMci,uint8_t bEnable);
extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure);
extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable);
extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci);
extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth);
extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot);
extern uint8_t HSMCI_GetSlot(Hsmci *pRMci);
extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure);
extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci);
#ifdef __cplusplus
}
#endif
/** @}*/
/**@}*/
#endif //#ifndef HSMCID_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _ICM_
#define _ICM_
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
/*------------------------------------------------------------------------------*/
/* Definition */
/*------------------------------------------------------------------------------*/
#define ICM_RCFG_CDWBN (0x1u << 0) /**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */
#define ICM_RCFG_WRAP (0x1u << 1) /**< \brief (ICM_RCFG) Wrap Command */
#define ICM_RCFG_EOM (0x1u << 2) /**< \brief (ICM_RCFG) End Of Monitoring */
#define ICM_RCFG_RHIEN (0x1u << 4) /**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */
#define ICM_RCFG_DMIEN (0x1u << 5) /**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */
#define ICM_RCFG_BEIEN (0x1u << 6) /**< \brief (ICM_RCFG) Bus error interrupt enable */
#define ICM_RCFG_WCIEN (0x1u << 7) /**< \brief (ICM_RCFG) Warp condition interrupt enable */
#define ICM_RCFG_ECIEN (0x1u << 8) /**< \brief (ICM_RCFG) End bit condition interrupt enable */
#define ICM_RCFG_SUIEN (0x1u << 9) /**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */
#define ICM_RCFG_PROCDLY (0x1u << 10) /**< \brief (ICM_RCFG) Processing Delay*/
#define ICM_RCFG_UALGO_Pos 12
#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) /**< \brief (ICM_RCFG) User SHA Algorithm */
#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) /**< \brief (ICM_RCFG) SHA1 algorithm processed */
#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) /**< \brief (ICM_RCFG) SHA256 algorithm processed */
#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) /**< \brief (ICM_RCFG) SHA224 algorithm processed */
#define ICM_RCFG_MRPROT_Pos 24
#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) /**< \brief (ICM_RCFG) Memory Region AHB Protection */
#define ICM_RCFG_MRPROT(value) ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos)))
/*------------------------------------------------------------------------------*/
/* Type */
/*------------------------------------------------------------------------------*/
/** \brief Structure ICM region descriptor area. */
typedef struct _LinkedListDescriporIcmRegion
{
/** the first byte address of the Region. */
uint32_t icm_raddr;
/** Configuration Structure Member. */
uint32_t icm_rcfg;
/** Control Structure Member. */
uint32_t icm_rctrl;
/** Next Address Structure Member. */
uint32_t icm_rnext;
}LinkedListDescriporIcmRegion;
/*------------------------------------------------------------------------------*/
/* Exported functions */
/*------------------------------------------------------------------------------*/
extern void ICM_Enable(void);
extern void ICM_Disable(void);
extern void ICM_SoftReset(void);
extern void ICM_ReComputeHash(uint8_t region);
extern void ICM_EnableMonitor(uint8_t region);
extern void ICM_DisableMonitor(uint8_t region);
extern void ICM_Configure(uint32_t mode);
extern void ICM_EnableIt(uint32_t sources);
extern void ICM_DisableIt(uint32_t sources);
extern uint32_t ICM_GetIntStatus(void);
extern uint32_t ICM_GetStatus(void);
extern uint32_t ICM_GetUStatus(void);
extern void ICM_SetDescStartAddress(uint32_t addr);
extern void ICM_SetHashStartAddress(uint32_t addr);
extern void ICM_SetInitHashValue(uint32_t val);
#endif /* #ifndef _ICM_ */

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@ -0,0 +1,98 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup isi_module
* @{
* \section gmac_usage Usage
* - ISI_Init: initialize ISI with default parameters
* - ISI_EnableInterrupt: enable one or more interrupts
* - ISI_DisableInterrupt: disable one or more interrupts
* - ISI_Enable: enable isi module
* - ISI_Disable: disable isi module
* - ISI_CodecPathFull: enable codec path
* - ISI_SetFrame: set frame rate
* - ISI_BytesForOnePixel: return number of byte for one pixel
* - ISI_StatusRegister: return ISI status register
* - ISI_Reset: make a software reset
*/
/**@}*/
#ifndef ISI_H
#define ISI_H
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** ISI descriptors */
typedef struct
{
/** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */
uint32_t CurrentLcdIndex;
/** set if Fifo Codec Empty is present */
volatile uint32_t DisplayCodec;
/** upgrade for each Fifo Codec Overflow (statistics use) */
uint32_t nb_codec_ovf;
/** upgrade for each Fifo Preview Overflow (statistics use) */
uint32_t nb_prev_ovf;
}ISI_Descriptors;
/** Frame Buffer Descriptors */
typedef struct
{
/** Address of the Current FrameBuffer */
uint32_t Current;
/** Address of the Control */
uint32_t Control;
/** Address of the Next FrameBuffer */
uint32_t Next;
}ISI_FrameBufferDescriptors;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ISI_Enable(void);
extern void ISI_Disable(void);
extern void ISI_DmaChannelEnable(uint32_t channel);
extern void ISI_DmaChannelDisable(uint32_t channel);
extern void ISI_EnableInterrupt(uint32_t flag);
extern void ISI_DisableInterrupt(uint32_t flag);
extern void ISI_CodecPathFull(void);
extern void ISI_SetFrame(uint32_t frate);
extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb);
extern void ISI_Reset(void);
extern void ISI_Init(pIsi_Video pVideo);
extern uint32_t ISI_StatusRegister(void);
#endif //#ifndef ISI_H

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