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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Cortex-M23: Do not use PSPLIM_NS (#791)
According to Armv8-M technical reference manual, if the main extension is not implemented then PSPLIM_NS is RES0. Update the cortex-M23 port to not use the reserved PSPLIM_NS.
This commit is contained in:
Devaraj Ranganna
GitHub
parent
a695b671aa
commit
9d2571d2ed
29 changed files with 833 additions and 145 deletions
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@ -67,6 +67,16 @@
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#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
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#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
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#endif
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/**
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* Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
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* only when FreeRTOS runs on secure side.
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*/
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#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
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#define portUSE_PSPLIM_REGISTER 0
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#else
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#define portUSE_PSPLIM_REGISTER 1
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#endif
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/*-----------------------------------------------------------*/
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/**
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@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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/* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
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* restore it when we exit from the system call. */
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pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
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__asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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#if ( portUSE_PSPLIM_REGISTER == 1 )
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{
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__asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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}
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#endif
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/* Use the pulSystemCallStack in thread mode. */
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__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
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#if ( portUSE_PSPLIM_REGISTER == 1 )
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{
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
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}
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#endif
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/* Remember the location where we should copy the stack frame when we exit from
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* the system call. */
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@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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/* Store the value of the LR and PSPLIM registers before the SVC was raised.
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* We need to restore it when we exit from the system call. */
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pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
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__asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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#if ( portUSE_PSPLIM_REGISTER == 1 )
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{
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__asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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}
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#endif
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/* Use the pulSystemCallStack in thread mode. */
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__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
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#if ( portUSE_PSPLIM_REGISTER == 1 )
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{
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
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}
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#endif
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/* Remember the location where we should copy the stack frame when we exit from
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* the system call. */
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@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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/* Restore the LR and PSPLIM to what they were at the time of
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* system call entry. */
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pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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#if ( portUSE_PSPLIM_REGISTER == 1 )
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{
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__asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
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}
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#endif
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/* If the hardware used padding to force the stack pointer
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* to be double word aligned, set the stacked xPSR bit[9],
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@ -109,7 +109,6 @@
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" ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
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" subs r2, #20 \n"
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" msr psp, r3 \n"
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" msr psplim, r4 \n"
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" msr control, r5 \n"
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" mov lr, r6 \n"
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" ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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@ -160,7 +159,6 @@
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" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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" ldr r4, xSecureContextConst2 \n"
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" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
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" movs r1, #2 \n" /* r1 = 2. */
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" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n" /* Discard everything up to r0. */
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@ -324,7 +322,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" \n"
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" save_special_regs: \n"
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" mrs r3, psp \n" /* r3 = PSP. */
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" mrs r4, psplim \n" /* r4 = PSPLIM. */
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" movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
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" mrs r5, control \n" /* r5 = CONTROL. */
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" mov r6, lr \n" /* r6 = LR. */
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" stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
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@ -392,7 +390,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
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" subs r2, #20 \n"
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" msr psp, r3 \n"
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" msr psplim, r4 \n"
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" msr control, r5 \n"
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" mov lr, r6 \n"
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" ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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@ -467,7 +464,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
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" subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
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" str r2, [r1] \n" /* Save the new top of stack in TCB. */
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" mrs r1, psplim \n" /* r1 = PSPLIM. */
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" movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
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" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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" stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
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" b select_next_task \n"
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@ -477,7 +474,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
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" subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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" str r2, [r1] \n" /* Save the new top of stack in TCB. */
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" mrs r1, psplim \n" /* r1 = PSPLIM. */
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" movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
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" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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" stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
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" mov r4, r8 \n" /* r4 = r8. */
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@ -496,7 +493,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
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" \n"
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" ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
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" msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
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" mov lr, r4 \n" /* LR = r4. */
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" ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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" str r0, [r3] \n" /* Restore the task's xSecureContext. */
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