len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-09-02 12:24:07 -04:00
Code Issues Projects Releases Packages Wiki Activity

Hardware and software for the MicroBlaze project that uses the full Ethernet IP is now building - but the MAC driver has not yet been written.

Browse source
This commit is contained in:
Richard Barry 2011-08-28 18:38:32 +00:00
parent d14eb96aeb
commit 9c92745440
56 changed files with 31544 additions and 291 deletions
Download patch file Download diff file Expand all files Collapse all files

38
Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp Normal file
View file

@ -0,0 +1,38 @@
#Please do not modify this file by hand
XmpVersion: 13.1
VerMgmt: 13.1
IntStyle: default
MHS File: system.mhs
Architecture: spartan6
Device: xc6slx45t
Package: fgg484
SpeedGrade: -3
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 1
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: VHDL
SimModel: BEHAVIORAL
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR
ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR
ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR
ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR
ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR
ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR
DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR
Processor: microblaze_0
ElfImp:
ElfSim: