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Add SimpleLink CC3220SF demo.

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Richard Barry 2017-02-24 02:12:27 +00:00
parent 67def3c14b
commit 9b213e8c34
138 changed files with 75502 additions and 0 deletions
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17
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.ccsproject Normal file
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195
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/.cproject Normal file
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229
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
See http://www.freertos.org/a00110.html for an explanation of the
definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application.
The comprehensive demo uses FreeRTOS+CLI to create a simple command line
interface through a UART.
The blinky demo uses FreeRTOS's tickless idle mode to reduce power consumption.
See the notes on the web page below regarding the difference in power saving
that can be achieved between using the generic tickless implementation (as used
by the blinky demo) and a tickless implementation that is tailored specifically
to the CC3220.
See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for
instructions. */
#define configCREATE_SIMPLE_TICKLESS_DEMO 0
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/* Constants related to the behaviour or the scheduler. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configUSE_PREEMPTION 1
#define configUSE_TIME_SLICING 1
#define configMAX_PRIORITIES ( 5 )
#define configIDLE_SHOULD_YIELD 1
#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants used to specify if only static allocation is to be supported (in
which case a heap_n.c file is not required), only dynamic allocation is to be
supported, or if both static and dynamic allocation are supported. */
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
/* Constants that describe the hardware and memory usage. */
#define configCPU_CLOCK_HZ ( ( unsigned long ) 80000000 )
#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 100 )
#define configMAX_TASK_NAME_LEN ( 12 )
/* Note heap_5.c is used so this only defines the part of the heap that is in
the first block of RAM on the LPC device. See the initialisation of the heap
in main.c. */
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
/* Constants that build features in or out. */
#define configUSE_MUTEXES 1
#define configUSE_TICKLESS_IDLE 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_NEWLIB_REENTRANT 0
#define configUSE_CO_ROUTINES 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_QUEUE_SETS 0
#define configUSE_TASK_NOTIFICATIONS 1
/* Constants that define which hook (callback) functions should be used. */
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configUSE_MALLOC_FAILED_HOOK 1
/* Constants provided for debugging and optimisation assistance. */
#define configCHECK_FOR_STACK_OVERFLOW 2
void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber );
#define configASSERT( x ) if( ( x ) == 0 ) { vMainAssertCalled( __FILE__, __LINE__ ); }
#define configQUEUE_REGISTRY_SIZE 0
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 3 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is only
necessary if the linker does not automatically remove functions that are not
referenced anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xSemaphoreGetMutexHolder 0
#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
interpreter. See the FreeRTOS+CLI documentation for more information:
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Cortex-M3/4 interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* The trace facility is turned on to make some functions available for use in
CLI commands. */
#define configUSE_TRACE_FACILITY 1
/* Constants related to the generation of run time stats. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE() 0
#endif /* FREERTOS_CONFIG_H */

224
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@ -0,0 +1,224 @@
;/*
; FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
; All rights reserved
;
; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
;
; ***************************************************************************
; >>! NOTE: The modification to the GPL is included to allow you to !<<
; >>! distribute a combined work that includes FreeRTOS without being !<<
; >>! obliged to provide the source code for proprietary components !<<
; >>! outside of the FreeRTOS kernel. !<<
; ***************************************************************************
;
; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
; FOR A PARTICULAR PURPOSE. Full license text is available on the following
; link: http://www.freertos.org/a00114.html
;
; ***************************************************************************
; * *
; * FreeRTOS provides completely free yet professionally developed, *
; * robust, strictly quality controlled, supported, and cross *
; * platform software that is more than just the market leader, it *
; * is the industry's de facto standard. *
; * *
; * Help yourself get started quickly while simultaneously helping *
; * to support the FreeRTOS project by purchasing a FreeRTOS *
; * tutorial book, reference manual, or both: *
; * http://www.FreeRTOS.org/Documentation *
; * *
; ***************************************************************************
;
; http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
; the FAQ page "My application does not run, what could be wrong?". Have you
; defined configASSERT()?
;
; http://www.FreeRTOS.org/support - In return for receiving this top quality
; embedded software for free we request you assist our global community by
; participating in the support forum.
;
; http://www.FreeRTOS.org/training - Investing in training allows your team to
; be as productive as possible as early as possible. Now you can receive
; FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
; Ltd, and the world's leading authority on the world's leading RTOS.
;
; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
; including FreeRTOS+Trace - an indispensable productivity tool, a DOS
; compatible FAT file system, and our tiny thread aware UDP/IP stack.
;
; http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
; Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
;
; http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
; Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
; licenses offer ticketed support, indemnification and commercial middleware.
;
; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
; engineered and independently SIL3 certified version for use in safety and
; mission critical applications that require provable dependability.
;
; 1 tab == 4 spaces!
;*/
.thumb
.ref ulRegTest1LoopCounter
.ref ulRegTest2LoopCounter
.def vRegTest1Implementation
.def vRegTest2Implementation
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
ulNVIC_INT_CTRL: .word 0xe000ed04
;/*-----------------------------------------------------------*/
.align 4
vRegTest1Implementation: .asmfunc
;/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
reg1_loop:
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
;/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, ulRegTest1LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
;/* Start again. */
b reg1_loop
reg1_error_loop:
;/* If this line is hit then there was an error in a core register value.
;The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
.endasmfunc
;/*-----------------------------------------------------------*/
.align 4
vRegTest2Implementation: .asmfunc
;/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
reg2_loop:
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
;/* Increment the loop counter to indicate this test is still functioning
;correctly. */
push { r0-r1 }
ldr r0, ulRegTest2LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
;/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, ulNVIC_INT_CTRL
lsl r0, r0, #28 ;/* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
;/* Start again. */
b reg2_loop
reg2_error_loop:
;/* If this line is hit then there was an error in a core register value.
;This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
;/*-----------------------------------------------------------*/
.end

425
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c Normal file
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/*
FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
* select between the two. See the notes on using
* configCREATE_SIMPLY_BLINKY_DEMO_ONLY in main.c. This file implements the
* comprehensive version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for
* instructions.
*
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill the core registers with known values, then
* check that each register maintains its expected value for the lifetime of the
* task. Each task uses a different set of values. The reg test tasks execute
* with a very low priority, so get preempted very frequently. A register
* containing an unexpected value is indicative of an error in the context
* switching mechanism.
*
* "Check" task - The check task period is initially set to three seconds. The
* task checks that all the standard demo tasks, and the register check tasks,
* are not only still executing, but are executing without reporting any errors.
* If the check task discovers that a task has either stalled, or reported an
* error, then it changes its own execution period from the initial three
* seconds, to just 200ms. The check task also toggles an LED each time it is
* called. This provides a visual indication of the system status: If the LED
* toggles every three seconds, then no issues have been discovered. If the LED
* toggles every 200ms, then an issue has been discovered with at least one
* task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "semtest.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "partest.h"
#include "TimerDemo.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
#include "StaticAllocation.h"
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
/* The priority used by the UART command console task. */
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period of the check task, in ms, provided no errors have been reported by
any of the standard demo tasks. ms are converted to the equivalent in ticks
using the pdMS_TO_TICKS() macro constant. */
#define mainNO_ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 3000UL ) )
/* The period of the check task, in ms, if an error has been reported in one of
the standard demo tasks. ms are converted to the equivalent in ticks using the
pdMS_TO_TICKS() macro. */
#define mainERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 200UL ) )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/*-----------------------------------------------------------*/
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file, but the
* entry points are kept in the C file for the convenience of checking the task
* parameter.
*/
static void prvRegTestTaskEntry1( void *pvParameters );
extern void vRegTest1Implementation( void );
static void prvRegTestTaskEntry2( void *pvParameters );
extern void vRegTest2Implementation( void );
/*
* Register commands that can be used with FreeRTOS+CLI. The commands are
* defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
*/
extern void vRegisterSampleCLICommands( void );
/*
* The task that manages the FreeRTOS+CLI input and output.
*/
extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
/*
* When the full demo is build the idle hook is used to create some timers that
* cannot be created in main() because the timer demo tasks need the entire
* command queue.
*/
void vFullDemoIdleHook( void );
/*
* Toggles the LED built onto the Launchpad hardware.
*/
extern void vMainToggleLED( void );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check task. If the variables keep incrementing,
then the register check tasks have not discovered any errors. If a variable
stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
vStartStaticallyAllocatedTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
/* Create the register check tasks, as described at the top of this file */
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the Idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details on the FreeRTOS heap
http://www.freertos.org/a00111.html. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The onboard LED is toggled on each iteration.
If an error is detected then the delay period is decreased from
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
effect of increasing the rate at which the onboard LED toggles, and in so
doing gives visual feedback of the system status. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks to ensure that they are all still running,
and that none have detected an error. */
if( xAreStaticAllocationTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 0UL;
}
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 5UL;
}
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 6UL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 8UL;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 10UL;
}
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 14UL;
}
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
{
ulErrorFound |= 1UL << 9UL;
}
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ulErrorFound |= 1UL << 12UL;
}
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 13UL;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound |= 1UL << 15UL;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound |= 1UL << 16UL;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
everything is ok. A faster toggle indicates an error. */
vMainToggleLED();
if( ulErrorFound != pdFALSE )
{
/* An error has been detected in one of the tasks - flash the LED
at a higher frequency to give visible feedback that something has
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
}
}
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry1( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check task will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry2( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check task will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 0 )
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
/* The full demo includes a software timer demo/test that requires
prodding periodically from the tick interrupt. */
vTimerPeriodicISRTests();
/* Call the periodic event group from ISR demo. */
vPeriodicEventGroupsProcessing();
/* Use task notifications from an interrupt. */
xNotifyTaskFromISR();
/* Use mutexes from interrupts. */
vInterruptSemaphorePeriodicTest();
}
#endif
/*-----------------------------------------------------------*/

301
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@ -0,0 +1,301 @@
/*
FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
*
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
* select between the two. See the notes on using
* configCREATE_SIMPLE_TICKLESS_DEMO in main.c. This file implements the
* simply blinky style version.
*
* The blinky demo uses FreeRTOS's tickless idle mode to reduce power
* consumption. See the notes on the web page below regarding the difference
* in power saving that can be achieved between using the generic tickless
* implementation (as used by the blinky demo) and a tickless implementation
* that is tailored specifically to the CC3220.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for
* instructions.
*
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles the LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
*/
void main_blinky( void );
/*
* The full demo configures the clocks for maximum frequency, wheras this blinky
* demo uses a slower clock as it also uses low power features.
*/
static void prvConfigureClocks( void );
/*
* Toggles the LED built onto the Launchpad hardware.
*/
extern void vMainToggleLED( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for
instructions and notes regarding the difference in power saving that can be
achieved between using the generic tickless RTOS implementation (as used by
the blinky demo) and a tickless RTOS implementation that is tailored
specifically to the MSP432. */
/* The full demo configures the clocks for maximum frequency, wheras this
blinky demo uses a slower clock as it also uses low power features. */
prvConfigureClocks();
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
static const TickType_t xShortBlock = pdMS_TO_TICKS( 50 );
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
/* Blip the LED for a short while so as not to use too much
power. */
vMainToggleLED();
vTaskDelay( xShortBlock );
vMainToggleLED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/
static void prvConfigureClocks( void )
{
}
/*-----------------------------------------------------------*/
void vPreSleepProcessing( uint32_t ulExpectedIdleTime )
{
}
/*-----------------------------------------------------------*/
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
/* Only the full demo uses the tick hook so there is no code is
executed here. */
}
#endif

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/*
FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting (defined in FreeRTOSConfig.h) is
* used to select between the two. The simply blinky demo is implemented and
* described in main_blinky.c. The more comprehensive test and demo application
* is implemented and described in main_full.c.
*
* The blinky demo uses FreeRTOS's tickless idle mode to reduce power
* consumption. See the notes on the web page below regarding the difference
* in power saving that can be achieved between using the generic tickless
* implementation (as used by the blinky demo) and a tickless implementation
* that is tailored specifically to the CC3220.
*
* This file implements the code that is not demo specific.
*
* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for
* instructions.
*
*/
/* Standard includes. */
#include <stdio.h>
/* TI includes. */
#include <ti/drivers/GPIO.h>
#include <ti/boards/CC3220SF_LAUNCHXL/Board.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
* main_full() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for
instructions. */
/* Prepare the hardware to run this demo. */
prvSetupHardware();
/* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top
of this file. */
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Call board init functions */
Board_initGeneral();
Board_initGPIO();
GPIO_write( Board_LED0, Board_GPIO_LED_OFF );
}
/*-----------------------------------------------------------*/
void vMainToggleLED( void )
{
static uint32_t ulLEDState = Board_GPIO_LED_OFF;
ulLEDState = !ulLEDState;
GPIO_write( Board_LED0, ulLEDState );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void *malloc( size_t xSize )
{
/* There should not be a heap defined, so trap any attempts to call
malloc. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
used by the Idle task. */
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
/* If the buffers to be provided to the Idle task are declared inside this
function then they must be declared static - otherwise they will be allocated on
the stack and so not exists after this function exits. */
static StaticTask_t xIdleTaskTCB;
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
/* Pass out a pointer to the StaticTask_t structure in which the Idle task's
state will be stored. */
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
/* Pass out the array that will be used as the Idle task's stack. */
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
Note that, as the array is necessarily of type StackType_t,
configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
application must provide an implementation of vApplicationGetTimerTaskMemory()
to provide the memory that is used by the Timer service task. */
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
{
/* If the buffers to be provided to the Timer task are declared inside this
function then they must be declared static - otherwise they will be allocated on
the stack and so not exists after this function exits. */
static StaticTask_t xTimerTaskTCB;
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
/* Pass out a pointer to the StaticTask_t structure in which the Timer
task's state will be stored. */
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
/* Pass out the array that will be used as the Timer task's stack. */
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
Note that, as the array is necessarily of type StackType_t,
configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}
/*-----------------------------------------------------------*/
/* Catch asserts so the file and line number of the assert can be viewed. */
void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
{
taskENTER_CRITICAL();
for( ;; )
{
/* Use the variables to prevent compiler warnings and in an attempt to
ensure they can be viewed in the debugger. If the variables get
optimised away then set copy their values to file scope or globals then
view the variables they are copied to. */
( void ) pcFileName;
( void ) ulLineNumber;
}
}
/*-----------------------------------------------------------*/
/* To enable the libraries to build. */
void PowerCC32XX_enterLPDS( void *driverlibFunc )
{
( void ) driverlibFunc;
/* This function is not implemented so trap any calls to it by halting
here. */
configASSERT( driverlibFunc == NULL );
}

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="CC3220SF" href="devices/CC3220SF.xml" id="CC3220SF" xml="CC3220SF.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

9
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The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
on the device and connection settings specified in your project on the Properties > General page.
Please note that in automatic target-configuration management, changes to the project's device and/or
connection settings will either modify an existing or generate a new target-configuration file. Thus,
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
you may create your own target-configuration file for this project and manage it manually. You can
always switch back to automatic target-configuration management by checking the "Manage the project's
target-configuration automatically" checkbox on the project's Properties > General page.

135
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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BOARD_H
#define __BOARD_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ti/drivers/ADC.h>
#include <ti/drivers/GPIO.h>
#include <ti/drivers/I2C.h>
#include <ti/drivers/I2S.h>
#include <ti/drivers/PWM.h>
#include <ti/drivers/SDSPI.h>
#include <ti/drivers/SD.h>
#include <ti/drivers/SPI.h>
#include <ti/drivers/UART.h>
#include <ti/drivers/Watchdog.h>
#include "CC3220SF_LAUNCHXL.h"
#define Board_initGeneral CC3220SF_LAUNCHXL_initGeneral
#define Board_ADC0 CC3220SF_LAUNCHXL_ADC0
#define Board_ADC1 CC3220SF_LAUNCHXL_ADC1
#define Board_CRYPTO0 CC3220SF_LAUNCHXL_CRYPTO0
#define Board_GPIO_LED_ON CC3220SF_LAUNCHXL_GPIO_LED_ON
#define Board_GPIO_LED_OFF CC3220SF_LAUNCHXL_GPIO_LED_OFF
#define Board_GPIO_LED0 CC3220SF_LAUNCHXL_GPIO_LED_D7
/*
* CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the I2C
* and PWM peripherals. In order for those examples to work, these LEDs are
* taken out of gpioPinCOnfig[]
*/
#define Board_GPIO_LED1 CC3220SF_LAUNCHXL_GPIO_LED_D7
#define Board_GPIO_LED2 CC3220SF_LAUNCHXL_GPIO_LED_D7
#define Board_GPIO_BUTTON0 CC3220SF_LAUNCHXL_GPIO_SW2
#define Board_GPIO_BUTTON1 CC3220SF_LAUNCHXL_GPIO_SW3
#define Board_I2C0 CC3220SF_LAUNCHXL_I2C0
#define Board_I2C_TMP CC3220SF_LAUNCHXL_I2C0
#define Board_I2S0 CC3220SF_LAUNCHXL_I2S0
#define Board_PWM0 CC3220SF_LAUNCHXL_PWM6
#define Board_PWM1 CC3220SF_LAUNCHXL_PWM7
#define Board_SDSPI0 CC3220SF_LAUNCHXL_SDSPI0
#define Board_SD0 CC3220SF_LAUNCHXL_SD0
#define Board_SDFatFS0 CC3220SF_LAUNCHXL_SD0
/* CC3220SF_LAUNCHXL_SPI0 is reserved for the NWP */
#define Board_SPI0 CC3220SF_LAUNCHXL_SPI1
#define Board_UART0 CC3220SF_LAUNCHXL_UART0
#define Board_UART1 CC3220SF_LAUNCHXL_UART1
#define Board_WATCHDOG0 CC3220SF_LAUNCHXL_WATCHDOG0
/* Board specific I2C addresses */
#define Board_TMP_ADDR (0x41)
#define Board_SENSORS_BP_TMP_ADDR (0x40)
/*
* These macros are provided for backwards compatibility.
* Please use the <Driver>_init functions directly rather
* than Board_init<Driver>.
*/
#define Board_initADC ADC_init
#define Board_initGPIO GPIO_init
#define Board_initI2C I2C_init
#define Board_initI2S I2S_init
#define Board_initPWM PWM_init
#define Board_initSDSPI SDSPI_init
#define Board_initSD SD_init
#define Board_initSDFatFS SDFatFS_init
#define Board_initSPI SPI_init
#define Board_initUART UART_init
#define Board_initWatchdog Watchdog_init
/*
* These macros are provided for backwards compatibility.
* Please use the corresponding 'Board_GPIO_xxx' macros as the macros
* below are deprecated.
*/
#define Board_LED_ON Board_GPIO_LED_ON
#define Board_LED_OFF Board_GPIO_LED_OFF
#define Board_LED0 Board_GPIO_LED0
#define Board_LED1 Board_GPIO_LED1
#define Board_LED2 Board_GPIO_LED2
#define Board_BUTTON0 Board_GPIO_BUTTON0
#define Board_BUTTON1 Board_GPIO_BUTTON1
#define Board_TMP006_ADDR Board_TMP_ADDR
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H */

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FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c Normal file
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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== CC3220SF_LAUNCHXL.c ========
* This file is responsible for setting up the board specific items for the
* CC3220SF_LAUNCHXL board.
*/
#include <stdint.h>
#include <stdbool.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/driverlib/rom.h>
#include <ti/devices/cc32xx/driverlib/rom_map.h>
#include <ti/devices/cc32xx/driverlib/adc.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
#include <ti/devices/cc32xx/driverlib/spi.h>
#include <ti/devices/cc32xx/driverlib/sdhost.h>
#include <ti/devices/cc32xx/driverlib/timer.h>
#include <ti/devices/cc32xx/driverlib/uart.h>
#include <ti/devices/cc32xx/driverlib/udma.h>
#include <ti/devices/cc32xx/driverlib/wdt.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC32XX.h>
#include "CC3220SF_LAUNCHXL.h"
/*
* This define determines whether to use the UARTCC32XXDMA driver
* or the UARTCC32XX (no DMA) driver. Set to 1 to use the UARTCC32XXDMA
* driver.
*/
#ifndef TI_DRIVERS_UART_DMA
#define TI_DRIVERS_UART_DMA 0
#endif
/*
* =============================== ADC ===============================
*/
#include <ti/drivers/ADC.h>
#include <ti/drivers/adc/ADCCC32XX.h>
ADCCC32XX_Object adcCC3220SObjects[CC3220SF_LAUNCHXL_ADCCOUNT];
const ADCCC32XX_HWAttrsV1 adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADCCOUNT] = {
{
.adcPin = ADCCC32XX_PIN_59_CH_2
},
{
.adcPin = ADCCC32XX_PIN_60_CH_3
}
};
const ADC_Config ADC_config[CC3220SF_LAUNCHXL_ADCCOUNT] = {
{
.fxnTablePtr = &ADCCC32XX_fxnTable,
.object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC0],
.hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC0]
},
{
.fxnTablePtr = &ADCCC32XX_fxnTable,
.object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC1],
.hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC1]
}
};
const uint_least8_t ADC_count = CC3220SF_LAUNCHXL_ADCCOUNT;
/*
* =============================== Crypto ===============================
*/
#include <ti/drivers/crypto/CryptoCC32XX.h>
CryptoCC32XX_Object cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTOCOUNT];
const CryptoCC32XX_Config CryptoCC32XX_config[CC3220SF_LAUNCHXL_CRYPTOCOUNT] = {
{
.object = &cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTO0]
}
};
const uint_least8_t CryptoCC32XX_count = CC3220SF_LAUNCHXL_CRYPTOCOUNT;
/*
* =============================== DMA ===============================
*/
#include <ti/drivers/dma/UDMACC32XX.h>
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(dmaControlTable, 1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
#endif
static tDMAControlTable dmaControlTable[64];
/*
* ======== dmaErrorFxn ========
* This is the handler for the uDMA error interrupt.
*/
static void dmaErrorFxn(uintptr_t arg)
{
int status = MAP_uDMAErrorStatusGet();
MAP_uDMAErrorStatusClear();
/* Suppress unused variable warning */
(void)status;
while (1);
}
UDMACC32XX_Object udmaCC3220SObject;
const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = {
.controlBaseAddr = (void *)dmaControlTable,
.dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn,
.intNum = INT_UDMAERR,
.intPriority = (~0)
};
const UDMACC32XX_Config UDMACC32XX_config = {
.object = &udmaCC3220SObject,
.hwAttrs = &udmaCC3220SHWAttrs
};
/*
* =============================== General ===============================
*/
/*
* ======== CC3220SF_LAUNCHXL_initGeneral ========
*/
void CC3220SF_LAUNCHXL_initGeneral(void)
{
PRCMCC3200MCUInit();
Power_init();
}
/*
* =============================== GPIO ===============================
*/
#include <ti/drivers/GPIO.h>
#include <ti/drivers/gpio/GPIOCC32XX.h>
/*
* Array of Pin configurations
* NOTE: The order of the pin configurations must coincide with what was
* defined in CC3220SF_LAUNCHXL.h
* NOTE: Pins not used for interrupts should be placed at the end of the
* array. Callback entries can be omitted from callbacks array to
* reduce memory usage.
*/
GPIO_PinConfig gpioPinConfigs[] = {
/* input pins with callbacks */
/* CC3220SF_LAUNCHXL_GPIO_SW2 */
GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,
/* CC3220SF_LAUNCHXL_GPIO_SW3 */
GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,
/* output pins */
/* CC3220SF_LAUNCHXL_GPIO_LED_D7 */
GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
/*
* CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the
* I2C and PWM peripherals. In order for those examples to work, these
* LEDs are taken out of gpioPinCOnfig[]
*/
/* CC3220SF_LAUNCHXL_GPIO_LED_D6 */
//GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
/* CC3220SF_LAUNCHXL_GPIO_LED_D5 */
//GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
};
/*
* Array of callback function pointers
* NOTE: The order of the pin configurations must coincide with what was
* defined in CC3220SF_LAUNCHXL.h
* NOTE: Pins not used for interrupts can be omitted from callbacks array to
* reduce memory usage (if placed at end of gpioPinConfigs array).
*/
GPIO_CallbackFxn gpioCallbackFunctions[] = {
NULL, /* CC3220SF_LAUNCHXL_GPIO_SW2 */
NULL /* CC3220SF_LAUNCHXL_GPIO_SW3 */
};
/* The device-specific GPIO_config structure */
const GPIOCC32XX_Config GPIOCC32XX_config = {
.pinConfigs = (GPIO_PinConfig *)gpioPinConfigs,
.callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions,
.numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig),
.numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn),
.intPriority = (~0)
};
/*
* ============================= Display =============================
*/
#if 0 /*_RB_*/
#include <ti/display/Display.h>
#include <ti/display/DisplayUart.h>
#define MAXPRINTLEN 1024
DisplayUart_Object displayUartObject;
static char displayBuf[MAXPRINTLEN];
const DisplayUart_HWAttrs displayUartHWAttrs = {
.uartIdx = 0,
.baudRate = 115200,
.mutexTimeout = (unsigned int)(-1),
.strBuf = displayBuf,
.strBufLen = MAXPRINTLEN
};
#ifndef BOARD_DISPLAY_USE_UART_ANSI
#define BOARD_DISPLAY_USE_UART_ANSI 0
#endif
const Display_Config Display_config[] = {
{
# if (BOARD_DISPLAY_USE_UART_ANSI)
.fxnTablePtr = &DisplayUartAnsi_fxnTable,
# else /* Default to minimal UART with no cursor placement */
.fxnTablePtr = &DisplayUartMin_fxnTable,
# endif
.object = &displayUartObject,
.hwAttrs = &displayUartHWAttrs
}
};
const uint_least8_t Display_count = sizeof(Display_config) / sizeof(Display_Config);
#endif /* 0 _RB_ */
/*
* =============================== I2C ===============================
*/
#include <ti/drivers/I2C.h>
#include <ti/drivers/i2c/I2CCC32XX.h>
I2CCC32XX_Object i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2CCOUNT];
const I2CCC32XX_HWAttrsV1 i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2CCOUNT] = {
{
.baseAddr = I2CA0_BASE,
.intNum = INT_I2CA0,
.intPriority = (~0),
.clkPin = I2CCC32XX_PIN_01_I2C_SCL,
.dataPin = I2CCC32XX_PIN_02_I2C_SDA
}
};
const I2C_Config I2C_config[CC3220SF_LAUNCHXL_I2CCOUNT] = {
{
.fxnTablePtr = &I2CCC32XX_fxnTable,
.object = &i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2C0],
.hwAttrs = &i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2C0]
}
};
const uint_least8_t I2C_count = CC3220SF_LAUNCHXL_I2CCOUNT;
/*
* =============================== I2S ===============================
*/
#include <ti/drivers/I2S.h>
#include <ti/drivers/i2s/I2SCC32XXDMA.h>
I2SCC32XXDMA_Object i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2SCOUNT];
const I2SCC32XXDMA_HWAttrsV1 i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2SCOUNT] = {
{
.baseAddr = I2S_BASE,
.intNum = INT_I2S,
.intPriority = (~0),
.rxChannelIndex = UDMA_CH4_I2S_RX,
.txChannelIndex = UDMA_CH5_I2S_TX,
.xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0,
.xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1,
.clkxPin = I2SCC32XXDMA_PIN_62_McACLKX,
.clkPin = I2SCC32XXDMA_PIN_53_McACLK,
.fsxPin = I2SCC32XXDMA_PIN_63_McAFSX,
}
};
const I2S_Config I2S_config[CC3220SF_LAUNCHXL_I2SCOUNT] = {
{
.fxnTablePtr = &I2SCC32XXDMA_fxnTable,
.object = &i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2S0],
.hwAttrs = &i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2S0]
}
};
const uint_least8_t I2S_count = CC3220SF_LAUNCHXL_I2SCOUNT;
/*
* =============================== Power ===============================
*/
/*
* This table defines the parking state to be set for each parkable pin
* during LPDS. (Device pins must be parked during LPDS to achieve maximum
* power savings.) If the pin should be left unparked, specify the state
* PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device
* will automatically park the pin in a high state during transition to LPDS,
* so the Power Manager does not need to explictly park the pin. So the
* corresponding entries in this table should indicate PowerCC32XX_DONT_PARK.
*/
PowerCC32XX_ParkInfo parkInfo[] = {
/* PIN PARK STATE PIN ALIAS (FUNCTION)
----------------- ------------------------------ -------------------- */
{PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */
{PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */
{PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */
{PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */
{PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */
{PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */
{PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */
{PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */
{PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */
{PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */
{PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */
{PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */
{PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */
{PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */
{PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */
{PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */
{PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */
{PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */
{PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */
{PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */
{PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */
{PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */
{PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (UART0_TX) */
{PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 */
{PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */
{PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */
{PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */
{PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */
{PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */
{PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */
{PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */
};
/*
* This structure defines the configuration for the Power Manager.
*
* In this configuration the Power policy is disabled by default (because
* enablePolicy is set to false). The Power policy can be enabled dynamically
* at runtime by calling Power_enablePolicy(), or at build time, by changing
* enablePolicy to true in this structure.
*/
const PowerCC32XX_ConfigV1 PowerCC32XX_config = {
.policyInitFxn = &PowerCC32XX_initPolicy,
.policyFxn = &PowerCC32XX_sleepPolicy,
.enterLPDSHookFxn = NULL,
.resumeLPDSHookFxn = NULL,
.enablePolicy = false,
.enableGPIOWakeupLPDS = true,
.enableGPIOWakeupShutdown = false,
.enableNetworkWakeupLPDS = true,
.wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13,
.wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE,
.wakeupGPIOFxnLPDS = NULL,
.wakeupGPIOFxnLPDSArg = 0,
.wakeupGPIOSourceShutdown = 0,
.wakeupGPIOTypeShutdown = 0,
.ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 |
PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4,
.keepDebugActiveDuringLPDS = false,
.ioRetentionShutdown = PRCM_IO_RET_GRP_1,
.pinParkDefs = parkInfo,
.numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo)
};
/*
* =============================== PWM ===============================
*/
#include <ti/drivers/PWM.h>
#include <ti/drivers/pwm/PWMTimerCC32XX.h>
PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT];
const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = {
{ /* CC3220SF_LAUNCHXL_PWM6 */
.pwmPin = PWMTimerCC32XX_PIN_01
},
{ /* CC3220SF_LAUNCHXL_PWM7 */
.pwmPin = PWMTimerCC32XX_PIN_02
}
};
const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = {
{
.fxnTablePtr = &PWMTimerCC32XX_fxnTable,
.object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6],
.hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6]
},
{
.fxnTablePtr = &PWMTimerCC32XX_fxnTable,
.object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7],
.hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7]
}
};
const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT;
/*
* =============================== SDFatFS ===============================
*/
#if 0 /*_RB_*/
#include <ti/drivers/SD.h>
#include <ti/drivers/SDFatFS.h>
/* Note: The SDFatFS and SD drivers must use the same count */
SDFatFS_Object sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFSCOUNT];
const SDFatFS_Config SDFatFS_config[CC3220SF_LAUNCHXL_SDFatFSCOUNT] = {
{
.object = &sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFS0]
}
};
const uint_least8_t SDFatFS_count = CC3220SF_LAUNCHXL_SDFatFSCOUNT;
/*
* =============================== SD ===============================
*/
#include <ti/drivers/SD.h>
#include <ti/drivers/sd/SDHostCC32XX.h>
SDHostCC32XX_Object sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SDCOUNT];
/* SDHost configuration structure, describing which pins are to be used */
const SDHostCC32XX_HWAttrsV1 sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SDCOUNT] = {
{
.clkRate = 8000000,
.intPriority = ~0,
.baseAddr = SDHOST_BASE,
.rxChIdx = UDMA_CH23_SDHOST_RX,
.txChIdx = UDMA_CH24_SDHOST_TX,
.dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA,
.cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD,
.clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK
}
};
const SD_Config SD_config[CC3220SF_LAUNCHXL_SDCOUNT] = {
{
.fxnTablePtr = &sdHostCC32XX_fxnTable,
.object = &sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SD0],
.hwAttrs = &sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SD0]
},
};
const uint_least8_t SD_count = CC3220SF_LAUNCHXL_SDCOUNT;
/*
* =============================== SDSPI ===============================
*/
#include <ti/drivers/SDSPI.h>
#include <ti/drivers/sdspi/SDSPICC32XX.h>
SDSPICC32XX_Object sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPICOUNT];
/* SDSPI configuration structure, describing which pins are to be used */
const SDSPICC32XX_HWAttrsV1 sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPICOUNT] = {
{
.baseAddr = GSPI_BASE,
.spiPRCM = PRCM_GSPI,
.clkPin = SDSPICC32XX_PIN_05_CLK,
.mosiPin = SDSPICC32XX_PIN_07_MOSI,
.misoPin = SDSPICC32XX_PIN_06_MISO,
.csPin = SDSPICC32XX_PIN_62_GPIO
}
};
const SDSPI_Config SDSPI_config[CC3220SF_LAUNCHXL_SDSPICOUNT] = {
{
.fxnTablePtr = &SDSPICC32XX_fxnTable,
.object = &sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPI0],
.hwAttrs = &sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPI0]
},
};
const uint_least8_t SDSPI_count = CC3220SF_LAUNCHXL_SDSPICOUNT;
#endif /* 0 _RB_ */
/*
* =============================== SPI ===============================
*/
#include <ti/drivers/SPI.h>
#include <ti/drivers/spi/SPICC32XXDMA.h>
SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT];
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(spiCC3220SDMAscratchBuf, 32)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=32
#elif defined(__GNUC__)
__attribute__ ((aligned (32)))
#endif
uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT];
const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = {
/* index 0 is reserved for LSPI that links to the NWP */
{
.baseAddr = LSPI_BASE,
.intNum = INT_LSPI,
.intPriority = (~0),
.spiPRCM = PRCM_LSPI,
.csControl = SPI_SW_CTRL_CS,
.csPolarity = SPI_CS_ACTIVEHIGH,
.pinMode = SPI_4PIN_MODE,
.turboMode = SPI_TURBO_OFF,
.scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CH12_LSPI_RX,
.txChannelIndex = UDMA_CH13_LSPI_TX,
.minDmaTransferSize = 100,
.mosiPin = SPICC32XXDMA_PIN_NO_CONFIG,
.misoPin = SPICC32XXDMA_PIN_NO_CONFIG,
.clkPin = SPICC32XXDMA_PIN_NO_CONFIG,
.csPin = SPICC32XXDMA_PIN_NO_CONFIG
},
{
.baseAddr = GSPI_BASE,
.intNum = INT_GSPI,
.intPriority = (~0),
.spiPRCM = PRCM_GSPI,
.csControl = SPI_HW_CTRL_CS,
.csPolarity = SPI_CS_ACTIVELOW,
.pinMode = SPI_4PIN_MODE,
.turboMode = SPI_TURBO_OFF,
.scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CH6_GSPI_RX,
.txChannelIndex = UDMA_CH7_GSPI_TX,
.minDmaTransferSize = 100,
.mosiPin = SPICC32XXDMA_PIN_07_MOSI,
.misoPin = SPICC32XXDMA_PIN_06_MISO,
.clkPin = SPICC32XXDMA_PIN_05_CLK,
.csPin = SPICC32XXDMA_PIN_08_CS
}
};
const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = {
{
.fxnTablePtr = &SPICC32XXDMA_fxnTable,
.object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0],
.hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
},
{
.fxnTablePtr = &SPICC32XXDMA_fxnTable,
.object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1],
.hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
}
};
const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
/*
* =============================== UART ===============================
*/
#include <ti/drivers/UART.h>
#if TI_DRIVERS_UART_DMA
#include <ti/drivers/uart/UARTCC32XXDMA.h>
UARTCC32XXDMA_Object uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UARTCOUNT];
/* UART configuration structure */
const UARTCC32XXDMA_HWAttrsV1 uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = {
{
.baseAddr = UARTA0_BASE,
.intNum = INT_UARTA0,
.intPriority = (~0),
.rxChannelIndex = UDMA_CH8_UARTA0_RX,
.txChannelIndex = UDMA_CH9_UARTA0_TX,
.rxPin = UARTCC32XXDMA_PIN_57_UART0_RX,
.txPin = UARTCC32XXDMA_PIN_55_UART0_TX
},
{
.baseAddr = UARTA1_BASE,
.intNum = INT_UARTA1,
.intPriority = (~0),
.rxChannelIndex = UDMA_CH10_UARTA1_RX,
.txChannelIndex = UDMA_CH11_UARTA1_TX,
.rxPin = UARTCC32XXDMA_PIN_08_UART1_RX,
.txPin = UARTCC32XXDMA_PIN_07_UART1_TX
}
};
const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = {
{
.fxnTablePtr = &UARTCC32XXDMA_fxnTable,
.object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART0],
.hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART0]
},
{
.fxnTablePtr = &UARTCC32XXDMA_fxnTable,
.object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART1],
.hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART1]
}
};
#else
#include <ti/drivers/uart/UARTCC32XX.h>
UARTCC32XX_Object uartCC3220SObjects[CC3220SF_LAUNCHXL_UARTCOUNT];
unsigned char uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UARTCOUNT][32];
/* UART configuration structure */
const UARTCC32XX_HWAttrsV1 uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = {
{
.baseAddr = UARTA0_BASE,
.intNum = INT_UARTA0,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0],
.ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0]),
.rxPin = UARTCC32XX_PIN_57_UART0_RX,
.txPin = UARTCC32XX_PIN_55_UART0_TX
},
{
.baseAddr = UARTA1_BASE,
.intNum = INT_UARTA1,
.intPriority = (~0),
.flowControl = UART_FLOWCONTROL_NONE,
.ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1],
.ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1]),
.rxPin = UARTCC32XX_PIN_08_UART1_RX,
.txPin = UARTCC32XX_PIN_07_UART1_TX
}
};
const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = {
{
.fxnTablePtr = &UARTCC32XX_fxnTable,
.object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART0],
.hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART0]
},
{
.fxnTablePtr = &UARTCC32XX_fxnTable,
.object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART1],
.hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART1]
}
};
#endif /* TI_DRIVERS_UART_DMA */
const uint_least8_t UART_count = CC3220SF_LAUNCHXL_UARTCOUNT;
/*
* =============================== Watchdog ===============================
*/
#include <ti/drivers/Watchdog.h>
#include <ti/drivers/watchdog/WatchdogCC32XX.h>
WatchdogCC32XX_Object watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOGCOUNT];
const WatchdogCC32XX_HWAttrs watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = {
{
.baseAddr = WDT_BASE,
.intNum = INT_WDT,
.intPriority = (~0),
.reloadValue = 80000000 // 1 second period at default CPU clock freq
}
};
const Watchdog_Config Watchdog_config[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = {
{
.fxnTablePtr = &WatchdogCC32XX_fxnTable,
.object = &watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOG0],
.hwAttrs = &watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOG0]
}
};
const uint_least8_t Watchdog_count = CC3220SF_LAUNCHXL_WATCHDOGCOUNT;
#if defined(__SF_DEBUG__)
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(ulDebugHeader, ".dbghdr")
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_location=".dbghdr"
#elif defined(__GNUC__)
__attribute__ ((section (".dbghdr")))
#endif
const unsigned long ulDebugHeader[]=
{
0x5AA5A55A,
0x000FF800,
0xEFA3247D
};
#endif

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file C3220SF_LAUNCHXL.h
*
* @brief CC3220 Board Specific APIs
*
* The CC3220SF_LAUNCHXL header file should be included in an application as
* follows:
* @code
* #include <CC3220SF_LAUNCHXL.h>
* @endcode
*
* ============================================================================
*/
#ifndef __CC3220SF_LAUNCHXL_H
#define __CC3220SF_LAUNCHXL_H
#ifdef __cplusplus
extern "C" {
#endif
#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0)
#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1)
/*!
* @def CC3220SF_LAUNCHXL_ADCName
* @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_ADCName {
CC3220SF_LAUNCHXL_ADC0 = 0,
CC3220SF_LAUNCHXL_ADC1,
CC3220SF_LAUNCHXL_ADCCOUNT
} CC3220SF_LAUNCHXL_ADCName;
/*!
* @def CC3220SF_LAUNCHXL_CryptoName
* @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_CryptoName {
CC3220SF_LAUNCHXL_CRYPTO0 = 0,
CC3220SF_LAUNCHXL_CRYPTOCOUNT
} CC3220SF_LAUNCHXL_CryptoName;
/*!
* @def CC3220SF_LAUNCHXL_GPIOName
* @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_GPIOName {
CC3220SF_LAUNCHXL_GPIO_SW2 = 0,
CC3220SF_LAUNCHXL_GPIO_SW3,
CC3220SF_LAUNCHXL_GPIO_LED_D7,
/*
* CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the
* I2C and PWM peripherals. In order for those examples to work, these
* LEDs are taken out of gpioPinCOnfig[]
*/
//CC3220SF_LAUNCHXL_GPIO_LED_D6,
//CC3220SF_LAUNCHXL_GPIO_LED_D5,
CC3220SF_LAUNCHXL_GPIOCOUNT
} CC3220SF_LAUNCHXL_GPIOName;
/*!
* @def CC3220SF_LAUNCHXL_I2CName
* @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_I2CName {
CC3220SF_LAUNCHXL_I2C0 = 0,
CC3220SF_LAUNCHXL_I2CCOUNT
} CC3220SF_LAUNCHXL_I2CName;
/*!
* @def CC3220SF_LAUNCHXL_I2SName
* @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_I2SName {
CC3220SF_LAUNCHXL_I2S0 = 0,
CC3220SF_LAUNCHXL_I2SCOUNT
} CC3220SF_LAUNCHXL_I2SName;
/*!
* @def CC3220SF_LAUNCHXL_PWMName
* @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_PWMName {
CC3220SF_LAUNCHXL_PWM6 = 0,
CC3220SF_LAUNCHXL_PWM7,
CC3220SF_LAUNCHXL_PWMCOUNT
} CC3220SF_LAUNCHXL_PWMName;
/*!
* @def CC3220SF_LAUNCHXL_SDFatFSName
* @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SDFatFSName {
CC3220SF_LAUNCHXL_SDFatFS0 = 0,
CC3220SF_LAUNCHXL_SDFatFSCOUNT
} CC3220SF_LAUNCHXL_SDFatFSName;
/*!
* @def CC3220SF_LAUNCHXL_SDName
* @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SDName {
CC3220SF_LAUNCHXL_SD0 = 0,
CC3220SF_LAUNCHXL_SDCOUNT
} CC3220SF_LAUNCHXL_SDName;
/*!
* @def CC3220SF_LAUNCHXL_SDSPIName
* @brief Enum of SDSPI names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SDSPIName {
CC3220SF_LAUNCHXL_SDSPI0 = 0,
CC3220SF_LAUNCHXL_SDSPICOUNT
} CC3220SF_LAUNCHXL_SDSPIName;
/*!
* @def CC3220SF_LAUNCHXL_SPIName
* @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SPIName {
CC3220SF_LAUNCHXL_SPI0 = 0,
CC3220SF_LAUNCHXL_SPI1,
CC3220SF_LAUNCHXL_SPICOUNT
} CC3220SF_LAUNCHXL_SPIName;
/*!
* @def CC3220SF_LAUNCHXL_UARTName
* @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_UARTName {
CC3220SF_LAUNCHXL_UART0 = 0,
CC3220SF_LAUNCHXL_UART1,
CC3220SF_LAUNCHXL_UARTCOUNT
} CC3220SF_LAUNCHXL_UARTName;
/*!
* @def CC3220SF_LAUNCHXL_WatchdogName
* @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_WatchdogName {
CC3220SF_LAUNCHXL_WATCHDOG0 = 0,
CC3220SF_LAUNCHXL_WATCHDOGCOUNT
} CC3220SF_LAUNCHXL_WatchdogName;
/*!
* @brief Initialize the general board specific settings
*
* This function initializes the general board specific settings.
*/
extern void CC3220SF_LAUNCHXL_initGeneral(void);
#ifdef __cplusplus
}
#endif
#endif /* __CC3220SF_LAUNCHXL_H */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== CC3220SF_LAUNCHXL.cmd ========
*/
--stack_size=1024
--heap_size=0 /* minimize heap since we are using heap_4.c */
--entry_point=resetISR
/*
* The starting address of the application. Normally the interrupt vectors
* must be located at the beginning of the application.
*/
#define SRAM_BASE 0x20000000
#define FLASH_BASE 0x01000800
MEMORY
{
/* Bootloader uses FLASH_HDR during initialization */
FLASH_HDR (RX) : origin = 0x01000000, length = 0x7FF /* 2 KB */
FLASH (RX) : origin = 0x01000800, length = 0x0FF800 /* 1022KB */
SRAM (RWX) : origin = 0x20000000, length = 0x00040000 /* 256KB */
}
/* Section allocation in memory */
SECTIONS
{
.dbghdr : > FLASH_HDR
.text : > FLASH
.TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT)
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM(HIGH)
/* these sections are used by FreeRTOS */
.resetVecs : > FLASH_BASE
.ramVecs : > SRAM_BASE, type=NOLOAD
}

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// adc.h
//
// Defines and Macros for the ADC.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to APIs as ulChannel parameter
//*****************************************************************************
#define ADC_CH_0 0x00000000
#define ADC_CH_1 0x00000008
#define ADC_CH_2 0x00000010
#define ADC_CH_3 0x00000018
//*****************************************************************************
//
// Values that can be passed to ADCIntEnable(), ADCIntDisable()
// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
//
//*****************************************************************************
#define ADC_DMA_DONE 0x00000010
#define ADC_FIFO_OVERFLOW 0x00000008
#define ADC_FIFO_UNDERFLOW 0x00000004
#define ADC_FIFO_EMPTY 0x00000002
#define ADC_FIFO_FULL 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void ADCEnable(unsigned long ulBase);
extern void ADCDisable(unsigned long ulBase);
extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
extern void ADCTimerEnable(unsigned long ulBase);
extern void ADCTimerDisable(unsigned long ulBase);
extern void ADCTimerReset(unsigned long ulBase);
extern unsigned long ADCTimerValueGet(unsigned long ulBase);
extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long ADCFIFORead(unsigned long ulBase,
unsigned long ulChannel);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// aes.h
//
// Defines and Macros for the AES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010040
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00020000
#define AES_INT_DMA_DATA_IN 0x00040000
#define AES_INT_DMA_DATA_OUT 0x00080000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000040
#define AES_DMA_DATA_OUT 0x00000020
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest,
uint32_t ui32Length);
extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,
uint32_t ui32Length,
uint8_t *pui8Tag);
extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length,
uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,
uint8_t *pui8Tag);
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// camera.h
//
// Prototypes and macros for the camera controller module.
//
//*****************************************************************************
#ifndef __CAMERA_H__
#define __CAMERA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Macro defining Camera buffer address
//*****************************************************************************
#define CAM_BUFFER_ADDR 0x44018100
//*****************************************************************************
// Value that can be passed to CameraXClkSet().
//*****************************************************************************
#define CAM_XCLK_STABLE_LO 0x00
#define CAM_XCLK_STABLE_HI 0x01
#define CAM_XCLK_DIV_BYPASS 0x02
//*****************************************************************************
// Value that can be passed to CameraIntEnable(), CameraIntDisable,
// CameraIntClear() or returned from CameraIntStatus().
//*****************************************************************************
#define CAM_INT_DMA 0x80000000
#define CAM_INT_FE 0x00010000
#define CAM_INT_FIFO_NOEMPTY 0x00000010
#define CAM_INT_FIFO_FULL 0x00000008
#define CAM_INT_FIFO_THR 0x00000004
#define CAM_INT_FIFO_OF 0x00000002
#define CAN_INT_FIFO_UR 0x00000001
//*****************************************************************************
// Value that can be passed to CameraXClkConfig().
//*****************************************************************************
#define CAM_HS_POL_HI 0x00000000
#define CAM_HS_POL_LO 0x00000200
#define CAM_VS_POL_HI 0x00000000
#define CAM_VS_POL_LO 0x00000100
#define CAM_PCLK_RISE_EDGE 0x00000000
#define CAM_PCLK_FALL_EDGE 0x00000400
#define CAM_ORDERCAM_SWAP 0x00000800
#define CAM_NOBT_SYNCHRO 0x00002000
#define CAM_IF_SYNCHRO 0x00080000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CameraReset(unsigned long ulBase);
extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol,
unsigned long ulVSPol, unsigned long ulFlags);
extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn,
unsigned long ulXClk);
extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags);
extern void CameraDMAEnable(unsigned long ulBase);
extern void CameraDMADisable(unsigned long ulBase);
extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold);
extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void CameraIntUnregister(unsigned long ulBase);
extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long CameraIntStatus(unsigned long ulBase);
extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate);
extern void CameraCaptureStart(unsigned long ulBase);
extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer,
unsigned char ucSize);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__CAMERA_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// cpu.c
//
// Instruction wrappers for special CPU instructions needed by the
//
//
//*****************************************************************************
#include "cpu.h"
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsid(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function returning the state of PRIMASK (indicating whether
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUprimask(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsie(void)
{
unsigned long ulRet;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the WFI instruction.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n");
}
#endif
#if defined(ccs)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n");
}
#endif
//*****************************************************************************
//
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n");
}
#endif
#if defined(ccs)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n");
}
#endif
//*****************************************************************************
//
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUbasepriGet(void)
{
unsigned long ulRet;
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// cpu.h
//
// Prototypes for the CPU instruction wrapper functions.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern unsigned long CPUprimask(void);
extern void CPUwfi(void);
extern unsigned long CPUbasepriGet(void);
extern void CPUbasepriSet(unsigned long ulNewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// crc.h
//
// Defines and Macros for CRC module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CRC_H__
#define __DRIVERLIB_CRC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used in the ui32Config argument of the
// ECConfig function.
//
//*****************************************************************************
#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed
#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s'
#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s'
#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size
#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size
#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable
#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable
#define CRC_CFG_IBR 0x00000080 // Bit reverse enable
#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word
#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word
#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005
#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021
#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7
#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41
#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
uint32_t ui32DataLength, uint32_t ui32Config);
extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
extern uint32_t CRCResultRead(uint32_t ui32Base);
extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CRC_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// debug.h
//
// Macros for assisting debug of the driver library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// des.h
//
// Defines and Macros for the DES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_DES_H__
#define __DRIVERLIB_DES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the direction with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_DIR_DECRYPT 0x00000000
#define DES_CFG_DIR_ENCRYPT 0x00000004
//*****************************************************************************
//
// The following defines are used to specify the operational with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_MODE_ECB 0x00000000
#define DES_CFG_MODE_CBC 0x00000010
#define DES_CFG_MODE_CFB 0x00000020
//*****************************************************************************
//
// The following defines are used to select between single DES and triple DES
// with the ui32Config argument in the DESConfig() function. Only one is
// permitted.
//
//*****************************************************************************
#define DES_CFG_SINGLE 0x00000000
#define DES_CFG_TRIPLE 0x00000008
//*****************************************************************************
//
// The following defines are used with the DESIntEnable(), DESIntDisable() and
// DESIntStatus() functions.
//
//*****************************************************************************
#define DES_INT_CONTEXT_IN 0x00000001
#define DES_INT_DATA_IN 0x00000002
#define DES_INT_DATA_OUT 0x00000004
#define DES_INT_DMA_CONTEXT_IN 0x00010000
#define DES_INT_DMA_DATA_IN 0x00020000
#define DES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// The following defines are used with the DESEnableDMA() and DESDisableDMA()
// functions.
//
//*****************************************************************************
#define DES_DMA_CONTEXT_IN 0x00000080
#define DES_DMA_DATA_OUT 0x00000040
#define DES_DMA_DATA_IN 0x00000020
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length);
extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
extern void DESIntUnregister(uint32_t ui32Base);
extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_DES_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// flash.c
//
// Driver for programming the on-chip flash.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_flash_ctrl.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_gprcm.h"
#include "inc/hw_hib1p2.h"
#include "inc/hw_hib3p3.h"
#include "inc/hw_common_reg.h"
#include "inc/hw_stack_die_ctrl.h"
#include "debug.h"
#include "flash.h"
#include "utils.h"
#include "interrupt.h"
#define HAVE_WRITE_BUFFER 1
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Program Enable (FMPPE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPPERegs[] =
{
FLASH_FMPPE0,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3,
FLASH_FMPPE4,
FLASH_FMPPE5,
FLASH_FMPPE6,
FLASH_FMPPE7,
FLASH_FMPPE8,
FLASH_FMPPE9,
FLASH_FMPPE10,
FLASH_FMPPE11,
FLASH_FMPPE12,
FLASH_FMPPE13,
FLASH_FMPPE14,
FLASH_FMPPE15
};
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Read Enable (FMPRE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPRERegs[] =
{
FLASH_FMPRE0,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3,
FLASH_FMPRE4,
FLASH_FMPRE5,
FLASH_FMPRE6,
FLASH_FMPRE7,
FLASH_FMPRE8,
FLASH_FMPRE9,
FLASH_FMPRE10,
FLASH_FMPRE11,
FLASH_FMPRE12,
FLASH_FMPRE13,
FLASH_FMPRE14,
FLASH_FMPRE15,
};
//*****************************************************************************
//
//! Flash Disable
//!
//! This function Disables the internal Flash.
//!
//! \return None.
//
//*****************************************************************************
void
FlashDisable()
{
//
// Wait for Flash Busy to get cleared
//
while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE)
& GPRCM_TOP_DIE_ENABLE_FLASH_BUSY))
{
}
//
// Assert reset
//
HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
//
// Disable TDFlash
//
HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
}
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
// Erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC)
= FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
//
// Wait until the block has been erased.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Erases a block of flash but does not wait for completion.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return None.
//
//*****************************************************************************
void
FlashEraseNonBlocking(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller to erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
}
//*****************************************************************************
//
//! Erases a complele flash at shot.
//!
//! This function erases a complele flash at shot
//!
//! \return Returns 0 on success, or -1 if the block is write-protected.
//
//*****************************************************************************
long
FlashMassErase()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
//
// Wait until mass erase completes.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return -1;
}
//
// Success.
//
return 0;
}
//*****************************************************************************
//
//! Erases a complele flash at shot but does not wait for completion.
//!
//!
//! This function will not return until the Flash has been erased.
//!
//! \return None.
//
//*****************************************************************************
void
FlashMassEraseNonBlocking()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
}
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times will result in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words. for 1 MB
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) ||
(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN
+ (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2)
= FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF)
{
}
}
}
#else
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
#endif
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Programs flash but does not poll for completion.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will start programming one or more words into the on-chip
//! flash and return immediately. The number of words that can be programmed
//! in a single call depends the part on which the function is running. For
//! parts without support for a flash write buffer, only a single word may be
//! programmed on each call to this function (\e ulCount must be 1). If a
//! write buffer is present, up to 32 words may be programmed on condition
//! that the block being programmed does not straddle a 32 word address
//! boundary. For example, wherease 32 words can be programmed if the address
//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could
//! be programmed at 0x104 since attempting to write 32 would cross the 32
//! word boundary at 0x180.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return 0 if the write was started successfully, -1 if there was an error.
//
//*****************************************************************************
long
FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Make sure the address/count specified doesn't straddle a 32 word
// boundary.
//
if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F))
{
return(-1);
}
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
}
}
#else
{
//
// We don't have a write buffer so we can only write a single word.
//
if(ulCount > 1)
{
return(-1);
}
//
// Write a single word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
}
#endif
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Calculate the Flash Bank from Base Address, and mask off the Bank
// from ulAddress for subsequent reference.
//
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16);
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
//
// Read the appropriate flash protection registers for the specified
// flash bank.
//
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// Check the appropriate protection bits for the block of memory that
// is specified by the address.
//
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fetch interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (that is, it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS.
//
//*****************************************************************************
unsigned long
FlashIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC));
}
else
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS));
}
}
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// flash.h
//
// Prototypes for the flash driver.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void FlashDisable(void);
extern long FlashErase(unsigned long ulAddress);
extern void FlashEraseNonBlocking(unsigned long ulAddress);
extern long FlashMassErase(void);
extern void FlashMassEraseNonBlocking(void);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern long FlashProgramNonBlocking(unsigned long *pulData,
unsigned long ulAddress,
unsigned long ulCount);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// gpio.c
//
// Driver for the GPIO module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup GPIO_General_Purpose_InputOutput_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_common_reg.h"
#include "debug.h"
#include "gpio.h"
#include "interrupt.h"
//*****************************************************************************
//
//! \internal
//! Checks a GPIO base address.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function determines if a GPIO port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
GPIOBaseValid(unsigned long ulPort)
{
return((ulPort == GPIOA0_BASE) ||
(ulPort == GPIOA1_BASE) ||
(ulPort == GPIOA2_BASE) ||
(ulPort == GPIOA3_BASE) ||
(ulPort == GPIOA4_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the GPIO interrupt number.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! Given a GPIO base address, returns the corresponding interrupt number.
//!
//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
//
//*****************************************************************************
static long
GPIOGetIntNumber(unsigned long ulPort)
{
unsigned int ulInt;
//
// Determine the GPIO interrupt number for the given module.
//
switch(ulPort)
{
case GPIOA0_BASE:
{
ulInt = INT_GPIOA0;
break;
}
case GPIOA1_BASE:
{
ulInt = INT_GPIOA1;
break;
}
case GPIOA2_BASE:
{
ulInt = INT_GPIOA2;
break;
}
case GPIOA3_BASE:
{
ulInt = INT_GPIOA3;
break;
}
default:
{
return(-1);
}
}
//
// Return GPIO interrupt number.
//
return(ulInt);
}
//*****************************************************************************
//
//! Sets the direction and mode of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulPinIO is the pin direction and/or mode.
//!
//! This function will set the specified pin(s) on the selected GPIO port
//! as either an input or output under software control, or it will set the
//! pin to be under hardware control.
//!
//! The parameter \e ulPinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
//! will be programmed as a software controlled output.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note GPIOPadConfigSet() must also be used to configure the corresponding
//! pad(s) in order for them to propagate the signal to/from the GPIO.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
//
// Set the pin direction and mode.
//
HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the direction and mode of a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input or
//! output under software control, or it can be under hardware control. The
//! type of control and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
unsigned long
GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulDir;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
//
ucPin = 1 << ucPin;
//
// Return the pin direction and mode.
//
ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
return(((ulDir & ucPin) ? 1 : 0));
}
//*****************************************************************************
//
//! Sets the interrupt type for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulIntType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin(s) on the selected GPIO port.
//!
//! The parameter \e ulIntType is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_FALLING_EDGE
//! - \b GPIO_RISING_EDGE
//! - \b GPIO_BOTH_EDGES
//! - \b GPIO_LOW_LEVEL
//! - \b GPIO_HIGH_LEVEL
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note In order to avoid any spurious interrupts, the user must
//! ensure that the GPIO inputs remain stable for the duration of
//! this function.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
(ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
(ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
//
// Set the pin interrupt type.
//
HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
(HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
(HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the interrupt type for a specified pin on the selected
//! GPIO port. The pin can be configured as a falling edge, rising edge, or
//! both edge detected interrupt, or it can be configured as a low level or
//! high level detected interrupt. The type of interrupt detection mechanism
//! is returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIOIntTypeSet().
//
//*****************************************************************************
unsigned long
GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulIBE, ulIS, ulIEV;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
//
ucPin = 1 << ucPin;
//
// Return the pin interrupt type.
//
ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
((ulIEV & ucPin) ? 4 : 0));
}
//*****************************************************************************
//
//! Enables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
//!
//! This function enables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Enable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function disables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Disable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets interrupt status for the specified GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status will be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in GPIOIntEnable().
//
//*****************************************************************************
long
GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the interrupt status.
//
if(bMasked)
{
return(HWREG(ulPort + GPIO_O_GPIO_MIS));
}
else
{
return(HWREG(ulPort + GPIO_O_GPIO_RIS));
}
}
//*****************************************************************************
//
//! Clears the interrupt for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! Clears the interrupt for the specified pin(s).
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to GPIOIntEnable().
//!
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Clear the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
//! function.
//!
//! This function will ensure that the interrupt handler specified by
//! \e pfnIntHandler is called when an interrupt is detected from the selected
//! GPIO port. This function will also enable the corresponding GPIO interrupt
//! in the interrupt controller; individual pin interrupts and interrupt
//! sources must be enabled with GPIOIntEnable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Register the interrupt handler.
//
IntRegister(ulPort, pfnIntHandler);
//
// Enable the GPIO interrupt.
//
IntEnable(ulPort);
}
//*****************************************************************************
//
//! Removes an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function will unregister the interrupt handler for the specified
//! GPIO port. This function will also disable the corresponding
//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
//! and interrupt sources must be disabled with GPIOIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntUnregister(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Disable the GPIO interrupt.
//
IntDisable(ulPort);
//
// Unregister the interrupt handler.
//
IntUnregister(ulPort);
}
//*****************************************************************************
//
//! Reads the values present of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! The values at the specified pin(s) are read, as specified by \e ucPins.
//! Values are returned for both input and output pin(s), and the value
//! for pin(s) that are not specified by \e ucPins are set to 0.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return Returns a bit-packed byte providing the state of the specified
//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
//! is returned as a 0. Bits 31:8 should be ignored.
//
//*****************************************************************************
long
GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the pin value(s).
//
return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
}
//*****************************************************************************
//
//! Writes a value to the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ucVal is the value to write to the pin(s).
//!
//! Writes the corresponding bit values to the output pin(s) specified by
//! \e ucPins. Writing to a pin configured as an input pin has no effect.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Write the pins.
//
HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
}
//*****************************************************************************
//
//! Enables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function enables a GPIO port to be used as a trigger to start a uDMA
//! transaction. The GPIO pin will still generate interrupts if the interrupt is
//! enabled for the selected pin.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerEnable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
}
}
//*****************************************************************************
//
//! Disables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function disables a GPIO port to be used as a trigger to start a uDMA
//! transaction. This function can be used to disable this feature if it was
//! enabled via a call to GPIODMATriggerEnable().
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerDisable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
}
}
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// gpio.h
//
// Defines and Macros for GPIO API.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
// in the ulIntFlags parameter.
//
//*****************************************************************************
#define GPIO_INT_DMA 0x00000100
#define GPIO_INT_PIN_0 0x00000001
#define GPIO_INT_PIN_1 0x00000002
#define GPIO_INT_PIN_2 0x00000004
#define GPIO_INT_PIN_3 0x00000008
#define GPIO_INT_PIN_4 0x00000010
#define GPIO_INT_PIN_5 0x00000020
#define GPIO_INT_PIN_6 0x00000040
#define GPIO_INT_PIN_7 0x00000080
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern void GPIODMATriggerEnable(unsigned long ulPort);
extern void GPIODMATriggerDisable(unsigned long ulPort);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
extern void GPIOIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.c
//
// Driver for the Apps-NWP spinlock
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup HwSpinLock_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_common_reg.h"
#include "hwspinlock.h"
//*****************************************************************************
// Global semaphore register list
//*****************************************************************************
static const uint32_t HwSpinLock_RegLst[]=
{
COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register
};
//*****************************************************************************
//
//! Acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function acquires specified spin lock and will not retun util the
//! specified lock is acquired.
//!
//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0.
//!
//! return None.
//
//*****************************************************************************
void HwSpinLockAcquire(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Retry untill we succeed
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) );
}
//*****************************************************************************
//
//! Try to acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param ui32Retry is the number of reties.
//!
//! This function tries acquire specified spin lock in \e ui32Retry retries.
//!
//! The parameter \e ui32Retry can be any value between 0 and 2^32.
//!
//! return Returns 0 on success, -1 otherwise.
//
//*****************************************************************************
int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Check for 0 retry.
//
if(ui32Retry == 0)
{
ui32Retry = 1;
}
//
// Retry the number of times specified
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
ui32Retry--;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry );
//
// Check the semaphore status
//
if(HWREG(ui32RegAddr) & (1 << ui32BitPos ))
{
return 0;
}
else
{
return -1;
}
}
//*****************************************************************************
//
//! Release a previously owned spin lock
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function releases previously owned spin lock.
//!
//! \return None.
//
//*****************************************************************************
void HwSpinLockRelease(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// Release the spin lock, only if already owned
//
if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos ))
{
ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos));
HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal;
}
}
//*****************************************************************************
//
//! Get the current or previous ownership status.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param bCurrentStatus is \b true for current status, \b flase otherwise
//!
//! This function gets the current or previous ownership status of the
//! specified spin lock based on \e bCurrentStatus parameter.
//!
//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or
//! \b HWSPINLOCK_OWNER_NONE.
//
//*****************************************************************************
uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
if(bCurrentStatus)
{
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// return semaphore
//
return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 );
}
else
{
//
// Extract the bit position
//
ui32BitPos = ((ui32LockID >> 24) & 0xFF);
//
// Identify which register to read
//
if(ui32LockID & 0xF > 4)
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3);
}
else
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3);
}
//
// return the owner
//
return ui32SemVal;
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

90
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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.h
//
// Prototypes for the Apps-NWP spinlock.
//
//*****************************************************************************
#ifndef __HWSPINLOCK_H__
#define __HWSPINLOCK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// values that can be passed to API as ui32LockID parameter
//*****************************************************************************
#define HWSPINLOCK_SSPI 0x02000000
//*****************************************************************************
// Values that are returned from HwSpinLockTest()
//*****************************************************************************
#define HWSPINLOCK_OWNER_APPS 0x00000001
#define HWSPINLOCK_OWNER_NWP 0x00000002
#define HWSPINLOCK_OWNER_NONE 0x00000000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HwSpinLockAcquire(uint32_t ui32LockID);
extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry);
extern void HwSpinLockRelease(uint32_t ui32LockID);
extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HWSPINLOCK_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2c.h
//
// Prototypes for the I2C Driver.
//
//*****************************************************************************
#ifndef __DRIVERLIB_I2C_H__
#define __DRIVERLIB_I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
0x00000013
#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \
0x00000046
#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \
0x00000046
#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \
0x00000042
#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \
0x00000040
#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \
0x0000004a
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \
0x00000048
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \
0x00000004
//*****************************************************************************
//
// I2C Master glitch filter configuration.
//
//*****************************************************************************
#define I2C_MASTER_GLITCH_FILTER_DISABLED \
0
#define I2C_MASTER_GLITCH_FILTER_1 \
0x00010000
#define I2C_MASTER_GLITCH_FILTER_2 \
0x00020000
#define I2C_MASTER_GLITCH_FILTER_3 \
0x00030000
#define I2C_MASTER_GLITCH_FILTER_4 \
0x00040000
#define I2C_MASTER_GLITCH_FILTER_8 \
0x00050000
#define I2C_MASTER_GLITCH_FILTER_16 \
0x00060000
#define I2C_MASTER_GLITCH_FILTER_32 \
0x00070000
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_RX_FIFO_FULL \
0x00000800 // RX FIFO Full Interrupt
#define I2C_MASTER_INT_TX_FIFO_EMPTY \
0x00000400 // TX FIFO Empty Interrupt
#define I2C_MASTER_INT_RX_FIFO_REQ \
0x00000200 // RX FIFO Request Interrupt
#define I2C_MASTER_INT_TX_FIFO_REQ \
0x00000100 // TX FIFO Request Interrupt
#define I2C_MASTER_INT_ARB_LOST \
0x00000080 // Arb Lost Interrupt
#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt
#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt
#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt
#define I2C_MASTER_INT_TX_DMA_DONE \
0x00000008 // TX DMA Complete Interrupt
#define I2C_MASTER_INT_RX_DMA_DONE \
0x00000004 // RX DMA Complete Interrupt
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_RX_FIFO_FULL \
0x00000100 // RX FIFO Full Interrupt
#define I2C_SLAVE_INT_TX_FIFO_EMPTY \
0x00000080 // TX FIFO Empty Interrupt
#define I2C_SLAVE_INT_RX_FIFO_REQ \
0x00000040 // RX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_FIFO_REQ \
0x00000020 // TX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_DMA_DONE \
0x00000010 // TX DMA Complete Interrupt
#define I2C_SLAVE_INT_RX_DMA_DONE \
0x00000008 // RX DMA Complete Interrupt
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave FIFO configuration macros.
//
//*****************************************************************************
#define I2C_SLAVE_TX_FIFO_ENABLE \
0x00000002
#define I2C_SLAVE_RX_FIFO_ENABLE \
0x00000004
//*****************************************************************************
//
// I2C FIFO configuration macros.
//
//*****************************************************************************
#define I2C_FIFO_CFG_TX_MASTER 0x00000000
#define I2C_FIFO_CFG_TX_SLAVE 0x00008000
#define I2C_FIFO_CFG_RX_MASTER 0x00000000
#define I2C_FIFO_CFG_RX_SLAVE 0x80000000
#define I2C_FIFO_CFG_TX_MASTER_DMA \
0x00002000
#define I2C_FIFO_CFG_TX_SLAVE_DMA \
0x0000a000
#define I2C_FIFO_CFG_RX_MASTER_DMA \
0x20000000
#define I2C_FIFO_CFG_RX_SLAVE_DMA \
0xa0000000
#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001
#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002
#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003
#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004
#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005
#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006
#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007
#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008
#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000
#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000
#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000
#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000
#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000
#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000
#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000
#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000
//*****************************************************************************
//
// I2C FIFO status.
//
//*****************************************************************************
#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \
0x00040000
#define I2C_FIFO_RX_FULL 0x00020000
#define I2C_FIFO_RX_EMPTY 0x00010000
#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \
0x00000004
#define I2C_FIFO_TX_FULL 0x00000002
#define I2C_FIFO_TX_EMPTY 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
extern void I2CIntUnregister(uint32_t ui32Base);
extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CTxFIFOFlush(uint32_t ui32Base);
extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CRxFIFOFlush(uint32_t ui32Base);
extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
uint8_t ui8Data);
extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
uint8_t *pui8Data);
extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
uint8_t ui8Length);
extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
uint32_t ui32Config);
extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CSlaveFIFODisable(uint32_t ui32Base);
extern bool I2CMasterBusBusy(uint32_t ui32Base);
extern bool I2CMasterBusy(uint32_t ui32Base);
extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CMasterDisable(uint32_t ui32Base);
extern void I2CMasterEnable(uint32_t ui32Base);
extern uint32_t I2CMasterErr(uint32_t ui32Base);
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast);
extern void I2CMasterIntClear(uint32_t ui32Base);
extern void I2CMasterIntDisable(uint32_t ui32Base);
extern void I2CMasterIntEnable(uint32_t ui32Base);
extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
extern void I2CMasterIntEnableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern void I2CMasterIntClearEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
uint8_t ui8SlaveAddr,
bool bReceive);
extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CSlaveDisable(uint32_t ui32Base);
extern void I2CSlaveEnable(uint32_t ui32Base);
extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
uint8_t ui8SlaveAddr);
extern void I2CSlaveIntClear(uint32_t ui32Base);
extern void I2CSlaveIntDisable(uint32_t ui32Base);
extern void I2CSlaveIntEnable(uint32_t ui32Base);
extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_I2C_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2s.h
//
// Defines and Macros for the I2S.
//
//*****************************************************************************
#ifndef __I2S_H__
#define __I2S_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// I2S DMA ports.
//
//*****************************************************************************
#define I2S_TX_DMA_PORT 0x4401E200
#define I2S_RX_DMA_PORT 0x4401E280
//*****************************************************************************
//
// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
//
//*****************************************************************************
#define I2S_SLOT_SIZE_8 0x00300032
#define I2S_SLOT_SIZE_16 0x00700074
#define I2S_SLOT_SIZE_24 0x00B000B6
#define I2S_PORT_CPU 0x00080008
#define I2S_PORT_DMA 0x00000000
#define I2S_MODE_MASTER 0x00000000
#define I2S_MODE_SLAVE 0x00008000
//*****************************************************************************
//
// Values that can be passed as ulDataLine parameter.
//
//*****************************************************************************
#define I2S_DATA_LINE_0 0x00000001
#define I2S_DATA_LINE_1 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulSerMode
// parameter.
//
//*****************************************************************************
#define I2S_SER_MODE_TX 0x00000001
#define I2S_SER_MODE_RX 0x00000002
#define I2S_SER_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulInActState
// parameter.
//
//*****************************************************************************
#define I2S_INACT_TRI_STATE 0x00000000
#define I2S_INACT_LOW_LEVEL 0x00000008
#define I2S_INACT_HIGH_LEVEL 0x0000000C
//*****************************************************************************
//
// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the
// ulIntFlags parameter.
//
//*****************************************************************************
#define I2S_INT_XUNDRN 0x00000001
#define I2S_INT_XSYNCERR 0x00000002
#define I2S_INT_XLAST 0x00000010
#define I2S_INT_XDATA 0x00000020
#define I2S_INT_XSTAFRM 0x00000080
#define I2S_INT_XDMA 0x80000000
#define I2S_INT_ROVRN 0x00010000
#define I2S_INT_RSYNCERR 0x00020000
#define I2S_INT_RLAST 0x00100000
#define I2S_INT_RDATA 0x00200000
#define I2S_INT_RSTAFRM 0x00800000
#define I2S_INT_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet
//
//*****************************************************************************
#define I2S_ACT_SLOT_EVEN 0x00000001
#define I2S_ACT_SLOT_ODD 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SIntClear() as the
// ulIntFlags parameter and returned from I2SIntStatus().
//
//*****************************************************************************
#define I2S_STS_XERR 0x00000100
#define I2S_STS_XDMAERR 0x00000080
#define I2S_STS_XSTAFRM 0x00000040
#define I2S_STS_XDATA 0x00000020
#define I2S_STS_XLAST 0x00000010
#define I2S_STS_XSYNCERR 0x00000002
#define I2S_STS_XUNDRN 0x00000001
#define I2S_STS_XDMA 0x80000000
#define I2S_STS_RERR 0x01000000
#define I2S_STS_RDMAERR 0x00800000
#define I2S_STS_RSTAFRM 0x00400000
#define I2S_STS_RDATA 0x00200000
#define I2S_STS_RLAST 0x00100000
#define I2S_STS_RSYNCERR 0x00020000
#define I2S_STS_ROVERN 0x00010000
#define I2S_STS_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SEnable() as the ulMode parameter.
//
//*****************************************************************************
#define I2S_MODE_TX_ONLY 0x00000001
#define I2S_MODE_TX_RX_SYNC 0x00000003
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);
extern void I2SDisable(unsigned long ulBase);
extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulData);
extern long I2SDataPutNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long ulData);
extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
unsigned long *pulData);
extern long I2SDataGetNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long *pulData);
extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
unsigned long ulBitClk, unsigned long ulConfig);
extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulWordsPerTransfer);
extern void I2STxFIFODisable(unsigned long ulBase);
extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
unsigned long ulWordsPerTransfer);
extern void I2SRxFIFODisable(unsigned long ulBase);
extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);
extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);
extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulSerMode, unsigned long ulInActState);
extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long I2SIntStatus(unsigned long ulBase);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__I2S_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// interrupt.c
//
// Driver for the NVIC Interrupt Controller.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37,
NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43,
NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4,
NVIC_UNPEND5
};
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
return(CPUcpsie());
}
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
return(CPUcpsid());
}
//*****************************************************************************
//
//! Sets the NVIC VTable base.
//!
//! \param ulVtableBase specifies the new base address of VTable
//!
//! This function is used to specify a new base address for the VTable.
//! This function must be called before using IntRegister() for registering
//! any interrupt handler.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntVTableBaseSet(unsigned long ulVtableBase)
{
HWREG(NVIC_VTABLE) = ulVtableBase;
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
IntUnregister(unsigned long ulInterrupt)
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler;
}
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the CC3200 , three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any prioritization must be performed in
//! those bits. The remaining bits can be used to sub-prioritize the interrupt
//! sources, and may be used by the hardware priority mechanism on a future
//! part. This arrangement allows priorities to migrate to different NVIC
//! implementations without changing the gross prioritization of the
//! interrupts.
//!
//! The parameter \e ucPriority can be any one of the following
//! -\b INT_PRIORITY_LVL_0
//! -\b INT_PRIORITY_LVL_1
//! -\b INT_PRIORITY_LVL_2
//! -\b INT_PRIORITY_LVL_3
//! -\b INT_PRIORITY_LVL_4
//! -\b INT_PRIORITY_LVL_5
//! -\b INT_PRIORITY_LVL_6
//! -\b INT_PRIORITY_LVL_7
//!
//! \return None.
//
//*****************************************************************************
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Pends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendSet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to pend.
//
if(ulInterrupt == FAULT_NMI)
{
//
// Pend the NMI interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Unpends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendClear(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to unpend.
//
if(ulInterrupt == FAULT_PENDSV)
{
//
// Unpend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityMaskSet(unsigned long ulPriorityMask)
{
CPUbasepriSet(ulPriorityMask);
}
//*****************************************************************************
//
//! Gets the priority masking level
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
unsigned long
IntPriorityMaskGet(void)
{
return(CPUbasepriGet());
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// interrupt.h
//
// Prototypes for the NVIC Interrupt Controller Driver.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
unsigned long ulPtr;
}
uVectorEntry;
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
// Interrupt priority levels
//*****************************************************************************
#define INT_PRIORITY_LVL_0 0x00
#define INT_PRIORITY_LVL_1 0x20
#define INT_PRIORITY_LVL_2 0x40
#define INT_PRIORITY_LVL_3 0x60
#define INT_PRIORITY_LVL_4 0x80
#define INT_PRIORITY_LVL_5 0xA0
#define INT_PRIORITY_LVL_6 0xC0
#define INT_PRIORITY_LVL_7 0xE0
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntVTableBaseSet(unsigned long ulVtableBase);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
extern void IntPendSet(unsigned long ulInterrupt);
extern void IntPendClear(unsigned long ulInterrupt);
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
extern unsigned long IntPriorityMaskGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

888
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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// pin.c
//
// Mapping of peripherals to pins.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup pin_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ocp_shared.h"
#include "pin.h"
//*****************************************************************************
// Macros
//*****************************************************************************
#define PAD_MODE_MASK 0x0000000F
#define PAD_STRENGTH_MASK 0x000000E0
#define PAD_TYPE_MASK 0x00000310
#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \
OCP_SHARED_O_GPIO_PAD_CONFIG_0))
//*****************************************************************************
// PIN to PAD matrix
//*****************************************************************************
static const unsigned long g_ulPinToPadMap[64] =
{
10,11,12,13,14,15,16,17,255,255,18,
19,20,21,22,23,24,40,28,29,25,255,
255,255,255,255,255,255,255,255,255,255,255,
255,255,255,255,255,255,255,255,255,255,255,
31,255,255,255,255,0,255,32,30,255,1,
255,2,3,4,5,6,7,8,9
};
//*****************************************************************************
//
//! Configures pin mux for the specified pin.
//!
//! \param ulPin is a valid pin.
//! \param ulPinMode is one of the valid mode
//!
//! This function configures the pin mux that selects the peripheral function
//! associated with a particular SOC pin. Only one peripheral function at a
//! time can be associated with a pin, and each peripheral function should
//! only be associated with a single pin at a time.
//!
//! \return none
//
//*****************************************************************************
void PinModeSet(unsigned long ulPin,unsigned long ulPinMode)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Set the mode.
//
HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10));
}
//*****************************************************************************
//
//! Gets current pin mux configuration of specified pin.
//!
//! \param ulPin is a valid pin.
//!
//! This function get the current configuration of the pin mux.
//!
//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise.
//
//*****************************************************************************
unsigned long PinModeGet(unsigned long ulPin)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ;
//
// return the mode.
//
return (HWREG(ulPad) & PAD_MODE_MASK);
}
//*****************************************************************************
//
//! Sets the direction of the specified pin(s).
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinIO is the pin direction and/or mode.
//!
//! This function configures the specified pin(s) as either input only or
//! output only or it configures the pin to be under hardware control.
//!
//! The parameter \e ulPinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b PIN_DIR_MODE_IN
//! - \b PIN_DIR_MODE_OUT
//! - \b PIN_DIR_MODE_HW
//!
//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a
//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is
//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is
//! placed under hardware control.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Set the direction
//
HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO);
}
//*****************************************************************************
//
//! Gets the direction of a pin.
//!
//! \param ulPin is one of the valid pin.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input only
//! or output only, or it can be under hardware control. The type of control
//! and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
unsigned long PinDirModeGet(unsigned long ulPin)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Return the direction
//
return ((HWREG(ulPad) & 0xC00));
}
//*****************************************************************************
//
//! Gets Pin output drive strength and Type
//!
//! \param ulPin is one of the valid pin
//! \param pulPinStrength is pointer to storage for output drive strength
//! \param pulPinType is pinter to storage for pin type
//!
//! This function gets the pin type and output drive strength for the pin
//! specified by \e ulPin parameter. Parameters \e pulPinStrength and
//! \e pulPinType corresponds to the values used in PinConfigSet().
//!
//!
//! \return None.
//
//*****************************************************************************
void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Get the type
//
*pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK);
//
// Get the output drive strength
//
*pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK);
}
//*****************************************************************************
//
//! Configure Pin output drive strength and Type
//!
//! \param ulPin is one of the valid pin
//! \param ulPinStrength is logical OR of valid output drive strengths.
//! \param ulPinType is one of the valid pin type.
//!
//! This function sets the pin type and strength for the pin specified by
//! \e ulPin parameter.
//!
//! The parameter \e ulPinStrength should be one of the following
//! - \b PIN_STRENGTH_2MA
//! - \b PIN_STRENGTH_4MA
//! - \b PIN_STRENGTH_6MA
//!
//!
//! The parameter \e ulPinType should be one of the following
//! For standard type
//!
//! - \b PIN_TYPE_STD
//! - \b PIN_TYPE_STD_PU
//! - \b PIN_TYPE_STD_PD
//!
//! And for Open drain type
//!
//! - \b PIN_TYPE_OD
//! - \b PIN_TYPE_OD_PU
//! - \b PIN_TYPE_OD_PD
//!
//! \return None.
//
//*****************************************************************************
void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
unsigned long ulPinType)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Write the register
//
if(ulPinType == PIN_TYPE_ANALOG)
{
//
// Isolate the input
//
HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8));
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Isolate the output
//
HWREG(ulPad) = 0xC00;
}
else
{
//
// Enable the input
//
HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8));
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Write the configuration
//
HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
(ulPinStrength | ulPinType ));
}
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by UART peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The UART pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin(s); other configurations may work as well depending upon the
//! board setup (for example, using the on-chip pull-ups).
//!
//!
//! \note This function cannot be used to turn any pin into a UART pin; it
//! only sets the pin mode and configures it for proper UART operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by I2C peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The I2C pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! the pin.
//!
//!
//! \note This function cannot be used to turn any pin into a I2C pin; it
//! only sets the pin mode and configures it for proper I2C operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for open-drain operation with a weak pull-up.
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by SPI peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The SPI pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a SPI pin; it
//! only sets the pin mode and configures it for proper SPI operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by I2S peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The I2S pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a I2S pin; it
//! only sets the pin mode and configures it for proper I2S operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by Timer peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The timer PWM pins must be properly configured for the Timer peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin; other configurations may work as well depending upon the
//! board setup (for example, using the on-chip pull-ups).
//!
//!
//! \note This function cannot be used to turn any pin into a timer PWM pin; it
//! only sets the pin mode and configures it for proper timer PWM operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by Camera peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The Camera pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a Camera pin; it
//! only sets the pin mode and configures it for proper Camera operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by GPIO peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//! \param bOpenDrain is one to decide either OpenDrain or STD
//!
//! The GPIO pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain)
{
//
// Set the pin for standard push-pull operation.
//
if(bOpenDrain)
{
PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD);
}
else
{
PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD);
}
//
// Set the pin to specified mode
//
PinModeSet(ulPin, ulPinMode);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by ADC
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The ADC pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a ADC pin; it
//! only sets the pin mode and configures it for proper ADC operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Configure the Pin
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by SD Host peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The MMC pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a SD Host pin; it
//! only sets the pin mode and configures it for proper SD Host operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set pin mode
//
PinModeSet(ulPin,ulPinMode);
//
// Configure the Pin
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the hysteresis for all the pins
//!
//! \param ulHysteresis is one of the valid predefined hysterisys values
//!
//! This function sets the hysteresis vlaue for all the pins. The parameter
//! \e ulHysteresis can be on one the following:
//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR
//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10%
//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20%
//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30%
//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40%
//!
//! \return None.
//
//*****************************************************************************
void PinHysteresisSet(unsigned long ulHysteresis)
{
unsigned long ulRegValue;
//
// Read the current value
//
ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG )
& ~(0x0000001C));
//
// Set the new Hysteresis
//
if( ulHysteresis != PIN_HYSTERESIS_OFF )
{
ulRegValue |= (ulHysteresis & 0x0000001C);
}
//
// Write the new value
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue;
}
//*****************************************************************************
//
//! Sets the level of the pin when locked
//!
//! \param ulPin is one of the valid pin.
//! \param ucLevel is the level the pin drives when locked
//!
//! This function sets the pin level when the pin is locked using
//! \sa PinLock() API.
//!
//! By default all pins are set to drive 0.
//!
//! \note Use case is to park the pins when entering LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel)
{
unsigned long ulPad;
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Get the required bit
//
ulPad = 1 << ulPad;
if(ucLevel)
{
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad;
}
else
{
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad;
}
}
}
//*****************************************************************************
//
//! Locks all the pins to configured level(s).
//!
//! \param ulOutEnable the bit-packed representation of pins to be set as output
//!
//! This function locks all the pins to the pre-configure level. By default
//! the pins are set to drive 0. Default level can be changed using
//! \sa PinLockLevelSet() API.
//!
//! The \e ulOutEnable paramter is bit-packed representation of pins that
//! are required to be enabled as output. If a bit is set 1, the corresponding
//! pin (as shown below) are set and locked as output.
//!
//! |------|-----------------------------------------------|
//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
//! |------|-----------------------------------------------|
//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07|
//! |------|-----------------------------------------------|
//!
//! |------|-----------------------------------------------|
//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
//! |------|-----------------------------------------------|
//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50|
//! |------|-----------------------------------------------|
//!
//!
//! \note Use case is to park the pins when entering LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinLock(unsigned long ulOutEnable)
{
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Enable/disable the pin(s) output
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable;
//
// Lock the pins to selected levels
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24);
}
}
//*****************************************************************************
//
//! Unlocks all the pins.
//!
//! This function unlocks all the pins and can be used for peripheral function.
//!
//! By default all the pins are in unlocked state.
//!
//! \note Use case is to un-park the pins when exiting LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinUnlock()
{
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Unlock the pins
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24);
}
}
//*****************************************************************************
//
// Gets pad number from pin number
//
// \param ulPin is a valid pin number
//
// This function return the pad corresponding to the specified pin
//
// \return Pad number on success, 0xFF otherwise
//
//*****************************************************************************
unsigned long PinToPadGet(unsigned long ulPin)
{
//
// Return the corresponding Pad
//
return g_ulPinToPadMap[ulPin & 0x3F];
}
//*****************************************************************************
//
// Gets pin number from pad number
//
// \param ulPad is a valid pad number
//
// This function return the pin corresponding to the specified pad
//
// \return Pin number on success, 0xFF otherwise
//
//*****************************************************************************
unsigned long PinFromPadGet(unsigned long ulPad)
{
unsigned long ulPin;
//
// search and return the pin number
//
for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++)
{
if(g_ulPinToPadMap[ulPin] == ulPad)
{
return ulPin;
}
}
return 0xFF;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// pin.h
//
// Defines and Macros for the pin mux module
//
//*****************************************************************************
#ifndef __PIN_H__
#define __PIN_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Macros Defining Pins
//*****************************************************************************
#define PIN_01 0x00000000
#define PIN_02 0x00000001
#define PIN_03 0x00000002
#define PIN_04 0x00000003
#define PIN_05 0x00000004
#define PIN_06 0x00000005
#define PIN_07 0x00000006
#define PIN_08 0x00000007
#define PIN_11 0x0000000A
#define PIN_12 0x0000000B
#define PIN_13 0x0000000C
#define PIN_14 0x0000000D
#define PIN_15 0x0000000E
#define PIN_16 0x0000000F
#define PIN_17 0x00000010
#define PIN_18 0x00000011
#define PIN_19 0x00000012
#define PIN_20 0x00000013
#define PIN_21 0x00000014
#define PIN_45 0x0000002C
#define PIN_46 0x0000002D
#define PIN_47 0x0000002E
#define PIN_48 0x0000002F
#define PIN_49 0x00000030
#define PIN_50 0x00000031
#define PIN_52 0x00000033
#define PIN_53 0x00000034
#define PIN_55 0x00000036
#define PIN_56 0x00000037
#define PIN_57 0x00000038
#define PIN_58 0x00000039
#define PIN_59 0x0000003A
#define PIN_60 0x0000003B
#define PIN_61 0x0000003C
#define PIN_62 0x0000003D
#define PIN_63 0x0000003E
#define PIN_64 0x0000003F
//*****************************************************************************
// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet()
//*****************************************************************************
#define PIN_MODE_0 0x00000000
#define PIN_MODE_1 0x00000001
#define PIN_MODE_2 0x00000002
#define PIN_MODE_3 0x00000003
#define PIN_MODE_4 0x00000004
#define PIN_MODE_5 0x00000005
#define PIN_MODE_6 0x00000006
#define PIN_MODE_7 0x00000007
#define PIN_MODE_8 0x00000008
#define PIN_MODE_9 0x00000009
#define PIN_MODE_10 0x0000000A
#define PIN_MODE_11 0x0000000B
#define PIN_MODE_12 0x0000000C
#define PIN_MODE_13 0x0000000D
#define PIN_MODE_14 0x0000000E
#define PIN_MODE_15 0x0000000F
// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation
// PIN_MODE_255 should never be used in any user code.
#define PIN_MODE_255 0x000000FF
//*****************************************************************************
// Macros that can be used with PinDirModeSet() and returned from
// PinDirModeGet().
//*****************************************************************************
#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input
#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output
#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function
//*****************************************************************************
// Macros that can be used with PinConfigSet()
//*****************************************************************************
#define PIN_STRENGTH_2MA 0x00000020
#define PIN_STRENGTH_4MA 0x00000040
#define PIN_STRENGTH_6MA 0x00000060
#define PIN_TYPE_STD 0x00000000
#define PIN_TYPE_STD_PU 0x00000100
#define PIN_TYPE_STD_PD 0x00000200
#define PIN_TYPE_OD 0x00000010
#define PIN_TYPE_OD_PU 0x00000110
#define PIN_TYPE_OD_PD 0x00000210
#define PIN_TYPE_ANALOG 0x10000000
//*****************************************************************************
// Macros that can be used with PinHysteresisSet()
//*****************************************************************************
#define PIN_HYSTERESIS_OFF 0x00000000
#define PIN_HYSTERESIS_10 0x00000004
#define PIN_HYSTERESIS_20 0x0000000C
#define PIN_HYSTERESIS_30 0x00000014
#define PIN_HYSTERESIS_40 0x0000001C
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode);
extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
extern unsigned long PinDirModeGet(unsigned long ulPin);
extern unsigned long PinModeGet(unsigned long ulPin);
extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType);
extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
unsigned long ulPinType);
extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,
tBoolean bOpenDrain);
extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode);
extern void PinHysteresisSet(unsigned long ulHysteresis);
extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel);
extern void PinLock(unsigned long ulOutEnable);
extern void PinUnlock(void);
extern unsigned long PinToPadGet(unsigned long ulPin);
extern unsigned long PinFromPadGet(unsigned long ulPad);
#ifdef __cplusplus
}
#endif
#endif //__PIN_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// prcm.h
//
// Prototypes for the PRCM control driver.
//
//*****************************************************************************
#ifndef __PRCM_H__
#define __PRCM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Peripheral clock and reset control registers
//
//*****************************************************************************
typedef struct _PRCM_PeripheralRegs_
{
unsigned long ulClkReg;
unsigned long ulRstReg;
}PRCM_PeriphRegs_t;
//*****************************************************************************
// Values that can be passed to PRCMPeripheralEnable() and
// PRCMPeripheralDisable()
//*****************************************************************************
#define PRCM_RUN_MODE_CLK 0x00000001
#define PRCM_SLP_MODE_CLK 0x00000100
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulSramColSel.
//*****************************************************************************
#define PRCM_SRAM_COL_1 0x00000001
#define PRCM_SRAM_COL_2 0x00000002
#define PRCM_SRAM_COL_3 0x00000004
#define PRCM_SRAM_COL_4 0x00000008
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulModeFlags.
//*****************************************************************************
#define PRCM_SRAM_LPDS_RET 0x00000002
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
//*****************************************************************************
#define PRCM_LPDS_HOST_IRQ 0x00000080
#define PRCM_LPDS_GPIO 0x00000010
#define PRCM_LPDS_TIMER 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
//*****************************************************************************
#define PRCM_LPDS_LOW_LEVEL 0x00000002
#define PRCM_LPDS_HIGH_LEVEL 0x00000000
#define PRCM_LPDS_FALL_EDGE 0x00000001
#define PRCM_LPDS_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_LPDS_GPIO2 0x00000000
#define PRCM_LPDS_GPIO4 0x00000001
#define PRCM_LPDS_GPIO13 0x00000002
#define PRCM_LPDS_GPIO17 0x00000003
#define PRCM_LPDS_GPIO11 0x00000004
#define PRCM_LPDS_GPIO24 0x00000005
#define PRCM_LPDS_GPIO26 0x00000006
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable().
//*****************************************************************************
#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
//*****************************************************************************
#define PRCM_HIB_LOW_LEVEL 0x00000000
#define PRCM_HIB_HIGH_LEVEL 0x00000001
#define PRCM_HIB_FALL_EDGE 0x00000002
#define PRCM_HIB_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_HIB_GPIO2 0x00010000
#define PRCM_HIB_GPIO4 0x00020000
#define PRCM_HIB_GPIO13 0x00040000
#define PRCM_HIB_GPIO17 0x00080000
#define PRCM_HIB_GPIO11 0x00100000
#define PRCM_HIB_GPIO24 0x00200000
#define PRCM_HIB_GPIO26 0x00400000
//*****************************************************************************
// Values that will be returned from PRCMSysResetCauseGet().
//*****************************************************************************
#define PRCM_POWER_ON 0x00000000
#define PRCM_LPDS_EXIT 0x00000001
#define PRCM_CORE_RESET 0x00000003
#define PRCM_MCU_RESET 0x00000004
#define PRCM_WDT_RESET 0x00000005
#define PRCM_SOC_RESET 0x00000006
#define PRCM_HIB_EXIT 0x00000007
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupCauseGet().
//*****************************************************************************
#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
//*****************************************************************************
// Values that can be passed to PRCMSEnableInterrupt
//*****************************************************************************
#define PRCM_INT_SLOW_CLK_CTR 0x00004000
//*****************************************************************************
// Values that can be passed to PRCMPeripheralClkEnable(),
// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
//*****************************************************************************
#define PRCM_CAMERA 0x00000000
#define PRCM_I2S 0x00000001
#define PRCM_SDHOST 0x00000002
#define PRCM_GSPI 0x00000003
#define PRCM_LSPI 0x00000004
#define PRCM_UDMA 0x00000005
#define PRCM_GPIOA0 0x00000006
#define PRCM_GPIOA1 0x00000007
#define PRCM_GPIOA2 0x00000008
#define PRCM_GPIOA3 0x00000009
#define PRCM_GPIOA4 0x0000000A
#define PRCM_WDT 0x0000000B
#define PRCM_UARTA0 0x0000000C
#define PRCM_UARTA1 0x0000000D
#define PRCM_TIMERA0 0x0000000E
#define PRCM_TIMERA1 0x0000000F
#define PRCM_TIMERA2 0x00000010
#define PRCM_TIMERA3 0x00000011
#define PRCM_DTHE 0x00000012
#define PRCM_SSPI 0x00000013
#define PRCM_I2CA0 0x00000014
// Note : PRCM_ADC is a dummy define for pinmux utility code generation
// PRCM_ADC should never be used in any user code.
#define PRCM_ADC 0x000000FF
//*****************************************************************************
// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable()
//*****************************************************************************
#define PRCM_IO_RET_GRP_0 0x00000001
#define PRCM_IO_RET_GRP_1 0x00000002
#define PRCM_IO_RET_GRP_2 0x00000004
#define PRCM_IO_RET_GRP_3 0x00000008
//*****************************************************************************
// Macros definig the device type
//*****************************************************************************
#define PRCM_DEV_TYPE_FLAG_R 0x00000001
#define PRCM_DEV_TYPE_FLAG_F 0x00000002
#define PRCM_DEV_TYPE_FLAG_Z 0x00000004
#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008
#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010
#define PRCM_DEV_TYPE_FLAG_3200 0x00000020
#define PRCM_DEV_TYPE_FLAG_3220 0x00000040
#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000
#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000
//*****************************************************************************
// Pre-defined helper macros
//*****************************************************************************
#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_F)
#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_Z)
#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F)
#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z)
#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_REV1)
#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_REV2)
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PRCMMCUReset(tBoolean bIncludeSubsystem);
extern unsigned long PRCMSysResetCauseGet(void);
extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral,
unsigned long ulClkFlags);
extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral,
unsigned long ulClkFlags);
extern void PRCMPeripheralReset(unsigned long ulPeripheral);
extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral);
extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq);
extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral);
extern void PRCMSleepEnter(void);
extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel,
unsigned long ulFlags);
extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel,
unsigned long ulFlags);
extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP,
unsigned long ulRestorePC);
extern void PRCMLPDSEnter(void);
extern void PRCMLPDSIntervalSet(unsigned long ulTicks);
extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc);
extern unsigned long PRCMLPDSWakeupCauseGet(void);
extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin,
unsigned long ulType);
extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc);
extern void PRCMHibernateEnter(void);
extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc);
extern unsigned long PRCMHibernateWakeupCauseGet(void);
extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap,
unsigned long ulType);
extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc);
extern void PRCMHibernateIntervalSet(unsigned long long ullTicks);
extern unsigned long long PRCMSlowClkCtrGet(void);
extern unsigned long long PRCMSlowClkCtrFastGet(void);
extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks);
extern unsigned long long PRCMSlowClkCtrMatchGet(void);
extern void PRCMOCRRegisterWrite(unsigned char ucIndex,
unsigned long ulRegValue);
extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex);
extern void PRCMIntRegister(void (*pfnHandler)(void));
extern void PRCMIntUnregister(void);
extern void PRCMIntEnable(unsigned long ulIntFlags);
extern void PRCMIntDisable(unsigned long ulIntFlags);
extern unsigned long PRCMIntStatus(void);
extern void PRCMRTCInUseSet(void);
extern tBoolean PRCMRTCInUseGet(void);
extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec);
extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec);
extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec);
extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
extern void PRCMCC3200MCUInit(void);
extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider,
unsigned char ulWidth);
extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags);
extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags);
extern unsigned long PRCMDeviceTypeGet(void);
extern void PRCMLPDSEnterKeepDebugIf(void);
extern void PRCMHibernateCycleTrigger(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PRCM_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM.
//
//
//*****************************************************************************
//
// List of API's in the ROM that need to be patched.
// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut
//*****************************************************************************
#ifndef __ROM_PATCH_H__
#define __ROM_PATCH_H__
#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API)
#undef ROM_ADCIntClear
#undef ROM_IntEnable
#undef ROM_IntDisable
#undef ROM_IntPendSet
#undef ROM_SDHostCardErrorMaskSet
#undef ROM_SDHostCardErrorMaskGet
#undef ROM_TimerConfigure
#undef ROM_TimerDMAEventSet
#undef ROM_TimerDMAEventGet
#undef ROM_SDHostDataNonBlockingWrite
#undef ROM_SDHostDataWrite
#undef ROM_SDHostDataRead
#undef ROM_SDHostDataNonBlockingRead
#undef ROM_PRCMSysResetCauseGet
#undef ROM_PRCMPeripheralClkEnable
#undef ROM_PRCMLPDSWakeUpGPIOSelect
#undef ROM_PRCMHibernateWakeupSourceEnable
#undef ROM_PRCMHibernateWakeupSourceDisable
#undef ROM_PRCMHibernateWakeupCauseGet
#undef ROM_PRCMHibernateIntervalSet
#undef ROM_PRCMHibernateWakeUpGPIOSelect
#undef ROM_PRCMHibernateEnter
#undef ROM_PRCMSlowClkCtrGet
#undef ROM_PRCMSlowClkCtrMatchSet
#undef ROM_PRCMSlowClkCtrMatchGet
#undef ROM_PRCMOCRRegisterWrite
#undef ROM_PRCMOCRRegisterRead
#undef ROM_PRCMIntEnable
#undef ROM_PRCMIntDisable
#undef ROM_PRCMRTCInUseSet
#undef ROM_PRCMRTCInUseGet
#undef ROM_PRCMRTCSet
#undef ROM_PRCMRTCGet
#undef ROM_PRCMRTCMatchSet
#undef ROM_PRCMRTCMatchGet
#undef ROM_PRCMPeripheralClkDisable
#undef ROM_PRCMPeripheralReset
#undef ROM_PRCMPeripheralStatusGet
#undef ROM_SPIConfigSetExpClk
#undef ROM_AESDataProcess
#undef ROM_DESDataProcess
#undef ROM_I2SEnable
#undef ROM_I2SConfigSetExpClk
#undef ROM_PinConfigSet
#undef ROM_PRCMLPDSEnter
#undef ROM_PRCMCC3200MCUInit
#undef ROM_SDHostIntStatus
#undef ROM_SDHostBlockCountSet
#undef ROM_UARTModemControlSet
#undef ROM_UARTModemControlClear
#undef ROM_CameraXClkSet
#undef ROM_PRCMMCUReset
#undef ROM_PRCMPeripheralClkEnable
#undef ROM_SPIDmaDisable
#endif
#if defined(USE_CC3220_ROM_DRV_API)
#undef ROM_PRCMDeviceTypeGet
#undef ROM_SDHostDataNonBlockingRead
#undef ROM_PRCMCC3200MCUInit
#endif
#endif // __ROM_PATCH_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// sdhost.h
//
// Defines and Macros for the SDHost.
//
//*****************************************************************************
#ifndef __SDHOST_H__
#define __SDHOST_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
//{
#endif
//*****************************************************************************
// Values that can be passed to SDHostRespGet().
//*****************************************************************************
#define SDHOST_RESP_10 0x00000003
#define SDHOST_RESP_32 0x00000002
#define SDHOST_RESP_54 0x00000001
#define SDHOST_RESP_76 0x00000000
//*****************************************************************************
// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(),
// SDHostIntClear() ,and returned from SDHostIntStatus().
//*****************************************************************************
#define SDHOST_INT_CC 0x00000001
#define SDHOST_INT_TC 0x00000002
#define SDHOST_INT_BWR 0x00000010
#define SDHOST_INT_BRR 0x00000020
#define SDHOST_INT_ERRI 0x00008000
#define SDHOST_INT_CTO 0x00010000
#define SDHOST_INT_CEB 0x00040000
#define SDHOST_INT_DTO 0x00100000
#define SDHOST_INT_DCRC 0x00200000
#define SDHOST_INT_DEB 0x00400000
#define SDHOST_INT_CERR 0x10000000
#define SDHOST_INT_BADA 0x20000000
#define SDHOST_INT_DMARD 0x40000000
#define SDHOST_INT_DMAWR 0x80000000
//*****************************************************************************
// Values that can be passed to SDHostCmdSend().
//*****************************************************************************
#define SDHOST_CMD_0 0x00000000
#define SDHOST_CMD_1 0x01000000
#define SDHOST_CMD_2 0x02000000
#define SDHOST_CMD_3 0x03000000
#define SDHOST_CMD_4 0x04000000
#define SDHOST_CMD_5 0x05000000
#define SDHOST_CMD_6 0x06000000
#define SDHOST_CMD_7 0x07000000
#define SDHOST_CMD_8 0x08000000
#define SDHOST_CMD_9 0x09000000
#define SDHOST_CMD_10 0x0A000000
#define SDHOST_CMD_11 0x0B000000
#define SDHOST_CMD_12 0x0C000000
#define SDHOST_CMD_13 0x0D000000
#define SDHOST_CMD_14 0x0E000000
#define SDHOST_CMD_15 0x0F000000
#define SDHOST_CMD_16 0x10000000
#define SDHOST_CMD_17 0x11000000
#define SDHOST_CMD_18 0x12000000
#define SDHOST_CMD_19 0x13000000
#define SDHOST_CMD_20 0x14000000
#define SDHOST_CMD_21 0x15000000
#define SDHOST_CMD_22 0x16000000
#define SDHOST_CMD_23 0x17000000
#define SDHOST_CMD_24 0x18000000
#define SDHOST_CMD_25 0x19000000
#define SDHOST_CMD_26 0x1A000000
#define SDHOST_CMD_27 0x1B000000
#define SDHOST_CMD_28 0x1C000000
#define SDHOST_CMD_29 0x1D000000
#define SDHOST_CMD_30 0x1E000000
#define SDHOST_CMD_31 0x1F000000
#define SDHOST_CMD_32 0x20000000
#define SDHOST_CMD_33 0x21000000
#define SDHOST_CMD_34 0x22000000
#define SDHOST_CMD_35 0x23000000
#define SDHOST_CMD_36 0x24000000
#define SDHOST_CMD_37 0x25000000
#define SDHOST_CMD_38 0x26000000
#define SDHOST_CMD_39 0x27000000
#define SDHOST_CMD_40 0x28000000
#define SDHOST_CMD_41 0x29000000
#define SDHOST_CMD_42 0x2A000000
#define SDHOST_CMD_43 0x2B000000
#define SDHOST_CMD_44 0x2C000000
#define SDHOST_CMD_45 0x2D000000
#define SDHOST_CMD_46 0x2E000000
#define SDHOST_CMD_47 0x2F000000
#define SDHOST_CMD_48 0x30000000
#define SDHOST_CMD_49 0x31000000
#define SDHOST_CMD_50 0x32000000
#define SDHOST_CMD_51 0x33000000
#define SDHOST_CMD_52 0x34000000
#define SDHOST_CMD_53 0x35000000
#define SDHOST_CMD_54 0x36000000
#define SDHOST_CMD_55 0x37000000
#define SDHOST_CMD_56 0x38000000
#define SDHOST_CMD_57 0x39000000
#define SDHOST_CMD_58 0x3A000000
#define SDHOST_CMD_59 0x3B000000
#define SDHOST_CMD_60 0x3C000000
#define SDHOST_CMD_61 0x3D000000
#define SDHOST_CMD_62 0x3E000000
#define SDHOST_CMD_63 0x3F000000
//*****************************************************************************
// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend().
//*****************************************************************************
#define SDHOST_MULTI_BLK 0x00000022
#define SDHOST_DMA_EN 0x00000001
#define SDHOST_WR_CMD 0x00200000
#define SDHOST_RD_CMD 0x00200010
#define SDHOST_RESP_LEN_136 0x00010000
#define SDHOST_RESP_LEN_48 0x00020000
#define SDHOST_RESP_LEN_48B 0x00030000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SDHostCmdReset(unsigned long ulBase);
extern void SDHostInit(unsigned long ulBase);
extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd,
unsigned ulArg);
extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void SDHostIntUnregister(unsigned long ulBase);
extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags);
extern unsigned long SDHostIntStatus(unsigned long ulBase);
extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostCardErrorMaskSet(unsigned long ulBase,
unsigned long ulErrMask);
extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase);
extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
unsigned long ulCardClk);
extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]);
extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize);
extern void SDHostBlockCountSet(unsigned long ulBase,
unsigned short ulBlkCount);
extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase,
unsigned long ulData);
extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase,
unsigned long *pulData);
extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData);
extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
//}
#endif
#endif // __SDHOST_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// shamd5.h
//
// Defines and Macros for the SHA/MD5.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SHAMD5_H__
#define __DRIVERLIB_SHAMD5_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the algorithm in use in the
// SHA/MD5 module.
//
//*****************************************************************************
#define SHAMD5_ALGO_MD5 0x00000018 // MD5
#define SHAMD5_ALGO_SHA1 0x0000001a // SHA-1
#define SHAMD5_ALGO_SHA224 0x0000001c // SHA-224
#define SHAMD5_ALGO_SHA256 0x0000001e // SHA-256
#define SHAMD5_ALGO_HMAC_MD5 0x00000000 // HMAC-MD5
#define SHAMD5_ALGO_HMAC_SHA1 0x00000002 // HMAC-SHA-1
#define SHAMD5_ALGO_HMAC_SHA224 0x00000004 // HMAC-SHA-224
#define SHAMD5_ALGO_HMAC_SHA256 0x00000006 // HMAC-SHA-256
//*****************************************************************************
//
// The following defines are used to represent the different interrupt sources
// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
// SHAMD5BlockOnIntStatus() functions.
//
//*****************************************************************************
#define SHAMD5_INT_CONTEXT_READY 0x00000008
#define SHAMD5_INT_PARTHASH_READY 0x00000004
#define SHAMD5_INT_INPUT_READY 0x00000002
#define SHAMD5_INT_OUTPUT_READY 0x00000001
#define SHAMD5_INT_DMA_CONTEXT_IN 0x00010000
#define SHAMD5_INT_DMA_DATA_IN 0x00020000
#define SHAMD5_INT_DMA_CONTEXT_OUT 0x00040000
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode);
extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5DMADisable(uint32_t ui32Base);
extern void SHAMD5DMAEnable(uint32_t ui32Base);
extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
uint8_t *pui8PPKey);
extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
extern void SHAMD5IntUnregister(uint32_t ui32Base);
extern void SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SHAMD5_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// spi.h
//
// Defines and Macros for the SPI.
//
//*****************************************************************************
#ifndef __SPI_H__
#define __SPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter
//*****************************************************************************
#define SPI_MODE_MASTER 0x00000000
#define SPI_MODE_SLAVE 0x00000004
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
//*****************************************************************************
#define SPI_SUB_MODE_0 0x00000000
#define SPI_SUB_MODE_1 0x00000001
#define SPI_SUB_MODE_2 0x00000002
#define SPI_SUB_MODE_3 0x00000003
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
//*****************************************************************************
#define SPI_SW_CTRL_CS 0x01000000
#define SPI_HW_CTRL_CS 0x00000000
#define SPI_3PIN_MODE 0x02000000
#define SPI_4PIN_MODE 0x00000000
#define SPI_TURBO_ON 0x00080000
#define SPI_TURBO_OFF 0x00000000
#define SPI_CS_ACTIVEHIGH 0x00000000
#define SPI_CS_ACTIVELOW 0x00000040
#define SPI_WL_8 0x00000380
#define SPI_WL_16 0x00000780
#define SPI_WL_32 0x00000F80
//*****************************************************************************
// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable()
//*****************************************************************************
#define SPI_TX_FIFO 0x08000000
#define SPI_RX_FIFO 0x10000000
//*****************************************************************************
// Values that can be passed to SPIDMAEnable() and SPIDMADisable()
//*****************************************************************************
#define SPI_RX_DMA 0x00008000
#define SPI_TX_DMA 0x00004000
//*****************************************************************************
// Values that can be passed to SPIIntEnable(), SPIIntDiasble(),
// SPIIntClear() or returned from SPIStatus()
//*****************************************************************************
#define SPI_INT_DMATX 0x20000000
#define SPI_INT_DMARX 0x10000000
#define SPI_INT_EOW 0x00020000
#define SPI_INT_WKS 0x00010000
#define SPI_INT_RX_OVRFLOW 0x00000008
#define SPI_INT_RX_FULL 0x00000004
#define SPI_INT_TX_UDRFLOW 0x00000002
#define SPI_INT_TX_EMPTY 0x00000001
//*****************************************************************************
// Values that can be passed to SPITransfer()
//*****************************************************************************
#define SPI_CS_ENABLE 0x00000001
#define SPI_CS_DISABLE 0x00000002
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SPIEnable(unsigned long ulBase);
extern void SPIDisable(unsigned long ulBase);
extern void SPIReset(unsigned long ulBase);
extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
unsigned long ulBitRate, unsigned long ulMode,
unsigned long ulSubMode, unsigned long ulConfig);
extern long SPIDataGetNonBlocking(unsigned long ulBase,
unsigned long * pulData);
extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SPIDataPutNonBlocking(unsigned long ulBase,
unsigned long ulData);
extern void SPIDataPut(unsigned long ulBase, unsigned long ulData);
extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount);
extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void SPIIntUnregister(unsigned long ulBase);
extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPICSEnable(unsigned long ulBase);
extern void SPICSDisable(unsigned long ulBase);
extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
unsigned char *ucDin, unsigned long ulSize,
unsigned long ulFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SPI_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.c
//
// Driver for the SysTick timer in NVIC.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This function starts the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function causes the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force the reload. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This function stops the SysTick counter. If an interrupt handler has been
//! registered, it is not called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This function registers the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function unregisters the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function enables the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler is not required to clear the SysTick
//! interrupt source because it is cleared automatically by the NVIC when the
//! interrupt handler is called.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function disables the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter and must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
//! the next clock after SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter, which is
//! a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.h
//
// Prototypes for the SysTick driver.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// timer.h
//
// Prototypes for the timer module
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
//*****************************************************************************
//
// Values that can be passed to TimerDMAEventSet() or returned from
// TimerDMAEventGet().
//
//*****************************************************************************
#define TIMER_DMA_MODEMATCH_B 0x00000800
#define TIMER_DMA_CAPEVENT_B 0x00000400
#define TIMER_DMA_CAPMATCH_B 0x00000200
#define TIMER_DMA_TIMEOUT_B 0x00000100
#define TIMER_DMA_MODEMATCH_A 0x00000010
#define TIMER_DMA_CAPEVENT_A 0x00000004
#define TIMER_DMA_CAPMATCH_A 0x00000002
#define TIMER_DMA_TIMEOUT_A 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent);
extern unsigned long TimerDMAEventGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// uart.h
//
// Defines and Macros for the UART.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask
#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask
#define UART_INT_EOT 0x800 // End of transfer interrupt Mask
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTModemControlSet()and UARTModemControlClear()
// or returned from UARTModemControlGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
//*****************************************************************************
//
// Values that can be returned from UARTModemStatusGet().
//
//*****************************************************************************
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// udma.h
//
// Prototypes and macros for the uDMA controller.
//
//*****************************************************************************
#ifndef __UDMA_H__
#define __UDMA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup uDMA_Micro_Direct_Memory_Access_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
// fields are used by the uDMA controller and normally it is not necessary for
// software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
//
// The ending source address of the data transfer.
//
volatile void *pvSrcEndAddr;
//
// The ending destination address of the data transfer.
//
volatile void *pvDstEndAddr;
//
// The channel control mode.
//
volatile unsigned long ulControl;
//
// An unused location.
//
volatile unsigned long ulSpare;
}
tDMAControlTable;
//*****************************************************************************
//
//! A helper macro for building scatter-gather task table entries.
//!
//! \param ulTransferCount is the count of items to transfer for this task.
//! \param ulItemSize is the bit size of the items to transfer for this task.
//! \param ulSrcIncrement is the bit size increment for source data.
//! \param pvSrcAddr is the starting address of the data to transfer.
//! \param ulDstIncrement is the bit size increment for destination data.
//! \param pvDstAddr is the starting address of the destination data.
//! \param ulArbSize is the arbitration size to use for the transfer task.
//! \param ulMode is the transfer mode for this task.
//!
//! This macro is intended to be used to help populate a table of uDMA tasks
//! for a scatter-gather transfer. This macro will calculate the values for
//! the fields of a task structure entry based on the input parameters.
//!
//! There are specific requirements for the values of each parameter. No
//! checking is done so it is up to the caller to ensure that correct values
//! are used for the parameters.
//!
//! The \e ulTransferCount parameter is the number of items that will be
//! transferred by this task. It must be in the range 1-1024.
//!
//! The \e ulItemSize parameter is the bit size of the transfer data. It must
//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
//!
//! The \e ulSrcIncrement parameter is the increment size for the source data.
//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
//!
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
//! data.
//!
//! The \e ulDstIncrement parameter is the increment size for the destination
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
//!
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
//! location where the data will be transferred.
//!
//! The \e ulArbSize parameter is the arbitration size for the transfer, and
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
//! powers of 2, from 1 to 1024.
//!
//! The \e ulMode parameter is the mode to use for this transfer task. It
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
//! that normally all tasks will be one of the scatter-gather modes while the
//! last task is a task list will be AUTO or BASIC.
//!
//! This macro is intended to be used to initialize individual entries of
//! a structure of tDMAControlTable type, like this:
//!
//! \verbatim
//! tDMAControlTable MyTaskList[] =
//! {
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
//! UDMA_SRC_INC_8, MySourceBuf,
//! UDMA_DST_INC_8, MyDestBuf,
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
//! uDMATaskStructEntry(Task2Count, ... ),
//! }
//! \endverbatim
//!
//! \return Nothing; this is not a function.
//
//*****************************************************************************
#define uDMATaskStructEntry(ulTransferCount, \
ulItemSize, \
ulSrcIncrement, \
pvSrcAddr, \
ulDstIncrement, \
pvDstAddr, \
ulArbSize, \
ulMode) \
{ \
(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
((ulSrcIncrement) >> 26)) - 1]))), \
(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
((ulDstIncrement) >> 30)) - 1]))), \
(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
(((ulTransferCount) - 1) << 4) | \
((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
//
//*****************************************************************************
#define UDMA_ATTR_USEBURST 0x00000001
#define UDMA_ATTR_ALTSELECT 0x00000002
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
#define UDMA_ATTR_REQMASK 0x00000008
#define UDMA_ATTR_ALL 0x0000000F
//*****************************************************************************
//
// DMA control modes that can be passed to uDMAModeSet() and returned
// uDMAModeGet().
//
//*****************************************************************************
#define UDMA_MODE_STOP 0x00000000
#define UDMA_MODE_BASIC 0x00000001
#define UDMA_MODE_AUTO 0x00000002
#define UDMA_MODE_PINGPONG 0x00000003
#define UDMA_MODE_MEM_SCATTER_GATHER \
0x00000004
#define UDMA_MODE_PER_SCATTER_GATHER \
0x00000006
#define UDMA_MODE_ALT_SELECT 0x00000001
//*****************************************************************************
//
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
// control structure should be used.
//
//*****************************************************************************
#define UDMA_PRI_SELECT 0x00000000
#define UDMA_ALT_SELECT 0x00000020
//*****************************************************************************
//
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
// uDMAIntUnregister().
//
//*****************************************************************************
#define UDMA_INT_SW INT_UDMA
#define UDMA_INT_ERR INT_UDMAERR
//*****************************************************************************
//*****************************************************************************
//
// Channel configuration values that can be passed to uDMAControlSet().
//
//*****************************************************************************
#define UDMA_DST_INC_8 0x00000000
#define UDMA_DST_INC_16 0x40000000
#define UDMA_DST_INC_32 0x80000000
#define UDMA_DST_INC_NONE 0xc0000000
#define UDMA_SRC_INC_8 0x00000000
#define UDMA_SRC_INC_16 0x04000000
#define UDMA_SRC_INC_32 0x08000000
#define UDMA_SRC_INC_NONE 0x0c000000
#define UDMA_SIZE_8 0x00000000
#define UDMA_SIZE_16 0x11000000
#define UDMA_SIZE_32 0x22000000
#define UDMA_ARB_1 0x00000000
#define UDMA_ARB_2 0x00004000
#define UDMA_ARB_4 0x00008000
#define UDMA_ARB_8 0x0000c000
#define UDMA_ARB_16 0x00010000
#define UDMA_ARB_32 0x00014000
#define UDMA_ARB_64 0x00018000
#define UDMA_ARB_128 0x0001c000
#define UDMA_ARB_256 0x00020000
#define UDMA_ARB_512 0x00024000
#define UDMA_ARB_1024 0x00028000
#define UDMA_NEXT_USEBURST 0x00000008
//*****************************************************************************
//
// Values that can be passed to uDMAChannelAssign() to select peripheral
// mapping for each channel. The channels named RESERVED may be assigned
// to a peripheral in future parts.
//
//*****************************************************************************
//
// Channel 0
//
#define UDMA_CH0_TIMERA0_A 0x00000000
#define UDMA_CH0_SHAMD5_CIN 0x00010000
#define UDMA_CH0_SW 0x00030000
//
// Channel 1
//
#define UDMA_CH1_TIMERA0_B 0x00000001
#define UDMA_CH1_SHAMD5_DIN 0x00010001
#define UDMA_CH1_SW 0x00030001
//
// Channel 2
//
#define UDMA_CH2_TIMERA1_A 0x00000002
#define UDMA_CH2_SHAMD5_COUT 0x00010002
#define UDMA_CH2_SW 0x00030002
//
// Channel 3
//
#define UDMA_CH3_TIMERA1_B 0x00000003
#define UDMA_CH3_DES_CIN 0x00010003
#define UDMA_CH3_SW 0x00030003
//
// Channel 4
//
#define UDMA_CH4_TIMERA2_A 0x00000004
#define UDMA_CH4_DES_DIN 0x00010004
#define UDMA_CH4_I2S_RX 0x00020004
#define UDMA_CH4_SW 0x00030004
//
// Channel 5
//
#define UDMA_CH5_TIMERA2_B 0x00000005
#define UDMA_CH5_DES_DOUT 0x00010005
#define UDMA_CH5_I2S_TX 0x00020005
#define UDMA_CH5_SW 0x00030005
//
// Channel 6
//
#define UDMA_CH6_TIMERA3_A 0x00000006
#define UDMA_CH6_GSPI_RX 0x00010006
#define UDMA_CH6_GPIOA2 0x00020006
#define UDMA_CH6_SW 0x00030006
//
// Channel 7
//
#define UDMA_CH7_TIMERA3_B 0x00000007
#define UDMA_CH7_GSPI_TX 0x00010007
#define UDMA_CH7_GPIOA3 0x00020007
#define UDMA_CH7_SW 0x00030007
//
// Channel 8
//
#define UDMA_CH8_UARTA0_RX 0x00000008
#define UDMA_CH8_TIMERA0_A 0x00010008
#define UDMA_CH8_TIMERA2_A 0x00020008
#define UDMA_CH8_SW 0x00030008
//
// Channel 9
//
#define UDMA_CH9_UARTA0_TX 0x00000009
#define UDMA_CH9_TIMERA0_B 0x00010009
#define UDMA_CH9_TIMERA2_B 0x00020009
#define UDMA_CH9_SW 0x00030009
//
// Channel 10
//
#define UDMA_CH10_UARTA1_RX 0x0000000A
#define UDMA_CH10_TIMERA1_A 0x0001000A
#define UDMA_CH10_TIMERA3_A 0x0002000A
#define UDMA_CH10_SW 0x0003000A
//
// Channel 11
//
#define UDMA_CH11_UARTA1_TX 0x0000000B
#define UDMA_CH11_TIMERA1_B 0x0001000B
#define UDMA_CH11_TIMERA3_B 0x0002000B
#define UDMA_CH11_SW 0x0003000B
//
// Channel 12
//
#define UDMA_CH12_LSPI_RX 0x0000000C
#define UDMA_CH12_SW 0x0003000C
//
// Channel 13
//
#define UDMA_CH13_LSPI_TX 0x0000000D
#define UDMA_CH13_SW 0x0003000D
//
// Channel 14
//
#define UDMA_CH14_ADC_CH0 0x0000000E
#define UDMA_CH14_SDHOST_RX 0x0002000E
#define UDMA_CH14_SW 0x0003000E
//
// Channel 15
//
#define UDMA_CH15_ADC_CH1 0x0000000F
#define UDMA_CH15_SDHOST_TX 0x0002000F
#define UDMA_CH15_SW 0x0003000F
//
// Channel 16
//
#define UDMA_CH16_ADC_CH2 0x00000010
#define UDMA_CH16_TIMERA2_A 0x00010010
#define UDMA_CH16_SW 0x00030010
//
// Channel 17
//
#define UDMA_CH17_ADC_CH3 0x00000011
#define UDMA_CH17_TIMERA2_B 0x00010011
#define UDMA_CH17_SW 0x00030011
//
// Channel 18
//
#define UDMA_CH18_GPIOA0 0x00000012
#define UDMA_CH18_AES_CIN 0x00010012
#define UDMA_CH18_I2S_RX 0x00020012
#define UDMA_CH18_SW 0x00030012
//
// Channel 19
//
#define UDMA_CH19_GPOIA1 0x00000013
#define UDMA_CH19_AES_COUT 0x00010013
#define UDMA_CH19_I2S_TX 0x00020013
#define UDMA_CH19_SW 0x00030013
//
// Channel 20
//
#define UDMA_CH20_GPIOA2 0x00000014
#define UDMA_CH20_AES_DIN 0x00010014
#define UDMA_CH20_SW 0x00030014
//
// Channel 21
//
#define UDMA_CH21_GPIOA3 0x00000015
#define UDMA_CH21_AES_DOUT 0x00010015
#define UDMA_CH21_SW 0x00030015
//
// Channel 22
//
#define UDMA_CH22_CAMERA 0x00000016
#define UDMA_CH22_GPIOA4 0x00010016
#define UDMA_CH22_SW 0x00030016
//
// Channel 23
//
#define UDMA_CH23_SDHOST_RX 0x00000017
#define UDMA_CH23_TIMERA3_A 0x00010017
#define UDMA_CH23_TIMERA2_A 0x00020017
#define UDMA_CH23_SW 0x00030017
//
// Channel 24
//
#define UDMA_CH24_SDHOST_TX 0x00000018
#define UDMA_CH24_TIMERA3_B 0x00010018
#define UDMA_CH24_TIMERA2_B 0x00020018
#define UDMA_CH24_SW 0x00030018
//
// Channel 25
//
#define UDMA_CH25_SSPI_RX 0x00000019
#define UDMA_CH25_I2CA0_RX 0x00010019
#define UDMA_CH25_SW 0x00030019
//
// Channel 26
//
#define UDMA_CH26_SSPI_TX 0x0000001A
#define UDMA_CH26_I2CA0_TX 0x0001001A
#define UDMA_CH26_SW 0x0003001A
//
// Channel 27
//
#define UDMA_CH27_GPIOA0 0x0001001B
#define UDMA_CH27_SW 0x0003001B
//
// Channel 28
//
#define UDMA_CH28_GPIOA1 0x0001001C
#define UDMA_CH28_SW 0x0003001C
//
// Channel 29
//
#define UDMA_CH29_GPIOA4 0x0000001D
#define UDMA_CH29_SW 0x0003001D
//
// Channel 30
//
#define UDMA_CH30_GSPI_RX 0x0000001E
#define UDMA_CH30_SDHOST_RX 0x0001001E
#define UDMA_CH30_I2CA0_RX 0x0002001E
#define UDMA_CH30_SW 0x0003001E
//
// Channel 31
//
#define UDMA_CH31_GSPI_TX 0x0000001F
#define UDMA_CH31_SDHOST_TX 0x0001001F
#define UDMA_CH31_I2CA0_RX 0x0002001F
#define UDMA_CH31_SW 0x0003001F
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannelNum);
extern void uDMAChannelDisable(unsigned long ulChannelNum);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void *uDMAControlAlternateBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannelNum);
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
unsigned ulTaskCount, void *pvTaskList,
unsigned long ulIsPeriphSG);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
extern void uDMAChannelAssign(unsigned long ulMapping);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UDMA_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// utils.c
//
// Utility APIs
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup Utils_api
//! @{
//
//*****************************************************************************
#include "utils.h"
//*****************************************************************************
//
//! Provides a small delay.
//!
//! \param ulCount is the number of delay loop iterations to perform.
//!
//! This function provides a means of generating a constant length delay. It
//! is written in assembly to keep the delay consistent across tool chains,
//! avoiding the need to tune the delay based on the tool chain in use.
//!
//! The loop takes 3 cycles/loop.
//!
//! \return None.
//
//*****************************************************************************
#if defined(ewarm) || defined(DOXYGEN)
void
UtilsDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne.n UtilsDelay\n");
}
#endif
#if defined(gcc)
void __attribute__((naked))
UtilsDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne UtilsDelay\n"
" bx lr");
}
#endif
//
// For CCS implement this function in pure assembly. This prevents the TI
// compiler from doing funny things with the optimizer.
//
#if defined(ccs)
__asm(" .sect \".text:UtilsDelay\"\n"
" .clink\n"
" .thumbfunc UtilsDelay\n"
" .thumb\n"
" .global UtilsDelay\n"
"UtilsDelay:\n"
" subs r0, #1\n"
" bne.n UtilsDelay\n"
" bx lr\n");
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// utils.h
//
// Prototypes and macros for utility APIs
//
//*****************************************************************************
#ifndef __UTILS_H__
#define __UTILS_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UtilsDelay(unsigned long ulCount);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__UTILS_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// version.h
//
// Contains Driverlib version details
//
//*****************************************************************************
#ifndef __DRIVERLIB_VERSION_H__
#define __DRIVERLIB_VERSION_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#define DRIVERLIB_MAJOR_VERSION_NUM 1
#define DRIVERLIB_MINOR_VERSION_NUM 50
#define DRIVERLIB_PATCH_VERSION_NUM 3_1
#define DRIVERLIB_BUILD_VERSION_NUM 00
#define DRIVERLIB_RELEASE_DAY 30
#define DRIVERLIB_RELEASE_MONTH 3
#define DRIVERLIB_RELEASE_YEAR 2016
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_VERSION_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// wdt.h - Prototypes for the Watchdog Timer API
//
//
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

231
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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
//*****************************************************************************
#ifndef __ASMDEFS_H__
#define __ASMDEFS_H__
//*****************************************************************************
//
// The defines required for code_red.
//
//*****************************************************************************
#ifdef codered
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // codered
//*****************************************************************************
//
// The defines required for EW-ARM.
//
//*****************************************************************************
#ifdef ewarm
//
// Section headers.
//
#define __LIBRARY__ module
#define __TEXT__ rseg CODE:CODE(2)
#define __DATA__ rseg DATA:DATA(2)
#define __BSS__ rseg DATA:DATA(2)
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
//
// Assembler nmenonics.
//
#define __ALIGN__ alignrom 2
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__ thumb
#define __WORD__ dcd
#define __INLINE_DATA__ data
#endif // ewarm
//*****************************************************************************
//
// The defines required for GCC.
//
//*****************************************************************************
#if defined(gcc)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // gcc
//*****************************************************************************
//
// The defines required for RV-MDK.
//
//*****************************************************************************
#ifdef rvmdk
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
thumb
require8
preserve8
//
// Section headers.
//
#define __LIBRARY__ ;
#define __TEXT__ area ||.text||, code, readonly, align=2
#define __DATA__ area ||.data||, data, align=2
#define __BSS__ area ||.bss||, noinit, align=2
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
//
// Assembler nmenonics.
//
#define __ALIGN__ align 4
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__
#define __WORD__ dcd
#define __INLINE_DATA__
#endif // rvmdk
//*****************************************************************************
//
// The defines required for Sourcery G++.
//
//*****************************************************************************
#if defined(sourcerygxx)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // sourcerygxx
#endif // __ASMDEF_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following are defines for the ADC register offsets.
//
//*****************************************************************************
#define ADC_O_ADC_CTRL 0x00000000 // ADC control register.
#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting
#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting
#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting
#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting
#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting
#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting
#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting
#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting
#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable
// register
#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable
// register
#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable
// register
#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable
// register
#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable
// register
#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable
// register
#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable
// register
#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable
// register
#define ADC_O_adc_ch0_irq_status \
0x00000044 // Channel 0 interrupt status
// register
#define ADC_O_adc_ch1_irq_status \
0x00000048 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_irq_status \
0x0000004C
#define ADC_O_adc_ch3_irq_status \
0x00000050 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_irq_status \
0x00000054 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_irq_status \
0x00000058
#define ADC_O_adc_ch6_irq_status \
0x0000005C // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_irq_status \
0x00000060 // Channel 7 interrupt status
// register
#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register
#define ADC_O_adc_timer_configuration \
0x00000068 // ADC timer configuration register
#define ADC_O_adc_timer_current_count \
0x00000070 // ADC timer current count register
#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register
#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register
#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register
#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register
#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register
#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register
#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register
#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register
#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register
#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_fifo_lvl 0x0000009C
#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_fifo_lvl 0x000000A8
#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status
// register
#define ADC_O_ADC_CH_ENABLE 0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
//
//******************************************************************************
#define ADC_ADC_CTRL_adc_cap_scale \
0x00000020 // ADC CAP SCALE.
#define ADC_ADC_CTRL_adc_buf_bypass \
0x00000010 // ADC ANA CIO buffer bypass.
// Signal is modelled in ANA TOP.
// When '1': ADC buffer is bypassed.
#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1:
// ADC buffer is enabled.
#define ADC_ADC_CTRL_adc_core_en \
0x00000004 // ANA ADC core en. This signal act
// as glbal enable to ADC CIO. When
// 1: ADC core is enabled.
#define ADC_ADC_CTRL_adc_soft_reset \
0x00000002 // ADC soft reset. When '1' : reset
// ADC internal logic.
#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC
// module is enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_gain register.
//
//******************************************************************************
#define ADC_adc_ch0_gain_adc_channel0_gain_M \
0x00000003 // gain setting for ADC channel 0.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_gain register.
//
//******************************************************************************
#define ADC_adc_ch1_gain_adc_channel1_gain_M \
0x00000003 // gain setting for ADC channel 1.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_gain register.
//
//******************************************************************************
#define ADC_adc_ch2_gain_adc_channel2_gain_M \
0x00000003 // gain setting for ADC channel 2.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_gain register.
//
//******************************************************************************
#define ADC_adc_ch3_gain_adc_channel3_gain_M \
0x00000003 // gain setting for ADC channel 3.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_gain register.
//
//******************************************************************************
#define ADC_adc_ch4_gain_adc_channel4_gain_M \
0x00000003 // gain setting for ADC channel 4
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_gain register.
//
//******************************************************************************
#define ADC_adc_ch5_gain_adc_channel5_gain_M \
0x00000003 // gain setting for ADC channel 5.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_gain register.
//
//******************************************************************************
#define ADC_adc_ch6_gain_adc_channel6_gain_M \
0x00000003 // gain setting for ADC channel 6
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_gain register.
//
//******************************************************************************
#define ADC_adc_ch7_gain_adc_channel7_gain_M \
0x00000003 // gain setting for ADC channel 7.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_dma_mode_en register.
//
//******************************************************************************
#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
0x000000FF // this register enable DMA mode.
// when '1' respective ADC channel
// is enabled for DMA. When '0' only
// interrupt mode is enabled. Bit 0:
// channel 0 DMA mode enable. Bit 1:
// channel 1 DMA mode enable. Bit 2:
// channel 2 DMA mode enable. Bit 3:
// channel 3 DMA mode enable. bit 4:
// channel 4 DMA mode enable. bit 5:
// channel 5 DMA mode enable. bit 6:
// channel 6 DMA mode enable. bit 7:
// channel 7 DMA mode enable.
#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_configuration register.
//
//******************************************************************************
#define ADC_adc_timer_configuration_timeren \
0x02000000 // when '1' timer is enabled.
#define ADC_adc_timer_configuration_timerreset \
0x01000000 // when '1' reset timer.
#define ADC_adc_timer_configuration_timercount_M \
0x00FFFFFF // Timer count configuration. 17
// bit counter is supported. Other
// MSB's are redundent.
#define ADC_adc_timer_configuration_timercount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_current_count register.
//
//******************************************************************************
#define ADC_adc_timer_current_count_timercurrentcount_M \
0x0001FFFF // Timer count configuration
#define ADC_adc_timer_current_count_timercurrentcount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel0FIFODATA register.
//
//******************************************************************************
#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel1FIFODATA register.
//
//******************************************************************************
#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel2FIFODATA register.
//
//******************************************************************************
#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel3FIFODATA register.
//
//******************************************************************************
#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel4FIFODATA register.
//
//******************************************************************************
#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel5FIFODATA register.
//
//******************************************************************************
#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel6FIFODATA register.
//
//******************************************************************************
#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel7FIFODATA register.
//
//******************************************************************************
#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
#endif // __HW_ADC_H__

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@ -0,0 +1,804 @@
/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_AES_H__
#define __HW_AES_H__
//*****************************************************************************
//
// The following are defines for the AES_P register offsets.
//
//*****************************************************************************
#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third
// key
#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit
// key) / CBC-MAC third key (MSW)
#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC
// third key (LSW)
#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit
// key) / CBC-MAC third key
#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit
// key) + CCM/CBC-MAC second key
// (MSW) / Hash Key input (MSW)
#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key
// (LSW) / Hash Key input (LSW)
#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key)
#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key)
#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key)
#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key)
#define AES_O_KEY1_2 0x00000030 // Key
#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key)
#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key)
#define AES_O_KEY1_1 0x0000003C // Key
#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input
// (LSW)
#define AES_O_IV_IN_1 0x00000044 // Initialization vector input
#define AES_O_IV_IN_2 0x00000048 // Initialization vector input
#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input
// (MSW)
#define AES_O_CTRL 0x00000050 // register determines the mode of
// operation of the AES Engine
#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The
// authentication length register
// store the authentication data
// length in bytes for combined
// modes only (GCM or CCM) Supported
// AAD-lengths for CCM are from 0 to
// (2^16 - 2^8) bytes. For GCM any
// value up to (2^32 - 1) bytes can
// be used. Once processing with
// this context is started@@ this
// length decrements to zero. A
// write to this register triggers
// the engine to start using this
// context for GCM and CCM. For XTS
// this register is optionally used
// to load ‘j’. Loading of ‘j’ is
// only required if ‘j’ != 0. ‘j’ is
// a 28-bit value and must be
// written to bits [31-4] of this
// register. ‘j’ represents the
// sequential number of the 128-bit
// block inside the data unit. For
// the first block in a unit@@ this
// value is zero. It is not required
// to provide a ‘j’ for each new
// data block within a unit. Note
// that it is possible to start with
// a ‘j’ unequal to zero; refer to
// Table 4 for more details. For a
// Host read operation@@ these
// registers return all-zeroes.
#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write
// plaintext/ciphertext (MSW)
#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write
// plaintext/ciphertext (LSW)
#define AES_O_TAG_OUT_0 0x00000070
#define AES_O_TAG_OUT_1 0x00000074
#define AES_O_TAG_OUT_2 0x00000078
#define AES_O_TAG_OUT_3 0x0000007C
#define AES_O_REVISION 0x00000080 // Register AES_REVISION
#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This
// register configures the DMA
// signals and controls the IDLE and
// reset logic
#define AES_O_SYSSTATUS 0x00000088
#define AES_O_IRQSTATUS 0x0000008C // This register indicates the
// interrupt status. If one of the
// interrupt bits is set the
// interrupt output will be asserted
#define AES_O_IRQENABLE 0x00000090 // This register contains an enable
// bit for each unique interrupt
// generated by the module. It
// matches the layout of
// AES_IRQSTATUS register. An
// interrupt is enabled when the bit
// in this register is set to ‘1’.
// An interrupt that is enabled is
// propagated to the SINTREQUEST_x
// output. All interrupts need to be
// enabled explicitly by writing
// this register.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_6 register.
//
//******************************************************************************
#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_7 register.
//
//******************************************************************************
#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_4 register.
//
//******************************************************************************
#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_5 register.
//
//******************************************************************************
#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_2 register.
//
//******************************************************************************
#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_3 register.
//
//******************************************************************************
#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_0 register.
//
//******************************************************************************
#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_1 register.
//
//******************************************************************************
#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_6 register.
//
//******************************************************************************
#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_7 register.
//
//******************************************************************************
#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_4 register.
//
//******************************************************************************
#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_5 register.
//
//******************************************************************************
#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_2 register.
//
//******************************************************************************
#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_3 register.
//
//******************************************************************************
#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_0 register.
//
//******************************************************************************
#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_1 register.
//
//******************************************************************************
#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
//
//******************************************************************************
#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
//
//******************************************************************************
#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
//
//******************************************************************************
#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
//
//******************************************************************************
#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_CTRL register.
//
//******************************************************************************
#define AES_CTRL_CONTEXT_READY \
0x80000000 // If ‘1’@@ this read-only status
// bit indicates that the context
// data registers can be overwritten
// and the host is permitted to
// write the next context.
#define AES_CTRL_SVCTXTRDY \
0x40000000 // If ‘1’@@ this read-only status
// bit indicates that an AES
// authentication TAG and/or IV
// block(s) is/are available for the
// host to retrieve. This bit is
// only asserted if the
// ‘save_context’ bit is set to ‘1’.
// The bit is mutual exclusive with
// the ‘context_ready’ bit.
#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate
// that an authentication TAG or
// result IV needs to be stored as a
// result context. If this bit is
// set@@ context output DMA and/or
// interrupt will be asserted if the
// operation is finished and related
// signals are enabled.
#define AES_CTRL_CCM_M 0x01C00000 // Defines “M� that indicated the
// length of the authentication
// field for CCM operations; the
// authentication field length
// equals two times (the value of
// CCM-M plus one). Note that the
// AES Engine always returns a
// 128-bit authentication field@@ of
// which the M least significant
// bytes are valid. All values are
// supported.
#define AES_CTRL_CCM_S 22
#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L� that indicated the
// width of the length field for CCM
// operations; the length field in
// bytes equals the value of CMM-L
// plus one. Supported values for L
// are (programmed value): 2 (1)@@ 4
// (3) and 8 (7).
#define AES_CTRL_CCM_L_S 19
#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a
// combined mode@@ using AES for
// both authentication and
// encryption. No additional mode
// selection is required. 0 Other
// mode selected 1 ccm mode selected
#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is
// a combined mode@@ using the
// Galois field multiplier GF(2^128)
// for authentication and AES-CTR
// mode for encryption@@ the bits
// specify the GCM mode. 0x0 No
// operation 0x1 GHASH with H loaded
// and Y0-encrypted forced to zero
// 0x2 GHASH with H loaded and
// Y0-encrypted calculated
// internally 0x3 Autonomous GHASH
// (both H and Y0-encrypted
// calculated internally)
#define AES_CTRL_GCM_S 16
#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the
// Direction bit must be set to ‘1’
// for this mode. 0 Other mode
// selected 1 cbcmac mode selected
#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f9 selected
#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f8 selected
#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected;
// the bits specify the XTS mode.01
// = Previous/intermediate tweak
// value and ‘j’ loaded (value is
// loaded via IV@@ j is loaded via
// the AAD length register) 0x0 No
// operation 0x1
// Previous/intermediate tweak value
// and ‘j’ loaded (value is loaded
// via IV@@ j is loaded via the AAD
// length register) 0x2 Key2@@ i and
// j loaded (i is loaded via IV@@ j
// is loaded via the AAD length
// register) 0x3 Key2 and i loaded@@
// j=0 (i is loaded via IV)
#define AES_CTRL_XTS_S 11
#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback
// mode (CFB128) is selected. 0
// other mode selected 1 cfb
// selected
#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM)
// is selected@@ this is a counter
// mode with a 16-bit wide counter.
// 0 Other mode selected. 1 ICM mode
// selected
#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for
// AES-CTR mode 0x0 Counter is 32
// bits 0x1 Counter is 64 bits 0x2
// Counter is 128 bits 0x3 Counter
// is 192 bits
#define AES_CTRL_CTR_WIDTH_S 7
#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for
// GCM and CCM@@ when
// encryption/decryption is
// required. 0 Other mode selected 1
// Counter mode
#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc
// mode
#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is
// 128 bits. 0x2 Key is 192 bits 0x3
// Key is 256
#define AES_CTRL_KEY_SIZE_S 3
#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt
// operation is performed. If set to
// ‘0’ a decrypt operation is
// performed. Read 0 decryption is
// selected Read 1 Encryption is
// selected
#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status
// bit indicates that the 16-byte
// input buffer is empty@@ and the
// host is permitted to write the
// next block of data.
#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status
// bit indicates that an AES output
// block is available for the host
// to retrieve.
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_1 register.
//
//******************************************************************************
#define AES_C_LENGTH_1_LENGTH_M \
0x1FFFFFFF // Data length (MSW) length
// registers (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_C_LENGTH_1_LENGTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_AUTH_LENGTH register.
//
//******************************************************************************
#define AES_AUTH_LENGTH_AUTH_M \
0xFFFFFFFF // data
#define AES_AUTH_LENGTH_AUTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
//
//******************************************************************************
#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
//
//******************************************************************************
#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
//
//******************************************************************************
#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
//
//******************************************************************************
#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
//
//******************************************************************************
#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_0_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
//
//******************************************************************************
#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_1_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
//
//******************************************************************************
#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_2_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
//
//******************************************************************************
#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW)
#define AES_TAG_OUT_3_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_REVISION register.
//
//******************************************************************************
#define AES_REVISION_SCHEME_M 0xC0000000
#define AES_REVISION_SCHEME_S 30
#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
// compatible module family. If
// there is no level of software
// compatibility a new Func number
// (and hence REVISION) should be
// assigned.
#define AES_REVISION_FUNC_S 16
#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by
// IP design owner. RTL follows a
// numbering such as X.Y.R.Z which
// are explained in this table. R
// changes ONLY when: (1) PDS
// uploads occur which may have been
// due to spec changes (2) Bug fixes
// occur (3) Resets to '0' when X or
// Y changes. Design team has an
// internal 'Z' (customer invisible)
// number which increments on every
// drop that happens due to DV and
// RTL updates. Z resets to 0 when R
// increments.
#define AES_REVISION_R_RTL_S 11
#define AES_REVISION_X_MAJOR_M \
0x00000700 // Major Revision (X)@@ maintained
// by IP specification owner. X
// changes ONLY when: (1) There is a
// major feature addition. An
// example would be adding Master
// Mode to Utopia Level2. The Func
// field (or Class/Type in old PID
// format) will remain the same. X
// does NOT change due to: (1) Bug
// fixes (2) Change in feature
// parameters.
#define AES_REVISION_X_MAJOR_S 8
#define AES_REVISION_CUSTOM_M 0x000000C0
#define AES_REVISION_CUSTOM_S 6
#define AES_REVISION_Y_MINOR_M \
0x0000003F // Minor Revision (Y)@@ maintained
// by IP specification owner. Y
// changes ONLY when: (1) Features
// are scaled (up or down).
// Flexibility exists in that this
// feature scalability may either be
// represented in the Y change or a
// specific register in the IP that
// indicates which features are
// exactly available. (2) When
// feature creeps from Is-Not list
// to Is list. But this may not be
// the case once it sees silicon; in
// which case X will change. Y does
// NOT change due to: (1) Bug fixes
// (2) Typos or clarifications (3)
// major functional/feature
// change/addition/deletion. Instead
// these changes may be reflected
// via R@@ S@@ X as applicable. Spec
// owner maintains a
// customer-invisible number 'S'
// which changes due to: (1)
// Typos/clarifications (2) Bug
// documentation. Note that this bug
// is not due to a spec change but
// due to implementation.
// Nevertheless@@ the spec tracks
// the IP bugs. An RTL release (say
// for silicon PG1.1) that occurs
// due to bug fix should document
// the corresponding spec number
// (X.Y.S) in its release notes.
#define AES_REVISION_Y_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
//
//******************************************************************************
#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
0x00000200 // If set to '1' the two context
// out requests
// (dma_req_context_out_en@@ Bit [8]
// above@@ and context_out interrupt
// enable@@ Bit [3] of AES_IRQENABLE
// register) are mapped on the
// corresponding data output request
// bit. In this case@@ the original
// ‘context out’ bit values are
// ignored.
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
0x00000100 // If set to ‘1’@@ the DMA context
// output request is enabled (for
// context data out@@ e.g. TAG for
// authentication modes). 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // If set to ‘1’@@ the DMA context
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // If set to ‘1’@@ the DMA output
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // If set to ‘1’@@ the DMA input
// request is enabled. 0 Dma
// disabled 1 Dma enabled
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
//
//******************************************************************************
#define AES_SYSSTATUS_RESETDONE \
0x00000001
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
//
//******************************************************************************
#define AES_IRQSTATUS_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQSTATUS_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQENABLE register.
//
//******************************************************************************
#define AES_IRQENABLE_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQENABLE_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
#endif // __HW_AES_H__

749
FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_apps_config.h Normal file
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@ -0,0 +1,749 @@
/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_APPS_CONFIG_H__
#define __HW_APPS_CONFIG_H__
//*****************************************************************************
//
// The following are defines for the APPS_CONFIG register offsets.
//
//*****************************************************************************
#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
0x00000000 // Patch trap address Register
// array
#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
0x00000078
#define APPS_CONFIG_O_FAULT_STATUS_REG \
0x0000007C
#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
0x00000080
#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
0x00000084
#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
0x0000008C
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
0x00000090
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
0x00000094
#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
0x00000098
#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
0x0000009C
#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
0x000000A0
#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
0x000000A4
#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
0x000000A8
#define APPS_CONFIG_O_RESERVD_REG_0 \
0x000000AC
#define APPS_CONFIG_O_GPT_TRIG_SEL \
0x000000B0
#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
0x000000B4
#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address
// PATCH_TRAP_ADDR_REG[n][31:0] from
// Idcode bus. The exception routine
// should take care to jump to the
// location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address PATCH_TRAP_ADD[n][31:0]
// from Idcode bus. The exception
// routine should take care to jump
// to the location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
0x0000003E // This field shows because of
// which patch trap address the
// bus_fault is generated. If the
// PATCH_ERR bit is set, then it
// means the bus fault is generated
// because of
// PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
0x00000001 // This bit is set when there is a
// bus fault because of patched
// address access to the Apps boot
// rom. Write 0 to clear this
// register.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
0x00000001 // This bit is set when there is a
// an error in memss write access.
// And the address causing this
// error is captured in
// MEMSS_ERR_ADDR_REG. To capture
// the next error address one have
// to clear this bit.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
0x0000F000 // 1= disable corresponding
// interrupt;0 = interrupt enabled
// bit 14: ADC channel 7 interrupt
// enable/disable bit 13: ADC
// channel 5 interrupt
// enable/disable bit 12: ADC
// channel 3 interrupt
// enable/disable bit 11: ADC
// channel 1 interrupt
// enable/disable
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
0x00000800 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
0x00000400 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
0x00000200 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
0x00000100 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
0x00000080 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
0x00000040 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
0x00000020 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
0x00000010 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
0x00000008 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
0x00000004 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
0x00000002 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
0x00000001 // 1= disable corresponding
// interrupt;0 = interrupt enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
0x0000F000 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ bit 13: ADC channel 5
// DMA Done IRQ bit 12: ADC channel
// 3 DMA Done IRQ bit 11: ADC
// channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
0x00000800 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
0x00000400 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
0x00000200 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
0x00000100 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000080 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000040 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000020 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000010 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
0x00000008 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
0x00000004 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
0x00000002 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
0x00000001 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
0x0000F000 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ mask bit 13: ADC channel
// 5 DMA Done IRQ mask bit 12: ADC
// channel 3 DMA Done IRQ mask bit
// 11: ADC channel 1 DMA Done IRQ
// mask
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
0x00000800 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
0x00000400 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
0x00000200 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
0x00000100 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000080 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000040 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000020 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000010 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000008 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000004 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
0x00000002 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
0x00000001 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
0xFFFFFFFF // write 1 or 0 to clear all
// DMA_DONE interrupt;
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
0x0000F000 // write 1 to clear corresponding
// interrupt; 0 = no effect; bit 14:
// ADC channel 7 DMA Done IRQ bit
// 13: ADC channel 5 DMA Done IRQ
// bit 12: ADC channel 3 DMA Done
// IRQ bit 11: ADC channel 1 DMA
// Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
0x00000800 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
0x00000400 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
0x00000200 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
0x00000100 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
0x00000080 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
0x00000040 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
0x00000020 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
0x00000010 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
0x00000008 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
0x00000004 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
0x00000002 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
0x00000001 // write 1 to clear corresponding
// interrupt; 0 = no effect;
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
0x0000F000 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask bit 14: ADC
// channel 7 DMA Done IRQ bit 13:
// ADC channel 5 DMA Done IRQ bit
// 12: ADC channel 3 DMA Done IRQ
// bit 11: ADC channel 1 DMA Done
// IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
0x00000800 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
0x00000400 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
0x00000200 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
0x00000100 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000080 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000040 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000020 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000010 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000008 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000004 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
0x00000002 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
0x00000001 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
0x0000F000 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive bit 14: ADC channel 7
// DMA Done IRQ bit 13: ADC channel
// 5 DMA Done IRQ bit 12: ADC
// channel 3 DMA Done IRQ bit 11:
// ADC channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
0x00000800 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
0x00000400 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
0x00000200 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
0x00000100 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000080 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000040 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000020 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000010 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
0x00000008 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
0x00000004 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
0x00000002 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
0x00000001 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
0x00000001 // Write 1 to clear the LSB of
// FAULT_STATUS_REG
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_RESERVD_REG_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_GPT_TRIG_SEL register.
//
//******************************************************************************
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
0x000000FF // This bit is implemented for GPT
// trigger mode select. GPT IP
// support 2 modes: RTC mode and
// external trigger. When this bit
// is set to logic '1': enable
// external trigger mode for APPS
// GPT CP0 and CP1 pin. bit 0: when
// set '1' enable external GPT
// trigger 0 on GPIO0 CP0 pin else
// RTC mode is selected. bit 1: when
// set '1' enable external GPT
// trigger 1 on GPIO0 CP1 pin else
// RTC mode is selected. bit 2: when
// set '1' enable external GPT
// trigger 2 on GPIO1 CP0 pin else
// RTC mode is selected. bit 3: when
// set '1' enable external GPT
// trigger 3 on GPIO1 CP1 pin else
// RTC mode is selected. bit 4: when
// set '1' enable external GPT
// trigger 4 on GPIO2 CP0 pin else
// RTC mode is selected. bit 5: when
// set '1' enable external GPT
// trigger 5 on GPIO2 CP1 pin else
// RTC mode is selected. bit 6: when
// set '1' enable external GPT
// trigger 6 on GPIO3 CP0 pin else
// RTC mode is selected. bit 7: when
// set '1' enable external GPT
// trigger 7 on GPIO3 CP1 pin else
// RTC mode is selected.
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
0x00000007 // Capture data from d2d_spare pads
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
0x00000007 // Send data to d2d_spare pads -
// eventually this will get
// registered in top die
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
#endif // __HW_APPS_CONFIG_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_CAMERA_H__
#define __HW_CAMERA_H__
//*****************************************************************************
//
// The following are defines for the CAMERA register offsets.
//
//*****************************************************************************
#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
// revision code ( Parallel Mode)
#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
// various parameters of the OCP
// interface (CCP and Parallel Mode)
#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
// information about the module
// excluding the interrupt status
// information (CCP and Parallel
// Mode)
#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
// all the status of the module
// internal events that can generate
// an interrupt (CCP & Parallel
// Mode)
#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
// allows to enable/disable the
// module internal sources of
// interrupt on an event-by-event
// basis (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
// various parameters of the Camera
// Core block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
// interface of the Camera Core
// block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
// of the clock divisor used to
// generate the external clock
// (Parallel Mode)
#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
// the FIFO and read from the FIFO
// (CCP & Parallel Mode)
#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
// of some important variables of
// the camera core module (CCP &
// Parallel Mode)
#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
// of the generic parameters of the
// module
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_REVISION register.
//
//******************************************************************************
#define CAMERA_CC_REVISION_REV_M \
0x000000FF // IP revision [7:4] Major revision
// [3:0] Minor revision Examples:
// 0x10 for 1.0 0x21 for 2.1
#define CAMERA_CC_REVISION_REV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSCONFIG register.
//
//******************************************************************************
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
0x00000018 // Slave interface power management
// req/ack control """00""
// Force-idle. An idle request is
// acknoledged unconditionally"
// """01"" No-idle. An idle request
// is never acknowledged" """10""
// reserved (Smart-idle not
// implemented)"
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
0x00000002 // Software reset. Set this bit to
// 1 to trigger a module reset. The
// bit is automatically reset by the
// hardware. During reset it always
// returns 0. 0 Normal mode 1 The
// module is reset
#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
0x00000001 // Internal OCP clock gating
// strategy 0 OCP clock is
// free-running 1 Automatic OCP
// clock gating strategy is applied
// based on the OCP interface
// activity
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
0x00000001 // Internal Reset Monitoring 0
// Internal module reset is on-going
// 1 Reset completed
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_IRQSTATUS_FS_IRQ \
0x00080000 // Frame Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LE_IRQ \
0x00040000 // Line End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LS_IRQ \
0x00020000 // Line Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FE_IRQ \
0x00010000 // Frame End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
0x00000800 // FSP code error 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
0x00000400 // Frame Height Error 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
0x00000200 // False Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
0x00000100 // Shifted Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
0x00000010 // FIFO is not empty 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
0x00000008 // FIFO is full 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
0x00000004 // FIFO threshold has been reached
// 0 Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
0x00000002 // FIFO overflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
0x00000001 // FIFO underflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQENABLE register.
//
//******************************************************************************
#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
0x00080000 // Frame Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
0x00040000 // Line End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
0x00020000 // Line Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
0x00010000 // Frame End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
0x00000800 // FSP code Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
0x00000400 // Frame Height Error Interrupt
// Enable 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
0x00000200 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
0x00000100 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
0x00000010 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
0x00000008 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
0x00000004 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
0x00000002 // FIFO Overflow Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
0x00000001 // FIFO Underflow Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
0x00080000 // Synchronize all camera sensor
// inputs This must be set during
// the configuration phase before
// CC_EN set to '1'. This can be
// used in very high frequency to
// avoid dependancy to the IO
// timings. 0 No synchro (most of
// applications) 1 Synchro enabled
// (should never be required)
#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
// states machines of the camera
// core module - by writing a 1 to
// this bit. must be applied when
// CC_EN = 0 Reads returns 0
#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
0x00020000 // Set the modality in which CC_EN
// works when a disabling of the
// sensor camera core is wanted "If
// CC_FRAME_TRIG = 1 by writing
// ""0"" to CC_EN" the module is
// disabled at the end of the frame
// "If CC_FRAME_TRIG = 0 by writing
// ""0"" to CC_EN" the module is
// disabled immediately
#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
// the camera core module "By
// writing ""1"" to this field the
// module is enabled." "By writing
// ""0"" to this field the module is
// disabled at" the end of the frame
// if CC_FRAM_TRIG =1 and is
// disabled immediately if
// CC_FRAM_TRIG = 0
#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
0x00002000 // Enables to start at the
// beginning of the frame or not in
// NoBT 0 Acquisition starts when
// Vertical synchro is high 1
// Acquisition starts when Vertical
// synchro goes from low to high
// (beginning of the frame) -
// Recommended.
#define CAMERA_CC_CTRL_BT_CORRECT \
0x00001000 // Enables the correction within
// the sync codes in BT mode 0
// correction is not enabled 1
// correction is enabled
#define CAMERA_CC_CTRL_PAR_ORDERCAM \
0x00000800 // Enables swap between image-data
// in parallel mode 0 swap is not
// enabled 1 swap is enabled
#define CAMERA_CC_CTRL_PAR_CLK_POL \
0x00000400 // Inverts the clock coming from
// the sensor in parallel mode 0
// clock not inverted - data sampled
// on rising edge 1 clock inverted -
// data sampled on falling edge
#define CAMERA_CC_CTRL_NOBT_HS_POL \
0x00000200 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_HS is
// active high 1 CAM_P_HS is active
// low
#define CAMERA_CC_CTRL_NOBT_VS_POL \
0x00000100 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_VS is
// active high 1 CAM_P_VS is active
// low
#define CAMERA_CC_CTRL_PAR_MODE_M \
0x0000000E // Sets the Protocol Mode of the
// Camera Core module in parallel
// mode (when CCP_MODE = 0) """000""
// Parallel NOBT 8-bit" """001""
// Parallel NOBT 10-bit" """010""
// Parallel NOBT 12-bit" """011""
// reserved" """100"" Parallet BT
// 8-bit" """101"" Parallel BT
// 10-bit" """110"" reserved"
// """111"" FIFO test mode. Refer to
// Table 12 - FIFO Write and Read
// access"
#define CAMERA_CC_CTRL_PAR_MODE_S 1
#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
// 0 CCP mode disabled 1 CCP mode
// enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_DMA register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_DMA_DMA_EN \
0x00000100 // Sets the number of dma request
// lines 0 DMA interface disabled
// The DMA request line stays
// inactive 1 DMA interface enabled
// The DMA request line is
// operational
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
0x0000007F // Sets the threshold of the FIFO
// the assertion of the dmarequest
// line takes place when the
// threshold is reached.
// """0000000"" threshold set to 1"
// """0000001"" threshold set to 2"
// … """1111111"" threshold set to
// 128"
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_XCLK register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
0x0000001F // Sets the clock divisor value for
// CAM_XCLK generation. based on
// CAM_MCK (value of CAM_MCLK is
// 96MHz) """00000"" CAM_XCLK Stable
// Low Level" Divider not enabled
// """00001"" CAM_XCLK Stable High
// Level" Divider not enabled from 2
// to 30 CAM_XCLK = CAM_MCLK /
// XCLK_DIV """11111"" Bypass -
// CAM_XCLK = CAM_MCLK"
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_FIFO_DATA register.
//
//******************************************************************************
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
0xFFFFFFFF // Writes the 32-bit word into the
// FIFO Reads the 32-bit word from
// the FIFO
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
//
//******************************************************************************
#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
0xFF000000 // FIFO READ Pointer This field
// shows the value of the FIFO read
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
0x00FF0000 // FIFO WRITE pointer This field
// shows the value of the FIFO write
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
#define CAMERA_CC_TEST_FIFO_LEVEL_M \
0x0000FF00 // FIFO level (how many 32-bit
// words the FIFO contains) This
// field shows the value of the FIFO
// level and can assume values from
// 0 to 128
#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
0x000000FF // FIFO level peak This field shows
// the max value of the FIFO level
// and can assume values from 0 to
// 128
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_GEN_PAR register.
//
//******************************************************************************
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
0x00000007 // Camera Core FIFO DEPTH generic
// parameter
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
#endif // __HW_CAMERA_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_DES_H__
#define __HW_DES_H__
//*****************************************************************************
//
// The following are defines for the DES_P register offsets.
//
//*****************************************************************************
#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key
#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key
#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key
#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key
#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit
// key/192-bit key
#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit
// key/192-bit key
#define DES_O_IV_L 0x00000018 // Initialization vector LSW
#define DES_O_IV_H 0x0000001C // Initialization vector MSW
#define DES_O_CTRL 0x00000020
#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data
// length in bytes for all modes.
// Once processing is started with
// this context this length
// decrements to zero. Data lengths
// up to (2^32 – 1) bytes are
// allowed. A write to this register
// triggers the engine to start
// using this context. For a Host
// read operation these registers
// return all-zeroes.
#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write
// encrypted/decrypted data.
#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write
// encrypted/decrypted data.
#define DES_O_REVISION 0x00000030
#define DES_O_SYSCONFIG 0x00000034
#define DES_O_SYSSTATUS 0x00000038
#define DES_O_IRQSTATUS 0x0000003C // This register indicates the
// interrupt status. If one of the
// interrupt bits is set the
// interrupt output will be asserted
#define DES_O_IRQENABLE 0x00000040 // This register contains an enable
// bit for each unique interrupt
// generated by the module. It
// matches the layout of
// DES_IRQSTATUS register. An
// interrupt is enabled when the bit
// in this register is set to 1
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_L register.
//
//******************************************************************************
#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3
#define DES_KEY3_L_KEY3_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_H register.
//
//******************************************************************************
#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3
#define DES_KEY3_H_KEY3_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_L register.
//
//******************************************************************************
#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2
#define DES_KEY2_L_KEY2_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_H register.
//
//******************************************************************************
#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2
#define DES_KEY2_H_KEY2_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_L register.
//
//******************************************************************************
#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1
#define DES_KEY1_L_KEY1_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_H register.
//
//******************************************************************************
#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1
#define DES_KEY1_H_KEY1_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_L register.
//
//******************************************************************************
#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC
// CFB modes
#define DES_IV_L_IV_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_H register.
//
//******************************************************************************
#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC
// CFB modes
#define DES_IV_H_IV_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_CTRL register.
//
//******************************************************************************
#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit
// indicates that the context data
// registers can be overwritten and
// the host is permitted to write
// the next context.
#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0
// ecb mode 0x1 cbc mode 0x2 cfb
// mode 0x3 reserved
#define DES_CTRL_MODE_S 4
#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
// encryption/decryption. 0 des mode
// 1 tdes mode
#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0
// decryption is selected 1
// Encryption is selected
#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to
// encrypt/decrypt data
#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data
// decrypted/encrypted ready
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_LENGTH register.
//
//******************************************************************************
#define DES_LENGTH_LENGTH_M 0xFFFFFFFF
#define DES_LENGTH_LENGTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_L register.
//
//******************************************************************************
#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption
#define DES_DATA_L_DATA_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_H register.
//
//******************************************************************************
#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption
#define DES_DATA_H_DATA_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_REVISION register.
//
//******************************************************************************
#define DES_REVISION_SCHEME_M 0xC0000000
#define DES_REVISION_SCHEME_S 30
#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
// compatible module family. If
// there is no level of software
// compatibility a new Func number
// (and hence REVISION) should be
// assigned.
#define DES_REVISION_FUNC_S 16
#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
// design owner. RTL follows a
// numbering such as X.Y.R.Z which
// are explained in this table. R
// changes ONLY when: (1) PDS
// uploads occur which may have been
// due to spec changes (2) Bug fixes
// occur (3) Resets to '0' when X or
// Y changes. Design team has an
// internal 'Z' (customer invisible)
// number which increments on every
// drop that happens due to DV and
// RTL updates. Z resets to 0 when R
// increments.
#define DES_REVISION_R_RTL_S 11
#define DES_REVISION_X_MAJOR_M \
0x00000700 // Major Revision (X) maintained by
// IP specification owner. X changes
// ONLY when: (1) There is a major
// feature addition. An example
// would be adding Master Mode to
// Utopia Level2. The Func field (or
// Class/Type in old PID format)
// will remain the same. X does NOT
// change due to: (1) Bug fixes (2)
// Change in feature parameters.
#define DES_REVISION_X_MAJOR_S 8
#define DES_REVISION_CUSTOM_M 0x000000C0
#define DES_REVISION_CUSTOM_S 6
#define DES_REVISION_Y_MINOR_M \
0x0000003F // Minor Revision (Y) maintained by
// IP specification owner. Y changes
// ONLY when: (1) Features are
// scaled (up or down). Flexibility
// exists in that this feature
// scalability may either be
// represented in the Y change or a
// specific register in the IP that
// indicates which features are
// exactly available. (2) When
// feature creeps from Is-Not list
// to Is list. But this may not be
// the case once it sees silicon; in
// which case X will change. Y does
// NOT change due to: (1) Bug fixes
// (2) Typos or clarifications (3)
// major functional/feature
// change/addition/deletion. Instead
// these changes may be reflected
// via R S X as applicable. Spec
// owner maintains a
// customer-invisible number 'S'
// which changes due to: (1)
// Typos/clarifications (2) Bug
// documentation. Note that this bug
// is not due to a spec change but
// due to implementation.
// Nevertheless the spec tracks the
// IP bugs. An RTL release (say for
// silicon PG1.1) that occurs due to
// bug fix should document the
// corresponding spec number (X.Y.S)
// in its release notes.
#define DES_REVISION_Y_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
//
//******************************************************************************
#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // If set to ‘1’ the DMA context
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // If set to ‘1’ the DMA output
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // If set to ‘1’ the DMA input
// request is enabled. 0 Dma
// disabled 1 Dma enabled
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
//
//******************************************************************************
#define DES_SYSSTATUS_RESETDONE \
0x00000001
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
//
//******************************************************************************
#define DES_IRQSTATUS_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define DES_IRQSTATUS_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQENABLE register.
//
//******************************************************************************
#define DES_IRQENABLE_M_DATA_OUT \
0x00000004 // If this bit is set to ‘1’ the
// secure data output interrupt is
// enabled.
#define DES_IRQENABLE_M_DATA_IN \
0x00000002 // If this bit is set to ‘1’ the
// secure data input interrupt is
// enabled.
#define DES_IRQENABLE_M_CONTEX_IN \
0x00000001 // If this bit is set to ‘1’ the
// secure context interrupt is
// enabled.
#endif // __HW_DES_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
#ifndef __HW_DTHE_H__
#define __HW_DTHE_H__
//*****************************************************************************
//
// The following are defines for the DTHE register offsets.
//
//*****************************************************************************
#define DTHE_O_SHA_IM 0x00000810
#define DTHE_O_SHA_RIS 0x00000814
#define DTHE_O_SHA_MIS 0x00000818
#define DTHE_O_SHA_IC 0x0000081C
#define DTHE_O_AES_IM 0x00000820
#define DTHE_O_AES_RIS 0x00000824
#define DTHE_O_AES_MIS 0x00000828
#define DTHE_O_AES_IC 0x0000082C
#define DTHE_O_DES_IM 0x00000830
#define DTHE_O_DES_RIS 0x00000834
#define DTHE_O_DES_MIS 0x00000838
#define DTHE_O_DES_IC 0x0000083C
#define DTHE_O_EIP_CGCFG 0x00000A00
#define DTHE_O_EIP_CGREQ 0x00000A04
#define DTHE_O_CRC_CTRL 0x00000C00
#define DTHE_O_CRC_SEED 0x00000C10
#define DTHE_O_CRC_DIN 0x00000C14
#define DTHE_O_CRC_RSLT_PP 0x00000C18
#define DTHE_O_RAND_KEY0 0x00000F00
#define DTHE_O_RAND_KEY1 0x00000F04
#define DTHE_O_RAND_KEY2 0x00000F08
#define DTHE_O_RAND_KEY3 0x00000F0C
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IMST register.
//
//******************************************************************************
#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is
// raised when DMA complets the
// output context movement from
// internal register
#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IRIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done
#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IMIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done
#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_ICIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done� flag
#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IMST register.
//
//******************************************************************************
#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is
// raised when DMA finishes writing
// last word of the process result
#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is
// raised when DMA complets the
// output context movement from
// internal register
#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IRIS register.
//
//******************************************************************************
#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done
#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IMIS register.
//
//******************************************************************************
#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done
#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_ICIS register.
//
//******************************************************************************
#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement
// done� flag
#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done� flag
#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IMST register.
//
//******************************************************************************
#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is
// raised when DMA finishes writing
// last word of the process result
#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IRIS register.
//
//******************************************************************************
#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IMIS register.
//
//******************************************************************************
#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_ICIS register.
//
//******************************************************************************
#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement
// done� flag
#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_EIP_CGCFG register.
//
//******************************************************************************
#define DTHE_EIP_CGCFG_EIP29_CFG \
0x00000010 // Clock gating protocol setting
// for EIP29T. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP75_CFG \
0x00000008 // Clock gating protocol setting
// for EIP75T. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP16_CFG \
0x00000004 // Clock gating protocol setting
// for DES. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP36_CFG \
0x00000002 // Clock gating protocol setting
// for AES. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP57_CFG \
0x00000001 // Clock gating protocol setting
// for SHAMD5. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_EIP_CGREQ register.
//
//******************************************************************************
#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5� write “1� to lower
// bits [4:0] will set the bit.
// Write “0� will be ignored When
// “0x2� write “1� to lower bit
// [4:0] will clear the bit. Write
// “0� will be ignored for other key
// value, regular read write
// operation
#define DTHE_EIP_CGREQ_Key_S 28
#define DTHE_EIP_CGREQ_EIP29_REQ \
0x00000010 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP75_REQ \
0x00000008 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP16_REQ \
0x00000004 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP36_REQ \
0x00000002 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP57_REQ \
0x00000001 // 0 – request clock gating 1 –
// request to un-gate the clock.
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register.
//
//******************************************************************************
#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED
// register context as starting
// value 10 – all “zero� 11 – all
// “one� This is self clearing. With
// first write to data register this
// value clears to zero and remain
// zero for rest of the operation
// unless written again
#define DTHE_CRC_CTRL_INIT_S 13
#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8
// bit
#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result
// before storing to CRC_RSLT_PP0
#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result
// byte before storing to
// CRC_RSLT_PP0. applicable for all
// bytes in word
#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For
// all bytes in word
#define DTHE_CRC_CTRL_ENDIAN_M \
0x00000030 // Endian control [0] – swap byte
// in half-word [1] – swap half word
#define DTHE_CRC_CTRL_ENDIAN_S 4
#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 –
// polynomial 0x8005 0001 –
// polynomial 0x1021 0010 –
// polynomial 0x4C11DB7 0011 –
// polynomial 0x1EDC6F41 1000 – TCP
// checksum TYPE in DTHE_S_CRC_CTRL
// & DTHE_S_CRC_CTRL should be
// exclusive
#define DTHE_CRC_CTRL_TYPE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_SEED register.
//
//******************************************************************************
#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and
// checksum operation. Please see
// CTRL register for more detail.
// This resister also holds the
// latest result of CRC or checksum
// operation
#define DTHE_CRC_SEED_SEED_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_DIN register.
//
//******************************************************************************
#define DTHE_CRC_DIN_DATA_IN_M \
0xFFFFFFFF // Input data for CRC or checksum
// operation
#define DTHE_CRC_DIN_DATA_IN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_CRC_RSLT_PP register.
//
//******************************************************************************
#define DTHE_CRC_RSLT_PP_RSLT_PP_M \
0xFFFFFFFF // Input data for CRC or checksum
// operation
#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY0 register.
//
//******************************************************************************
#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [31:0]
#define DTHE_RAND_KEY0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY1 register.
//
//******************************************************************************
#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [63:32]
#define DTHE_RAND_KEY1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY2 register.
//
//******************************************************************************
#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [95:34]
#define DTHE_RAND_KEY2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY3 register.
//
//******************************************************************************
#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [127:96]
#define DTHE_RAND_KEY3_KEY_S 0
#endif // __HW_DTHE_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000
#define I2C_O_MCS 0x00000004
#define I2C_O_MDR 0x00000008
#define I2C_O_MTPR 0x0000000C
#define I2C_O_MIMR 0x00000010
#define I2C_O_MRIS 0x00000014
#define I2C_O_MMIS 0x00000018
#define I2C_O_MICR 0x0000001C
#define I2C_O_MCR 0x00000020
#define I2C_O_MCLKOCNT 0x00000024
#define I2C_O_MBMON 0x0000002C
#define I2C_O_MBLEN 0x00000030
#define I2C_O_MBCNT 0x00000034
#define I2C_O_SOAR 0x00000800
#define I2C_O_SCSR 0x00000804
#define I2C_O_SDR 0x00000808
#define I2C_O_SIMR 0x0000080C
#define I2C_O_SRIS 0x00000810
#define I2C_O_SMIS 0x00000814
#define I2C_O_SICR 0x00000818
#define I2C_O_SOAR2 0x0000081C
#define I2C_O_SACKCTL 0x00000820
#define I2C_O_FIFODATA 0x00000F00
#define I2C_O_FIFOCTL 0x00000F04
#define I2C_O_FIFOSTATUS 0x00000F08
#define I2C_O_OBSMUXSEL0 0x00000F80
#define I2C_O_OBSMUXSEL1 0x00000F84
#define I2C_O_MUXROUTE 0x00000F88
#define I2C_O_PV 0x00000FB0
#define I2C_O_PP 0x00000FC0
#define I2C_O_PC 0x00000FC4
#define I2C_O_CC 0x00000FC8
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//******************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_SA_S 1
#define I2C_MSA_RS 0x00000001 // Receive not send
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//******************************************************************************
#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//******************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
#define I2C_MDR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//******************************************************************************
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
#define I2C_MTPR_TPR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//******************************************************************************
#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
// Mask
#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//******************************************************************************
#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
// Status
#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
// Status
#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
// Status
#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
// Status
#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
// Status
#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
// Status
#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
// Status
#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//******************************************************************************
#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//******************************************************************************
#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
// Clear
#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
// Clear
#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
// Clear
#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
// Clear
#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
// Clear
#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//******************************************************************************
#define I2C_MCR_MMD 0x00000040 // Multi-master Disable
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//******************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//******************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBLEN register.
//
//******************************************************************************
#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
#define I2C_MBLEN_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBCNT register.
//
//******************************************************************************
#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
#define I2C_MBCNT_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//******************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//******************************************************************************
#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//******************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//******************************************************************************
#define I2C_SIMR_IM 0x00000100 // Interrupt Mask
#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//******************************************************************************
#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status
#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
// Status
#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
// Status
#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//******************************************************************************
#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
// Status
#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
// Status
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//******************************************************************************
#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//******************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//******************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFODATA register.
//
//******************************************************************************
#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte
#define I2C_FIFODATA_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
//
//******************************************************************************
#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
#define I2C_FIFOCTL_RXTRIG_S 16
#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
#define I2C_FIFOCTL_TXTRIG_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register.
//
//******************************************************************************
#define I2C_FIFOSTATUS_RXABVTRIG \
0x00040000 // RX FIFO Above Trigger Level
#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
#define I2C_FIFOSTATUS_TXBLWTRIG \
0x00000004 // TX FIFO Below Trigger Level
#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register.
//
//******************************************************************************
#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3
#define I2C_OBSMUXSEL0_LN3_S 24
#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2
#define I2C_OBSMUXSEL0_LN2_S 16
#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1
#define I2C_OBSMUXSEL0_LN1_S 8
#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0
#define I2C_OBSMUXSEL0_LN0_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register.
//
//******************************************************************************
#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7
#define I2C_OBSMUXSEL1_LN7_S 24
#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6
#define I2C_OBSMUXSEL1_LN6_S 16
#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5
#define I2C_OBSMUXSEL1_LN5_S 8
#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4
#define I2C_OBSMUXSEL1_LN4_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MUXROUTE register.
//
//******************************************************************************
#define I2C_MUXROUTE_LN7ROUTE_M \
0x70000000 // Lane 7 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN7ROUTE_S 28
#define I2C_MUXROUTE_LN6ROUTE_M \
0x07000000 // Lane 6 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN6ROUTE_S 24
#define I2C_MUXROUTE_LN5ROUTE_M \
0x00700000 // Lane 5 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN5ROUTE_S 20
#define I2C_MUXROUTE_LN4ROUTE_M \
0x00070000 // Lane 4 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN4ROUTE_S 16
#define I2C_MUXROUTE_LN3ROUTE_M \
0x00007000 // Lane 3 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN3ROUTE_S 12
#define I2C_MUXROUTE_LN2ROUTE_M \
0x00000700 // Lane 2 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN2ROUTE_S 8
#define I2C_MUXROUTE_LN1ROUTE_M \
0x00000070 // Lane 1 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN1ROUTE_S 4
#define I2C_MUXROUTE_LN0ROUTE_M \
0x00000007 // Lane 0 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN0ROUTE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PV register.
//
//******************************************************************************
#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision
#define I2C_PV_MAJOR_S 8
#define I2C_PV_MINOR_M 0x000000FF // Minor Revision
#define I2C_PV_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//******************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PC register.
//
//******************************************************************************
#define I2C_PC_HS 0x00000001 // High-Speed Capable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_CC register.
//
//******************************************************************************
#endif // __HW_I2C_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on CC3200.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA0 16 // GPIO Port S0
#define INT_GPIOA1 17 // GPIO Port S1
#define INT_GPIOA2 18 // GPIO Port S2
#define INT_GPIOA3 19 // GPIO Port S3
#define INT_UARTA0 21 // UART0 Rx and Tx
#define INT_UARTA1 22 // UART1 Rx and Tx
#define INT_I2CA0 24 // I2C controller
#define INT_ADCCH0 30 // ADC Sequence 0
#define INT_ADCCH1 31 // ADC Sequence 1
#define INT_ADCCH2 32 // ADC Sequence 2
#define INT_ADCCH3 33 // ADC Sequence 3
#define INT_WDT 34 // Watchdog Timer0
#define INT_TIMERA0A 35 // Timer 0 subtimer A
#define INT_TIMERA0B 36 // Timer 0 subtimer B
#define INT_TIMERA1A 37 // Timer 1 subtimer A
#define INT_TIMERA1B 38 // Timer 1 subtimer B
#define INT_TIMERA2A 39 // Timer 2 subtimer A
#define INT_TIMERA2B 40 // Timer 2 subtimer B
#define INT_FLASH 45 // FLASH Control
#define INT_TIMERA3A 51 // Timer 3 subtimer A
#define INT_TIMERA3B 52 // Timer 3 subtimer B
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_SHA 164 // SHA
#define INT_AES 167 // AES
#define INT_DES 169 // DES
#define INT_MMCHS 175 // SDIO
#define INT_I2S 177 // McAPS
#define INT_CAMERA 179 // Camera
#define INT_NWPIC 187 // Interprocessor communication
#define INT_PRCM 188 // Power, Reset and Clock Module
#define INT_SSPI 191 // Shared SPI
#define INT_GSPI 192 // Generic SPI
#define INT_LSPI 193 // Link SPI
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 195 //The above number plus 2?
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals on the slave_1 interface.
//
//*****************************************************************************
#define FLASH_BASE 0x01000000
#define SRAM_BASE 0x20000000
#define WDT_BASE 0x40000000
#define GPIOA0_BASE 0x40004000
#define GPIOA1_BASE 0x40005000
#define GPIOA2_BASE 0x40006000
#define GPIOA3_BASE 0x40007000
#define GPIOA4_BASE 0x40024000
#define UARTA0_BASE 0x4000C000
#define UARTA1_BASE 0x4000D000
#define I2CA0_BASE 0x40020000
#define TIMERA0_BASE 0x40030000
#define TIMERA1_BASE 0x40031000
#define TIMERA2_BASE 0x40032000
#define TIMERA3_BASE 0x40033000
#define STACKDIE_CTRL_BASE 0x400F5000
#define COMMON_REG_BASE 0x400F7000
#define FLASH_CONTROL_BASE 0x400FD000
#define SYSTEM_CONTROL_BASE 0x400FE000
#define UDMA_BASE 0x400FF000
#define SDHOST_BASE 0x44010000
#define CAMERA_BASE 0x44018000
#define I2S_BASE 0x4401C000
#define SSPI_BASE 0x44020000
#define GSPI_BASE 0x44021000
#define LSPI_BASE 0x44022000
#define ARCM_BASE 0x44025000
#define APPS_CONFIG_BASE 0x44026000
#define GPRCM_BASE 0x4402D000
#define OCP_SHARED_BASE 0x4402E000
#define ADC_BASE 0x4402E800
#define HIB1P2_BASE 0x4402F000
#define HIB3P3_BASE 0x4402F800
#define DTHE_BASE 0x44030000
#define SHAMD5_BASE 0x44035000
#define AES_BASE 0x44037000
#define DES_BASE 0x44039000
#endif // __HW_MEMMAP_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_STACK_DIE_CTRL_H__
#define __HW_STACK_DIE_CTRL_H__
//*****************************************************************************
//
// The following are defines for the STACK_DIE_CTRL register offsets.
//
//*****************************************************************************
#define STACK_DIE_CTRL_O_STK_UP_RESET \
0x00000000 // Can be written only by Base
// Processor. Writing to this
// register will reset the stack
// processor reset will be
// de-asserted upon clearing this
// register.
#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \
0x00000004 // This register defines who among
// base processor and stack
// processor have highest priority
// for Sram Access. Can be written
// only by Base Processor.
#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \
0x00000008 // In Spinlock mode this Register
// defines who among base processor
// and stack processor have access
// to Sram Bank2 right now. In
// Handshake mode this Register
// defines who among base processor
// and stack processor have access
// to Sram Bank2 and Bank3 right
// now. Its Clear only register and
// is set by hardware. Lower bit can
// be cleared only by Base Processor
// and Upper bit Cleared only by the
// Stack processor.
#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \
0x0000000C // In Spinlock mode whenever Base
// processor wants the access to
// Sram Bank2 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by Stack
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \
0x00000010 // In Spinlock mode Whenever Stack
// processor wants the access to
// Sram Bank2 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by the Base
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \
0x00000014 // Register defines who among base
// processor and stack processor
// have access to Sram Bank3 right
// now. Its Clear only register and
// is set by hardware. Lower bit can
// be cleared only by Base Processor
// and Upper bit Cleared only by the
// Stack processor.
#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \
0x00000018 // In Spinlock mode whenever Base
// processor wants the access to
// Sram Bank3 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by Stack
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \
0x0000001C // In Spinlock mode Whenever Stack
// processor wants the access to
// Sram Bank3 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by the Base
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \
0x00000020 // Read State Machine timing
// configuration register. Generally
// Bit 4 and 3 will be identical.
// For stacked die always 43 are 0
// and 6:5 == 1 for 120Mhz.
#define STACK_DIE_CTRL_O_RDSM_CFG_EE \
0x00000024 // Read State Machine timing
// configuration register. Generally
// Bit 4 and 3 will be identical.
// For stacked die always 43 are 0
// and 6:5 == 1 for 120Mhz.
#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \
0x00000028 // Reading this register Base
// procesor will able to know the
// reason for the interrupt. This is
// clear only register - set by HW
// upon an interrupt to Base
// processor and can be cleared only
// by BASE processor.
#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \
0x0000002C // Reading this register Stack
// procesor will able to know the
// reason for the interrupt. This is
// clear only register - set by HW
// upon an interrupt to Stack
// processor and can be cleared only
// by Stack processor.
#define STACK_DIE_CTRL_O_STK_CLK_EN \
0x00000030 // Can be written only by base
// processor. Controls the enable
// pin of the cgcs for the clocks
// going to CM3 dft ctrl block and
// Sram.
#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \
0x00000034 // Can be written only by the base
// processor. Decides the ram
// sharing mode :: handshake or
// Spinlock mode.
#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \
0x00000038 // Stores the last bus fault
// address.
#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \
0x0000003C // write only registers on read
// returns 0.W Write 1 to clear the
// bust fault to store the new bus
// fault address
#define STACK_DIE_CTRL_O_RESET_CAUSE \
0x00000040 // Reset cause value captured from
// the ICR_CLKRST block.
#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \
0x00000044 // Watchdog timer event value
// captured from the ICR_CLKRST
// block
#define STACK_DIE_CTRL_O_DMA_REQ \
0x00000048 // To send Dma Request to bottom
// die.
#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \
0x0000004C // Address offset within SRAM to
// which CM3 should jump after
// reset.
#define STACK_DIE_CTRL_O_SW_REG1 \
0x00000050 // These are sw registers for
// topdie processor and bottom die
// processor to communicate. Both
// can set and read these registers.
// In case of write clash bottom
// die's processor wins and top die
// processor access is ignored.
#define STACK_DIE_CTRL_O_SW_REG2 \
0x00000054 // These are sw registers for
// topdie processor and bottom die
// processor to communicate. Both
// can set and read these registers.
// In case of write clash bottom
// die's processor wins and top die
// processor access is ignored.
#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \
0x00000058 // By posting the request Flash can
// be put into low-power mode
// (Sleep) without powering down the
// Flash. Earlier (in Garnet) this
// was fully h/w controlled and the
// control for this was coming from
// SysCtl while entering into Cortex
// Deep-sleep mode. But for our
// device the D2D i/f doesnt support
// this. The Firmware has to program
// the register in the top-die for
// entering into this mode and wait
// for an interrupt.
#define STACK_DIE_CTRL_O_MISC_CTL \
0x0000005C // Miscellanious control register.
#define STACK_DIE_CTRL_O_SW_DFT_CTL \
0x000000FC // DFT control and status bits
#define STACK_DIE_CTRL_O_PADN_CTL_0 \
0x00000100 // Mainly for For controlling the
// pads OEN pins. There are total 60
// pads and hence 60 control registe
// i.e n value varies from 0 to 59.
// Here is the mapping for the
// pad_ctl register number and the
// functionality : 0 D2DPAD_DMAREQ1
// 1 D2DPAD_DMAREQ0 2
// D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4
// D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6
// D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8
// D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS
// 10 D2DPAD_JTAG_TDI 11-27
// D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE
// -1:0] 28-56 D2DPAD_TOSTACK
// [D2D_TOSTACK_SIZE -1:0] 57-59
// D2DPAD_SPARE [D2D_SPARE_PAD_SIZE
// -1:0] 0:00
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_RESET register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \
0x00000001 // 1 :Assert Reset 0 : Deassert the
// Reset
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \
0x00000003 // 00 : Equal Priority 01 : Stack
// Processor have priority 10 : Base
// Processor have priority 11 :
// Unused
#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \
0x00000002 // Stack Processor should clear it
// when it is done with the sram
// bank usage. Set by HW It is set
// when Stack Processor is granted
// the access to this bank
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \
0x00000001 // Base Processor should clear it
// when it is done wth the sram
// usage. Set by HW It is set when
// Base Processor is granted the
// access to this bank
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \
0x00000001 // Base Processor will set when
// Sram access is needed in Spin
// Lock mode. In Handshake mode
// Stack Processor will set to
// inform Base Processor that it is
// done with the processing of data
// in SRAM and is now ready to use
// by the base processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \
0x00000001 // Stack Processor will set when
// Sram access is needed in Spin
// Lock mode. In Handshake mode Base
// Processor will set to inform
// Stack Processor to start
// processing the data in the Ram.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \
0x00000002 // Stack Processor should clear it
// when it is done with the sram
// bank usage. Set by HW It is set
// when Stack Processor is granted
// the access to this bank.
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \
0x00000001 // Base Processor should clear it
// when it is done wth the sram
// usage. Set by HW it is set when
// Base Processor is granted the
// access to this bank.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \
0x00000001 // Base Processor will set when
// Sram access is needed in Spin
// Lock mode. Not used in handshake
// mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \
0x00000001 // Stack Processor will set when
// Sram access is needed in Spin
// Lock mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RDSM_CFG_CPU register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \
0x000000C0 // Bank Clock Hi Time 00 : HCLK
// pulse 01 : 1 cycle of HCLK 10 :
// 1.5 cycles of HCLK 11 : 2 cycles
// of HCLK
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \
0x00000020 // FLCLK 0 : indicates flash clock
// rise aligns on HCLK rise 1 :
// indicates flash clock rise aligns
// on HCLK fall
#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \
0x00000010 // 0 : Always register flash rdata
// before sending to CPU 1 : Drive
// Flash rdata directly out on MISS
// (Both ICODE / DCODE)
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \
0x0000000F // Number of wait states inserted
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RDSM_CFG_EE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \
0x000000C0 // Bank Clock Hi Time 00 : HCLK
// pulse 01 : 1 cycle of HCLK 10 :
// 1.5 cycles of HCLK 11 : 2 cycles
// of HCLK
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \
0x00000020 // FLCLK 0 : indicates flash clock
// rise aligns on HCLK rise 1 :
// indicates flash clock rise aligns
// on HCLK fall
#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \
0x00000010 // 0 : Always register flash rdata
// before sending to CPU 1 : Drive
// Flash rdata directly out on MISS
// (Both ICODE / DCODE)
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \
0x0000000F // Number of wait states inserted
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \
0x00000010 // Set when Relinquish Interrupt
// sent to Base processor for Bank3.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \
0x00000008 // Set when Relinquish Interrupt
// sent to Base processor for Bank2.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \
0x00000004 // Set when Bank3 is granted to
// Base processor.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \
0x00000002 // Set when Bank2 is granted to
// BAse processor.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \
0x00000001 // Set when there Base processor do
// an Invalid access to Sram. Ex :
// Accessing the bank which is not
// granted for BAse processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \
0x00000008 // Set when Relinquish Interrupt
// sent to Stack processor for
// Bank3.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \
0x00000004 // Set when Relinquish Interrupt
// sent to Stack processor for
// Bank2.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \
0x00000002 // Set when Bank3 is granted to
// Stack processor.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \
0x00000001 // Set when Bank2 is granted to
// Stack processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_CLK_EN register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \
0x00000004 // Enable the clock going to sram.
#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \
0x00000002 // Enable the clock going to dft
// control block
#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \
0x00000001 // Enable the clock going to Cm3
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \
0x00000001 // 0 : Handshake Mode 1 : Spinlock
// mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \
0xFFFFFFFF // Fault Address
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BUS_FAULT_CLR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \
0x00000001 // When set it'll clear the bust
// fault address register to store
// the new bus fault address
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RESET_CAUSE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register.
//
//******************************************************************************
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_DMA_REQ register.
//
//******************************************************************************
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \
0x00000002 // Generate DMAREQ1 on setting this
// bit.
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \
0x00000001 // Generate DMAREQ0 on setting this
// bit.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_REG1 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_REG2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \
0x00000002 // captures the status of of
// fmc_lpm_ack
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \
0x00000001 // When set assert
// iflpe2fmc_lpm_req to FMC.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_MISC_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \
0x00000080 // 1 : will reset the async wdog
// timer runing on piosc clock
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \
0x00000020 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \
0x00000010 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \
0x00000008 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \
0x00000004 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 3 goes to Bank3 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank2
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \
0x00000002 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 2 goes to Bank2 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank2
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \
0x00000001 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 1 goes to Bank1 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank1
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_DFT_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \
0x20000000 // when set to '1' all flash
// control signals switch over to
// CM3 control when '0' it is under
// the D2D interface control
#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \
0x10000000 // 1 indicates in SWIF mode the
// control signals to flash are from
// FMC CPU read controls the clock
// and address. that is one can give
// address via FMC and read through
// IDMEM.
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \
0x00800000 // 'CPU Done' bit for PBIST. Write
// '1' to indicate test done.
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \
0x00400000 // 'CPU Fail' bit for PBIST. Write
// '1' to indicate test failed.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \
0x00001000 // when set to '1' flash bank 4
// (EEPROM) is owned by the CM3for
// reads over DCODE bus. When '0'
// access control given to D2D
// interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \
0x00000800 // when set to '1' flash bank 3 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \
0x00000400 // when set to '1' flash bank 2 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \
0x00000200 // when set to '1' flash bank 1 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \
0x00000100 // when set to '1' flash bank 0 is
// owned by the CM3 for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_PADN_CTL_0 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \
0x00000008 // This bit is valid for only the
// spare pads ie for n=57 to 59.
// value to drive at the output of
// the pad
#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \
0x00000004 // This bit is valid for only the
// spare pads ie for n=57 to 59.
// captures the 'Y' pin of the pad
// which is the data being driven
// into the die
#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \
0x00000002 // OEN2X control when '1' enables
// the output with 1x. Total drive
// strength is decided bu oen1x
// setting + oen2x setting.
#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \
0x00000001 // OEN1X control when '1' enables
// the output with 1x . Total drive
// strength is decided bu oen1x
// setting + oen2x setting.
#endif // __HW_STACK_DIE_CTRL_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
//*****************************************************************************
//##### INTERNAL BEGIN #####
//
// This is an auto-generated file. Do not edit by hand.
// Created by version 6779 of DriverLib.
//
//##### INTERNAL END #####
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the Timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
//##### GARNET BEGIN #####
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
//##### GARNET END #####
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
//##### GARNET END #####
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
//##### GARNET END #####
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//##### GARNET BEGIN #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11
#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of
// GPTM11 is triggered
#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of
// GPTM11 is triggered
#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM11 is
// triggered
#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10
#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of
// GPTM10 is triggered
#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of
// GPTM10 is triggered
#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM10 is
// triggered
#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9
#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of
// GPTM9 is triggered
#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of
// GPTM9 is triggered
#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM9 is
// triggered
#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8
#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of
// GPTM8 is triggered
#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of
// GPTM8 is triggered
#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM8 is
// triggered
#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7
#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of
// GPTM7 is triggered
#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of
// GPTM7 is triggered
#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM7 is
// triggered
#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6
#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of
// GPTM6 is triggered
#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of
// GPTM6 is triggered
#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM6 is
// triggered
#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5
#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of
// GPTM5 is triggered
#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of
// GPTM5 is triggered
#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM5 is
// triggered
#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4
#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of
// GPTM4 is triggered
#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of
// GPTM4 is triggered
#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM4 is
// triggered
#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3
#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of
// GPTM3 is triggered
#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of
// GPTM3 is triggered
#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM3 is
// triggered
#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2
#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of
// GPTM2 is triggered
#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of
// GPTM2 is triggered
#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM2 is
// triggered
#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1
#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of
// GPTM1 is triggered
#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of
// GPTM1 is triggered
#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM1 is
// triggered
#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0
#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of
// GPTM0 is triggered
#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of
// GPTM0 is triggered
#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM0 is
// triggered
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Mask
//##### GARNET END #####
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
// Interrupt Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
// Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
// Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
// Interrupt Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
// Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
// Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Raw Interrupt Status
//##### GARNET END #####
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
// Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
// Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
// Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
// Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
// Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
// Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Masked Interrupt Status
//##### GARNET END #####
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
// Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
// Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
// Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
// Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Clear
//##### GARNET END #####
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
// Interrupt Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
// Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
// Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
// Interrupt Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
// Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
// Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
//##### GARNET END #####
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAILR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
//##### GARNET END #####
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBILR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
//##### GARNET END #####
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAMATCHR_TAMR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
//##### GARNET END #####
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
//##### GARNET BEGIN #####
#define TIMER_TBMATCHR_TBMR_S 0
//##### GARNET END #####
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
//##### GARNET END #####
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
//##### GARNET BEGIN #####
#define TIMER_TAPR_TAPSRH_S 8
//##### GARNET END #####
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
//##### GARNET END #####
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
//##### GARNET BEGIN #####
#define TIMER_TBPR_TBPSRH_S 8
//##### GARNET END #####
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
//##### GARNET END #####
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
//##### GARNET BEGIN #####
#define TIMER_TAPMR_TAPSMRH_S 8
//##### GARNET END #####
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
//##### GARNET END #####
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
//##### GARNET BEGIN #####
#define TIMER_TBPMR_TBPSMRH_S 8
//##### GARNET END #####
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
//##### GARNET END #####
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
//##### GARNET END #####
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
//##### GARNET END #####
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAV_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
//##### GARNET END #####
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are
// 32 bits each with an 16-bit
// prescale counter
//##### GARNET END #####
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CFG
// register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CTL
// register.
//
//*****************************************************************************
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_RIS
// register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
// register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
// register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAR
// register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBR
// register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the timer
// registers.
//
//*****************************************************************************
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnMR
// register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPR
// register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPMR
// register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
#endif
#endif // __HW_TIMER_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000
#define UART_O_RSR 0x00000004
#define UART_O_ECR 0x00000004
#define UART_O_FR 0x00000018
#define UART_O_ILPR 0x00000020
#define UART_O_IBRD 0x00000024
#define UART_O_FBRD 0x00000028
#define UART_O_LCRH 0x0000002C
#define UART_O_CTL 0x00000030
#define UART_O_IFLS 0x00000034
#define UART_O_IM 0x00000038
#define UART_O_RIS 0x0000003C
#define UART_O_MIS 0x00000040
#define UART_O_ICR 0x00000044
#define UART_O_DMACTL 0x00000048
#define UART_O_LCTL 0x00000090
#define UART_O_LSS 0x00000094
#define UART_O_LTIM 0x00000098
#define UART_O_9BITADDR 0x000000A4
#define UART_O_9BITAMASK 0x000000A8
#define UART_O_PP 0x00000FC0
#define UART_O_CC 0x00000FC8
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//******************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//******************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//******************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//******************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//******************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//******************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//******************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//******************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 :
// UART_LCRH_WLEN_5 : 5 bits
// (default) 0x00000020 :
// UART_LCRH_WLEN_6 : 6 bits
// 0x00000040 : UART_LCRH_WLEN_7 : 7
// bits 0x00000060 :
// UART_LCRH_WLEN_8 : 8 bits
#define UART_LCRH_WLEN_S 5
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//******************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RI 0x00002000 // Ring Indicator
#define UART_CTL_DCD 0x00001000 // Data Carrier Detect
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//******************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX_S 3
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//******************************************************************************
#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
// Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//******************************************************************************
#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
// Status
#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
// Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//******************************************************************************
#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
// Status
#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
// Status
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
// Interrupt Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//******************************************************************************
#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
// Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//******************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//******************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 :
// UART_LCTL_BLEN_13T : Sync break
// length is 13T bits (default)
// 0x00000010 : UART_LCTL_BLEN_14T :
// Sync break length is 14T bits
// 0x00000020 : UART_LCTL_BLEN_15T :
// Sync break length is 15T bits
// 0x00000030 : UART_LCTL_BLEN_16T :
// Sync break length is 16T bits
#define UART_LCTL_BLEN_S 4
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//******************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
#define UART_LSS_TSS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//******************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UART_O_9BITADDR register.
//
//******************************************************************************
#define UART_9BITADDR_9BITEN \
0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M \
0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UART_O_9BITAMASK register.
//
//******************************************************************************
#define UART_9BITAMASK_RANGE_M \
0x0000FF00 // Self Address Range for 9-Bit
// Mode
#define UART_9BITAMASK_RANGE_S 8
#define UART_9BITAMASK_MASK_M \
0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_MASK_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//******************************************************************************
#define UART_PP_MSE 0x00000008 // Modem Support Extended
#define UART_PP_MS 0x00000004 // Modem Support
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//******************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
// 0x00000005 : UART_CC_CS_PIOSC :
// PIOSC 0x00000000 :
// UART_CC_CS_SYSCLK : The system
// clock (default)
#define UART_CC_CS_S 0
#endif // __HW_UART_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the UDMA register offsets.
//
//*****************************************************************************
#define UDMA_O_STAT 0x00000000
#define UDMA_O_CFG 0x00000004
#define UDMA_O_CTLBASE 0x00000008
#define UDMA_O_ALTBASE 0x0000000C
#define UDMA_O_WAITSTAT 0x00000010
#define UDMA_O_SWREQ 0x00000014
#define UDMA_O_USEBURSTSET 0x00000018
#define UDMA_O_USEBURSTCLR 0x0000001C
#define UDMA_O_REQMASKSET 0x00000020
#define UDMA_O_REQMASKCLR 0x00000024
#define UDMA_O_ENASET 0x00000028
#define UDMA_O_ENACLR 0x0000002C
#define UDMA_O_ALTSET 0x00000030
#define UDMA_O_ALTCLR 0x00000034
#define UDMA_O_PRIOSET 0x00000038
#define UDMA_O_PRIOCLR 0x0000003C
#define UDMA_O_ERRCLR 0x0000004C
#define UDMA_O_CHASGN 0x00000500
#define UDMA_O_CHIS 0x00000504
#define UDMA_O_CHMAP0 0x00000510
#define UDMA_O_CHMAP1 0x00000514
#define UDMA_O_CHMAP2 0x00000518
#define UDMA_O_CHMAP3 0x0000051C
#define UDMA_O_PV 0x00000FB0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_STAT register.
//
//******************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
#define UDMA_STAT_DMACHANS_S 16
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
// 0x00000090 : UDMA_STAT_STATE_DONE
// : Done 0x00000000 :
// UDMA_STAT_STATE_IDLE : Idle
// 0x00000010 :
// UDMA_STAT_STATE_RD_CTRL : Reading
// channel controller data
// 0x00000030 :
// UDMA_STAT_STATE_RD_DSTENDP :
// Reading destination end pointer
// 0x00000040 :
// UDMA_STAT_STATE_RD_SRCDAT :
// Reading source data 0x00000020 :
// UDMA_STAT_STATE_RD_SRCENDP :
// Reading source end pointer
// 0x00000080 :
// UDMA_STAT_STATE_STALL : Stalled
// 0x000000A0 :
// UDMA_STAT_STATE_UNDEF : Undefined
// 0x00000060 : UDMA_STAT_STATE_WAIT
// : Waiting for uDMA request to
// clear 0x00000070 :
// UDMA_STAT_STATE_WR_CTRL : Writing
// channel controller data
// 0x00000050 :
// UDMA_STAT_STATE_WR_DSTDAT :
// Writing destination data
#define UDMA_STAT_STATE_S 4
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CFG register.
//
//******************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CTLBASE register.
//
//******************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
#define UDMA_CTLBASE_ADDR_S 10
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTBASE register.
//
//******************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer
#define UDMA_ALTBASE_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_WAITSTAT register.
//
//******************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M \
0xFFFFFFFF // Channel [n] Wait Status
#define UDMA_WAITSTAT_WAITREQ_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SWREQ register.
//
//******************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
#define UDMA_SWREQ_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_O_USEBURSTSET register.
//
//******************************************************************************
#define UDMA_USEBURSTSET_SET_M \
0xFFFFFFFF // Channel [n] Useburst Set
#define UDMA_USEBURSTSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_O_USEBURSTCLR register.
//
//******************************************************************************
#define UDMA_USEBURSTCLR_CLR_M \
0xFFFFFFFF // Channel [n] Useburst Clear
#define UDMA_USEBURSTCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_REQMASKSET register.
//
//******************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
#define UDMA_REQMASKSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register.
//
//******************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
#define UDMA_REQMASKCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ENASET register.
//
//******************************************************************************
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
#define UDMA_ENASET_CHENSET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ENACLR register.
//
//******************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
#define UDMA_ENACLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTSET register.
//
//******************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
#define UDMA_ALTSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTCLR register.
//
//******************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
#define UDMA_ALTCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PRIOSET register.
//
//******************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
#define UDMA_PRIOSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PRIOCLR register.
//
//******************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
#define UDMA_PRIOCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ERRCLR register.
//
//******************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHASGN register.
//
//******************************************************************************
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
#define UDMA_CHASGN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHIS register.
//
//******************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
#define UDMA_CHIS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP0 register.
//
//******************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
#define UDMA_CHMAP0_CH0SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP1 register.
//
//******************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
#define UDMA_CHMAP1_CH8SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP2 register.
//
//******************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
#define UDMA_CHMAP2_CH16SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP3 register.
//
//******************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
#define UDMA_CHMAP3_CH24SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PV register.
//
//******************************************************************************
#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision
#define UDMA_PV_MAJOR_S 8
#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision
#define UDMA_PV_MINOR_S 0
#endif // __HW_UDMA_H__

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/*
* -------------------------------------------
* CC3220 SDK - v0.10.00.00
* -------------------------------------------
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_WDT_H__
#define __HW_WDT_H__
//*****************************************************************************
//
// The following are defines for the WDT register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000
#define WDT_O_VALUE 0x00000004
#define WDT_O_CTL 0x00000008
#define WDT_O_ICR 0x0000000C
#define WDT_O_RIS 0x00000010
#define WDT_O_MIS 0x00000014
#define WDT_O_TEST 0x00000418
#define WDT_O_LOCK 0x00000C00
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//******************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
#define WDT_LOAD_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//******************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
#define WDT_VALUE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//******************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit
// is not used in cc3xx, WDOG shall
// always generate RESET to system
// irrespective of this bit setting.
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//******************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
#define WDT_ICR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//******************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//******************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_TEST register.
//
//******************************************************************************
#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable
#define WDT_TEST_STALL_EN_S 10
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOCK register.
//
//******************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
#define WDT_LOCK_S 0
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
#define WDT_LOCK_LOCKED 0x00000001 // Locked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
// WDT_MIS registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
#endif // __HW_WDT_H__

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file ADC.h
*
* @brief ADC driver interface
*
* The ADC header file should be included in an application as follows:
* @code
* #include <ti/drivers/ADC.h>
* @endcode
*
* # Operation #
* The ADC driver operates as a simplified ADC module with only single channel
* sampling support. It also operates on blocking only mode which means users
* have to wait the current sampling finished before starting another sampling.
* The sampling channel needs to be specified in the ADC_open() before calling
* ADC_convert().
*
* The APIs in this driver serve as an interface to a typical TI-RTOS
* application. The specific peripheral implementations are responsible to
* create all the SYS/BIOS specific primitives to allow for thread-safe
* operation.
* User can use the ADC driver or the ADCBuf driver that has more features.
* But both ADC and ADCBuf cannot be used together in an application.
*
* ## Opening the driver #
*
* @code
* ADC_Handle adc;
* ADC_Params params;
*
* ADC_Params_init(&params);
* adc = ADC_open(Board_ADCCHANNEL_A0, &params);
* if (adc != NULL) {
* ADC_close(adc);
* }
* @endcode
*
* ## Converting #
* An ADC conversion with a ADC peripheral is started by calling ADC_convert().
* The result value is returned by ADC_convert() once the conversion is
* finished.
*
* @code
* int_fast16_t res;
* uint_fast16_t adcValue;
*
* res = ADC_convert(adc, &adcValue);
* if (res == ADC_STATUS_SUCCESS) {
* //use adcValue
* }
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* ADC_FxnTable.
*
* The ADC driver interface module is joined (at link time) to a
* NULL-terminated array of ADC_Config data structures named *ADC_config*.
* *ADC_config* is implemented in the application with each entry being an
* instance of a ADC peripheral. Each entry in *ADC_config* contains a:
* - (ADC_FxnTable *) to a set of functions that implement a ADC peripheral
* - (void *) data object that is associated with the ADC_FxnTable
* - (void *) hardware attributes that are associated to the ADC_FxnTable
*
* # Instrumentation #
* The ADC driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_ADC__include
#define ti_drivers_ADC__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/**
* @defgroup ADC_CONTROL ADC_control command and status codes
* These ADC macros are reservations for ADC.h
* @{
*/
/*!
* Common ADC_control command code reservation offset.
* ADC driver implementations should offset command codes with ADC_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0
* #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1
* @endcode
*/
#define ADC_CMD_RESERVED (32)
/*!
* Common ADC_control status code reservation offset.
* ADC driver implementations should offset status codes with
* ADC_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0
* #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1
* #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2
* @endcode
*/
#define ADC_STATUS_RESERVED (-32)
/*!
* @brief Successful status code returned by ADC_control().
*
* ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed
* successfully.
* @{
* @ingroup ADC_CONTROL
*/
#define ADC_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by ADC_control().
*
* ADC_control() returns ADC_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define ADC_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by ADC_control() for undefined
* command codes.
*
* ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define ADC_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup ADC_CMD Command Codes
* ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC
* driver implementations support these command codes.
* @{
* @ingroup ADC_CONTROL
*/
/* Add ADC_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from a ADC_open() call.
*/
typedef struct ADC_Config_ *ADC_Handle;
/*!
* @brief ADC Parameters
*
* ADC parameters are used to with the ADC_open() call. Only custom argument
* is supported in the parameters. Default values for these parameters are
* set using ADC_Params_init().
*
* @sa ADC_Params_init()
*/
typedef struct ADC_Params_ {
void *custom; /*!< Custom argument used by driver
implementation */
bool isProtected; /*!< By default ADC uses a semaphore
to guarantee thread safety. Setting
this parameter to 'false' will eliminate
the usage of a semaphore for thread
safety. The user is then responsible
for ensuring that parallel invocations
of ADC_convert() are thread safe. */
} ADC_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_close().
*/
typedef void (*ADC_CloseFxn) (ADC_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_control().
*/
typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_ConvertFxn().
*/
typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t *value);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_convertRawToMicroVolts().
*/
typedef uint32_t (*ADC_ConvertRawToMicroVolts) (ADC_Handle handle,
uint16_t rawAdcValue);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_init().
*/
typedef void (*ADC_InitFxn) (ADC_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_open().
*/
typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params *params);
/*!
* @brief The definition of a ADC function table that contains the
* required set of functions to control a specific ADC driver
* implementation.
*/
typedef struct ADC_FxnTable_ {
/*! Function to close the specified peripheral */
ADC_CloseFxn closeFxn;
/*! Function to perform implementation specific features */
ADC_ControlFxn controlFxn;
/*! Function to initiate a ADC single channel conversion */
ADC_ConvertFxn convertFxn;
/*! Function to convert raw ADC result to microvolts */
ADC_ConvertRawToMicroVolts convertRawToMicroVolts;
/*! Function to initialize the given data object */
ADC_InitFxn initFxn;
/*! Function to open the specified peripheral */
ADC_OpenFxn openFxn;
} ADC_FxnTable;
/*!
* @brief ADC Global configuration
*
* The ADC_Config structure contains a set of pointers used to characterize
* the ADC driver implementation.
*
* This structure needs to be defined before calling ADC_init() and it must
* not be changed thereafter.
*
* @sa ADC_init()
*/
typedef struct ADC_Config_ {
/*! Pointer to a table of driver-specific implementations of ADC APIs */
ADC_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} ADC_Config;
/*!
* @brief Function to close a ADC driver
*
* @pre ADC_open() has to be called first.
*
* @param handle An ADC handle returned from ADC_open()
*
* @sa ADC_open()
*/
extern void ADC_close(ADC_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* ADC_Handle.
*
* @pre ADC_open() has to be called first.
*
* @param handle A ADC handle returned from ADC_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param arg An optional R/W (read/write) argument that is
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa ADC_open()
*/
extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to perform ADC conversion
*
* Function to perform ADC single channel single sample conversion.
*
* @pre ADC_open() has been called
*
* @param handle An ADC_Handle
* @param value A pointer to the conversion result
*
* @return The return value indicates the conversion is succeeded or
* failed. The value could be ADC_STATUS_SUCCESS or
* ADC_STATUS_ERROR.
*
* @sa ADC_open()
* @sa ADC_close()
*/
extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value);
/*!
* @brief Function performs conversion from raw ADC result to actual value in
* microvolts.
*
* @pre ADC_open() and ADC_convert() has to be called first.
*
* @param handle A ADC handle returned from ADC_open()
*
* @param rawAdcValue A sampling result return from ADC_convert()
*
* @return The actual sampling result in micro volts unit.
*
* @sa ADC_open()
*/
extern uint32_t ADC_convertRawToMicroVolts(ADC_Handle handle,
uint16_t rawAdcValue);
/*!
* @brief Function to initializes the ADC driver
*
* @pre The ADC_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other ADC driver APIs.
*/
extern void ADC_init(void);
/*!
* @brief Function to initialize the ADC peripheral
*
* Function to initialize the ADC peripheral specified by the
* particular index value.
*
* @pre ADC_init() has been called
*
* @param index Logical peripheral number for the ADC indexed into
* the ADC_config table
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A ADC_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa ADC_init()
* @sa ADC_close()
*/
extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params);
/*!
* @brief Function to initialize the ADC_Params struct to its defaults
*
* @param params An pointer to ADC_Params structure for
* initialization
*
* Defaults values are:
* custom = NULL
*/
extern void ADC_Params_init(ADC_Params *params);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_ADC__include */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file ADCBuf.h
*
* @brief ADCBuf driver interface
*
* The ADCBuf header file should be included in an application as follows:
* @code
* #include <ti/drivers/ADCBuf.h>
* @endcode
*
* # Operation #
* The ADCBuf driver in TI-RTOS samples an analogue waveform at a specified
* frequency. The resulting samples are transferred to a buffer provided by
* the application. The driver can either take n samples once, or continuously
* sample by double-buffering and providing a callback to process each finished
* buffer.
*
* The APIs in this driver serve as an interface to a typical TI-RTOS
* application. The specific peripheral implementations are responsible to
* create all the SYS/BIOS specific primitives to allow for thread-safe
* operation.
* User can use the ADC driver or the ADCBuf driver. But both ADC and ADCBuf
* cannot be used together in an application.
*
* ## Opening the driver #
*
* @code
* ADCBuf_Handle adcBufHandle;
* ADCBuf_Params adcBufParams;
*
* ADCBuf_Params_init(&adcBufParams);
* adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams);
* @endcode
*
* ## Making a conversion #
* In this context, a conversion refers to taking multiple ADC samples and
* transferring them to an application-provided buffer.
* To start a conversion, the application must configure an ADCBuf_Conversion struct
* and call ADCBuf_convert(). In blocking mode, ADCBuf_convert() will return
* when the conversion is finished and the desired number of samples have been made.
* In callback mode, ADCBuf_convert() will return immediately and the application will
* get a callback when the conversion is done.
*
* @code
* ADCBuf_Conversion blockingConversion;
*
* blockingConversion.arg = NULL;
* blockingConversion.adcChannel = Board_ADCCHANNEL_A1;
* blockingConversion.sampleBuffer = sampleBufferOnePtr;
* blockingConversion.sampleBufferTwo = NULL;
* blockingConversion.samplesRequestedCount = ADCBUFFERSIZE;
*
* if (!ADCBuf_convert(adcBuf, &continuousConversion, 1)) {
* // handle error
* }
* @endcode
*
* ## Canceling a conversion #
* ADCBuf_convertCancel() is used to cancel an ADCBuf conversion when the driver is
* used in ::ADCBuf_RETURN_MODE_CALLBACK.
*
* Calling this API while no conversion is in progress has no effect. If a
* conversion is in progress, it is canceled and the provided callback function
* is called.
*
* In ::ADCBuf_RECURRENCE_MODE_CONTINUOUS, this function must be called to stop the
* conversion. The driver will continue providing callbacks with fresh samples
* until thie ADCBuf_convertCancel() function is called. The callback function is not
* called after ADCBuf_convertCancel() while in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS.
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS applications. Its
* purpose is to redirect the module's APIs to specific peripheral
* implementations which are specified using a pointer to an ADCBuf_FxnTable.
*
* The ADCBuf driver interface module is joined (at link time) to a
* NULL-terminated array of ADCBuf_Config data structures named *ADCBuf_config*.
* *ADCBuf_config* is implemented in the application with each entry being an
* instance of an ADCBuf peripheral. Each entry in *ADCBuf_config* contains a:
* - (ADCBuf_FxnTable *) to a set of functions that implement an ADCBuf peripheral
* - (void *) data object that is associated with the ADCBuf_FxnTable
* - (void *) hardware attributes that are associated to the ADCBuf_FxnTable
*
* # Instrumentation #
*
* The ADCBuf driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ---------------------------------|
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_adcbuf__include
#define ti_drivers_adcbuf__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/**
* @defgroup ADCBUF_CONTROL ADCBuf_control command and status codes
* These ADCBuf macros are reservations for ADCBuf.h
* @{
*/
/*!
* Common ADCBuf_control command code reservation offset.
* ADC driver implementations should offset command codes with ADCBuf_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0
* #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1
* @endcode
*/
#define ADCBuf_CMD_RESERVED (32)
/*!
* Common ADCBuf_control status code reservation offset.
* ADC driver implementations should offset status codes with
* ADCBuf_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0
* #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1
* #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2
* @endcode
*/
#define ADCBuf_STATUS_RESERVED (-32)
/*!
* \brief Success status code returned by:
* ADCBuf_control()
*
* Functions return ADCBuf_STATUS_SUCCESS if the call was executed
* successfully.
* @{
* @ingroup ADCBUF_CONTROL
*/
#define ADCBuf_STATUS_SUCCESS (0)
/*!
* \brief Generic error status code returned by ADCBuf_control().
*
* ADCBuf_control() returns ADCBuf_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define ADCBuf_STATUS_ERROR (-1)
/*!
* \brief An error status code returned by ADCBuf_control() for undefined
* command codes.
*
* ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define ADCBuf_STATUS_UNDEFINEDCMD (-2)
/*!
* \brief An error status code returned by ADCBuf_adjustRawValues() if the
* function is not supported by a particular driver implementation.
*
* ADCBuf_adjustRawValues() returns ADCBuf_STATUS_UNSUPPORTED if the function is
* not supported by the driver implementation.
*/
#define ADCBuf_STATUS_UNSUPPORTED (-3)
/** @}*/
/**
* @defgroup ADCBUF_CMD Command Codes
* ADCBUF_CMD_* macros are general command codes for I2C_control(). Not all ADCBuf
* driver implementations support these command codes.
* @{
* @ingroup ADCBUF_CONTROL
*/
/* Add ADCBUF_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an ADCBuf_open() call.
*/
typedef struct ADCBuf_Config_ *ADCBuf_Handle;
/*!
* @brief
* An ::ADCBuf_Conversion data structure is used with ADCBuf_convert(). It indicates
* which channel to perform the ADC conversion on, how many conversions to make, and where to put them.
* The arg variable is an user-definable argument which gets passed to the
* ::ADCBuf_Callback when the ADC driver is in ::ADCBuf_RETURN_MODE_CALLBACK.
*/
typedef struct ADCBuf_Conversion_ {
uint16_t samplesRequestedCount; /*!< Number of samples to convert and return */
void *sampleBuffer; /*!< Buffer the results of the conversions are stored in */
void *sampleBufferTwo; /*!< A second buffer that is filled in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS mode while
the first buffer is processed by the application. The value is not used in
::ADCBuf_RECURRENCE_MODE_ONE_SHOT mode. */
void *arg; /*!< Argument to be passed to the callback function in ::ADCBuf_RETURN_MODE_CALLBACK */
uint32_t adcChannel; /*!< Channel to perform the ADC conversion on. Mapping of channel to pin or internal signal is device specific. */
} ADCBuf_Conversion;
/*!
* @brief The definition of a callback function used by the ADC driver
* when used in ::ADCBuf_RETURN_MODE_CALLBACK. It is called in a HWI or SWI context depending on the device specific implementation.
*/
typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle,
ADCBuf_Conversion *conversion,
void *completedADCBuffer,
uint32_t completedChannel);
/*!
* @brief ADC trigger mode settings
*
* This enum defines if the driver should make n conversions and return
* or run indefinitely and run a callback function every n conversions.
*/
typedef enum ADCBuf_Recurrence_Mode_ {
/*!
* The driver makes n measurements and returns or runs a callback function depending
* on the ::ADCBuf_Return_Mode setting.
*/
ADCBuf_RECURRENCE_MODE_ONE_SHOT,
/*!
* The driver makes n measurements and then runs a callback function. This process happens
* until the application calls ::ADCBuf_ConvertCancelFxn(). This setting can only be used in
* ::ADCBuf_RETURN_MODE_CALLBACK.
*/
ADCBuf_RECURRENCE_MODE_CONTINUOUS
} ADCBuf_Recurrence_Mode;
/*!
* @brief ADC return mode settings
*
* This enum defines how the ADCBuf_convert() function returns.
* It either blocks or returns immediately and calls a callback function when the provided buffer has been filled.
*/
typedef enum ADCBuf_Return_Mode_ {
/*!
* Uses a semaphore to block while ADC conversions are performed. Context of the call
* must be a Task.
*
* @note Blocking return mode cannot be used in combination with ::ADCBuf_RECURRENCE_MODE_CONTINUOUS
*/
ADCBuf_RETURN_MODE_BLOCKING,
/*!
* Non-blocking and will return immediately. When the conversion
* is finished the configured callback function is called.
*/
ADCBuf_RETURN_MODE_CALLBACK
} ADCBuf_Return_Mode;
/*!
* @brief ADC Parameters
*
* ADC Parameters are used to with the ADCBuf_open() call. Default values for
* these parameters are set using ADCBuf_Params_init().
*
* @sa ADCBuf_Params_init()
*/
typedef struct ADCBuf_Params_ {
uint32_t blockingTimeout; /*!< Timeout for semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */
uint32_t samplingFrequency; /*!< The frequency at which the ADC will produce a sample */
ADCBuf_Return_Mode returnMode; /*!< Return mode for all conversions */
ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */
ADCBuf_Recurrence_Mode recurrenceMode; /*!< One-shot or continuous conversion */
void *custom; /*!< Pointer to a device specific extension of the ADCBuf_Params */
} ADCBuf_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_close().
*/
typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_open().
*/
typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle,
const ADCBuf_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_control().
*/
typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle,
uint_fast8_t cmd,
void *arg);
/*
* @brief A function pointer to a driver specific implementation of
* ADCBuf_init().
*/
typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convert().
*/
typedef int_fast16_t (*ADCBuf_ConvertFxn) (ADCBuf_Handle handle,
ADCBuf_Conversion conversions[],
uint_fast8_t channelCount);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convertCancel().
*/
typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_GetResolution();
*/
typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_adjustRawValues();
*/
typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle,
void *sampleBuffer,
uint_fast16_t sampleCount,
uint32_t adcChannel);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convertAdjustedToMicroVolts();
*/
typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) (ADCBuf_Handle handle,
uint32_t adcChannel,
void *adjustedSampleBuffer,
uint32_t outputMicroVoltBuffer[],
uint_fast16_t sampleCount);
/*!
* @brief The definition of an ADCBuf function table that contains the
* required set of functions to control a specific ADC driver
* implementation.
*/
typedef struct ADCBuf_FxnTable_ {
/*! Function to close the specified peripheral */
ADCBuf_CloseFxn closeFxn;
/*! Function to driver implementation specific control function */
ADCBuf_ControlFxn controlFxn;
/*! Function to initialize the given data object */
ADCBuf_InitFxn initFxn;
/*! Function to open the specified peripheral */
ADCBuf_OpenFxn openFxn;
/*! Function to start an ADC conversion with the specified peripheral */
ADCBuf_ConvertFxn convertFxn;
/*! Function to abort a conversion being carried out by the specified peripheral */
ADCBuf_ConvertCancelFxn convertCancelFxn;
/*! Function to get the resolution in bits of the ADC */
ADCBuf_GetResolutionFxn getResolutionFxn;
/*! Function to adjust raw ADC return bit values to values comparable between devices of the same type */
ADCBuf_adjustRawValuesFxn adjustRawValuesFxn;
/*! Function to convert adjusted ADC values to microvolts */
ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn;
} ADCBuf_FxnTable;
/*!
* @brief ADCBuf Global configuration
*
* The ADCBuf_Config structure contains a set of pointers used to characterise
* the ADC driver implementation.
*
* This structure needs to be defined before calling ADCBuf_init() and it must
* not be changed thereafter.
*
* @sa ADCBuf_init()
*/
typedef struct ADCBuf_Config_ {
/*! Pointer to a table of driver-specific implementations of ADC APIs */
const ADCBuf_FxnTable *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} ADCBuf_Config;
/*!
* @brief Function to close an ADC peripheral specified by the ADC handle
*
* @pre ADCBuf_open() has to be called first.
*
* @pre In ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call ADCBuf_convertCancel() first.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @sa ADCBuf_open()
*/
extern void ADCBuf_close(ADCBuf_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* ADCBuf_Handle.
*
* @pre ADCBuf_open() has to be called first.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param cmdArg A pointer to an optional R/W (read/write) argument that
* is accompanied with cmd
*
* @return An ADCBuf_Status describing an error or success state. Negative values
* indicates an error.
*
* @sa ADCBuf_open()
*/
extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg);
/*!
* @brief This function initializes the ADC module. This function must
*
* @pre The ADCBuf_Config structure must exist and be persistent before this
* function can be called.
* This function call does not modify any peripheral registers.
* Function should only be called once.
*/
extern void ADCBuf_init(void);
/*!
* @brief This function sets all fields of a specified ADCBuf_Params structure to their
* default values.
*
* @param params A pointer to ADCBuf_Params structure for initialization
*
* Default values are:
* returnMode = ADCBuf_RETURN_MODE_BLOCKING,
* blockingTimeout = 25000,
* callbackFxn = NULL,
* recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT,
* samplingFrequency = 10000,
* custom = NULL
*
* ADCBuf_Params::blockingTimeout should be set large enough to allow for the desired number of samples to be
* collected with the specified frequency.
*/
extern void ADCBuf_Params_init(ADCBuf_Params *params);
/*!
* @brief This function opens a given ADCBuf peripheral.
*
* @param index Logical peripheral number for the ADCBuf indexed into
* the ADCBuf_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values.
*
* @return An ADCBuf_Handle on success or a NULL on an error or if it has been
* opened already. If NULL is returned further ADC API calls will
* result in undefined behaviour.
*
* @sa ADCBuf_close()
*/
extern ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params);
/*!
* @brief This function starts a set of conversions on one or more channels.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param conversions A pointer to an array of ADCBuf_Conversion structs with the specific parameters
* for each channel. Only use one ADCBuf_Conversion struct per channel.
*
* @param channelCount The number of channels to convert on in this call. Should be the length of the conversions array.
* Depending on the device, multiple simultaneous conversions may not be supported. See device
* specific implementation.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*
* @sa ADCBuf_convertCancel()
*/
extern int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount);
/*!
* @brief This function cancels an ADC conversion that is in progress.
*
* This function must be called before calling ADCBuf_close().
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @sa ADCBuf_convert()
*/
extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle);
/*!
* @brief This function returns the resolution in bits of the specified ADC.
*
* @param handle An ADCBuf handle returned from ADCBuf_open().
*
* @return The resolution in bits of the specified ADC.
*
* @pre ADCBuf_open() must have been called prior.
*/
extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle);
/*!
* @brief This function adjusts a raw ADC output buffer such that the result is comparable between devices of the same make.
* The function does the adjustment in-place.
*
* @param handle An ADCBuf handle returned from ADCBuf_open().
*
* @param sampleBuf A buffer full of raw sample values.
*
* @param sampleCount The number of samples to adjust.
*
* @param adcChan The channel the buffer was sampled on.
*
* @return A buffer full of adjusted samples contained in sampleBuffer.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*/
extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan);
/*!
* @brief This function converts a raw ADC output value to a value scaled in micro volts.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param adcChan The ADC channel the samples stem from. This parameter is only necessary for certain devices.
* See device specific implementation for details.
*
* @param adjustedSampleBuffer A buffer full of adjusted samples.
*
* @param outputMicroVoltBuffer The output buffer. The conversion does not occur in place due to the differing data type sizes.
*
* @param sampleCount The number of samples to convert.
*
* @return A number of measurements scaled in micro volts inside outputMicroVoltBuffer.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*
* @pre ADCBuf_adjustRawValues() must be called on adjustedSampleBuffer prior.
*/
extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChan, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_adcbuf__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file Camera.h
*
* @brief Camera driver interface
*
* The Camera header file should be included in an application as follows:
* @code
* #include <ti/drivers/Camera.h>
* @endcode
*
* # Overview #
* The Camera driver is used to retrieve the data being transferred by the
* Camera sensor.
* This driver provides an API for capturing the image from the Camera sensor.
* The camera sensor control and implementation are the responsibility of the
* application using the interface.
*
* The Camera driver has been designed to operate in an RTOS environment. It
* protects its transactions with OS primitives supplied by the underlying
* RTOS.
*
* # Usage #
*
* The Camera driver includes the following APIs:
* - Camera_init(): Initialize the Camera driver.
* - Camera_Params_init(): Initialize a #Camera_Params structure with default
* vaules.
* - Camera_open(): Open an instance of the Camera driver.
* - Camera_control(): Performs implemenation-specific features on a given
* Camera peripheral.
* - Camera_capture(): Capture a frame.
* - Camera_close(): De-initialize a given Camera instance.
*
*
* ### Camera Driver Configuration #
*
* In order to use the Camera APIs, the application is required
* to provide device-specific Camera configuration in the Board.c file.
* The Camera driver interface defines a configuration data structure:
*
* @code
* typedef struct Camera_Config_ {
* Camera_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } Camera_Config;
* @endcode
*
* The application must declare an array of Camera_Config elements, named
* Camera_config[]. Each element of Camera_config[] must be populated with
* pointers to a device specific Camera driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the Camera peripheral's base address.
* Each element in Camera_config[] corresponds to
* a Camera instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as Camera0 or Camera1). For example, it
* is possible to use Camera_config[0] for Camera1.
*
* Because the Camera configuration is very device dependent, you will need to
* check the doxygen for the device specific Camera implementation. There you
* will find a description of the Camera hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the Camera
* configuration.
*
* ### Initializing the Camear Driver #
* The application initializes the Camera driver by calling Camera_init().
* This function must be called before any other Camera API. Camera_init()
* iterates through the elements of the Camera_config[] array, calling
* the element's device implementation Camera initialization function.
* ### Camera Parameters
*
* The #Camera_Params structure is passed to Camera_open(). If NULL
* is passed for the parameters, Camera_open() uses default parameters.
* A #Camera_Params structure is initialized with default values by passing
* it to Camera_Params_init().
* Some of the Camera parameters are described below. To see brief descriptions
* of all the parameters, see #Camera_Params.
*
* #### Camera Modes
* The Camera driver operates in either blocking mode or callback mode:
* - #Camera_MODE_BLOCKING: The call to Camera_capture() blocks until the
* capture has completed.
* - #Camera_MODE_CALLBACK: The call to Camera_capture() returns immediately.
* When the capture completes, the Camera driver will call a user-
* specified callback function.
*
* The capture mode is determined by the #Camera_Params.captureMode parameter
* passed to Camera_open(). The Camera driver defaults to blocking mode, if the
* application does not set it.
*
* Once a Camera driver instance is opened, the only way
* to change the capture mode is to close and re-open the Camera
* instance with the new capture mode.
*
* ### Opening the driver #
* The following example opens a Camera driver instance in blocking mode:
* @code
* Camera_Handle handle;
* Camera_Params params;
*
* Camera_Params_init(&params);
* params.captureMode = Camera_MODE_BLOCKING;
* < Change any other params as required >
*
* handle = Camera_open(someCamera_configIndexValue, &params);
* if (!handle) {
* // Error opening the Camera driver
* }
* @endcode
*
* ### Capturing an Image #
*
* The following code example captures a frame.
*
* @code
* unsigned char captureBuffer[1920];
*
* ret = Camera_capture(handle, &captureBuffer, sizeof(captureBuffer));
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* #Camera_FxnTable.
*
* The Camera driver interface module is joined (at link time) to an
* array of #Camera_Config data structures named *Camera_config*.
* *Camera_config* is implemented in the application with each entry being an
* instance of a Camera peripheral. Each entry in *Camera_config* contains a:
* - (Camera_FxnTable *) to a set of functions that implement a Camera
* peripheral
* - (void *) data object that is associated with the Camera_FxnTable
* - (void *) hardware attributes that are associated to the Camera_FxnTable
*
*******************************************************************************
*/
#ifndef ti_drivers_Camera__include
#define ti_drivers_Camera__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/**
* @defgroup CAMERA_CONTROL Camera_control command and status codes
* These Camera macros are reservations for Camera.h
* @{
*/
/*!
* Common Camera_control command code reservation offset.
* Camera driver implementations should offset command codes with
* CAMERA_CMD_RESERVED growing positively
*
* Example implementation specific command codes:
* @code
* #define CAMERAXYZ_CMD_COMMAND0 CAMERA_CMD_RESERVED + 0
* #define CAMERAXYZ_CMD_COMMAND1 CAMERA_CMD_RESERVED + 1
* @endcode
*/
#define CAMERA_CMD_RESERVED (32)
/*!
* Common Camera_control status code reservation offset.
* Camera driver implementations should offset status codes with
* CAMERA_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define CAMERAXYZ_STATUS_ERROR0 CAMERA_STATUS_RESERVED - 0
* #define CAMERAXYZ_STATUS_ERROR1 CAMERA_STATUS_RESERVED - 1
* #define CAMERAXYZ_STATUS_ERROR2 CAMERA_STATUS_RESERVED - 2
* @endcode
*/
#define CAMERA_STATUS_RESERVED (-32)
/**
* @defgroup Camera_STATUS Status Codes
* Camera_STATUS_* macros are general status codes returned by Camera_control()
* @{
* @ingroup Camera_CONTROL
*/
/*!
* @brief Successful status code returned by Camera_control().
*
* Camera_control() returns CAMERA_STATUS_SUCCESS if the control code was
* executed successfully.
*/
#define CAMERA_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by Camera_control().
*
* Camera_control() returns CAMERA_STATUS_ERROR if the control code was not
* executed successfully.
*/
#define CAMERA_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by Camera_control() for undefined
* command codes.
*
* Camera_control() returns CAMERA_STATUS_UNDEFINEDCMD if the control code is
* not recognized by the driver implementation.
*/
#define CAMERA_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup Camera_CMD Command Codes
* Camera_CMD_* macros are general command codes for Camera_control(). Not all
* Camera driver implementations support these command codes.
* @{
* @ingroup Camera_CONTROL
*/
/* Add Camera_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief Wait forever define
*/
#define Camera_WAIT_FOREVER (~(0U))
/*!
* @brief A handle that is returned from a Camera_open() call.
*/
typedef struct Camera_Config_ *Camera_Handle;
/*!
* @brief The definition of a callback function used by the Camera driver
* when used in ::Camera_MODE_CALLBACK
*
* @param Camera_Handle Camera_Handle
*
* @param buf Pointer to capture buffer
*
* @param frameLength length of frame
*
*/
typedef void (*Camera_Callback) (Camera_Handle handle, void *buf,
size_t frameLength);
/*!
* @brief Camera capture mode settings
*
* This enum defines the capture mode for the
* configured Camera.
*/
typedef enum Camera_CaptureMode_ {
/*!
* Uses a semaphore to block while data is being sent. Context of
* the call must be a Task.
*/
Camera_MODE_BLOCKING,
/*!
* Non-blocking and will return immediately. When the capture
* by the interrupt is finished the configured callback function
* is called.
*/
Camera_MODE_CALLBACK
} Camera_CaptureMode;
/*!
* @brief Camera HSync polarity
*
* This enum defines the polarity of the HSync signal.
*/
typedef enum Camera_HSyncPolarity_ {
Camera_HSYNC_POLARITY_HIGH = 0,
Camera_HSYNC_POLARITY_LOW
} Camera_HSyncPolarity;
/*!
* @brief Camera VSync polarity
*
* This enum defines the polarity of the VSync signal.
*/
typedef enum Camera_VSyncPolarity_ {
Camera_VSYNC_POLARITY_HIGH = 0,
Camera_VSYNC_POLARITY_LOW
} Camera_VSyncPolarity;
/*!
* @brief Camera pixel clock configuration
*
* This enum defines the pixel clock configuration.
*/
typedef enum Camera_PixelClkConfig_ {
Camera_PCLK_CONFIG_RISING_EDGE = 0,
Camera_PCLK_CONFIG_FALLING_EDGE
} Camera_PixelClkConfig;
/*!
* @brief Camera byte order
*
* This enum defines the byte order of camera capture.
*
* In normal mode, the byte order is:
* | byte3 | byte2 | byte1 | byte0 |
*
* In swap mode, the bytes are ordered as:
* | byte2 | byte3 | byte0 | byte1 |
*/
typedef enum Camera_ByteOrder_ {
Camera_BYTE_ORDER_NORMAL = 0,
Camera_BYTE_ORDER_SWAP
} Camera_ByteOrder;
/*!
* @brief Camera interface synchronization
*
* This enum defines the sensor to camera interface synchronization
* configuration.
*/
typedef enum Camera_IfSynchoronisation_ {
Camera_INTERFACE_SYNC_OFF = 0,
Camera_INTERFACE_SYNC_ON
} Camera_IfSynchoronisation;
/*!
* @brief Camera stop capture configuration
*
* This enum defines the stop capture configuration.
*/
typedef enum Camera_StopCaptureConfig_ {
Camera_STOP_CAPTURE_IMMEDIATE = 0,
Camera_STOP_CAPTURE_FRAME_END
} Camera_StopCaptureConfig;
/*!
* @brief Camera start capture configuration
*
* This enum defines the start capture configuration.
*/
typedef enum Camera_StartCaptureConfig_ {
Camera_START_CAPTURE_IMMEDIATE = 0,
Camera_START_CAPTURE_FRAME_START
} Camera_StartCaptureConfig;
/*!
* @brief Camera Parameters
*
* Camera parameters are used to with the Camera_open() call.
* Default values for these parameters are set using Camera_Params_init().
*
* If Camera_CaptureMode is set to Camera_MODE_BLOCKING then Camera_capture
* function calls will block thread execution until the capture has completed.
*
* If Camera_CaptureMode is set to Camera_MODE_CALLBACK then Camera_capture
* will not block thread execution and it will call the function specified by
* captureCallbackFxn.
*
* @sa Camera_Params_init()
*/
typedef struct Camera_Params_ {
/*!< Mode for camera capture */
Camera_CaptureMode captureMode;
/*!< Output clock to set divider */
uint32_t outputClock;
/*!< Polarity of Hsync */
Camera_HSyncPolarity hsyncPolarity;
/*!< Polarity of VSync */
Camera_VSyncPolarity vsyncPolarity;
/*!< Pixel clock configuration */
Camera_PixelClkConfig pixelClkConfig;
/*!< camera capture byte order */
Camera_ByteOrder byteOrder;
/*!< Camera-Sensor synchronization */
Camera_IfSynchoronisation interfaceSync;
/*!< Camera stop configuration */
Camera_StopCaptureConfig stopConfig;
/*!< Camera start configuration */
Camera_StartCaptureConfig startConfig;
/*!< Timeout for capture semaphore */
uint32_t captureTimeout;
/*!< Pointer to capture callback */
Camera_Callback captureCallback;
/*!< Custom argument used by driver implementation */
void *custom;
} Camera_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_close().
*/
typedef void (*Camera_CloseFxn) (Camera_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_control().
*/
typedef int_fast16_t (*Camera_ControlFxn) (Camera_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_init().
*/
typedef void (*Camera_InitFxn) (Camera_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_open().
*/
typedef Camera_Handle (*Camera_OpenFxn) (Camera_Handle handle,
Camera_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_capture().
*/
typedef int_fast16_t (*Camera_CaptureFxn) (Camera_Handle handle, void *buffer,
size_t bufferlen, size_t *frameLen);
/*!
* @brief The definition of a Camera function table that contains the
* required set of functions to control a specific Camera driver
* implementation.
*/
typedef struct Camera_FxnTable_ {
/*! Function to close the specified peripheral */
Camera_CloseFxn closeFxn;
/*! Function to implementation specific control function */
Camera_ControlFxn controlFxn;
/*! Function to initialize the given data object */
Camera_InitFxn initFxn;
/*! Function to open the specified peripheral */
Camera_OpenFxn openFxn;
/*! Function to initiate a Camera capture */
Camera_CaptureFxn captureFxn;
} Camera_FxnTable;
/*!
* @brief Camera Global configuration
*
* The Camera_Config structure contains a set of pointers used to characterize
* the Camera driver implementation.
*
* This structure needs to be defined before calling Camera_init() and it must
* not be changed thereafter.
*
* @sa Camera_init()
*/
typedef struct Camera_Config_ {
/*! Pointer to a table of driver-specific implementations of Camera APIs */
Camera_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} Camera_Config;
/*!
* @brief Function to close a Camera peripheral specified by the Camera handle
*
* @pre Camera_open() had to be called first.
*
* @param handle A Camera_Handle returned from Camera_open
*
* @sa Camera_open()
*/
extern void Camera_close(Camera_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* Camera_Handle.
*
* Commands for Camera_control can originate from Camera.h or from
* implementation specific Camera*.h (_CameraCC32XX.h_, etc.. ) files.
* While commands from Camera.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific Camera*.h files add
* unique driver capabilities but are not API portable across all Camera driver
* implementations.
*
* Commands supported by Camera.h follow a Camera_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by Camera*.h follow a Camera*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref Camera_CMD "Camera_control command codes" for command codes.
*
* See @ref Camera_STATUS "Camera_control return status codes" for status codes.
*
* @pre Camera_open() has to be called first.
*
* @param handle A Camera handle returned from Camera_open()
*
* @param cmd Camera.h or Camera*.h commands.
*
* @param arg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa Camera_open()
*/
extern int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initializes the Camera module
*
* @pre The Camera_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other Camera driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void Camera_init(void);
/*!
* @brief Function to initialize a given Camera peripheral specified by the
* particular index value. The parameter specifies which mode the
* Camera will operate.
*
* @pre Camera controller has been initialized
*
* @param index Logical peripheral number for the Camera indexed into
* the Camera_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A Camera_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa Camera_init()
* @sa Camera_close()
*/
extern Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params);
/*!
* @brief Function to initialize the Camera_Params structure to its defaults
*
* @param params An pointer to Camera_Params structure for
* initialization
*
* Defaults values are:
* captureMode = Camera_MODE_BLOCKING;
* outputClock = 24000000;
* hsyncPolarity = Camera_HSYNC_POLARITY_HIGH;
* vsyncPolarity = Camera_VSYNC_POLARITY_HIGH;
* pixelClkConfig = Camera_PCLK_CONFIG_RISING_EDGE;
* byteOrder = Camera_BYTE_ORDER_NORMAL;
* interfaceSync = Camera_INTERFACE_SYNC_ON;
* stopConfig = Camera_STOP_CAPTURE_FRAME_END;
* startConfig = Camera_START_CAPTURE_FRAME_START;
* captureTimeout = Camera_WAIT_FOREVER;
* captureCallback = NULL;
*/
extern void Camera_Params_init(Camera_Params *params);
/*!
* @brief Function that handles the Camera capture of a frame.
*
* In Camera_MODE_BLOCKING, Camera_capture will block task execution until
* the capture is complete.
*
* In Camera_MODE_CALLBACK, Camera_capture does not block task execution
* and calls a callback function specified by captureCallbackFxn.
* The Camera buffer must stay persistent until the Camera_capture
* function has completed!
*
* @param handle A Camera_Handle
*
* @param buffer A pointer to a WO (write-only) buffer into which the
* captured frame is placed
*
* @param bufferlen Length (in bytes) of the capture buffer
*
* @param frameLen Pointer to return number of bytes captured.
*
* @return CAMERA_STATUS_SUCCESS on successful capture, CAMERA_STATUS_ERROR if
* if otherwise.
*
* @sa Camera_open
*/
extern int_fast16_t Camera_capture(Camera_Handle handle, void *buffer,
size_t bufferlen, size_t *frameLen);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_Camera__include */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file Capture.h
*
* @brief Capture driver interface
*
* The Capture header file should be included in an application as follows:
* @code
* #include <ti/drivers/Capture.h>
* @endcode
*
* # Operation #
* The Capture driver facilitates the capture routines by using general purpose
* timers. Capture instances must be opened by calling Capture_open() while
* passing in a Capture index and parameters data structure.
*
* When a capture instance is opened, the capture triggering edge and callback
* function are configured. The capture is stopped after calling Capture_open()
* until Capture_start() is called.
*
* When Capture_open() is called, it tries to occupy the user-specified timer by
* calling Timer_open(). If that timer is already allocated for other modules,
* NULL is returned. Otherwise, the Capture_Handle is returned.
* A capture is triggered based on the user-specified capture mode:
* - CAPTURE_MODE_RISING_RISING
* - CAPTURE_MODE_RISING_FALLING
* - CAPTURE_MODE_ANY_EDGE
* The user-specified callback function is called once the input signal matches
* the capture mode and the value passed into callback function is the interval
* between two triggering edge in the user-specified unit.
*
* ## opening the driver ##
*
* @code
* Capture_Handle handle;
* Capture_Params params;
*
* Capture_Params_init(&params);
* params.mode = CAPTURE_MODE_RISING_FALLING;
* params.callbackFxn = someCaptureCallbackFunction;
* params.periodUnit = CAPTURE_PERIOD_US;
* handle = Capture_open(someCapture_configIndexValue, &params);
* if (!handle)
* {
* System_printf("Capture did not open");
* }
*
* ## starting the driver ##
* @code
* status = Capture_start(handle);
* if (status == Capture_STATUS_ERROR)
* {
* System_printf("Capture cannot start");
* }
* @endcode
*
* ## stoping the driver ##
*
* @code
* Capture_stop(handle);
* @endcode
*
* ## closing the driver ##
*
* @code
* Capture_close(handle);
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* Capture_FxnTable.
*
* The Capture driver interface module is joined (at link time) to a
* NULL-terminated array of Capture_Config data structures named *Capture_Config*.
* *Capture_Config* is implemented in the application with each entry being an
* instance of a Capture module. Each entry in *Capture_Config* contains a:
* - (Capture_FxnTable *) to a set of functions that implement a Capture module
* - (void *) data object that is associated with the Capture_FxnTable
* - (void *) hardware attributes that are associated to the Capture_FxnTable
*
* # Instrumentation #
* The Capture driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_Capture__include
#define ti_drivers_Capture__include
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
/*!
* @brief A handle that is returned from a Capture_open() call.
*/
typedef struct Capture_Config_ *Capture_Handle;
/*!
* Common Capture_control command code reservation offset.
* Capture driver implementations should offset command codes with CAPTURE_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define CAPTUREXYZ_CMD_COMMAND0 CAPTURE_CMD_RESERVED + 0
* #define CAPTUREXYZ_CMD_COMMAND1 CAPTURE_CMD_RESERVED + 1
* @endcode
*/
#define CAPTURE_CMD_RESERVED (32)
/*!
* Common Capture_control status code reservation offset.
* Capture driver implementations should offset status codes with
* CAPTURE_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define CAPTUREXYZ_STATUS_ERROR0 CAPTURE_STATUS_RESERVED - 0
* #define CAPTUREXYZ_STATUS_ERROR1 CAPTURE_STATUS_RESERVED - 1
* #define CAPTUREXYZ_STATUS_ERROR2 CAPTURE_STATUS_RESERVED - 2
* @endcode
*/
#define CAPTURE_STATUS_RESERVED (-32)
/*!
* @brief Successful status code returned by Capture_control().
*
* Capture_control() returns TIMER_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define CAPTURE_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by Capture_control().
*
* Capture_control() returns CAPTURE_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define CAPTURE_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by Capture_control() for undefined
* command codes.
*
* Capture_control() returns TIMER_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define CAPTURE_STATUS_UNDEFINEDCMD (-2)
/*!
* @brief Capture period unit enum
*
* The Capture period unit needs to be passed in Capture_open() to
* specify the unit of two capture triggering interval.
*
*/
typedef enum Capture_Period_Unit_ {
CAPTURE_PERIOD_US, /* Period in microseconds */
CAPTURE_PERIOD_HZ, /* Period in frequency */
CAPTURE_PERIOD_COUNTS, /* Period in counts */
} Capture_Period_Unit;
/*!
* @brief Capture mode enum
*
* The Capture mode needs to be passed in Capture_open() to specify the capture
* triggering mode.
*
*/
typedef enum Capture_Mode_ {
CAPTURE_MODE_RISING_RISING, /*!< capture is triggered at the rising edge followed by the rising edge */
CAPTURE_MODE_FALLING_FALLING, /*!< capture is triggered at the falling edge followed by the falling edge */
CAPTURE_MODE_ANY_EDGE
/*!< capture is triggered at the falling edge followed by the rising edge */
} Capture_Mode;
/*!
* @brief Capture callback function
*
* User definable callback function prototype. The Capture driver will call the
* defined function and pass in the Capture driver's handle and the pointer to the
* user-specified the argument.
*
* @param handle Capture_Handle
*
* @param interval Interval of two triggering edge in Capture_Period_Unit
*
*/
typedef void (*Capture_CallBackFxn)(Capture_Handle handle, uint32_t interval);
/*!
* @brief Capture Parameters
*
* Capture parameters are used to with the Capture_open() call. Default values for
* these parameters are set using Capture_Params_init().
*
*/
typedef struct Capture_Params_ {
Capture_Mode mode; /*!< Capture triggering mode */
Capture_CallBackFxn callbackFxn; /*!< Callback function pointer */
Capture_Period_Unit periodUnit; /*!< Period unit */
} Capture_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_close().
*/
typedef void (*Capture_CloseFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_control().
*/
typedef int_fast16_t (*Capture_ControlFxn)(Capture_Handle handle,
uint_fast16_t cmd, void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_init().
*/
typedef void (*Capture_InitFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_open().
*/
typedef Capture_Handle (*Capture_OpenFxn)(Capture_Handle handle,
Capture_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_start().
*/
typedef void (*Capture_StartFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_stop().
*/
typedef void (*Capture_StopFxn)(Capture_Handle handle);
/*!
* @brief The definition of a Capture function table that contains the
* required set of functions to control a specific Capture driver
* implementation.
*/
typedef struct Capture_FxnTable_ {
/*! Function to close the specified peripheral */
Capture_CloseFxn closeFxn;
/*! Function to send control commands to the specified peripheral */
Capture_ControlFxn controlFxn;
/*! Function to initialize the specified peripheral */
Capture_InitFxn initFxn;
/*! Function to open the specified peripheral */
Capture_OpenFxn openFxn;
/*! Function to start the specified peripheral */
Capture_StartFxn startFxn;
/*! Function to stop the specified peripheral */
Capture_StopFxn stopFxn;
} Capture_FxnTable;
typedef struct Capture_Config_ {
Capture_FxnTable const *fxnTablePtr;
void *object;
void const *hwAttrs;
} Capture_Config;
/*!
* @brief Function to close a Capture module specified by the Capture handle
*
* The function takes care of timer resource allocation. The corresponding timer
* resource to the Capture_Handle is released to be an available timer resource.
*
* @pre Capture_open() had to be called first.
*
* @param handle A Capture_Handle returned from Capture_open
*
* @sa Capture_open()
*/
extern void Capture_close(Capture_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* Capture_Handle.
*
* @pre Capture_open() must have been called first.
*
* @param handle A Capture_Handle returned from Capture_open().
*
* @param cmd A command value defined by the driver specific
* implementation.
*
* @param arg A pointer to an optional R/W (read/write) argument that
* is accompanied with cmd.
*
* @return A Capture_Status describing an error or success state. Negative values
* indicate an error occurred.
*
* @sa Capture_open()
*/
extern int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initialize Capture.
*/
extern void Capture_init(void);
/*!
* @brief Function to initialize a given Capture module specified by the
* particular index value. The parameter specifies which mode the Capture
* will operate.
*
* The function takes care of timer resource allocation. If the particular timer
* passed by user has already been used by other modules, the return value is NULL.
* If the particular timer is available to use, Capture module owns it and returns
* a Capture_Handle.
*
* @param index Logical instance number for the Capture indexed into
* the Capture_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A Capture_Handle on success or a NULL on an error if it has been
* opened already or used by other modules.
*
* @sa Capture_init()
* @sa Capture_close()
*/
extern Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params);
/*!
* @brief Function to initialize the Capture_Params struct to its defaults
*
* @param params An pointer to Capture_Params structure for
* initialization
*
* Defaults values are:
* mode = CAPTURE_MODE_RISING_RISING
* callbackFxn = user_specified_callbackFxn
* periodUnit = Capture_PERIOD_COUNTS
*/
extern void Capture_Params_init(Capture_Params *params);
/*!
* @brief Function to start capture. The Capture running mode
* and interval period unit are specfied in the Capture_Params when calling
* Capture_open().
*
* @param handle Capture_Handle
*
* @return CAPTURE_STATUS_SUCCESS if Capture starts successfully.
* CAPTURE_STATUS_ERROR if Capture fails to start.
*
*/
extern void Capture_start(Capture_Handle handle);
/*!
* @brief Function to stop Capture after Capture_start() is called with success.
*
* @param handle Capture_Handle
*
*/
extern void Capture_stop(Capture_Handle handle);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_Capture__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file GPIO.h
*
* @brief GPIO driver
*
* The GPIO header file should be included in an application as follows:
* @code
* #include <ti/drivers/GPIO.h>
* @endcode
*
* # Overview #
* The GPIO module allows you to manage General Purpose I/O pins via simple
* and portable APIs. GPIO pin behavior is usually configured statically,
* but can also be configured or reconfigured at runtime.
*
* Because of its simplicity, the GPIO driver does not follow the model of
* other TI-RTOS drivers in which a driver application interface has
* separate device-specific implementations. This difference is most
* apparent in the GPIOxxx_Config structure, which does not require you to
* specify a particular function table or object.
*
* # Usage #
* The following code example demonstrates how
* to configure a GPIO pin to generate an interrupt and how to toggle an
* an LED on and off within the registered interrupt callback function.
*
* @code
* #include <stdint.h>
* #include <stddef.h>
*
* // Driver Header file
* #include <ti/drivers/GPIO.h>
*
* // Example/Board Header file
* #include "Board.h"
*
* main()
* {
* // Call GPIO driver init function
* GPIO_init();
*
* // Turn on user LED
* GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON);
*
* // install Button callback
* GPIO_setCallback(Board_GPIO_BUTTON0, gpioButtonFxn0);
*
* // Enable interrupts
* GPIO_enableInt(Board_GPIO_BUTTON0);
*
* ...
* }
*
* //
* // ======== gpioButtonFxn0 ========
* // Callback function for the GPIO interrupt on Board_GPIO_BUTTON0.
* //
* void gpioButtonFxn0(unsigned int index)
* {
* // Toggle the LED
* GPIO_toggle(Board_GPIO_LED0);
* }
*
* @endcode
*
* Details for the example code above are described in the following
* subsections.
*
* ### GPIO Driver Configuration #
*
* In order to use the GPIO APIs, the application is required
* to provide 3 structures in the Board.c file:
* 1. An array of @ref GPIO_PinConfig elements that defines the
* initial configuration of each pin used by the application. A
* pin is referenced in the application by its corresponding index in this
* array. The pin type (that is, INPUT/OUTPUT), its initial state (that is
* OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and
* device specific pin identification are configured in each element
* of this array (see @ref GPIO_PinConfigSettings).
* Below is an MSP432 device specific example of the GPIO_PinConfig array:
* @code
* //
* // Array of Pin configurations
* // NOTE: The order of the pin configurations must coincide with what was
* // defined in MSP_EXP432P401R.h
* // NOTE: Pins not used for interrupts should be placed at the end of the
* // array. Callback entries can be omitted from callbacks array to
* // reduce memory usage.
* //
* GPIO_PinConfig gpioPinConfigs[] = {
* // Input pins
* // MSP_EXP432P401R_GPIO_S1
* GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING,
* // MSP_EXP432P401R_GPIO_S2
* GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING,
*
* // Output pins
* // MSP_EXP432P401R_GPIO_LED1
* GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
* // MSP_EXP432P401R_GPIO_LED_RED
* GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
* };
* @endcode
*
* 2. An array of @ref GPIO_CallbackFxn elements that is used to store
* callback function pointers for GPIO pins configured with interrupts.
* The indexes for these array elements correspond to the pins defined
* in the GPIO_pinConfig array. These function pointers can be defined
* statically by referencing the callback function name in the array
* element, or dynamically, by setting the array element to NULL and using
* GPIO_setCallback() at runtime to plug the callback entry.
* Pins not used for interrupts can be omitted from the callback array to
* reduce memory usage (if they are placed at the end of GPIO_pinConfig
* array). The callback function syntax should match the following:
* @code
* void (*GPIO_CallbackFxn)(unsigned int index);
* @endcode
* The index parameter is the same index that was passed to
* GPIO_setCallback(). This allows the same callback function to be used
* for multiple GPIO interrupts, by using the index to identify the GPIO
* that caused the interrupt.
* Keep in mind that the callback functions will be called in the context of
* an interrupt service routine and should be designed accordingly. When an
* interrupt is triggered, the interrupt status of all (interrupt enabled) pins
* on a port will be read, cleared, and the respective callbacks will be
* executed. Callbacks will be called in order from least significant bit to
* most significant bit.
* Below is an MSP432 device specific example of the GPIO_CallbackFxn array:
* @code
* //
* // Array of callback function pointers
* // NOTE: The order of the pin configurations must coincide with what was
* // defined in MSP_EXP432P401R.h
* // NOTE: Pins not used for interrupts can be omitted from callbacks array
* // to reduce memory usage (if placed at end of gpioPinConfigs
* // array).
* //
* GPIO_CallbackFxn gpioCallbackFunctions[] = {
* // MSP_EXP432P401R_GPIO_S1
* NULL,
* // MSP_EXP432P401R_GPIO_S2
* NULL
* };
* @endcode
*
* 3. A device specific GPIOxxx_Config structure that tells the GPIO
* driver where the two aforementioned arrays are and the number of elements
* in each. The interrupt priority of all pins configured to generate
* interrupts is also specified here. Values for the interrupt priority are
* device-specific. You should be well-acquainted with the interrupt
* controller used in your device before setting this parameter to a
* non-default value. The sentinel value of (~0) (the default value) is
* used to indicate that the lowest possible priority should be used.
* Below is an MSP432 device specific example of a GPIOxxx_Config
* structure:
* @code
* //
* // MSP432 specific GPIOxxx_Config structure
* //
* const GPIOMSP432_Config GPIOMSP432_config = {
* .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs,
* .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions,
* .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig),
* .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn),
* .intPriority = (~0)
* };
* @endcode
*
* ### Initializing the GPIO Driver #
*
* GPIO_init() must be called before any other GPIO APIs. This function
* configures each GPIO pin in the user-provided @ref GPIO_PinConfig
* array according to the defined settings. The user can also reconfigure
* a pin dynamically after GPIO_init() is called by using the
* GPIO_setConfig(), and GPIO_setCallback() APIs.
*
* # Implementation #
*
* Unlike most other TI-RTOS drivers, the GPIO driver has no generic function
* table with pointers to device-specific API implementations. All the generic
* GPIO APIs are implemented by the device-specific GPIO driver module.
* Additionally, there is no notion of an instance 'handle' with the GPIO driver.
* GPIO pins are referenced by their numeric index in the GPIO_PinConfig array.
* This design approach was used to enhance runtime and memory efficiency.
*
* ============================================================================
*/
#ifndef ti_drivers_GPIO__include
#define ti_drivers_GPIO__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs.
* @{
*/
/*!
* @brief Common GPIO status code reservation offset.
*
* GPIO driver implementations should offset status codes with
* GPIO_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define GPIOTXYZ_STATUS_ERROR1 GPIO_STATUS_RESERVED - 1
* #define GPIOTXYZ_STATUS_ERROR0 GPIO_STATUS_RESERVED - 0
* #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2
* @endcode
*/
#define GPIO_STATUS_RESERVED (-32)
/*!
* @brief Successful status code returned by GPI_setConfig().
*
* GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed
* successfully.
*/
#define GPIO_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by GPI_setConfig().
*
* GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed
* successfully.
*/
#define GPIO_STATUS_ERROR (-1)
/** @}*/
/*!
* @brief GPIO pin configuration settings
*
* The upper 16 bits of the 32 bit PinConfig is reserved
* for pin configuration settings.
*
* The lower 16 bits are reserved for device-specific
* port/pin identifications
*/
typedef uint32_t GPIO_PinConfig;
/*!
* @cond NODOC
* Internally used configuration bit access macros.
*/
#define GPIO_CFG_IO_MASK 0x00ff0000
#define GPIO_CFG_IO_LSB 16
#define GPIO_CFG_OUT_TYPE_MASK 0x00060000
#define GPIO_CFG_OUT_TYPE_LSB 17
#define GPIO_CFG_IN_TYPE_MASK 0x00060000
#define GPIO_CFG_IN_TYPE_LSB 17
#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000
#define GPIO_CFG_OUT_STRENGTH_LSB 20
#define GPIO_CFG_INT_MASK 0x07000000
#define GPIO_CFG_INT_LSB 24
#define GPIO_CFG_OUT_BIT 19
/*! @endcond */
/*!
* \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins
* @{
*/
/** @name GPIO_PinConfig output pin configuration macros
* @{
*/
#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */
#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */
#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */
#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */
#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */
#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to low */
#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to medium */
#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to high */
#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */
#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */
/** @} */
/** @name GPIO_PinConfig input pin configuration macros
* @{
*/
#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */
#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */
#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */
#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */
/** @} */
/** @name GPIO_PinConfig interrupt configuration macros
* @{
*/
#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */
#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */
#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */
#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */
#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */
#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */
/** @} */
/** @name Special GPIO_PinConfig configuration macros
* @{
*/
/*!
* @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig()
* to only configure the interrupt attributes of a GPIO input pin.
*/
#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */
/*!
* @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init()
* NOT to configure the corresponding pin
*/
#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */
/** @} */
/** @} end of GPIO_PinConfigSettings group */
/*!
* @brief GPIO callback function type
*
* @param index GPIO index. This is the same index that
* was passed to GPIO_setCallback(). This allows
* you to use the same callback function for multiple
* GPIO interrupts, by using the index to identify
* the GPIO that caused the interrupt.
*/
typedef void (*GPIO_CallbackFxn)(uint_least8_t index);
/*!
* @brief Clear a GPIO pin interrupt flag
*
* Clears the GPIO interrupt for the specified index.
*
* Note: It is not necessary to call this API within a
* callback assigned to a pin.
*
* @param index GPIO index
*/
extern void GPIO_clearInt(uint_least8_t index);
/*!
* @brief Disable a GPIO pin interrupt
*
* Disables interrupts for the specified GPIO index.
*
* @param index GPIO index
*/
extern void GPIO_disableInt(uint_least8_t index);
/*!
* @brief Enable a GPIO pin interrupt
*
* Enables GPIO interrupts for the selected index to occur.
*
* Note: Prior to enabling a GPIO pin interrupt, make sure
* that a corresponding callback function has been provided.
* Use the GPIO_setCallback() API for this purpose at runtime.
* Alternatively, the callback function can be statically
* configured in the GPIO_CallbackFxn array provided.
*
* @param index GPIO index
*/
extern void GPIO_enableInt(uint_least8_t index);
/*!
* @brief Get the current configuration for a gpio pin
*
* The pin configuration is provided in the static GPIO_PinConfig array,
* but can be changed with GPIO_setConfig(). GPIO_getConfig() gets the
* current pin configuration.
*
* @param index GPIO index
* @param pinConfig Location to store device specific pin
* configuration settings
*/
extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig);
/*!
* @brief Initializes the GPIO module
*
* The pins defined in the application-provided *GPIOXXX_config* structure
* are initialized accordingly.
*
* @pre The GPIO_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other GPIO driver APIs.
*/
extern void GPIO_init();
/*!
* @brief Reads the value of a GPIO pin
*
* The value returned will either be zero or one depending on the
* state of the pin.
*
* @param index GPIO index
*
* @return 0 or 1, depending on the state of the pin.
*/
extern uint_fast8_t GPIO_read(uint_least8_t index);
/*!
* @brief Bind a callback function to a GPIO pin interrupt
*
* Associate a callback function with a particular GPIO pin interrupt.
*
* Callbacks can be changed at any time, making it easy to switch between
* efficient, state-specific interrupt handlers.
*
* Note: The callback function is called within the context of an interrupt
* handler.
*
* Note: This API does not enable the GPIO pin interrupt.
* Use GPIO_enableInt() and GPIO_disableInt() to enable
* and disable the pin interrupt as necessary.
*
* Note: it is not necessary to call GPIO_clearInt() within a callback.
* That operation is performed internally before the callback is invoked.
*
* @param index GPIO index
* @param callback address of the callback function
*/
extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback);
/*!
* @brief Configure the gpio pin
*
* Dynamically configure a gpio pin to a device specific setting.
* For many applications, the pin configurations provided in the static
* GPIO_PinConfig array is sufficient.
*
* For input pins with interrupt configurations, a corresponding interrupt
* object will be created as needed.
*
* @param index GPIO index
* @param pinConfig device specific pin configuration settings
*/
extern int_fast16_t GPIO_setConfig(uint_least8_t index,
GPIO_PinConfig pinConfig);
/*!
* @brief Toggles the current state of a GPIO
*
* @param index GPIO index
*/
extern void GPIO_toggle(uint_least8_t index);
/*!
* @brief Writes the value to a GPIO pin
*
* @param index GPIO index
* @param value must be either 0 or 1
*/
extern void GPIO_write(uint_least8_t index, unsigned int value);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_GPIO__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file I2C.h
*
* @brief I2C driver interface
*
* The I2C driver interface provides device independent APIs, data types,
* and macros. The I2C header file should be included in an application as
* follows:
* @code
* #include <ti/drivers/I2C.h>
* @endcode
*
* # Overview #
* This section assumes that you have background knowledge and understanding
* about how the I2C protocol operates. For the full I2C specifications and
* user manual (UM10204), see the NXP Semiconductors website.
*
* The I2C driver has been designed to operate as a single I2C master by
* performing I2C transactions between the target and I2C slave peripherals.
* The I2C driver does not support I2C slave mode.
* I2C is a communication protocol - the specifications define how data
* transactions are to occur via the I2C bus. The specifications do not
* define how data is to be formatted or handled, allowing for flexible
* implementations across different peripheral vendors. As a result, the
* I2C handles only the exchange of data (or transactions) between master
* and slaves. It is the left to the application to interpret and
* manipulate the contents of each specific I2C peripheral.
*
* The I2C driver has been designed to operate in an RTOS environment. It
* protects its transactions with OS primitives supplied by the underlying
* RTOS.
*
* # Usage #
*
* The I2C driver includes the following APIs:
* - I2C_init(): Initialize the I2C driver.
* - I2C_Params_init(): Initialize an #I2C_Params structure with default
* vaules.
* - I2C_open(): Open an instance of the I2C driver.
* - I2C_control(): Performs implemenation-specific features on a given
* I2C peripheral.
* - I2C_transfer(): Transfer the data.
* - I2C_close(): De-initialize the I2C instance.
*
*
* ### I2C Driver Configuration #
*
* In order to use the I2C APIs, the application is required
* to provide device-specific I2C configuration in the Board.c file.
* The I2C driver interface defines a configuration data structure:
*
* @code
* typedef struct I2C_Config_ {
* I2C_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } I2C_Config;
* @endcode
*
* The application must declare an array of I2C_Config elements, named
* I2C_config[]. Each element of I2C_config[] must be populated with
* pointers to a device specific I2C driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the I2C peripheral's base address and
* pins. Each element in I2C_config[] corresponds to
* an I2C instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as I2C0 or I2C1). For example, it is
* possible to use I2C_config[0] for I2C1.
*
* Because the I2C configuration is very device dependent, you will need to
* check the doxygen for the device specific I2C implementation. There you
* will find a description of the I2C hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the I2C
* configuration.
*
* ### Initializing the I2C Driver #
*
* I2C_init() must be called before any other I2C APIs. This function
* iterates through the elements of the I2C_config[] array, calling
* the element's device implementation I2C initialization function.
*
* ### I2C Parameters
*
* The #I2C_Params structure is passed to the I2C_open() call. If NULL
* is passed for the parameters, I2C_open() uses default parameters.
* An #I2C_Params structure is initialized with default values by passing
* it to I2C_Params_init().
* Some of the I2C parameters are described below. To see brief descriptions
* of all the parameters, see #I2C_Params.
*
* #### I2C Transfer Mode
* The I2C driver supports two transfer modes of operation: blocking and
* callback:
* - #I2C_MODE_BLOCKING: The call to I2C_transfer() blocks until the
* transfer completes.
* - #I2C_MODE_CALLBACK: The call to I2C_transfer() returns immediately.
* When the transfer completes, the I2C driver will call a user-
* specified callback function.
*
* The transfer mode is determined by the #I2C_Params.transferMode parameter
* passed to I2C_open(). The I2C driver defaults to blocking mode, if the
* application does not set it.
*
* In blocking mode, a task calling I2C_transfer() is blocked until the
* transaction completes. Other tasks requesting I2C transactions while
* a transaction is currently taking place, are also placed into a
* blocked state.
*
* In callback mode, an I2C_transfer() functions asynchronously, which
* means that it does not block a calling task's execution. In this
* mode, the user must set #I2C_Params.transferCallbackFxn to a user-
* provided callback function. After an I2C transaction has completed,
* the I2C driver calls the user- provided callback function.
* If another I2C transaction is requested, the transaction is queued up.
* As each transfer completes, the I2C driver will call the user-specified
* callback function. The user callback will be called from either hardware
* or software interrupt context, depending upon the device implementation.
*
* Once an I2C driver instance is opened, the
* only way to change the transfer mode is to close and re-open the I2C
* instance with the new transfer mode.
*
* #### Specifying an I2C Bus Frequency
* The I2C controller's bus frequency is determined by #I2C_Params.bitRate
* passed to I2C_open(). The standard I2C bus frequencies are 100 kHz and
* 400 kHz, with 100 kHz being the default.
*
* ### Opening the I2C Driver #
* After initializing the I2C driver by calling I2C_init(), the application
* can open an I2C instance by calling I2C_open(). This function
* takes an index into the I2C_config[] array and an I2C parameters data
* structure. The I2C instance is specified by the index of the I2C in
* I2C_config[]. Only one I2C index can be used at a time;
* calling I2C_open() a second time with the same index previosly
* passed to I2C_open() will result in an error. You can,
* though, re-use the index if the instance is closed via I2C_close().
*
* If no I2C_Params structure is passed to I2C_open(), default values are
* used. If the open call is successful, it returns a non-NULL value.
*
* Example opening an I2C driver instance in blocking mode:
* @code
* I2C_Handle i2c;
*
* // NULL params are used, so default to blocking mode, 100 KHz
* i2c = I2C_open(Board_I2C0, NULL);
*
* if (!i2c) {
* // Error opening the I2C
* }
* @endcode
*
* Example opening an I2C driver instance in callback mode and 400KHz bit rate:
*
* @code
* I2C_Handle i2c;
* I2C_Params params;
*
* I2C_Params_init(&params);
* params.transferMode = I2C_MODE_CALLBACK;
* params.transferCallbackFxn = myCallbackFunction;
* params.bitRate = I2C_400kHz;
*
* handle = I2C_open(Board_I2C0, &params);
* if (!i2c) {
* // Error opening I2C
* }
* @endcode
*
* ### Transferring data #
* An I2C transaction with an I2C peripheral is started by calling
* I2C_transfer(). Three types of transactions are supported: Write, Read,
* or Write/Read. Each transfer is completed before another transfer is
* initiated.
*
* For Write/Read transactions, the specified data is first written to the
* peripheral, then a repeated start is sent by the driver, which initiates
* the read operation. This type of transfer is useful if an I2C peripheral
* has a pointer register that needs to be adjusted prior to reading from
* the referenced data register.
*
* The details of each transaction are specified with an #I2C_Transaction data
* structure. This structure defines the slave I2C address, pointers
* to write and read buffers, and their associated byte counts. If
* no data needs to be written or read, the corresponding byte counts should
* be set to zero.
*
* If an I2C transaction is requested while a transaction is currently
* taking place, the new transaction is placed onto a queue to be processed
* in the order in which it was received.
*
* The below example shows sending three bytes of data to a slave peripheral
* at address 0x50, in blocking mode:
*
* @code
* unsigned char writeBuffer[3];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = writeBuffer;
* i2cTransaction.writeCount = 3;
* i2cTransaction.readBuf = NULL;
* i2cTransaction.readCount = 0;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* The next example shows reading of five bytes of data from the I2C
* peripheral, also in blocking mode:
*
* @code
* unsigned char readBuffer[5];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = NULL;
* i2cTransaction.writeCount = 0;
* i2cTransaction.readBuf = readBuffer;
* i2cTransaction.readCount = 5;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* This example shows writing of two bytes and reading of four bytes in a
* single transaction.
*
* @code
* unsigned char readBuffer[4];
* unsigned char writeBuffer[2];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = writeBuffer;
* i2cTransaction.writeCount = 2;
* i2cTransaction.readBuf = readBuffer;
* i2cTransaction.readCount = 4;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* This final example shows usage of asynchronous callback mode, with queuing
* of multiple transactions. Because multiple transactions are simultaneously
* queued, separate I2C_Transaction structures must be used. (This is a
* general rule, that I2C_Transaction structures cannot be reused until
* it is known that the previous transaction has completed.)
*
* First, for the callback function (that is specified in the I2C_open() call)
* the "arg" in the I2C_Transaction structure is a SemaphoreP_Handle; when
* this value is non-NULL, SemaphoreP_post() is called in the callback using
* the specified handle, to signal completion to the task that queued the
* transactions:
*
* @code
* Void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, Bool transfer) {
* if (msg->arg != NULL) {
* SemaphoreP_post((SemaphoreP_Handle)(msg->arg));
* }
* }
* @endcode
*
* Snippets of the task code that initiates the transactions are shown below.
* Note the use of multiple I2C_Transaction structures, and passing of the
* handle of the semaphore to be posted via i2cTransaction2.arg.
* I2C_transfer() is called three times to initiate each transaction.
* Since callback mode is used, these functions return immediately. After
* the transactions have been queued, other work can be done, and then
* eventually SemaphoreP_pend() is called to wait for the last I2C
* transaction to complete. Once the callback posts the semaphore, the task
* will be moved to the ready state, so the task can resume execution, after
* the SemaphoreP_pend() call.
*
* @code
* Void taskfxn(arg0, arg1) {
*
* I2C_Transaction i2cTransaction0;
* I2C_Transaction i2cTransaction1;
* I2C_Transaction i2cTransaction2;
*
* ...
* i2cTransaction0.arg = NULL;
* i2cTransaction1.arg = NULL;
* i2cTransaction2.arg = semaphoreHandle;
*
* ...
* I2C_transfer(i2c, &i2cTransaction0);
* I2C_transfer(i2c, &i2cTransaction1);
* I2C_transfer(i2c, &i2cTransaction2);
*
* ...
*
* SemaphoreP_pend(semaphoreHandle);
*
* ...
* }
* @endcode
*
* # Implementation #
*
* This top-level I2C module serves as the main interface for RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to an
* #I2C_FxnTable.
*
* The I2C driver interface module is joined (at link time) to an
* array of I2C_Config data structures named *I2C_config*.
* *I2C_config* is typically defined in the Board.c file used for the
* application. If there are multiple instances of I2C peripherals on the
* device, there will typically be multiple I2C_Config structures defined in
* the board file. Each entry in *I2C_config* contains a:
* - (I2C_FxnTable *) to a set of functions that implement a I2C peripheral
* - (void *) data object that is associated with the I2C_FxnTable
* - (void *) hardware attributes that are associated to the I2C_FxnTable
*
*******************************************************************************
*/
#ifndef ti_drivers_I2C__include
#define ti_drivers_I2C__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/**
* @defgroup I2C_CONTROL I2C_control command and status codes
* These I2C macros are reservations for I2C.h
* @{
*/
/*!
* Common I2C_control command code reservation offset.
* I2C driver implementations should offset command codes with I2C_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define I2CXYZ_CMD_COMMAND0 I2C_CMD_RESERVED + 0
* #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1
* @endcode
*/
#define I2C_CMD_RESERVED (32)
/*!
* Common I2C_control status code reservation offset.
* I2C driver implementations should offset status codes with
* I2C_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0
* #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1
* #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2
* @endcode
*/
#define I2C_STATUS_RESERVED (-32)
/**
* @defgroup I2C_STATUS Status Codes
* I2C_STATUS_* macros are general status codes returned by I2C_control()
* @{
* @ingroup I2C_CONTROL
*/
/*!
* @brief Successful status code returned by I2C_control().
*
* I2C_control() returns I2C_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define I2C_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by I2C_control().
*
* I2C_control() returns I2C_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define I2C_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by I2C_control() for undefined
* command codes.
*
* I2C_control() returns I2C_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define I2C_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup I2C_CMD Command Codes
* I2C_CMD_* macros are general command codes for I2C_control(). Not all I2C
* driver implementations support these command codes.
* @{
* @ingroup I2C_CONTROL
*/
/* Add I2C_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an I2C_open() call.
*/
typedef struct I2C_Config_ *I2C_Handle;
/*!
* @brief I2C transaction
*
* This structure defines an I2C transaction. It specifies the buffer(s) and
* buffer size(s) to be written to and/or read from an I2C slave peripheral.
* arg is an optional user-supplied argument that will be passed
* to the user-supplied callback function when the I2C driver is in
* I2C_MODE_CALLBACK.
* nextPtr is a pointer used internally by the driver for queuing of multiple
* transactions; this value must never be modified by the user application.
*/
typedef struct I2C_Transaction_ {
void *writeBuf; /*!< Buffer containing data to be written */
size_t writeCount; /*!< Number of bytes to be written to the slave */
void *readBuf; /*!< Buffer to which data is to be read into */
size_t readCount; /*!< Number of bytes to be read from the slave */
uint_least8_t slaveAddress; /*!< Address of the I2C slave peripheral */
void *arg; /*!< Argument to be passed to the callback function */
void *nextPtr; /*!< Used for queuing in I2C_MODE_CALLBACK mode */
} I2C_Transaction;
/*!
* @brief I2C transfer mode
*
* I2C_MODE_BLOCKING blocks task execution while an I2C transfer is in
* progress.
* I2C_MODE_CALLBACK does not block task execution, but calls a callback
* function when the I2C transfer has completed.
*/
typedef enum I2C_TransferMode_ {
I2C_MODE_BLOCKING, /*!< I2C_transfer() blocks execution */
I2C_MODE_CALLBACK /*!< I2C_transfer() does not block */
} I2C_TransferMode;
/*!
* @brief I2C callback function
*
* User-definable callback function prototype. The I2C driver will call this
* callback upon transfer completion, specifying the I2C handle for the
* transfer (as returned from I2C_open()), the pointer to the I2C_Transaction
* that just completed, and the return value of I2C_transfer(). Note that
* this return value will be the same as if the transfer were performed in
* blocking mode.
*
* @param I2C_Handle I2C_Handle
* @param I2C_Transaction* Address of the I2C_Transaction
* @param bool Result of the I2C transfer
*/
typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction,
bool transferStatus);
/*!
* @brief I2C bitRate
*
* Specifies one of the standard I2C bus bit rates for I2C communications.
* The default is I2C_100kHz.
*/
typedef enum I2C_BitRate_ {
I2C_100kHz = 0,
I2C_400kHz = 1
} I2C_BitRate;
/*!
* @brief I2C Parameters
*
* I2C parameters are used with the I2C_open() call. Default values for
* these parameters are set using I2C_Params_init().
*
* If I2C_TransferMode is set to I2C_MODE_BLOCKING, I2C_transfer() function
* calls will block thread execution until the transaction has completed. In
* this case, the transferCallbackFxn parameter will be ignored.
*
* If I2C_TransferMode is set to I2C_MODE_CALLBACK, I2C_transfer() will not
* block thread execution, but it will call the function specified by
* transferCallbackFxn upon transfer completion. Sequential calls to
* I2C_transfer() in I2C_MODE_CALLBACK will put the I2C_Transaction structures
* onto an internal queue that automatically starts queued transactions after
* the previous transaction has completed. This queuing occurs regardless of
* any error state from previous transactions.
*
* I2C_BitRate specifies the I2C bus rate used for I2C communications.
*
* @sa I2C_Params_init()
*/
typedef struct I2C_Params_ {
I2C_TransferMode transferMode; /*!< Blocking or Callback mode */
I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */
I2C_BitRate bitRate; /*!< I2C bus bit rate */
void *custom; /*!< Custom argument used by driver
implementation */
} I2C_Params;
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_cancel().
*/
typedef void (*I2C_CancelFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_close().
*/
typedef void (*I2C_CloseFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_control().
*/
typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd,
void *controlArg);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_init().
*/
typedef void (*I2C_InitFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_open().
*/
typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params *params);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_transfer().
*/
typedef bool (*I2C_TransferFxn) (I2C_Handle handle,
I2C_Transaction *transaction);
/*!
* @brief The definition of an I2C function table that contains the
* required set of functions to control a specific I2C driver
* implementation.
*/
typedef struct I2C_FxnTable_ {
/*! Cancel all I2C data transfers */
I2C_CancelFxn cancelFxn;
/*! Close the specified peripheral */
I2C_CloseFxn closeFxn;
/*! Implementation-specific control function */
I2C_ControlFxn controlFxn;
/*! Initialize the given data object */
I2C_InitFxn initFxn;
/*! Open the specified peripheral */
I2C_OpenFxn openFxn;
/*! Initiate an I2C data transfer */
I2C_TransferFxn transferFxn;
} I2C_FxnTable;
/*!
* @brief I2C global configuration
*
* The I2C_Config structure contains a set of pointers used to characterize
* the I2C driver implementation.
*
* This structure needs to be defined before calling I2C_init() and it must
* not be changed thereafter.
*
* @sa I2C_init()
*/
typedef struct I2C_Config_ {
/*! Pointer to a table of driver-specific implementations of I2C APIs */
I2C_FxnTable const *fxnTablePtr;
/*! Pointer to a driver-specific data object */
void *object;
/*! Pointer to a driver-specific hardware attributes structure */
void const *hwAttrs;
} I2C_Config;
/*!
* @brief Cancel all I2C transfers
*
* This function will cancel asynchronous I2C_transfer() operations, and is
* applicable only for I2C_MODE_CALLBACK. An in progress transfer, as well
* as any queued transfers will be canceled. The individual callback functions
* for each transfer will be called from the context that I2C_cancel() is
* called.
*
* @pre I2C_Transfer() has been called.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @note Different I2C slave devices will behave differently when an
* in-progress transfer fails and needs to be canceled. The slave
* may need to be reset, or there may be other slave-specific
* steps that can be used to successfully resume communication.
*
* @sa I2C_transfer()
*/
extern void I2C_cancel(I2C_Handle handle);
/*!
* @brief Close an I2C peripheral specified by an I2C_Handle
*
* @pre I2C_open() has been called.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @sa I2C_open()
*/
extern void I2C_close(I2C_Handle handle);
/*!
* @brief Perform implementation-specific features on a given
* I2C_Handle.
*
* Commands for I2C_control() can originate from I2C.h or from implementation
* specific I2C*.h (I2CCC26XX.h_, I2CMSP432.h_, etc.) files.
* While commands from I2C.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific I2C*.h files add
* unique driver capabilities but are not API portable across all I2C driver
* implementations.
*
* Commands supported by I2C.h follow a I2C_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by I2C*.h follow a I2C*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref I2C_CMD "I2C_control command codes" for command codes.
*
* See @ref I2C_STATUS "I2C_control return status codes" for status codes.
*
* @pre I2C_open() has to be called first.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @param cmd I2C.h or I2C*.h command.
*
* @param controlArg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation-specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa I2C_open()
*/
extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd,
void *controlArg);
/*!
* @brief Initializes the I2C module
*
* @pre The I2C_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other I2C driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void I2C_init(void);
/*!
* @brief Initialize a given I2C peripheral as identified by an index value.
* The I2C_Params structure defines the operating mode, and any
* related settings.
*
* @pre The I2C controller has been initialized, via a previous call to
* I2C_init()
*
* @param index Logical peripheral number for the I2C indexed into
* the I2C_config table
*
* @param params Pointer to a parameter block. Default values will be
* used if NULL is specified for params. All the fields
* in this structure are are considered RO (read-only).
*
* @return An I2C_Handle on success, or NULL on an error, or if the peripheral
* is already opened.
*
* @sa I2C_init()
* @sa I2C_close()
*/
extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params);
/*!
* @brief Initialize an I2C_Params struct to its defaults
*
* @param params A pointer to I2C_Params structure for
* initialization
*
* Defaults values are:
* transferMode = I2C_MODE_BLOCKING
* transferCallbackFxn = NULL
* bitRate = I2C_100kHz
*/
extern void I2C_Params_init(I2C_Params *params);
/*!
* @brief Perform an I2C transaction with an I2C slave peripheral.
*
* This function will perform an I2C transfer, as specified by an
* I2C_Transaction structure.
*
* An I2C transaction may write data to a peripheral, or read data from a
* peripheral, or both write and read data, in a single transaction. If there
* is any data to be written, it will always be sent before any data is read
* from the peripheral.
*
* The data written to the peripheral is preceded with the peripheral's 7-bit
* I2C slave address (with the Write bit set).
* After all the data has been transmitted, the driver will evaluate if any
* data needs to be read from the device.
* If yes, another START bit is sent, along with the same 7-bit I2C slave
* address (with the Read bit). After the specified number of bytes have been
* read, the transfer is ended with a NACK and a STOP bit. Otherwise, if
* no data is to be read, the transfer is concluded with a STOP bit.
*
* In I2C_MODE_BLOCKING, I2C_transfer() will block thread execution until the
* transaction completes. Therefore, this function must only be called from an
* appropriate thread context (e.g., Task context for the TI-RTOS kernel).
*
* In I2C_MODE_CALLBACK, the I2C_transfer() call does not block thread
* execution. Instead, a callback function (specified during I2C_open(), via
* the transferCallbackFxn field in the I2C_Params structure) is called when
* the transfer completes. Success or failure of the transaction is reported
* via the callback function's bool argument. If a transfer is already in
* progress, the new transaction is put on an internal queue. The driver
* services the queue in a first come first served basis.
*
* @param handle An I2C_Handle
*
* @param transaction A pointer to an I2C_Transaction. All of the fields
* within the transaction structure should be considered
* write only, unless otherwise noted in the driver
* implementation.
*
* @note The I2C_Transaction structure must persist unmodified until the
* corresponding call to I2C_transfer() has completed.
*
* @return In I2C_MODE_BLOCKING: true for a successful transfer; false for an
* error (for example, an I2C bus fault (NACK)).
*
* In I2C_MODE_CALLBACK: always true. The transferCallbackFxn's bool
* argument will be true to indicate success, and false to indicate
* an error.
*
* @sa I2C_open
*/
extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_I2C__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file I2CSlave.h
*
* @brief I2CSlave driver interface
*
* The I2CSlave header file should be included in an application as follows:
* @code
* #include <ti/drivers/I2CSlave.h>
* @endcode
*
* # Operation #
* The I2CSlave driver operates as a slave on an I2C bus in either
* I2CSLAVE_MODE_BLOCKING or I2CSLAVE_MODE_CALLBACK.
* In blocking mode, the task's execution is blocked during the I2CSlave
* read/write transfer. When the transfer has completed, code execution will
* resume. In callback mode, the task's execution is not blocked, allowing
* for other transactions to be queued up or to process some other code. When
* the transfer has completed, the I2CSlave driver will call a user-specified
* callback function (from a HWI context).
*
* The APIs in this driver serve as an interface to a typical TI-RTOS
* application. The specific peripheral implementations are responsible to
* create all the SYS/BIOS specific primitives to allow for thread-safe
* operation.
*
* ## Opening the driver #
*
* @code
* I2CSlave_Handle handle;
* I2CSlave_Params params;
*
* I2CSlave_Params_init(&params);
* params.transferMode = I2CSLAVE_MODE_CALLBACK;
* params.transferCallbackFxn = someI2CSlaveCallbackFunction;
* handle = I2CSlave_open(someI2CSlave_configIndexValue, &params);
* if (!handle) {
* System_printf("I2CSlave did not open");
* }
* @endcode
*
* ## Transferring data #
* A I2CSlave transaction with a I2CSlave peripheral is started by calling
* I2CSlave_read() or I2CSlave_write().
* Each transfer is performed atomically with the I2CSlave peripheral.
*
* @code
* ret = I2CSlave_read(i2cSlave, buffer, 5)
* if (!ret) {
* System_printf("Unsuccessful I2CSlave read");
* }
*
* I2CSlave_write(i2cSlave, buffer, 3);
* if (!ret) {
* System_printf("Unsuccessful I2CSlave write");
* }
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* I2CSlave_FxnTable.
*
* The I2CSlave driver interface module is joined (at link time) to a
* NULL-terminated array of I2CSlave_Config data structures named
* *I2CSlave_config*. *I2CSlave_config* is implemented in the application
* with each entry being an instance of a I2CSlave peripheral. Each entry in
* *I2CSlave_config* contains a:
* - (I2CSlave_FxnTable *) to a set of functions that implement an I2CSlave
* - (void *) data object that is associated with the I2CSlave_FxnTable
* - (void *) hardware attributes that are associated to the I2CSlave_FxnTable
*
* # Instrumentation #
* The I2CSlave driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_I2CSLAVE__include
#define ti_drivers_I2CSLAVE__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/**
* @defgroup I2CSLAVE_CONTROL I2CSlave_control command and status codes
* These I2CSlave macros are reservations for I2CSlave.h
* @{
*/
/*!
* Common I2CSlave_control command code reservation offset.
* I2CSlave driver implementations should offset command codes with
* I2CSLAVE_CMD_RESERVED growing positively
*
* Example implementation specific command codes:
* @code
* #define I2CSLAVEXYZ_COMMAND0 I2CSLAVE_CMD_RESERVED + 0
* #define I2CSLAVEXYZ_COMMAND1 I2CSLAVE_CMD_RESERVED + 1
* @endcode
*/
#define I2CSLAVE_CMD_RESERVED (32)
/*!
* Common I2CSlave_control status code reservation offset.
* I2CSlave driver implementations should offset status codes with
* I2CSLAVE_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define I2CSLAVEXYZ_STATUS_ERROR0 I2CSLAVE_STATUS_RESERVED - 0
* #define I2CSLAVEXYZ_STATUS_ERROR1 I2CSLAVE_STATUS_RESERVED - 1
* #define I2CSLAVEXYZ_STATUS_ERROR2 I2CSLAVE_STATUS_RESERVED - 2
* @endcode
*/
#define I2CSLAVE_STATUS_RESERVED (-32)
/**
* @defgroup I2CSLAVE_STATUS Status Codes
* I2CSLAVE_STATUS_SUCCESS_* macros are general status codes returned by I2CSlave_control()
* @{
* @ingroup I2CSLAVE_CONTROL
*/
/*!
* @brief Successful status code returned by I2CSlave_control().
*
* I2CSlave_control() returns I2CSLAVE_STATUS_SUCCESS if the control code was
* executed successfully.
*/
#define I2CSLAVE_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by I2CSlave_control().
*
* I2CSlave_control() returns I2CSLAVE_STATUS_ERROR if the control code was not
* executed successfully.
*/
#define I2CSLAVE_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by I2CSlave_control() for undefined
* command codes.
*
* I2CSlave_control() returns I2CSLAVE_STATUS_UNDEFINEDCMD if the control code
* is not recognized by the driver implementation.
*/
#define I2CSLAVE_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup I2CSLAVE_CMD Command Codes
* I2C_CMD_* macros are general command codes for I2CSlave_control(). Not all I2CSlave
* driver implementations support these command codes.
* @{
* @ingroup I2CSLAVE_CONTROL
*/
/* Add I2CSLAVE_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from a I2CSlave_open() call.
*/
typedef struct I2CSlave_Config_ *I2CSlave_Handle;
/*!
* @brief I2CSlave mode
*
* This enum defines the state of the I2CSlave driver's state-machine. Do not
* modify.
*/
typedef enum I2CSlave_Mode_ {
I2CSLAVE_IDLE_MODE = 0, /*!< I2CSlave is not performing a transaction */
I2CSLAVE_WRITE_MODE = 1, /*!< I2CSlave is currently performing write */
I2CSLAVE_READ_MODE = 2, /*!< I2CSlave is currently performing read */
I2CSLAVE_START_MODE = 3, /*!< I2CSlave received a START from a master */
I2CSLAVE_ERROR = 0xFF /*!< I2CSlave error has occurred, exit gracefully */
} I2CSlave_Mode;
/*!
* @brief I2CSlave transfer mode
*
* I2CSLAVE_MODE_BLOCKING block task execution a I2CSlave transfer is in
* progress. I2CSLAVE_MODE_CALLBACK does not block task execution; but calls a
* callback function when the I2CSlave transfer has completed
*/
typedef enum I2CSlave_TransferMode_ {
I2CSLAVE_MODE_BLOCKING, /*!< I2CSlave read/write blocks execution*/
I2CSLAVE_MODE_CALLBACK /*!< I2CSlave read/wrire queues transactions and
does not block */
} I2CSlave_TransferMode;
/*!
* @brief I2CSlave callback function
*
* User definable callback function prototype. The I2CSlave driver will call
* the defined function and pass in the I2CSlave driver's handle, and the
* return value of I2CSlave_read/I2CSlave_write.
*
* @param I2CSlave_Handle I2CSlave_Handle
* @param bool Results of the I2CSlave transaction
*/
typedef void (*I2CSlave_CallbackFxn)(I2CSlave_Handle handle, bool status);
/*!
* @brief I2CSlave Parameters
*
* I2CSlave parameters are used to with the I2CSlave_open() call. Default
* values for
* these parameters are set using I2CSlave_Params_init().
*
* If I2CSlave_TransferMode is set to I2CSLAVE_MODE_BLOCKING then I2CSlave_read
* or I2CSlave_write function calls will block thread execution until the
* transaction has completed.
*
* If I2CSlave_TransferMode is set to I2CSLAVE_MODE_CALLBACK then
* I2CSlave read/write will not block thread execution and it will call the
* function specified by transferCallbackFxn.
* (regardless of error state).
*
*
* @sa I2CSlave_Params_init()
*/
typedef struct I2CSlave_Params_ {
/*!< Blocking or Callback mode */
I2CSlave_TransferMode transferMode;
/*!< Callback function pointer */
I2CSlave_CallbackFxn transferCallbackFxn;
/*!< Custom argument used by driver implementation */
void *custom;
} I2CSlave_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_close().
*/
typedef void (*I2CSlave_CloseFxn) (I2CSlave_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_control().
*/
typedef int_fast16_t (*I2CSlave_ControlFxn) (I2CSlave_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_init().
*/
typedef void (*I2CSlave_InitFxn) (I2CSlave_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_open().
*/
typedef I2CSlave_Handle (*I2CSlave_OpenFxn) (I2CSlave_Handle handle,
I2CSlave_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_WriteTransaction().
*/
typedef bool (*I2CSlave_WriteFxn) (I2CSlave_Handle handle,
const void *buffer, size_t size);
/*!
* @brief A function pointer to a driver specific implementation of
* I2CSlave_ReadFxn().
*/
typedef bool (*I2CSlave_ReadFxn) (I2CSlave_Handle handle, void *buffer,
size_t size);
/*!
* @brief The definition of a I2CSlave function table that contains the
* required set of functions to control a specific I2CSlave
* driver implementation.
*/
typedef struct I2CSlave_FxnTable_ {
/*! Function to close the specified peripheral */
I2CSlave_CloseFxn closeFxn;
/*! Function to implementation specific control function */
I2CSlave_ControlFxn controlFxn;
/*! Function to initialize the given data object */
I2CSlave_InitFxn initFxn;
/*! Function to open the specified peripheral */
I2CSlave_OpenFxn openFxn;
/*! Function to initiate a I2CSlave data read */
I2CSlave_ReadFxn readFxn;
/*! Function to initiate a I2CSlave data write */
I2CSlave_WriteFxn writeFxn;
} I2CSlave_FxnTable;
/*!
* @brief I2CSlave Global configuration
*
* The I2CSlave_Config structure contains a set of pointers used to
* characterize the I2CSlave driver implementation.
*
* This structure needs to be defined before calling I2CSlave_init() and it
* must not be changed thereafter.
*
* @sa I2CSlave_init()
*/
typedef struct I2CSlave_Config_ {
/*! Pointer to a table of driver-specific implementations of I2CSlave APIs*/
I2CSlave_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} I2CSlave_Config;
/*!
* @brief Function to close a I2CSlave peripheral specified by the I2CSlave
* handle
* @pre I2CSlave_open() had to be called first.
*
* @param handle A I2CSlave_Handle returned from I2CSlave_open
*
* @sa I2CSlave_open()
*/
extern void I2CSlave_close(I2CSlave_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* I2CSlave_Handle.
*
* Commands for I2CSlave_control can originate from I2CSlave.h or from implementation
* specific I2CSlave*.h (_I2CMSP432.h_, etc.. ) files.
* While commands from I2CSlave.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific I2CSlave*.h files add
* unique driver capabilities but are not API portable across all I2CSlave driver
* implementations.
*
* Commands supported by I2CSlave.h follow a I2CSLAVE_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by I2CSlave*.h follow a I2CSLAVE*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref I2CSLAVE_CMD "I2CSlave_control command codes" for command codes.
*
* See @ref I2CSLAVE_STATUS "I2CSlave_control return status codes" for status codes.
*
* @pre I2CSlave_open() has to be called first.
*
* @param handle A I2CSlave handle returned from I2CSlave_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param arg An optional R/W (read/write) argument that is
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa I2CSlave_open()
*/
extern int_fast16_t I2CSlave_control(I2CSlave_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initializes the I2CSlave module
*
* @pre The I2CSlave_config structure must exist and be persistent before
* this function can be called. This function must also be called
* before any other I2CSlave driver APIs. This function call does not
* modify any peripheral registers.
*/
extern void I2CSlave_init(void);
/*!
* @brief Function to initialize a given I2CSlave peripheral specified by the
* particular index value. The parameter specifies which mode the
* I2CSlave will operate.
*
* @pre I2CSlave controller has been initialized
*
* @param index Logical peripheral number for the I2CSlave indexed
* into the I2CSlave_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A I2CSlave_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa I2CSlave_init()
* @sa I2CSlave_close()
*/
extern I2CSlave_Handle I2CSlave_open(uint_least8_t index,
I2CSlave_Params *params);
/*!
* @brief Function to initialize the I2CSlave_Params struct to its defaults
*
* @param params An pointer to I2CSlave_Params structure for
* initialization
*
* Defaults values are:
* transferMode = I2CSLAVE_MODE_BLOCKING
* transferCallbackFxn = NULL
*/
extern void I2CSlave_Params_init(I2CSlave_Params *params);
/*!
* @brief Function that handles the I2CSlave read for SYS/BIOS
*
* This function will start a I2CSlave read and can only be called from a
* Task context when in I2CSLAVE_MODE_BLOCKING.
* The I2CSlave read procedure starts with evaluating how many bytes are to be
* readby the I2CSlave peripheral.
*
* The data written by the I2CSlave is synchronized with the START and STOP
* from the master.
*
* In I2CSLAVE_MODE_BLOCKING, I2CSlave read/write will block task execution until
* the transaction has completed.
*
* In I2CSLAVE_MODE_CALLBACK, I2CSlave read/write does not block task execution
* and calls a callback function specified by transferCallbackFxn. If a
* transfer is already taking place, the transaction is put on an internal
* queue. The queue is serviced in a first come first served basis.
*
* @param handle A I2CSlave_Handle
*
* @param buffer A RO (read-only) pointer to an empty buffer in which
* received data should be written to.
*
* @param size The number of bytes to be written into buffer
*
* @return true on successful transfer
* false on an error
*
* @sa I2CSlave_open
*/
extern bool I2CSlave_read(I2CSlave_Handle handle, void *buffer,
size_t size);
/*!
* @brief Function that handles the I2CSlave write for SYS/BIOS
*
* This function will start a I2CSlave write and can only be called from a
* Task context when in I2CSLAVE_MODE_BLOCKING.
* The I2CSlave transfer procedure starts with evaluating how many bytes are
* to be written.
*
* The data written by the I2CSlave is synchronized with the START and STOP
* from the master. If slave does not have as many bytes requested by master
* it writes 0xFF. I2CSlave keeps sending 0xFF till master sends a STOP.
*
* In I2CSLAVE_MODE_BLOCKING, I2CSlave read/write will block task execution
* until the transaction has completed.
*
* In I2CSLAVE_MODE_CALLBACK, I2CSlave read/write does not block task execution
* and calls a callback function specified by transferCallbackFxn. If a
* transfer is already taking place, the transaction is put on an internal
* queue. The queue is serviced in a first come first served basis.
* The I2CSlave_Transaction structure must stay persistent until the
* I2CSlave read/write function has completed!
*
* @param handle A I2CSlave_Handle
*
* @param buffer A WO (write-only) pointer to buffer containing data to
* be written to the master.
*
* @param size The number of bytes in buffer that should be written
* onto the master.
*
* @return true on successful write
* false on an error
*
* @sa I2CSlave_open
*/
extern bool I2CSlave_write(I2CSlave_Handle handle, const void *buffer,
size_t size);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_I2CSLAVE__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file I2S.h
*
* @brief I2S driver interface
*
* The I2S header file should be included in an application as follows:
* @code
* #include <ti/drivers/I2S.h>
* @endcode
*
* # Overview #
* The I2S driver facilitates the use of Inter-IC Sound (I2S), which is
* used to connect digital audio devices so that audio signals can be
* communicated between devices. The I2S driver simplifies reading and
* writing to any of the Multichannel Audio Serial Port (McASP) peripherals
* on the board with Receive and Transmit support. These include blocking,
* non-blocking, read and write characters on the McASP peripheral.
*
* The APIs in this driver serve as an interface to a typical RTOS
* application. Its purpose is to redirect the I2S APIs to specific
* driver implementations which are specified using a pointer to an
* #I2S_FxnTable.
* The specific peripheral implementations are responsible
* for creating all the RTOS specific primitives to allow for thread-safe
* operation.
*
* # Usage #
*
* To use the I2S driver for reaading and writing data to the I2S peripheral,
* the application calls the following APIs:
* - I2S_init(): Initialize the I2S driver.
* - I2S_Params_init(): Initialize a #I2S_Params structure with default
* vaules. Then change the parameters from non-default values as
* needed.
* - I2S_open(): Open an instance of the I2S driver, passing the
* initialized parameters, or NULL, and an index (described later).
* - If using callback mode, I2S_read() and I2S_write().
* - If using issue/reclaim mode, I2S_readIssue(), I2S_readReclaim(),
* I2S_writeIssue() and I2S_writeReclaim().
* - I2S_close(): De-initialize the I2S instance.
*
* ### I2S Driver Configuration #
*
* In order to use the I2S APIs, the application is required
* to provide device-specific I2S configuration in the Board.c file.
* The I2S driver interface defines a configuration data structure:
*
* @code
* typedef struct I2S_Config_ {
* // Pointer to driver-specific implementation of I2S functions
* I2S_FxnTable const *fxnTablePtr;
* void *object; // Driver specific data object
* void const *hwAttrs; // Driver specific hardware attributes
* } I2S_Config;
* @endcode
*
* The application must declare an array of I2S_Config elements, named
* I2S_config[]. Each element of I2S_config[] must be populated with
* pointers to a device specific I2S driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the I2S peripheral's base address and pins.
* Each element in I2S_config[] corresponds to an I2S instance, and
* and none of the elements should have NULL pointers.
* There is no correlation between the index and the peripheral
* designation (such as I2S0 or I2S1). For example, it is possible
* to use I2S_config[0] for I2S1.
*
* Because I2S configuration is very device dependent, you will need to
* check the doxygen for the device specific I2S implementation. There you
* will find a description of the I2S hardware attributes. Please also
* refer to the board.c file of any of your examples to see the I2S
* configuration.
*
* ### Initializing the I2S Driver #
*
* I2S_init() must be called before any other I2S APIs. This function
* iterates through the elements of the I2S_config[] array, calling
* the element's device implementation I2S initialization function.
*
* ### I2S Parameters
*
* The #I2S_Params structure is passed to the I2S_open() call. If NULL
* is passed for the parameters, I2S_open() uses default parameters.
* An #I2S_Params structure is initialized with default values by passing
* it to I2S_Params_init().
* Some of the I2S parameters are described below. To see brief descriptions
* of all the parameters, see #I2S_Params.
*
* #### I2S Operation Mode
* The I2S operation mode determines whether transmit and/or receive modes
* are enabled. The mode is specified with one of the following constants:
* - #I2S_OPMODE_TX_ONLY: Enable transmit only.
* - #I2S_OPMODE_RX_ONLY: Enable receive only.
* - #I2S_OPMODE_TX_RX_SYNC: Enable both receive and transmit.
*
* #### I2S Data Mode
* A separate data mode may be specified for read calls and write calls.
* The available modes are:
* - #I2S_MODE_CALLBACK: This mode is non-blocking. Calls to I2S_read() or
* I2S_write() return immediately. When the transfer is finished, the
* user configured callback function is called.
* - #I2S_MODE_ISSUERECLAIM: Call I2S_readIssue() and I2S_writeIssue() to
* queue buffers to the I2S. I2S_readReclaim() blocks until a buffer
* of data is available. I2S_writeReclaim() blocks until a buffer of
* data has been issued and the descriptor can be returned back to the
* caller.
*
* ### Opening the I2S Driver #
* After initializing the I2S driver by calling I2S_init(), the application
* can open an I2S instance by calling I2S_open(). This function
* takes an index into the I2S_config[] array, and an I2S parameters data
* structure. The I2S instance is specified by the index of the I2S in
* I2S_config[]. Only one I2S index can be used at a time;
* calling I2S_open() a second time with the same index previosly
* passed to I2S_open() will result in an error. You can,
* though, re-use the index if the instance is closed via I2S_close().
*
* If NULL is passed for the I2S_Params structure to I2S_open(), default values
* are used. If the open call is successful, it returns a non-NULL value.
*
* Example opening an I2S driver instance:
* @code
* I2S_Handle handle;
* I2S_Params params;
*
* I2S_Params_init(&params);
* params.operationMode = I2S_MODE_TX_RX_SYNC;
* < Change other params as required >
*
* handle = I2S_open(Board_I2S0, &params);
* if (!handle) {
* // Error opening I2S, handle accordingly
* }
* @endcode
*
* ### Writing Data #
* The following example calls I2S_writeIssue() to write to an I2S driver
* instance that has been opened. It first queues up two buffers of text.
* Within an infinite loop, it calls I2S_writeReclaim() to retrieve a
* buffer and then re-queues the buffer.
*
* @code
* const unsigned char hello[] = "Hello World\n";
* const unsigned char hello1[] = "Hello World1\n";
* I2S_BufDesc writeBuffer1;
* I2S_BufDesc writeBuffer2;
* I2S_BufDesc *pDesc = NULL;
*
* writeBuffer1.bufPtr = &hello;
* writeBuffer1.bufSize = sizeof(hello);
* writeBuffer2.bufPtr = &hello1;
* writeBuffer2.bufSize = sizeof(hello1);
*
* ret = I2S_writeIssue(handle, &writeBuffer1);
* ret = I2S_writeIssue(handle, &writeBuffer2);
*
* while(1) {
* ret = I2S_writeReclaim(handle, &pDesc);
* pDesc->bufPtr = &hello;;
* pDesc->bufSize = sizeof(hello);
* ret = I2S_writeIssue(handle, pDesc);
* }
*
* @endcode
*
* ### Reading Data #
* The following example calls I2S_readIssue() to queue a buffer for
* reading from an I2S driver instance. It first queues up two buffers of
* text. Within an infinite loop, it then calls I2S_readReclaim() to retrieve
* a full buffer of data.
*
* @code
* unsigned char rxBuffer[20];
* unsigned char rxBuffer1[20];
* I2S_BufDesc readBuffer1;
* I2S_BufDesc readBuffer2;
* I2S_BufDesc *pDesc = NULL;
*
* readBuffer1.bufPtr = &rxBuffer;
* readBuffer1.bufSize = 20;
* readBuffer2.bufPtr = &rxBuffer1;
* readBuffer2.bufSize = 20;
*
* ret = I2S_readIssue(handle, &readBuffer1);
* ret = I2S_readIssue(handle, &readBuffer2);
*
* while(1)
* {
* ret = I2S_readReclaim(handle, &pDesc);
* pDesc->bufPtr = &rxBuffer;
* pDesc->bufSize = 20;
* ret = I2S_readIssue(handle, pDesc);
* }
* @endcode
*
* # Implementation #
*
* The I2S driver interface module is joined (at link time) to an
* array of I2S_Config data structures named *I2S_config*.
* *I2S_config* is implemented in the application with each entry being an
* instance of a I2S peripheral. Each entry in *I2S_config* contains a:
* - (I2S_FxnTable *) to a set of functions that implement a I2S peripheral
* - (void *) data object that is associated with the I2S_FxnTable
* - (void *) hardware attributes that are associated to the I2S_FxnTable
*
*******************************************************************************
*/
#ifndef ti_drivers_I2S__include
#define ti_drivers_I2S__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
#include <ti/drivers/utils/List.h>
/**
* @defgroup I2S_CONTROL I2S_control command and status codes
* These I2S macros are reservations for I2S.h
* @{
*/
/*!
* Common I2S_control command code reservation offset.
* I2S driver implementations should offset command codes with I2S_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define I2SXYZ_CMD_COMMAND0 I2S_CMD_RESERVED + 0
* #define I2SXYZ_CMD_COMMAND1 I2S_CMD_RESERVED + 1
* @endcode
*/
#define I2S_CMD_RESERVED (32)
/*!
* Common I2S_control status code reservation offset.
* I2S driver implementations should offset status codes with
* I2S_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define I2SXYZ_STATUS_ERROR0 I2S_STATUS_RESERVED - 0
* #define I2SXYZ_STATUS_ERROR1 I2S_STATUS_RESERVED - 1
* #define I2SXYZ_STATUS_ERROR2 I2S_STATUS_RESERVED - 2
* @endcode
*/
#define I2S_STATUS_RESERVED (-32)
/**
* @defgroup I2S_STATUS Status Codes
* I2S_STATUS_* macros are general status codes returned by I2S_control()
* @{
* @ingroup I2S_CONTROL
*/
/*!
* @brief Successful status code returned by I2S_control().
*
* I2S_control() returns I2S_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define I2S_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by I2S_control().
*
* I2S_control() returns I2S_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define I2S_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by I2S_control() for undefined
* command codes.
*
* I2S_control() returns I2S_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define I2S_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup I2S_CMD Command Codes
* I2S_CMD_* macros are general command codes for I2S_control(). Not all I2S
* driver implementations support these command codes.
* @{
* @ingroup I2S_CONTROL
*/
/* Add I2S_CMD_<commands> here */
/** @}*/
/** @}*/
#define I2S_ERROR (I2S_STATUS_ERROR)
/*!
* @brief Wait forever define
*/
#define I2S_WAIT_FOREVER (~(0U))
/*!
* @brief A handle that is returned from a I2S_open() call.
*/
typedef struct I2S_Config_ *I2S_Handle;
/*!
* @brief I2S buffer descriptor for issue/reclaim mode.
*/
typedef struct I2S_BufDesc_ {
/*! Used internally to link descriptors together */
List_Elem qElem;
/*! Pointer to the buffer */
void *bufPtr;
/*! Size of the buffer (target MAUs). */
size_t bufSize;
/*! Optional argument associated with the descriptor. */
uintptr_t descArg;
} I2S_BufDesc;
/*!
* @brief The definition of a callback function used by the I2S driver
* when used in ::I2S_MODE_CALLBACK
*
* @param I2S_Handle I2S_Handle
*
* @param buf Pointer to read/write buffer
*
* @param count Number of elements read/written
*/
typedef void (*I2S_Callback)(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief I2S mode settings
*
* This enum defines the read and write modes for the
* configured I2S.
*/
typedef enum I2S_DataMode_ {
/*!
* Non-blocking and will return immediately. When the transfer by the intr
* is finished the configured callback function is called.
*/
I2S_MODE_CALLBACK,
/*!
* Use I2S_readIssue, I2S_writeIssue calls to queue buffers to the
* I2S. I2S_readReclaim() blocks until a buffer of data is available.
* I2S_writeReclaim() blocks until a buffer of data has been written
* and the descriptor can be returned back to the caller.
*/
I2S_MODE_ISSUERECLAIM
} I2S_DataMode;
/*!
* @brief I2S mode settings
*
* This enumeration defines the mode for I2S operation.
*/
typedef enum I2S_OpMode_ {
I2S_OPMODE_TX_ONLY, /*!< Only Transmit enabled */
I2S_OPMODE_RX_ONLY, /*!< Only Receive enabled */
I2S_OPMODE_TX_RX_SYNC /*!< Receive and Transmit are enabled in Sync */
} I2S_OpMode;
/*!
* @brief I2S Serializer InActive state settings
*
* This enumeration defines the Serializer configuration
* in inactive state.
*/
typedef enum I2S_SerInActiveConfig_ {
I2S_SERCONFIG_INACT_TRI_STATE, /*!< Inactive state to tristate */
I2S_SERCONFIG_INACT_LOW_LEVEL, /*!< Inactive state to low */
I2S_SERCONFIG_INACT_HIGH_LEVEL /*!< Inactive state to high */
} I2S_SerInActiveConfig;
/*!
* @brief I2S serial pin mode
*
* This enumeration defines the Serial pin configuration
*/
typedef enum I2S_PinMode_ {
I2S_PINMODE_RX, /*!< Operate the pin in Rx mode */
I2S_PINMODE_TX, /*!< Operate the pin in Tx mode */
I2S_PINMODE_INACTIVE /*!< Pin in inactive mode */
} I2S_PinMode;
/*!
* @brief Basic I2S Parameters
*
* I2S parameters are used to with the I2S_open() call. Default values for
* these parameters are set using I2S_Params_init().
*
* @sa I2S_Params_init()
*/
typedef struct I2S_Params_ {
/*!< I2S operational mode */
I2S_OpMode operationMode;
/*!< I2S sampling frequency configuration in samples/second */
uint32_t samplingFrequency;
/*!< Slot length */
uint8_t slotLength;
/*!< Bits per sample (Word length) */
uint8_t bitsPerSample;
/*!< Number of channels (slots per frame) */
uint8_t numChannels;
/*!< Mode for all read calls */
I2S_DataMode readMode;
/*!< Pointer to read callback */
I2S_Callback readCallback;
/*!< Timeout for read semaphore */
uint32_t readTimeout;
/*!< Mode for all write calls */
I2S_DataMode writeMode;
/*!< Pointer to write callback */
I2S_Callback writeCallback;
/*!< Timeout for write semaphore */
uint32_t writeTimeout;
/*!< Pointer to device specific custom params */
void *customParams;
} I2S_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_CloseFxn().
*/
typedef void (*I2S_CloseFxn) (I2S_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_control().
*/
typedef int_fast16_t (*I2S_ControlFxn)(I2S_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_init().
*/
typedef void (*I2S_InitFxn)(I2S_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_OpenFxn().
*/
typedef I2S_Handle (*I2S_OpenFxn)(I2S_Handle handle, I2S_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_IssueFxn().
*/
typedef int_fast16_t (*I2S_IssueFxn)(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief A function pointer to a driver specific implementation of
* I2S_ReclaimFxn().
*/
typedef size_t (*I2S_ReclaimFxn)(I2S_Handle handle, I2S_BufDesc **desc);
/*!
* @brief The definition of a I2S function table that contains the
* required set of functions to control a specific I2S driver
* implementation.
*/
typedef struct I2S_FxnTable_ {
/*! Function to close the specified peripheral */
I2S_CloseFxn closeFxn;
/*! Function to implementation specific control function */
I2S_ControlFxn controlFxn;
/*! Function to initialize the given data object */
I2S_InitFxn initFxn;
/*! Function to open the specified peripheral */
I2S_OpenFxn openFxn;
/*! Function to queue a buffer for reading from the specified peripheral */
I2S_IssueFxn readIssueFxn;
/*! Function to retrieve a received buffer of data from the specified peripheral */
I2S_ReclaimFxn readReclaimFxn;
/*! Function to queue a buffer for writing from the specified peripheral */
I2S_IssueFxn writeIssueFxn;
/*! Function to retrieve a sent buffer of data from the specified peripheral */
I2S_ReclaimFxn writeReclaimFxn;
} I2S_FxnTable;
/*! @brief I2S Global configuration
*
* The I2S_Config structure contains a set of pointers used to characterize
* the I2S driver implementation.
*
* This structure needs to be defined before calling I2S_init() and it must
* not be changed thereafter.
*
* @sa I2S_init()
*/
typedef struct I2S_Config_ {
/*! Pointer to a table of a driver-specific implementation of I2S
functions */
I2S_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} I2S_Config;
/*!
* @brief Function to close a given I2S peripheral specified by the I2S
* handle.
*
* @pre I2S_open() had to be called first.
*
* @param handle A I2S_Handle returned from I2S_open
*
* @sa I2S_open()
*/
extern void I2S_close(I2S_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* I2S_Handle.
*
* Commands for I2S_control can originate from I2S.h or from
* implementation specific I2S*.h (_I2SCC32XX.h_, etc.. ) files.
* While commands from I2S.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific I2S*.h files add
* unique driver capabilities but are not API portable across all I2S driver
* implementations.
*
* Commands supported by I2S.h follow a I2S_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by I2S*.h follow a I2S*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref I2S_CMD "I2S_control command codes" for command codes.
*
* See @ref I2S_STATUS "I2S_control return status codes" for status codes.
*
* @pre I2S_open() has to be called first.
*
* @param handle A I2S handle returned from I2S_open()
*
* @param cmd I2S.h or I2S*.h commands.
*
* @param arg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa I2S_open()
*/
extern int_fast16_t I2S_control(I2S_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initializes the I2S module
*
* @pre The I2S_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other I2S driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void I2S_init(void);
/*!
* @brief Function to initialize a given I2S peripheral specified by the
* particular index value. The parameter specifies which mode the I2S
* will operate.
*
* @pre I2S controller has been initialized
*
* @param index Logical peripheral number for the I2S indexed into
* the I2S_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A I2S_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa I2S_init()
* @sa I2S_close()
*/
extern I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params);
/*!
* @brief Function to initialize the I2S_Params struct to its defaults
*
* @param params An pointer to I2S_Params structure for
* initialization
*
* Defaults values are:
* @code
* params.operationMode = #I2S_OPMODE_TX_RX_SYNC;
* params.samplingFrequency = 16000;
* params.slotLength = 16;
* params.bitsPerSample = 16;
* params.numChannels = 2;
* params.readMode = #I2S_MODE_ISSUERECLAIM;
* params.readCallback = NULL;
* params.readTimeout = #I2S_WAIT_FOREVER;
* params.writeMode = #I2S_MODE_ISSUERECLAIM;
* params.writeCallback = NULL;
* params.writeTimeout = #I2S_WAIT_FOREVER;
* params.customParams = NULL;
* @endcode
*
* @param params Parameter structure to initialize
*/
extern void I2S_Params_init(I2S_Params *params);
/*!
* @brief Function to queue a buffer of data to the I2S in callback mode
* for reading.
*
* @param handle A I2S_Handle
*
* @param desc A pointer to a I2S_BufDesc object. The bufPtr
* and bufSize fields must be set to a buffer and the
* size of the buffer before passing to this function.
* @return Returns 0 if successful else would return
* I2S_STATUS_UNDEFINEDCMD on an error.
*/
extern int_fast16_t I2S_read(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief Function to queue a buffer of data to the I2S in Issue/Reclaim
* mode for reading.
*
* @param handle A I2S_Handle
*
* @param desc A pointer to a I2S_BufDesc object. The bufPtr
* and bufSize fields must be set to a buffer and the
* size of the buffer before passing to this function.
* @return Returns 0 if successful else would return
* I2S_STATUS_UNDEFINEDCMD on an error.
*/
extern int_fast16_t I2S_readIssue(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief Function to retrieve a full buffer of data read by the I2S.
*
* @param handle A I2S_Handle
*
* @param pDesc A pointer to a I2S_BufDesc pointer.
*
* @return Returns the number of bytes read from the I2S, or 0 on timeout.
*/
extern size_t I2S_readReclaim(I2S_Handle handle, I2S_BufDesc **pDesc);
/*!
* @brief Function to queue a buffer of data to the I2S in
* callback mode for writing.
*
* @param handle A I2S_Handle
*
* @param desc A pointer to a I2S_BufDesc object. The bufPtr
* and bufSize fields must be set to a buffer and the
* size of the buffer before passing to this function.
* @return Returns 0 if successful else would return
* I2S_STATUS_UNDEFINEDCMD on an error.
*/
extern int_fast16_t I2S_write(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief Function to queue a buffer of data to the I2S in
* Issue/Reclaim mode for writing.
*
* @param handle A I2S_Handle
*
* @param desc A pointer to a I2S_BufDesc object. The bufPtr
* and bufSize fields must be set to a buffer and the
* size of the buffer before passing to this function.
* @return Returns 0 if successful else would return
* I2S_STATUS_UNDEFINEDCMD on an error.
*/
extern int_fast16_t I2S_writeIssue(I2S_Handle handle, I2S_BufDesc *desc);
/*!
* @brief Function to retrieve a buffer that the I2S has finished writing.
*
* @param handle A I2S_Handle
*
* @param pDesc A pointer to a I2S_BufDesc pointer.
*
* @return Returns the number of bytes that have been written to the I2S,
* 0 on timeout.
*/
extern size_t I2S_writeReclaim(I2S_Handle handle, I2S_BufDesc **pDesc);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_I2S__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ==========================================================================
* @file NVS.h
*
* @brief <b>PRELIMINARY</b> Non-Volatile Storage Driver.
*
* <b>WARNING</b> These APIs are <b>PRELIMINARY</b>, and subject to
* change in the next few months.
*
* The NVS header file should be included in an application as follows:
* @code
* #include <ti/drivers/NVS.h>
* @endcode
*
* # Operation #
*
* The NVS module allows you to manage non-volatile memory. Using the
* NVS APIs, you can read and write data to persistant storage. Each NVS
* object manages a 'block' of non-volatile memory of a size specified in
* the NVS object's hardware attributes. A 'page' will refer to the
* smallest unit of non-volatile storage that can be erased at one time,
* and the page size is the size of this unit. This is hardware specific
* and may be meaningless for some persistant storage systems. However,
* in the case of flash memory, page size should be taken into account
* when deciding the block size for NVS to manage. For example on
* TM4C129x devices, a page size is 16KB.
*
* When page size is relevant (e.g. for flash memory), the size of an
* NVS block size must be less than or equal to the page size. The block
* size can be less than the page size, however, care must be taken not
* to use the area in the page outside of the block. When the block is
* erased, the entire page will be erased, clearing anything in the page
* that was written outside of the block.
*
* See the device specific NVS header file for configuration details.
*
* ==========================================================================
*/
#ifndef ti_drivers_NVS__include
#define ti_drivers_NVS__include
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#if defined (__cplusplus)
extern "C" {
#endif
/**
* @defgroup NVS_CONTROL NVS_control command and status codes
* These NVS macros are reservations for NVS.h
* @{
*/
/*!
* Common NVS_control command code reservation offset.
* NVS driver implementations should offset command codes with NVS_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define NVSXYZ_CMD_COMMAND0 NVS_CMD_RESERVED + 0
* #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1
* @endcode
*/
#define NVS_CMD_RESERVED 32
/*!
* Common NVS_control status code reservation offset.
* NVS driver implementations should offset status codes with
* NVS_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define NVSXYZ_STATUS_ERROR0 NVS_STATUS_RESERVED - 0
* #define NVSXYZ_STATUS_ERROR1 NVS_STATUS_RESERVED - 1
* #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2
* @endcode
*/
#define NVS_STATUS_RESERVED -32
/**
* @defgroup NVS_STATUS Status Codes
* NVS_STATUS_* macros are general status codes returned by NVS_control()
* @{
* @ingroup NVS_CONTROL
*/
/*!
* @brief Successful status code returned by NVS_control().
*
* NVS_control() returns NVS_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define NVS_STATUS_SUCCESS 0
/*!
* @brief Generic error status code returned by NVS_control().
*
* NVS_control() returns NVS_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define NVS_STATUS_ERROR -1
/*!
* @brief An error status code returned by NVS_control() for undefined
* command codes.
*
* NVS_control() returns NVS_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define NVS_STATUS_UNDEFINEDCMD -2
/** @}*/
/**
* @defgroup NVS_CMD Command Codes
* NVS_CMD_* macros are general command codes for NVS_control(). Not all NVS
* driver implementations support these command codes.
* @{
* @ingroup NVS_CONTROL
*/
/* Add NVS_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief Success return code
*/
#define NVS_SOK (0)
/*!
* @brief General failure return code
*/
#define NVS_EFAIL (-1)
#define NVS_EOFFSET (-3)
#define NVS_EALIGN (-4)
#define NVS_ENOTENOUGHBYTES (-5)
#define NVS_EALREADYWRITTEN (-6)
#define NVS_ECOPYBLOCK (-7)
/*!
* @brief NVS write flags
*
* The following flags can be or'd together and passed as a bit mask
* to NVS_write.
*/
/*!
* @brief Exclusive write flag
*
* Only write if the area has not already been written to since the last
* erase. In the case of flash memory on some devices, once data is written
* to a location, that location cannot be written to again without first
* erasing the entire flash page. If the NVS_WRITE_EXCLUSIVE flag is
* set in the flags passed to NVS_write(), the location where the data
* will be written to is first checked if it has been modified since the
* last time the NVS block was erarsed. If that is the case, NVS_write()
* will return an error.
*/
#define NVS_WRITE_EXCLUSIVE (0x1)
/*!
* @brief Erase write flag.
*
* If NVS_WRITE_ERASE is set in the flags passed to NVS_write(), the entire
* NVS block will be erased before being written to.
*/
#define NVS_WRITE_ERASE (0x2)
/*!
* @brief Validate write flag.
*
* If NVS_WRITE_VALIDATE is set in the flags passed to NVS_write(), the region
* in the NVS block that was written to will be validated (i.e., compared
* against the data buffer passed to NVS_write()).
*/
#define NVS_WRITE_VALIDATE (0x4)
/*!
* @brief NVS Parameters
*
* NVS parameters are used with the NVS_open() call. Default values for
* these parameters are set using NVS_Params_init().
*
* @sa NVS_Params_init()
*/
typedef struct NVS_Params {
bool eraseOnOpen; /*!< Erase block on open */
} NVS_Params;
/*!
* @brief NVS attributes
*
* The address of an NVS_Attrs structure can be passed to NVS_getAttrs()
* to fill in the fields.
*
* pageSize is the size of the smallest erase page. This is hardware
* specific. For example, all TM4C123x devices use 1KB pages, but
* TM4C129x devices use 16KB pages. Please consult the device datasheet
* to determine the pageSize to use.
*
* blockSize is the actual size of the NVS storage block that the
* application chooses to manage.
* If pageSize is greater than blockSize, care should be taken not to
* use the storage on the page that is outside of the block, since it
* may be erased when writing to the block. The block size must not be
* greater than the page size.
*
* @sa NVS_getAttrs()
*/
typedef struct NVS_Attrs {
size_t pageSize; /*! Hardware page size */
size_t blockSize; /*! Size of the NVS block to manage */
} NVS_Attrs;
/*!
* @brief A handle that is returned from the NVS_open() call.
*/
typedef struct NVS_Config *NVS_Handle;
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_close().
*/
typedef void (*NVS_CloseFxn) (NVS_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_control().
*/
typedef int (*NVS_ControlFxn) (NVS_Handle handle, unsigned int cmd,
uintptr_t arg);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_exit().
*/
typedef void (*NVS_ExitFxn) (NVS_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_getAttrs().
*/
typedef int (*NVS_GetAttrsFxn) (NVS_Handle handle, NVS_Attrs *attrs);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_init().
*/
typedef void (*NVS_InitFxn) (NVS_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_open().
*/
typedef NVS_Handle (*NVS_OpenFxn) (NVS_Handle handle, NVS_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_read().
*/
typedef int (*NVS_ReadFxn) (NVS_Handle handle, size_t offset,
void *buffer, size_t bufferSize);
/*!
* @brief A function pointer to a driver specific implementation of
* NVS_write().
*/
typedef int (*NVS_WriteFxn) (NVS_Handle handle, size_t offset,
void *buffer, size_t bufferSize,
unsigned int flags);
/*!
* @brief The definition of an NVS function table that contains the
* required set of functions to control a specific NVS driver
* implementation.
*/
typedef struct NVS_FxnTable {
/*! Function to close the specified NVS block */
NVS_CloseFxn closeFxn;
/*! Function to apply control command to the specified NVS block */
NVS_ControlFxn controlFxn;
/*! Function to de-initialize the NVS module */
NVS_ExitFxn exitFxn;
/*! Function to get the NVS device-specific attributes */
NVS_GetAttrsFxn getAttrsFxn;
/*! Function to initialize the NVS module */
NVS_InitFxn initFxn;
/*! Function to open an NVS block */
NVS_OpenFxn openFxn;
/*! Function to read from the specified NVS block */
NVS_ReadFxn readFxn;
/*! Function to write to the specified NVS block */
NVS_WriteFxn writeFxn;
} NVS_FxnTable;
/*!
* @brief NVS Global configuration
*
* The NVS_Config structure contains a set of pointers used to characterize
* the NVS driver implementation.
*
* This structure needs to be defined before calling NVS_init() and it must
* not be changed thereafter.
*
* @sa NVS_init()
*/
typedef struct NVS_Config {
/*! Pointer to a table of driver-specific implementations of NVS APIs */
NVS_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} NVS_Config;
/*!
* @brief Function to close an NVS handle
*
* @param handle A handle returned from NVS_open()
*
* @sa NVS_open()
*/
extern void NVS_close(NVS_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* NVS_Handle.
*
* @pre NVS_open() must be called first.
*
* @param handle An NVS handle returned from NVS_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param arg An optional R/W (read/write) argument that is
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa NVS_open()
*/
extern int NVS_control(NVS_Handle handle, unsigned int cmd, uintptr_t arg);
/*!
* @brief Erase the block of storage reference by an NVS handle
*
* @param handle A handle returned from NVS_open()
*
* @return NVS_SOK Success.
* @return NVS_EFAIL An error occurred erasing the flash.
*/
extern int NVS_erase(NVS_Handle handle);
/*!
* @brief Function to de-initialize the NVS module
*
* @pre NVS_init() was called.
*/
extern void NVS_exit(void);
/*!
* @brief Function to get the NVS attributes
*
* @param handle A handle returned from NVS_open()
*
* @param attrs Location to store attributes.
*/
extern int NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs);
/*!
* @brief Function to initialize the NVS module
*
* @pre The NVS_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other NVS APIs.
*/
extern void NVS_init(void);
/*!
* @brief Get an NVS block for reading and writing.
*
* @pre NVS_init() was called.
*
* @param index Index in the NVS_config table of the block
* to manage.
*
* @param params Pointer to a parameter block. If NULL, default
* parameter values will be used.
*/
extern NVS_Handle NVS_open(int index, NVS_Params *params);
/*!
* @brief Read data from an NVS block.
*
* @param handle A handle returned from NVS_open()
*
* @param offset The byte offset into the NVS block to start
* reading from.
*
* @param buffer A buffer to copy the data to.
*
* @param bufferSize The size of the buffer (number of bytes to read).
*
* @return NVS_SOK Success.
* @return NVS_EOFFSET The location and size to read from does not
* lie completely within the NVS block.
*
* @remark This call may block to ensure atomic access to the block.
*/
extern int NVS_read(NVS_Handle handle, size_t offset, void *buffer,
size_t bufferSize);
/*!
* @brief Write data to an NVS block.
*
* @param handle A handle returned from NVS_open()
*
* @param offset The byte offset into the NVS block to start
* writing. offset must be 4-byte aligned.
*
* @param buffer A buffer conntaining data to write to
* the NVS block. If buffer is NULL, the block
* will be erased. A non-NULL buffer must be
* aligned on a 4-byte boundary.
*
* @param bufferSize The size of the buffer (number of bytes to write).
* bufferSize must be a multiple of 4 bytes.
*
* @param flags Write flags (NVS_WRITE_EXCLUSIVE, NVS_WRITE_ERASE,
* NVS_WRITE_VALIDATE).
*
* @return NVS_SOK Success.
* @return NVS_EOFFSET The location and size to write to does not
* lie completely within the NVS block.
* @return NVS_EALIGN The offset or bufferSize is not 4-byte aligned.
* @return NVS_ALREADYWRITTEN
* The region to write to (the bufferSize region
* starting at offset into the block) has already
* been written to since the last erase, and
* NVS_WRITE_EXCLUSIVE is set in the flags parameter.
*
* @remark This call may block to ensure atomic access to the block.
*/
extern int NVS_write(NVS_Handle handle, size_t offset, void *buffer,
size_t bufferSize, unsigned int flags);
#if defined (__cplusplus)
}
#endif /* defined (__cplusplus) */
/*@}*/
#endif /* ti_drivers_NVS__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file PWM.h
* @brief PWM driver interface
*
* To use the PWM driver, ensure that the correct driver library for your
* device is linked in and include this header file as follows:
* @code
* #include <ti/drivers/PWM.h>
* @endcode
*
* This module serves as the main interface for applications. Its purpose
* is to redirect the PWM APIs to specific driver implementations
* which are specified using a pointer to a #PWM_FxnTable.
*
* # Overview #
* The PWM driver in TI-RTOS facilitates the generation of Pulse Width
* Modulated signals via simple and portable APIs. PWM instances must be
* opened by calling PWM_open() while passing in a PWM index and a parameters
* data structure.
*
* The driver APIs serve as an interface to a typical TI-RTOS application.
* The specific peripheral implementations are responsible for creating all OS
* specific primitives to allow for thread-safe operation.
*
* When a PWM instance is opened, the period, duty cycle and idle level are
* configured and the PWM is stopped (waveforms not generated until PWM_start()
* is called). The maximum period and duty supported is device dependent;
* refer to the implementation specific documentation for values.
*
* PWM outputs are active-high, meaning the duty will control the duration of
* high output on the pin (at 0% duty, the output is always low, at 100% duty,
* the output is always high).
*
* # Usage #
*
* @code
* PWM_Handle pwm;
* PWM_Params pwmParams;
*
* // Initialize the PWM driver.
* PWM_init();
*
* // Initialize the PWM parameters
* PWM_Params_init(&pwmParams);
* pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running
* pwmParams.period.unit = PWM_PERIOD_HZ; // Period is in Hz
* pwmParams.period.value = 1e6; // 1MHz
* pwmParams.duty.unit = PWM_DUTY_FRACTION; // Duty is in fractional percentage
* pwmParams.duty.value = 0; // 0% initial duty cycle
*
* // Open the PWM instance
* pwm = PWM_open(Board_PWM0, &pwmParams);
*
* if (pwm == NULL) {
* // PWM_open() failed
* while (1);
* }
*
* PWM_start(handle); // start PWM with 0% duty cycle
*
* PWM_setDuty(pwm,
* (PWM_DUTY_FRACTION_MAX / 2)); // set duty cycle to 50%
* @endcode
*
* Details for the example code above are described in the following
* subsections.
*
* ### PWM Driver Configuration #
*
* In order to use the PWM APIs, the application is required
* to provide device-specific PWM configuration in the Board.c file.
* The PWM driver interface defines a configuration data structure:
*
* @code
* typedef struct PWM_Config_ {
* PWM_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } PWM_Config;
* @endcode
*
* The application must declare an array of PWM_Config elements, named
* PWM_config[]. Each element of PWM_config[] is populated with
* pointers to a device specific PWM driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as which pin will be driven, and which timer peripheral
* will be used. Each element in PWM_config[] corresponds to
* a PWM instance, and none of the elements should have NULL pointers.
*
* Additionally, the PWM driver interface defines a global integer variable
* 'PWM_count' which is initialized to the number of PWM instances the
* application has defined in the PWM_Config array.
*
* You will need to check the device-specific PWM driver implementation's
* header file for example configuration. Please also refer to the
* Board.c file of any of your examples to see the PWM configuration.
*
* ### Initializing the PWM Driver #
*
* PWM_init() must be called before any other PWM APIs. This function
* calls the device implementation's PWM initialization function, for each
* element of PWM_config[].
*
* ### Opening the PWM Driver #
*
* Opening a PWM requires four steps:
* 1. Create and initialize a PWM_Params structure.
* 2. Fill in the desired parameters.
* 3. Call PWM_open(), passing the index of the PWM in the PWM_config
* structure, and the address of the PWM_Params structure. The
* PWM instance is specified by the index in the PWM_config structure.
* 4. Check that the PWM handle returned by PWM_open() is non-NULL,
* and save it. The handle will be used to read and write to the
* PWM you just opened.
*
* Only one PWM index can be used at a time; calling PWM_open() a second
* time with the same index previously passed to PWM_open() will result in
* an error. You can, though, re-use the index if the instance is closed
* via PWM_close().
* In the example code, Board_PWM0 is passed to PWM_open(). This macro
* is defined in the example's Board.h file.
*
* ### Modes of Operation #
*
* A PWM instance can be configured to interpret the period as one of three
* units:
* - #PWM_PERIOD_US: The period is in microseconds.
* - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz.
* - #PWM_PERIOD_COUNTS: The period is in timer counts.
*
* A PWM instance can be configured to interpret the duty as one of three
* units:
* - #PWM_DUTY_US: The duty is in microseconds.
* - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period
* where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%.
* - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than
* the period.
*
* The idle level parameter is used to set the output to high/low when the
* PWM is not running (stopped or not started). The idle level can be
* set to:
* - #PWM_IDLE_LOW
* - #PWM_IDLE_HIGH
*
* The default PWM configuration is to set a duty of 0% with a 1MHz frequency.
* The default period units are in PWM_PERIOD_HZ and the default duty units
* are in PWM_DUTY_FRACTION. Finally, the default output idle level is
* PWM_IDLE_LOW. It is the application's responsibility to set the duty for
* each PWM output used.
*
* ### Controlling the PWM Duty Cycle #
*
* Once the PWM instance has been opened and started, the primary API used
* by the application will be #PWM_setDuty() to control the duty cycle of a
* PWM pin:
*
* @code
* PWM_setDuty(pwm, PWM_DUTY_FRACTION_MAX / 2); // Set 50% duty cycle
* @endcode
*
* # Implementation #
*
* The PWM driver interface module is joined (at link time) to an
* array of PWM_Config data structures named *PWM_config*.
* PWM_config is implemented in the application with each entry being a
* PWM instance. Each entry in *PWM_config* contains a:
* - (PWM_FxnTable *) to a set of functions that implement a PWM peripheral
* - (void *) data object that is associated with the PWM_FxnTable
* - (void *) hardware attributes that are associated with the PWM_FxnTable
*
* The PWM APIs are redirected to the device specific implementations
* using the PWM_FxnTable pointer of the PWM_config entry.
* In order to use device specific functions of the PWM driver directly,
* link in the correct driver library for your device and include the
* device specific PWM driver header file (which in turn includes PWM.h).
* For example, for the MSP432 family of devices, you would include the
* following header file:
* @code
* #include <ti/drivers/pwm/PWMTimerMSP432.h>
* @endcode
*
* ============================================================================
*/
#ifndef ti_drivers_PWM__include
#define ti_drivers_PWM__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*!
* @brief Maximum duty (100%) when configuring duty cycle as a fraction of
* period.
*/
#define PWM_DUTY_FRACTION_MAX ((uint32_t) ~0)
/*!
* Common PWM_control command code reservation offset.
* PWM driver implementations should offset command codes with PWM_CMD_RESERVED
* growing positively.
*
* Example implementation specific command codes:
* @code
* #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0)
* #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1)
* @endcode
*/
#define PWM_CMD_RESERVED (32)
/*!
* Common PWM_control status code reservation offset.
* PWM driver implementations should offset status codes with
* PWM_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0)
* #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1)
* #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2)
* @endcode
*/
#define PWM_STATUS_RESERVED (-32)
/*!
* @brief Success status code returned by:
* PWM_control(), PWM_setDuty(), PWM_setPeriod().
*
* Functions return PWM_STATUS_SUCCESS if the call was executed
* successfully.
*/
#define PWM_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by PWM_control().
*
* PWM_control() returns PWM_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define PWM_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by PWM_control() for undefined
* command codes.
*
* PWM_control() returns PWM_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define PWM_STATUS_UNDEFINEDCMD (-2)
/*!
* @brief An error status code returned by PWM_setPeriod().
*
* PWM_setPeriod() returns PWM_STATUS_INVALID_PERIOD if the period argument is
* invalid for the current configuration.
*/
#define PWM_STATUS_INVALID_PERIOD (-3)
/*!
* @brief An error status code returned by PWM_setDuty().
*
* PWM_setDuty() returns PWM_STATUS_INVALID_DUTY if the duty cycle argument is
* invalid for the current configuration.
*/
#define PWM_STATUS_INVALID_DUTY (-4)
/*!
* @brief PWM period unit definitions. Refer to device specific
* implementation if using PWM_PERIOD_COUNTS (raw PWM/Timer counts).
*/
typedef enum PWM_Period_Units_ {
PWM_PERIOD_US, /* Period in microseconds */
PWM_PERIOD_HZ, /* Period in (reciprocal) Hertz
(for example 2MHz = 0.5us period) */
PWM_PERIOD_COUNTS /* Period in timer counts */
} PWM_Period_Units;
/*!
* @brief PWM duty cycle unit definitions. Refer to device specific
* implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts).
*/
typedef enum PWM_Duty_Units_ {
PWM_DUTY_US, /* Duty cycle in microseconds */
PWM_DUTY_FRACTION, /* Duty as a fractional part of PWM_DUTY_FRACTION_MAX */
PWM_DUTY_COUNTS /* Duty in timer counts */
} PWM_Duty_Units;
/*!
* @brief Idle output level when PWM is not running (stopped / not started).
*/
typedef enum PWM_IdleLevel_ {
PWM_IDLE_LOW = 0,
PWM_IDLE_HIGH = 1,
} PWM_IdleLevel;
/*!
* @brief PWM Parameters
*
* PWM Parameters are used to with the PWM_open() call. Default values for
* these parameters are set using PWM_Params_init().
*
* @sa PWM_Params_init()
*/
typedef struct PWM_Params_ {
PWM_Period_Units periodUnits; /*!< Units in which the period is specified */
uint32_t periodValue; /*!< PWM initial period */
PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */
uint32_t dutyValue; /*!< PWM initial duty */
PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */
void *custom; /*!< Custom argument used by driver
implementation */
} PWM_Params;
/*!
* @brief A handle that is returned from a PWM_open() call.
*/
typedef struct PWM_Config_ *PWM_Handle;
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_close().
*/
typedef void (*PWM_CloseFxn) (PWM_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_control().
*/
typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_init().
*/
typedef void (*PWM_InitFxn) (PWM_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_open().
*/
typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_setDuty().
*/
typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle,
uint32_t duty);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_setPeriod().
*/
typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle,
uint32_t period);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_start().
*/
typedef void (*PWM_StartFxn) (PWM_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* PWM_stop().
*/
typedef void (*PWM_StopFxn) (PWM_Handle handle);
/*!
* @brief The definition of a PWM function table that contains the
* required set of functions to control a specific PWM driver
* implementation.
*/
typedef struct PWM_FxnTable_ {
/*! Function to close the specified instance */
PWM_CloseFxn closeFxn;
/*! Function to driver implementation specific control function */
PWM_ControlFxn controlFxn;
/*! Function to initialize the given data object */
PWM_InitFxn initFxn;
/*! Function to open the specified instance */
PWM_OpenFxn openFxn;
/*! Function to set the duty cycle for a specific instance */
PWM_SetDutyFxn setDutyFxn;
/*! Function to set the period for a specific instance */
PWM_SetPeriodFxn setPeriodFxn;
/*! Function to start the PWM output for a specific instance */
PWM_StartFxn startFxn;
/*! Function to stop the PWM output for a specific instance */
PWM_StopFxn stopFxn;
} PWM_FxnTable;
/*!
* @brief PWM Global configuration.
*
* The PWM_Config structure contains a set of pointers used to characterize
* the PWM driver implementation.
*
*/
typedef struct PWM_Config_ {
/*! Pointer to a table of driver-specific implementations of PWM APIs */
PWM_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} PWM_Config;
/*!
* @brief Function to close a PWM instance specified by the PWM handle.
*
* @pre PWM_open() must have been called first.
* @pre PWM_stop() must have been called first if PWM was started.
*
* @param handle A PWM handle returned from PWM_open().
*
* @sa PWM_open()
* @sa PWM_start()
* @sa PWM_stop()
*/
extern void PWM_close(PWM_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* PWM_Handle.
*
* @pre PWM_open() must have been called first.
*
* @param handle A PWM handle returned from PWM_open().
*
* @param cmd A command value defined by the driver specific
* implementation.
*
* @param arg A pointer to an optional R/W (read/write) argument that
* is accompanied with cmd.
*
* @return A PWM_Status describing an error or success state. Negative values
* indicate an error occurred.
*
* @sa PWM_open()
*/
extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief This function initializes the PWM module.
*
* @pre The PWM_config structure must exist and be persistent before this
* function can be called. This function must be called before any
* other PWM driver APIs. This function does not modify any peripheral
* registers & should only be called once.
*/
extern void PWM_init(void);
/*!
* @brief This function opens a given PWM instance and sets the period,
* duty and idle level to those specified in the params argument.
*
* @param index Logical instance number for the PWM indexed into
* the PWM_config table.
*
* @param params Pointer to an parameter structure. If NULL default
* values are used.
*
* @return A PWM_Handle if successful or NULL on an error or if it has been
* opened already. If NULL is returned further PWM API calls will
* result in undefined behavior.
*
* @sa PWM_close()
*/
extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params);
/*!
* @brief Function to initialize the PWM_Params structure to default values.
*
* @param params A pointer to PWM_Params structure for initialization.
*
* Defaults values are:
* Period units: PWM_PERIOD_HZ
* Period: 1e6 (1MHz)
* Duty cycle units: PWM_DUTY_FRACTION
* Duty cycle: 0%
* Idle level: PWM_IDLE_LOW
*/
extern void PWM_Params_init(PWM_Params *params);
/*!
* @brief Function to set the duty cycle of the specified PWM handle. PWM
* instances run in active high output mode; 0% is always low output,
* 100% is always high output. This API can be called while the PWM
* is running & duty must always be lower than or equal to the period.
* If an error occurs while calling the function the PWM duty cycle
* will remain unchanged.
*
* @pre PWM_open() must have been called first.
*
* @param handle A PWM handle returned from PWM_open().
*
* @param duty Duty cycle in the units specified by the params used
* in PWM_open().
*
* @return A PWM status describing an error or success. Negative values
* indicate an error.
*
* @sa PWM_open()
*/
extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty);
/*!
* @brief Function to set the period of the specified PWM handle. This API
* can be called while the PWM is running & the period must always be
* larger than the duty cycle.
* If an error occurs while calling the function the PWM period
* will remain unchanged.
*
* @pre PWM_open() must have been called first.
*
* @param handle A PWM handle returned from PWM_open().
*
* @param period Period in the units specified by the params used
* in PWM_open().
*
* @return A PWM status describing an error or success state. Negative values
* indicate an error.
*
* @sa PWM_open()
*/
extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period);
/*!
* @brief Function to start the specified PWM handle with current settings.
*
* @pre PWM_open() has to have been called first.
*
* @param handle A PWM handle returned from PWM_open().
*
* @sa PWM_open()
* @sa PWM_stop()
*/
extern void PWM_start(PWM_Handle handle);
/*!
* @brief Function to stop the specified PWM handle. Output will set to the
* idle level specified by params in PWM_open().
*
* @pre PWM_open() has to have been called first.
*
* @param handle A PWM handle returned from PWM_open().
*
* @sa PWM_open()
* @sa PWM_start()
*/
extern void PWM_stop(PWM_Handle handle);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_PWM__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file Power.h
*
* @brief Power manager interface
*
* The Power header file should be included in an application as follows:
* @code
* #include <ti/drivers/Power.h>
* @endcode
*
* # Operation #
* The Power manager facilitates the transition of the MCU from active state
* to one of the sleep states and vice versa. It provides drivers the
* ability to set and release dependencies on hardware resources and keeps
* a reference count on each resource to know when to enable or disable the
* peripheral clock to the resource. It provides drivers the ability to
* register a callback function upon a specific power event. In addition,
* drivers and apps can set or release constraints to prevent the MCU from
* transitioning into a particular sleep state.
*
* ============================================================================
*/
#ifndef ti_drivers_Power__include
#define ti_drivers_Power__include
#include <stdint.h>
#include <ti/drivers/utils/List.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Power latency types */
#define Power_TOTAL (1U) /*!< total latency */
#define Power_RESUME (2U) /*!< resume latency */
/* Power notify responses */
#define Power_NOTIFYDONE (0) /*!< OK, notify completed */
#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */
/* Power status */
#define Power_SOK (0) /*!< OK, operation succeeded */
#define Power_EFAIL (-1) /*!< general failure */
#define Power_EINVALIDINPUT (-2) /*!< invalid data value */
#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */
#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */
#define Power_EBUSY (-5) /*!< busy with another transition */
/* Power transition states */
#define Power_ACTIVE (1U) /*!< normal active state */
#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */
#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */
#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */
#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */
/*!
* @brief Power policy initialization function pointer
*/
typedef void (*Power_PolicyInitFxn)(void);
/*!
* @brief Power policy function pointer
*/
typedef void (*Power_PolicyFxn)(void);
/*!
* @brief Power notify function pointer
*/
typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType,
uintptr_t eventArg, uintptr_t clientArg);
/*!
* @brief Power notify object structure.
*
* This struct specification is for internal use. Notification clients must
* pre-allocate a notify object when registering for a notification;
* Power_registerNotify() will take care initializing the internal elements
* appropriately.
*/
typedef struct Power_NotifyObj_ {
List_Elem link; /*!< for placing on the notify list */
uint_fast16_t eventTypes; /*!< the event type */
Power_NotifyFxn notifyFxn; /*!< notification function */
uintptr_t clientArg; /*!< argument provided by client */
} Power_NotifyObj;
/*!
* @brief Disable the configured power policy from running when the CPU is
* idle
*
* Calling this function clears the flag that controls whether the configured
* power policy function is invoked on each pass through the Idle loop.
* This function call will override both a 'true' setting of the
* "enablePolicy" setting in the Power manager configuration object, as well
* as a previous runtime call to the Power_enablePolicy() function.
*
* @sa Power_enablePolicy
*/
void Power_disablePolicy(void);
/*!
* @brief Enable the configured power policy to run when the CPU is idle
*
* Calling this function sets a flag that will cause the configured power
* policy function to be invoked on each pass through the Idle loop. This
* function call will override both a 'false' setting of the "enablePolicy"
* setting in the Power manager configuration object, as well as a previous
* runtime call to the Power_disablePolicy() function.
*
* For some processor families, automatic power transitions can make initial
* application development more difficult, as well as being at odds with
* basic debugger operation. This convenience function allows an application
* to be initially configured, built, and debugged, without automatic power
* transitions during idle time. When the application is found to be working,
* this function can be called (typically in main()) to enable the policy
* to run, without having to change the application configuration.
*
* @sa Power_disablePolicy
*/
void Power_enablePolicy(void);
/*!
* @brief Get the constraints that have been declared with Power
*
* This function returns a bitmask indicating the constraints that are
* currently declared to the Power manager (via previous calls to
* Power_setConstraint()). For each constraint that is currently declared,
* the corresponding bit in the bitmask will be set. For example, if two
* clients have independently declared two different constraints, the returned
* bitmask will have two bits set.
*
* Constraint identifiers are device specific, and defined in the
* device-specific Power include file. For example, the constraints for
* MSP432 are defined in PowerMSP432.h. The corresponding bit in the
* bitmask returned by this function can be derived by a left-shift using
* the constraint identifier. For example, for MSP432, for the corresponding
* bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is
* determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP)
*
* @return A bitmask of the currently declared constraints.
*
* @sa Power_setConstraint
*/
uint_fast32_t Power_getConstraintMask(void);
/*!
* @brief Get the current dependency count for a resource
*
* This function returns the number of dependencies that are currently
* declared upon a resource.
*
* Resource identifiers are device specific, and defined in the
* device-specific Power include file. For example, the resources for
* CC32XX are defined in PowerCC32XX.h.
*
* @param resourceId resource id
*
* @return The number of dependencies declared for the resource.
* Power_EINVALIDINPUT if the resourceId is invalid.
*
* @sa Power_setDependency
*/
int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId);
/*!
* @brief Get the current performance level
*
* This function returns the current device performance level in effect.
*
* If performance scaling is not supported for the device, this function
* will always indicate a performance level of zero.
*
* @return The current performance level.
*
* @sa Power_setPerformanceLevel
*/
uint_fast16_t Power_getPerformanceLevel(void);
/*!
* @brief Get the hardware transition latency for a sleep state
*
* This function reports the minimal hardware transition latency for a specific
* sleep state. The reported latency is that for a direct transition, and does
* not include any additional latency that might occur due to software-based
* notifications.
*
* Sleep states are device specific, and defined in the device-specific Power
* include file. For example, the sleep states for CC32XX are defined in
* PowerCC32XX.h.
*
* This function is typically called by the power policy function. The latency
* is reported in units of microseconds.
*
* @param sleepState the sleep state
*
* @param type the latency type (Power_TOTAL or Power_RESUME)
*
* @return The latency value, in units of microseconds.
*/
uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState,
uint_fast16_t type);
/*!
* @brief Get the current transition state of the Power manager
*
* This function returns the current transition state for the Power manager.
* For example, when no transitions are in progress, a status of Power_ACTIVE
* is returned. Power_ENTERING_SLEEP is returned during the transition to
* sleep, before sleep has occurred. Power_EXITING_SLEEP is returned
* after wakeup, as the device is being transitioned back to Power_ACTIVE.
* And Power_CHANGING_PERF_LEVEL is returned when a change is being made
* to the performance level.
*
* @return The current Power manager transition state.
*/
uint_fast16_t Power_getTransitionState(void);
/*!
* @brief Power function to be added to the application idle loop
*
* This function should be added to the application idle loop. (The method to
* do this depends upon the operating system being used.) This function
* will invoke the configured power policy function when appropriate. The
* specific policy function to be invoked is configured as the 'policyFxn'
* in the application-defined Power configuration object.
*
*/
void Power_idleFunc(void);
/*!
* @brief Power initialization function
*
* This function initializes Power manager internal state. It must be called
* prior to any other Power API. This function is normally called as part
* of TI-RTOS board initialization, for example, from within the
* \<board name\>_initGeneral() function.
*
* @return Power_SOK
*/
int_fast16_t Power_init(void);
/*!
* @brief Register a function to be called upon a specific power event
*
* This function registers a function to be called when a Power event occurs.
* Registrations and the corresponding notifications are processed in
* first-in-first-out (FIFO) order. The function registered must behave as
* described later, below.
*
* The pNotifyObj parameter is a pointer to a pre-allocated, opaque object
* that will be used by Power to support the notification. This object could
* be dynamically allocated, or declared as a global object. This function
* will properly initialized the object's fields as appropriate; the caller
* just needs to provide a pointer to this pre-existing object.
*
* The eventTypes parameter identifies the type of power event(s) for which
* the notify function being registered is to be called. (Event identifiers are
* device specific, and defined in the device-specific Power include file.
* For example, the events for MSP432 are defined in PowerMSP432.h.) The
* eventTypes parameter for this function call is treated as a bitmask, so
* multiple event types can be registered at once, using a common callback
* function. For example, to call the specified notifyFxn when both
* the entering deepsleep and awake from deepsleep events occur, eventTypes
* should be specified as: PowerMSP432_ENTERING_DEEPSLEEP |
* PowerMSP432_AWAKE_DEEPSLEEP
*
* The notifyFxn parameter specifies a callback function to be called when the
* specified Power event occurs. The notifyFxn must implement the following
* signature:
* status = notifyFxn(eventType, eventArg, clientArg);
*
* Where: eventType identifies the event being signalled, eventArg is an
* optional event-specific argument, and clientArg is an abitrary argument
* specified by the client at registration. Note that multipe types of events
* can be specified when registering the notification callback function,
* but when the callback function is actually called by Power, only a
* single eventType will be specified for the callback (i.e., the current
* event). The status returned by the client notification function must
* be one of the following constants: Power_NOTIFYDONE if the client processed
* the notification successfully, or Power_NOTIFYERROR if an error occurred
* during notification.
*
* The clientArg parameter is an arbitrary, client-defined argument to be
* passed back to the client upon notification. This argument may allow one
* notify function to be used by multiple instances of a driver (that is, the
* clientArg can be used to identify the instance of the driver that is being
* notified).
*
* @param pNotifyObj notification object (preallocated by caller)
*
* @param eventTypes event type or types
*
* @param notifyFxn client's callback function
*
* @param clientArg client-specified argument to pass with notification
*
* @return Power_SOK on success.
* Power_EINVALIDPOINTER if either pNotifyObj or notifyFxn are NULL.
*
* @sa Power_unregisterNotify
*/
int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj,
uint_fast16_t eventTypes,
Power_NotifyFxn notifyFxn,
uintptr_t clientArg);
/*!
* @brief Release a previously declared constraint
*
* This function releases a constraint that was previously declared with
* Power_setConstraint(). For example, if a device driver is starting an I/O
* transaction and wants to prohibit activation of a sleep state during the
* transaction, it uses Power_setConstraint() to declare the constraint,
* before starting the transaction. When the transaction completes, the
* driver calls this function to release the constraint, to allow the Power
* manager to once again allow transitions to sleep.
*
* Constraint identifiers are device specific, and defined in the
* device-specific Power include file. For example, the constraints for
* MSP432 are defined in PowerMSP432.h.
*
* Only one constraint can be specified with each call to this function; to
* release multiple constraints this function must be called multiple times.
*
* It is critical that clients call Power_releaseConstraint() when operational
* constraints no longer exists. Otherwise, Power may be left unnecessarily
* restricted from activating power savings.
*
* @param constraintId constraint id
*
* @return Power_SOK on success.
* Power_EINVALIDINPUT if the constraintId is incorrect.
* Power_EFAIL if the constraint cannot be released.
*
* @sa Power_setConstraint
*/
int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId);
/*!
* @brief Release a previously declared dependency
*
* This function releases a dependency that had been previously declared upon
* a resource (by a call to Power_setDependency()).
*
* Resource identifiers are device specific, and defined in the
* device-specific Power include file. For example, the resources for
* CC32XX are defined in PowerCC32XX.h.
*
* @param resourceId resource id
*
* @return Power_SOK on success.
* Power_EINVALIDINPUT if the resourceId is incorrect.
* Power_EFAIL if the resource dependency cannot be released.
*
* @sa Power_setDependency
*/
int_fast16_t Power_releaseDependency(uint_fast16_t resourceId);
/*!
* @brief Declare an operational constraint
*
* Before taking certain actions, the Power manager checks to see if the
* requested action would conflict with a client-declared constraint. If the
* action does conflict, Power will not proceed with the request. This is the
* function that allows clients to declare their constraints with Power.
*
* Constraint identifiers are device specific, and defined in the
* device-specific Power include file. For example, the constraints for
* MSP432 are defined in PowerMSP432.h.
*
* Only one constraint can be specified with each call to this function; to
* declare multiple constraints this function must be called multiple times.
*
* @param constraintId constraint id
*
* @return Power_SOK on success.
* Power_EINVALIDINPUT if the constraintId is incorrect.
*
* @sa Power_releaseConstraint
*/
int_fast16_t Power_setConstraint(uint_fast16_t constraintId);
/*!
* @brief Declare a dependency upon a resource
*
* This function declares a dependency upon a resource. For example, if a
* UART driver needs a specific UART peripheral, it uses this function to
* declare this to the Power manager. If the resource had been inactive,
* then Power will activate the peripheral during this function call.
*
* What is needed to make a peripheral resource 'active' will vary by device
* family. For some devices this may be a simple enable of a clock to the
* specified peripheral. For others it may also require a power on of a
* power domain. In either case, the Power manager will take care of these
* details, and will also implement reference counting for resources and their
* interdependencies. For example, if multiple UART peripherals reside in
* a shared serial power domain, the Power manager will power up the serial
* domain when it is first needed, and then automatically power the domain off
* later, when all related dependencies for the relevant peripherals are
* released.
*
* Resource identifiers are device specific, and defined in the
* device-specific Power include file. For example, the resources for
* CC32XX are defined in PowerCC32XX.h.
*
* @param resourceId resource id
*
* @return Power_SOK on success.
* Power_EINVALIDINPUT if the resourceId is incorrect.
*
* @sa Power_releaseDependency
*/
int_fast16_t Power_setDependency(uint_fast16_t resourceId);
/*!
* @brief Set the MCU performance level
*
* This function manages a transition to a new device performance level.
* Before the actual transition is initiated, notifications will be sent to
* any clients who've registered (with Power_registerNotify()) for a
* 'start change performance level' notification. The event name is device
* specific, and defined in the device-specific Power include file. For
* example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL",
* which is defined in PowerMSP432.h. Once notifications have been completed,
* the change to the performance level is initiated. After the level change
* is completed, there is a comparable event that can be used to signal a
* client that the change has completed. For example, on MSP432 the
* "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal
* completion.
*
* This function will not return until the new performance level is in effect.
* If performance scaling is not supported for the device, or is prohibited
* by an active constraint, or if the specified level is invalid, then an
* error status will be returned.
*
* @param level the new performance level
*
* @return Power_SOK on success.
* Power_EINVALIDINPUT if the specified performance level is out of
* range of valid levels.
* Power_EBUSY if another transition is already in progress, or if
* a single constraint is set to prohibit any change to the
* performance level.
* Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits
* a change to the requested level.
* Power_EFAIL if performance scaling is not supported, if an
* error occurred during initialization, or if an error occurred
* during client notifications.
*
* @sa Power_getPerformanceLevel
*/
int_fast16_t Power_setPerformanceLevel(uint_fast16_t level);
/*!
* @brief Set a new Power policy
*
* This function allows a new Power policy function to be selected at runtime.
*
* @param policy the new Power policy function
*/
void Power_setPolicy(Power_PolicyFxn policy);
/*!
* @brief Put the device into a shutdown state
*
* This function will transition the device into a shutdown state.
* Before the actual transition is initiated, notifications will be sent to
* any clients who've registered (with Power_registerNotify()) for an
* 'entering shutdown' event. The event name is device specific, and defined
* in the device-specific Power include file. For example, for CC32XX, the
* event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in
* PowerCC32XX.h. Once notifications have been completed, the device shutdown
* will commence.
*
* If the device is successfully transitioned to shutdown, this function
* call will never return. Upon wakeup, the device and application will
* be rebooted (through a device reset). If the transition is not
* successful, one of the error codes listed below will be returned.
*
* On some devices a timed wakeup from shutdown can be specified, using
* the shutdownTime parameter. This enables an autonomous application reboot
* at a future time. For example, an application can go to shutdown, and then
* automatically reboot at a future time to do some work. And once that work
* is done, the application can shutdown again, for another timed interval.
* The time interval is specified via the shutdownTime parameter. (On devices
* that do not support this feature, any value specified for shutdownTime will
* be ignored.) If the specified shutdownTime is less than the total
* shutdown latency for the device, then shutdownTime will be ignored. The
* shutdown latency for the device can be found in the device-specific Power
* include file. For example, for the CC32XX, this latency is defined in
* PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".)
*
* @param shutdownState the device-specific shutdown state
*
* @param shutdownTime the amount of time (in milliseconds) to keep the
* the device in the shutdown state; this parameter
* is not supported on all device families
*
* @return Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting shutdown.
* Power_EFAIL if an error occurred during client notifications.
* Power_EINVALIDINPUT if the shutdownState is invalid.
* Power_EBUSY if another transition is already in progress.
*/
int_fast16_t Power_shutdown(uint_fast16_t shutdownState,
uint_fast32_t shutdownTime);
/*!
* @brief Transition the device into a sleep state
*
* This function is called from the power policy when it has made a decision
* to put the device in a specific sleep state. This function returns to the
* caller (the policy function) once the device has awoken from sleep.
*
* This function must be called with interrupts disabled, and should not be
* called directly by the application, or by any drivers.
* This function does not check declared constraints; the policy function
* must check constraints before calling this function to initiate sleep.
*
* @param sleepState the sleep state
*
* @return Power_SOK on success, the device has slept and is awake again.
* Power_EFAIL if an error occurred during client notifications.
* Power_EINVALIDINPUT if the sleepState is invalid.
* Power_EBUSY if another transition is already in progress.
*/
int_fast16_t Power_sleep(uint_fast16_t sleepState);
/*!
* @brief Unregister previously registered notifications
*
* This function unregisters for event notifications that were previously
* registered with Power_registerNotify(). The caller must specify a pointer
* to the same notification object used during registration.
*
* @param pNotifyObj notify object
*
* @sa Power_registerNotify
*/
void Power_unregisterNotify(Power_NotifyObj *pNotifyObj);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_Power__include */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file SD.h
*
* @brief SD driver interface
*
* The SD header file should be included in an application as follows:
* @code
* #include <ti/drivers/SD.h>
* @endcode
*
* # Operation #
*
* The SD driver is designed to serve as an interface to perform basic
* transfers directly to the SD card.
*
* ## Opening the driver #
*
* @code
* SD_Handle handle;
*
* handle = SD_open(index, NULL);
* if (handle == NULL) {
* System_printf("Error opening SD driver\n");
* }
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS applications. Its
* purpose is to redirect the module's APIs to specific peripheral
* implementations which are specified using a pointer to a
* SD_FxnTable.
*
* The SD driver interface module is joined (at link time) to a
* NULL-terminated array of SD_Config data structures named *SD_config*.
* *SD_config* is implemented in the application with each entry being an
* instance of a SD peripheral. Each entry in *SD_config* contains a:
* - (SD_FxnTable *) to a set of functions that implement a SD peripheral
* - (uintptr_t) data object that is associated with the SD_FxnTable
* - (uintptr_t) hardware attributes that are associated to the SD_FxnTable
*
* # Instrumentation #
*
* The SD driver interface produces log statements if
* instrumentation is enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_SD__include
#define ti_drivers_SD__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @defgroup SD_CONTROL SD_control command and status codes
* @{
*/
/*!
* Common SD_control command code reservation offset.
* SD driver implementations should offset command codes with
* SD_CMD_RESERVED growing positively.
*
* Example implementation specific command codes:
* @code
* #define SDXYZ_CMD_COMMAND0 (SD_CMD_RESERVED + 0)
* #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1)
* @endcode
*/
#define SD_CMD_RESERVED (32)
/*!
* Common SD_control status code reservation offset.
* SD driver implementations should offset status codes with
* SD_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define SDXYZ_STATUS_ERROR0 (SD_STATUS_RESERVED - 0)
* #define SDXYZ_STATUS_ERROR1 (SD_STATUS_RESERVED - 1)
* #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2)
* @endcode
*/
#define SD_STATUS_RESERVED (-32)
/**
* @defgroup SD_STATUS Status Codes
* SD_STATUS_* macros are general status codes returned by SD_control()
* @{
* @ingroup SD_CONTROL
*/
/*!
* @brief Successful status code returned by SD_control().
*
* SD_control() returns SD_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define SD_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by SD_control().
*
* SD_control() returns SD_STATUS_ERROR if the control code
* was not executed successfully.
*/
#define SD_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by SD_control() for
* undefined command codes.
*
* SD_control() returns SD_STATUS_UNDEFINEDCMD if the
* control code is not recognized by the driver implementation.
*/
#define SD_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup SD_CMD Command Codes
* SD_CMD_* macros are general command codes for SD_control(). Not all SD
* driver implementations support these command codes.
* @{
* @ingroup SD_CONTROL
*/
/* Add SD_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief SD Card type inserted
*/
typedef enum SD_CardType_ {
SD_NOCARD = 0, /*!< Unrecognized Card */
SD_MMC = 1, /*!< Multi-media Memory Card (MMC) */
SD_SDSC = 2, /*!< Standard SDCard (SDSC) */
SD_SDHC = 3 /*!< High Capacity SDCard (SDHC) */
} SD_CardType;
/*!
* @brief A handle that is returned from a SD_open() call.
*/
typedef struct SD_Config_ *SD_Handle;
/*!
* @brief SD Parameters
*
* SD Parameters are used to with the SD_open() call.
* Default values for these parameters are set using SD_Params_init().
*
* @sa SD_Params_init()
*/
/* SD Parameters */
typedef struct SD_Params_ {
void *custom; /*!< Custom argument used by driver implementation */
} SD_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* SD_CloseFxn().
*/
typedef void (*SD_CloseFxn) (SD_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_controlFxn().
*/
typedef int_fast16_t (*SD_ControlFxn) (SD_Handle handle,
uint_fast16_t cmd, void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_getNumSectorsFxn().
*/
typedef uint_fast32_t (*SD_getNumSectorsFxn) (SD_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_getSectorSizeFxn().
*/
typedef uint_fast32_t (*SD_getSectorSizeFxn) (void);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_InitFxn().
*/
typedef void (*SD_InitFxn) (SD_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_initializeFxn().
*/
typedef int_fast16_t (*SD_InitializeFxn) (SD_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_OpenFxn().
*/
typedef SD_Handle (*SD_OpenFxn) (SD_Handle handle, SD_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_readFxn().
*/
typedef int_fast16_t (*SD_ReadFxn) (SD_Handle handle, void *buf,
int_fast32_t sector, uint_fast32_t secCount);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_writeFxn().
*/
typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void *buf,
int_fast32_t sector, uint_fast32_t secCount);
/*!
* @brief The definition of a SD function table that contains the
* required set of functions to control a specific SD driver
* implementation.
*/
typedef struct SD_FxnTable_ {
/*! Function to close the specified peripheral */
SD_CloseFxn closeFxn;
/*! Function to implementation specific control function */
SD_ControlFxn controlFxn;
/*! Function to return the total number of sectors on the SD card */
SD_getNumSectorsFxn getNumSectorsFxn;
/*! Function to return the sector size used to address the SD card */
SD_getSectorSizeFxn getSectorSizeFxn;
/*! Function to initialize the given data object */
SD_InitFxn initFxn;
/*! Function to initialize the SD card */
SD_InitializeFxn initializeFxn;
/*! Function to open the specified peripheral */
SD_OpenFxn openFxn;
/*! Function to read from the SD card */
SD_ReadFxn readFxn;
/*! Function to write to the SD card */
SD_WriteFxn writeFxn;
} SD_FxnTable;
/*!
* @brief SD Global configuration
*
* The SD_Config structure contains a set of pointers used
* to characterize the SD driver implementation.
*
* This structure needs to be defined before calling SD_init() and it must
* not be changed thereafter.
*
* @sa SD_init()
*/
typedef struct SD_Config_ {
/*! Pointer to a table of driver-specific implementations of SD APIs */
SD_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} SD_Config;
/*!
* @brief Function to close a SD peripheral specified by the SD handle.
*
* @pre SD_open() had to be called first.
*
* @param handle A SD handle returned from SD_open
*
* @sa SD_open()
*/
extern void SD_close(SD_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* SD_Handle.
*
* Commands for SD_control can originate from SD.h or from implementation
* specific SD*.h (SDHostCC32XX.h etc.. ) files.
* While commands from SD.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific SD*.h files add
* unique driver capabilities but are not API portable across all SD driver
* implementations.
*
* Commands supported by SD.h follow a SD*_CMD naming
* convention.
*
* Commands supported by SD*.h follow a SD*_CMD naming
* convention.
* Each control command defines arg differently. The types of arg are
* documented with each command.
*
* See @ref SD_CMD "SD_control command codes" for command codes.
*
* See @ref SD_STATUS "SD_control return status codes" for status codes.
*
* @pre SD_open() has to be called first.
*
* @param handle A SD handle returned from SD_open().
*
* @param cmd SD.h or SD*.h commands.
*
* @param arg An optional R/W (read/write) command argument
* accompanied with cmd.
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa SD_open()
*/
extern int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_getNumSectors().
* Note: Total Card capacity is the (NumberOfSectors * SectorSize).
*
* @pre SD Card has been initialized using SD_initialize().
*
* @param handle A SD handle returned from SD_open().
*
* @return The total number of sectors on the SD card,
* or 0 if an error occurred.
*
* @sa SD_initialize()
*/
extern uint_fast32_t SD_getNumSectors(SD_Handle handle);
/*!
* @brief Function to obtain the sector size used to access the SD card.
*
* @pre SD Card has been initialized using SD_initialize().
*
* @param handle A SD handle returned from SD_open().
*
* @return The sector size set for use during SD card read/write operations.
*
* @sa SD_initialize()
*/
extern uint_fast32_t SD_getSectorSize(SD_Handle handle);
/*!
* @brief This function initializes the SD driver.
*
* @pre The SD_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other SD driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void SD_init(void);
/*!
* @brief Function to initialize the SD_Params struct to its defaults.
*
* @param params A pointer to SD_Params structure for initialization.
*/
extern void SD_Params_init(SD_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_initialize().
*
* @pre SD controller has been opened by calling SD_open().
*
* @param handle A SD handle returned from SD_open().
*
* @return SD_STATUS_SUCCESS if no errors occurred during the initialization,
* SD_STATUS_ERROR otherwise.
*/
extern int_fast16_t SD_initialize(SD_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_open().
*
* @pre SD controller has been initialized using SD_init().
*
* @param index Logical peripheral number for the SD indexed into
* the SD_config table.
*
* @param params Pointer to a parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A SD_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa SD_init()
* @sa SD_close()
*/
extern SD_Handle SD_open(uint_least8_t index, SD_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_read().
*
* @pre SD controller has been opened and initialized by calling SD_open()
* followed by SD_initialize().
*
* @param handle A SD handle returned from SD_open().
*
* @param buf Pointer to a buffer to read data into.
*
* @param sector Starting sector on the disk to read from.
*
* @param secCount Number of sectors to be read.
*
* @return SD_STATUS_SUCCESS if no errors occurred during the write,
* SD_STATUS_ERROR otherwise.
*
* @sa SD_initialize()
*/
extern int_fast16_t SD_read(SD_Handle handle, void *buf,
int_fast32_t sector, uint_fast32_t secCount);
/*!
* @brief A function pointer to a driver specific implementation of
* SD_write().
*
* @pre SD controller has been opened and initialized by calling SD_open()
* followed by SD_initialize().
*
* @param handle A SD handle returned from SD_open().
*
* @param buf Pointer to a buffer containing data to write to disk.
*
* @param sector Starting sector on the disk to write to.
*
* @param secCount Number of sectors to be written.
*
* @return SD_STATUS_SUCCESS if no errors occurred during the write,
* SD_STATUS_ERROR otherwise.
*
* @sa SD_initialize()
*/
extern int_fast16_t SD_write(SD_Handle handle, const void *buf,
int_fast32_t sector, uint_fast32_t secCount);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_SD__include */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file SDFatFS.h
*
* @brief FATFS driver interface
*
* The SDFatFS header file should be included in an application as follows:
* @code
* #include <ti/drivers/SDFatFS.h>
* #include <ti/drivers/SD.h>
* @endcode
*
* # Operation #
*
* The SDFatFS driver is designed to hook into FatFs by implementing a
* set of functions that FatFs needs to call to perform basic block data
* transfers. This driver makes use of the SD driver for lower level disk IO
* operations.
*
* The only functions that should be called by the application are the
* standard driver framework functions (_open, _close, etc...).
*
* The application may use the FatFs APIs or the standard C
* runtime file I/O calls (fopen, fclose, etc...) given that SDFatFS_open has
* has been successfully called. After the SDFatFS_close API is called,
* ensure the application does NOT make any file I/O calls.
*
* ## Opening the driver #
*
* @code
* SDFatFS_Handle handle;
*
* handle = SDFatFS_open(index, driveNum, NULL);
* if (!handle) {
* System_printf("Error opening SDFatFS driver\n");
* }
* @endcode
*
* # Implementation #
*
* The SDFatFS driver interface module is joined (at link time) to a NULL
* terminated array of SDFatFS_Config data structures named *SDFatFS_config*.
* *SDFatFS_config* is implemented in the application with each entry being an
* instance of the driver. Each entry in *SDFatFS_config* contains a:
* - (void *) data object that contains internal driver data structures
*
* # Instrumentation #
*
* The SDFatFS driver interface produces log statements if
* instrumentation is enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
* ============================================================================
*/
#ifndef ti_drivers_SDFatFS__include
#define ti_drivers_SDFatFS__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <ti/drivers/SD.h>
#include <third_party/fatfs/ff.h>
#include <third_party/fatfs/diskio.h>
/*!
* @brief SDFatFS Object
* The application must not access any member variables of this structure!
*/
typedef struct SDFatFS_Object_ {
uint_fast32_t driveNum;
DSTATUS diskState;
FATFS filesystem; /* FATFS data object */
SD_Handle sdHandle;
} SDFatFS_Object;
/*!
* @brief A handle that is returned from a SDFatFS_open() call.
*/
typedef struct SDFatFS_Config_ *SDFatFS_Handle;
/*!
* @brief SDFatFS Global configuration
*
* The SDFatFS_Config structure contains a single pointer used to characterize
* the SDFatFS driver implementation.
*
* This structure needs to be defined before calling SDFatFS_init() and it must
* not be changed thereafter.
*
* @sa SDFatFS_init()
*/
typedef struct SDFatFS_Config_ {
/*! Pointer to a SDFatFS object */
void *object;
} SDFatFS_Config;
/*!
* @brief Function to open a SDFatFS instance on the specified drive.
*
* Function to mount the FatFs filesystem and register the SDFatFS disk
* I/O functions with the FatFS module.
*
* @param idx Logical peripheral number indexed into the HWAttrs
* table.
* @param drive Drive Number
*/
extern SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive);
/*!
* @brief Function to close a SDFatFS instance specified by the SDFatFS
* handle.
*
* This function unmounts the file system mounted by SDFatFS_open and
* unregisters the SDFatFS driver from the FatFs module.
*
* @pre SDFatFS_open() had to be called first.
*
* @param handle A SDFatFS handle returned from SDFatFS_open
*
* @sa SDFatFS_open()
*/
extern void SDFatFS_close(SDFatFS_Handle handle);
/*!
* Function to initialize a SDFatFS instance
*/
extern void SDFatFS_init(void);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_SDFatFS__include */

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file SDSPI.h
*
* @brief SDSPI driver interface
*
* The SDSPI header file should be included in an application as follows:
* @code
* #include <ti/drivers/SDSPI.h>
* @endcode
*
* # Overview #
* The SDSPI FatFs driver is used to communicate with SD (Secure Digital)
* cards via SPI (Serial Peripheral Interface).
*
* The SDSPI driver is a FatFs driver module for the FatFs middleware
* module. With the exception of the standard driver APIs -
* SDSPI_open(), SDSPI_close(), and SDSPI_init() - the SDSPI driver
* is exclusively used by FatFs module to handle the low-level hardware
* communications.
*
* The SDSPI driver only supports one SSI (SPI) peripheral at a given time.
* It does not utilize interrupts.
*
* The SDSPI driver is polling based for performance reasons and due to the
* relatively high SPI bus bit rate. This means it does not utilize the
* SPI's peripheral interrupts, and it consumes the entire CPU time when
* communicating with the SPI bus. Data transfers to or from the SD card
* are typically 512 bytes, which could take a significant amount of time
* to complete. During this time, only higher priority Tasks, Swis, and
* Hwis can preempt Tasks making calls that use the FatFs.
*
* # Usage #
* Before any FatFs or C I/O APIs can be used, the application needs to
* open the SDSPI driver. The SDSPI_open() function ensures that the SDSPI
* disk functions get registered with the FatFs module that subsequently
* mounts the FatFs volume to that particular drive.
*
* @code
* SDSPI_Handle sdspiHandle;
* SDSPI_Params sdspiParams;
* UInt peripheralNum = 0;
* UInt FatFsDriveNum = 0;
*
* SDSPI_Params_init(&sdspiParams);
*
* sdspiHandle = SDSPI_open(peripheralNum, FatFsDriveNum, &sdspiParams);
* if (sdspiHandle == NULL) {
* System_abort("Error opening SDSPI\n");
* }
* @endcode
*
* Similarly, the SDSPI_close() function unmounts the FatFs volume and
* unregisters SDSPI disk functions.
*
* @code
* SDSPI_close(sdspiHandle);
* @endcode
*
* Note that it is up to the application to ensure the no FatFs or C I/O
* APIs are called before the SDSPI driver has been opened or after the
* SDSPI driver has been closed.
*
* ### SDSPI Driver Configuration #
* The SDSPI driver requires the application to initialize board-specific
* portions of the SDSPI and provide the SDSPI driver with the SDSPI_config
* structure.
*
* #### Board-Specific Configuration #
*
* The SDSPI_init() initializes the SDSPI driver snd any board-specific
* SDSPI peripheral settings.
*
* #### SDSPI_config Structure #
*
* The \<*board*\>.c file declares the SDSPI_config structure. This
* structure must be provided to the SDSPI driver. It must be initialized
* before the SDSPI_init() function is called and cannot be changed
* afterwards.
*
* The SDSPI driver interface defines a configuration data structure:
*
* @code
* typedef struct SDSPI_Config_ {
* SDSPI_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } SDSPI_Config;
* @endcode
*
* # Operation #
*
* The SDSPI driver is a driver designed to hook into FatFs. It implements a
* set of functions that FatFs needs to call to perform basic block data
* transfers.
*
* A SDSPI driver peripheral implementation doesn't require RTOS protection
* primitives due to the resource protection provided with FatFs. The only
* functions that can be called by the application are the standard driver
* framework functions (_open, _close, etc...).
*
* Once the driver has been opened, the application may used the FatFs APIs or
* the standard C runtime file I/O calls (fopen, fclose, etc...). Once the
* driver has been closed, ensure the application does NOT make any file I/O
* calls.
*
* ### Opening the SDSPI driver #
*
* @code
* SDSPI_Handle handle;
* SDSPI_Params params;
*
* SDSPI_Params_init(&params);
* params.bitRate = someNewBitRate;
* handle = SDSPI_open(someSDSPI_configIndexValue, &params);
* if (!handle) {
* System_printf("SDSPI did not open");
* }
* @endcode
*
* # Implementation #
*
* The SDSPI driver interface module is joined (at link time) to an
* array of SDSPI_Config data structures named *SDSPI_config*.
* SDSPI_config is implemented in the application with each entry being an
* instance of a SDSPI peripheral. Each entry in *SDSPI_config* contains a:
* - (SDSPI_FxnTable *) to a set of functions that implement a SDSPI peripheral
* - (void *) data object that is associated with the SDSPI_FxnTable
* - (void *) hardware attributes that are associated with the SDSPI_FxnTable
*
* The SDSPI APIs are redirected to the device specific implementations
* using the SDSPI_FxnTable pointer of the SDSPI_config entry.
* In order to use device specific functions of the SDSPI driver directly,
* link in the correct driver library for your device and include the
* device specific SDSPI driver header file (which in turn includes SDSPI.h).
* For example, for the MSP432 family of devices, you would include the
* following header file:
* @code
* #include <ti/drivers/sdspi/SDSPIMSP432.h>
* @endcode
*
*******************************************************************************
*/
#ifndef ti_drivers_SDSPI__include
#define ti_drivers_SDSPI__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @defgroup SDSPI_CONTROL SDSPI_control command and status codes
* These SDSPI macros are reservations for SDSPI.h
* @{
*/
/*!
* Common SDSPI_control command code reservation offset.
* SDSPI driver implementations should offset command codes with
* SDSPI_CMD_RESERVED growing positively
*
* Example implementation specific command codes:
* @code
* #define SDSPIXYZ_CMD_COMMAND0 SDSPI_CMD_RESERVED + 0
* #define SDSPIXYZ_CMD_COMMAND1 SDSPI_CMD_RESERVED + 1
* @endcode
*/
#define SDSPI_CMD_RESERVED (32)
/*!
* Common SDSPI_control status code reservation offset.
* SDSPI driver implementations should offset status codes with
* SDSPI_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define SDSPIXYZ_STATUS_ERROR0 SDSPI_STATUS_RESERVED - 0
* #define SDSPIXYZ_STATUS_ERROR1 SDSPI_STATUS_RESERVED - 1
* #define SDSPIXYZ_STATUS_ERROR2 SDSPI_STATUS_RESERVED - 2
* @endcode
*/
#define SDSPI_STATUS_RESERVED (-32)
/**
* @defgroup SDSPI_STATUS Status Codes
* SDSPI_STATUS_* macros are general status codes returned by SDSPI_control()
* @{
* @ingroup SDSPI_CONTROL
*/
/*!
* @brief Successful status code returned by SDSPI_control().
*
* SDSPI_control() returns SDSPI_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define SDSPI_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by SDSPI_control().
*
* SDSPI_control() returns SDSPI_STATUS_ERROR if the control code was not
* executed successfully.
*/
#define SDSPI_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by SDSPI_control() for undefined
* command codes.
*
* SDSPI_control() returns SDSPI_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define SDSPI_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup SDSPI_CMD Command Codes
* SDSPI_CMD_* macros are general command codes for SDSPI_control(). Not all SDSPI
* driver implementations support these command codes.
* @{
* @ingroup SDSPI_CONTROL
*/
/* Add SDSPI_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from a SDSPI_open() call.
*/
typedef struct SDSPI_Config_ *SDSPI_Handle;
/*!
* @brief SDSPI Parameters
*
* SDSPI Parameters are used to with the SDSPI_open() call. Default values for
* these parameters are set using SDSPI_Params_init().
*
* @sa SDSPI_Params_init()
*/
typedef struct SDSPI_Params_ {
uint32_t bitRate; /*!< SPI bit rate in Hz */
void *custom; /*!< Custom argument used by driver implementation */
} SDSPI_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* SDSPI_init().
*/
typedef void (*SDSPI_InitFxn) (SDSPI_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SDSPI_open().
*/
typedef SDSPI_Handle (*SDSPI_OpenFxn) (SDSPI_Handle handle,
uint_least8_t drv,
SDSPI_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* SDSPI_close().
*/
typedef void (*SDSPI_CloseFxn) (SDSPI_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* SDSPI_control().
*/
typedef int_fast16_t (*SDSPI_ControlFxn) (SDSPI_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief The definition of a SDSPI function table that contains the
* required set of functions to control a specific SDSPI driver
* implementation.
*/
typedef struct SDSPI_FxnTable_ {
/*! Function to initialized the given data object */
SDSPI_InitFxn initFxn;
/*! Function to open the specified peripheral */
SDSPI_OpenFxn openFxn;
/*! Function to close the specified peripheral */
SDSPI_CloseFxn closeFxn;
/*! Function to implementation specific control function */
SDSPI_ControlFxn controlFxn;
} SDSPI_FxnTable;
/*!
* @brief SDSPI Global configuration
*
* The SDSPI_Config structure contains a set of pointers used to characterize
* the SDSPI driver implementation.
*
* This structure needs to be defined before calling SDSPI_init() and it must
* not be changed thereafter.
*
* @sa SDSPI_init()
*/
typedef struct SDSPI_Config_ {
/*! Pointer to a table of driver-specific implementations of SDSPI APIs */
SDSPI_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} SDSPI_Config;
/*!
* @brief Function to close a SDSPI peripheral specified by the SDSPI handle.
* This function unmounts the file system mounted by SDSPI_open and
* unregisters the SDSPI driver from BIOS' FatFs module.
*
* @pre SDSPI_open() had to be called first.
*
* @param handle A SDSPI handle returned from SDSPI_open
*
* @sa SDSPI_open()
*/
extern void SDSPI_close(SDSPI_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* SDSPI_Handle.
*
* Commands for SDSPI_control can originate from SDSPI.h or from implementation
* specific SDSPI*.h (_SDSPICC26XX.h_, _SDSPIMSP432.h_, etc.. ) files.
* While commands from SDSPI.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific SDSPI*.h files add
* unique driver capabilities but are not API portable across all SDSPI driver
* implementations.
*
* Commands supported by SDSPI.h follow a SDSPI_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by SDSPI*.h follow a SDSPI*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref SDSPI_CMD "SDSPI_control command codes" for command codes.
*
* See @ref SDSPI_STATUS "SDSPI_control return status codes" for status codes.
*
* @pre SDSPI_open() has to be called first.
*
* @param handle A SDSPI handle returned from SDSPI_open()
*
* @param cmd SDSPI.h or SDSPI*.h commands.
*
* @param arg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa SDSPI_open()
*/
extern int_fast16_t SDSPI_control(SDSPI_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief This function initializes the SDSPI driver module.
*
* @pre The SDSPI_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other SDSPI driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void SDSPI_init(void);
/*!
* @brief This function registers the SDSPI driver with BIOS' FatFs module
* and mounts the FatFs file system.
*
* @pre SDSPI controller has been initialized using SDSPI_init()
*
* @param index Logical peripheral number for the SDSPI indexed into
* the SDSPI_config table
*
* @param drv Drive number to be associated with the SDSPI FatFs
* driver
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A SDSPI_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa SDSPI_init()
* @sa SDSPI_close()
*/
extern SDSPI_Handle SDSPI_open(uint_least8_t index, uint_least8_t drv,
SDSPI_Params *params);
/*!
* @brief Function to initialize the SDSPI_Params struct to its defaults
*
* @param params An pointer to SDSPI_Params structure for
* initialization
*
* Defaults values are:
* bitRate = 12500000 (Hz)
*/
extern void SDSPI_Params_init(SDSPI_Params *params);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_SDSPI__include */

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