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Add memory barrier instructions to Tasking CM4F port.
This commit is contained in:
Richard Barry
parent
7132e88685
commit
9a15f50b00
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@ -56,19 +56,19 @@
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
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fully thread aware and reentrant UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
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indemnification and middleware, under the OpenRTOS brand.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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@ -83,12 +83,10 @@
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 )
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#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 )
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#define portNVIC_INT_CTRL ( ( volatile unsigned long * ) 0xe000ed04 )
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#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 )
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#define portNVIC_SYSTICK_CLK 0x00000004
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#define portNVIC_SYSTICK_INT 0x00000002
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#define portNVIC_SYSTICK_ENABLE 0x00000001
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#define portNVIC_PENDSVSET 0x10000000
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#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
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#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
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@ -204,10 +202,15 @@ void vPortEndScheduler( void )
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}
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/*-----------------------------------------------------------*/
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void vPortYieldFromISR( void )
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void vPortYield( void )
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{
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/* Set a PendSV to request a context switch. */
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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/* Barriers are normally not required but do ensure the code is completely
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within the specified behaviour for the architecture. */
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__DSB();
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__ISB();
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}
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/*-----------------------------------------------------------*/
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@ -215,6 +218,8 @@ void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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ulCriticalNesting++;
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__DSB();
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__ISB();
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}
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/*-----------------------------------------------------------*/
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@ -56,19 +56,19 @@
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
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license and Real Time Engineers Ltd. contact details.
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|
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
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fully thread aware and reentrant UDP/IP stack.
|
||||
|
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
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Integrity Systems, who sell the code with commercial support,
|
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
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Integrity Systems, who sell the code with commercial support,
|
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indemnification and middleware, under the OpenRTOS brand.
|
||||
|
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
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engineered and independently SIL3 certified version for use in safety and
|
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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@ -81,7 +81,7 @@ extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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@ -106,40 +106,41 @@ extern "C" {
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typedef unsigned portLONG portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffffffff
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#endif
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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extern void vPortYieldFromISR( void );
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extern void vPortYield( void );
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#define portNVIC_INT_CTRL ( ( volatile unsigned long * ) 0xe000ed04 )
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#define portNVIC_PENDSVSET 0x10000000
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#define portYIELD() vPortYield()
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#define portYIELD() vPortYieldFromISR()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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/*
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/*
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* Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
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* registers. r0 is clobbered.
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*/
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*/
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#define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
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/*
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* Set basepri back to 0 without effective other registers.
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
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*/
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#define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
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@ -153,7 +154,7 @@ extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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/* There are an uneven number of items on the initial stack, so
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/* There are an uneven number of items on the initial stack, so
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portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */
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#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )
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