Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject

@@ -20,7 +20,7 @@
 							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53" id="xilinx.arm.a53.target.gnu.base.debug.565045804" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.a53.target.gnu.base.debug"/>
 							<builder buildPath="${workspace_loc:/RTOSDemo_A53}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.a53.toolchain.builder.debug.1503003921" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.a53.toolchain.builder.debug"/>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.assembler.debug.1142300561" name="ARM A53 gcc assembler" superClass="xilinx.gnu.arm.a53.c.toolchain.assembler.debug">
-								<option id="xilinx.gnu.both.assembler.option.flags.139020974" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
+								<option id="xilinx.gnu.both.assembler.option.flags.139020974" name="Assembler Flags" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
 								<inputType id="xilinx.gnu.assembler.input.478741574" superClass="xilinx.gnu.assembler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.compiler.debug.587400676" name="ARM A53 gcc compiler" superClass="xilinx.gnu.arm.a53.c.toolchain.compiler.debug">
@@ -29,14 +29,15 @@
 								<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1218722002" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="../../RTOSDemo_A53_bsp/psu_cortexa53_0/include"/>
 								</option>
-								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CA53_64_BIT}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
 								</option>
-								<option id="xilinx.gnu.compiler.misc.other.1651312713" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.misc.other.1651312713" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.symbols.defined.890730491" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols"/>
 								<inputType id="xilinx.gnu.arm.a53.c.compiler.input.1725216366" name="C source files" superClass="xilinx.gnu.arm.a53.c.compiler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug.986847379" name="ARM A53 g++ compiler" superClass="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug">
@@ -55,6 +56,7 @@
 									<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
 								</option>
 								<option id="xilinx.gnu.c.linker.option.lscript.210457854" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+								<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other" valueType="stringList"/>
 								<inputType id="xilinx.gnu.linker.input.294386883" superClass="xilinx.gnu.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -164,4 +166,5 @@
 			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53GCCManagedMakePerProjectProfileC"/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c

@@ -288,64 +288,6 @@ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
 }
 /*-----------------------------------------------------------*/
 
-void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;
-size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	if( pvDest != pvSource )
-	{
-		for( x = 0; x < xBytes; x++ )
-		{
-			pcDest[ x ] = pcSource[ x ];
-		}
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-void *memset( void *pvDest, int iValue, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	for( x = 0; x < xBytes; x++ )
-	{
-		pcDest[ x ] = ( unsigned char ) iValue;
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes )
-{
-const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-    for( x = 0; x < xBytes; x++ )
-    {
-        if( pucMem1[ x ] != pucMem2[ x ] )
-        {
-            break;
-        }
-    }
-
-    return xBytes - x;
-}
-/*-----------------------------------------------------------*/
-
 void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
 {
 	xil_printf( "ASSERT!  Line %lu of file %s\r\n", ulLineNumber, pcFileName );

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h

@@ -260,12 +260,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -275,12 +275,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -452,8 +452,6 @@
 
 
 /* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
 
 
 /* Definitions for peripheral PSU_IOU_SCNTR */
@@ -512,8 +510,6 @@
 
 
 /* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
 
 
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
@@ -651,7 +647,7 @@
 
 /******************************************************************/
 
-#define  XPAR_XIPIPSU_NUM_INSTANCES  1
+#define  XPAR_XIPIPSU_NUM_INSTANCES  3
 
 /* Parameter definitions for peripheral psu_ipi_0 */
 #define  XPAR_PSU_IPI_0_DEVICE_ID  0
@@ -660,6 +656,20 @@
 #define  XPAR_PSU_IPI_0_BUFFER_INDEX  2
 #define  XPAR_PSU_IPI_0_INT_ID  67
 
+/* Parameter definitions for peripheral psu_ipi_1 */
+#define  XPAR_PSU_IPI_1_DEVICE_ID  1
+#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000
+#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100
+#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0
+#define  XPAR_PSU_IPI_1_INT_ID  65
+
+/* Parameter definitions for peripheral psu_ipi_2 */
+#define  XPAR_PSU_IPI_2_DEVICE_ID  2
+#define  XPAR_PSU_IPI_2_BASE_ADDRESS  0xFF320000
+#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200
+#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1
+#define  XPAR_PSU_IPI_2_INT_ID  66
+
 /* Canonical definitions for peripheral psu_ipi_0 */
 #define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSU_IPI_0_DEVICE_ID
 #define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSU_IPI_0_BASE_ADDRESS
@@ -667,6 +677,20 @@
 #define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSU_IPI_0_BUFFER_INDEX
 #define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSU_IPI_0_INT_ID
 
+/* Canonical definitions for peripheral psu_ipi_1 */
+#define  XPAR_XIPIPSU_1_DEVICE_ID	XPAR_PSU_IPI_1_DEVICE_ID
+#define  XPAR_XIPIPSU_1_BASE_ADDRESS	XPAR_PSU_IPI_1_BASE_ADDRESS
+#define  XPAR_XIPIPSU_1_BIT_MASK	XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPSU_1_BUFFER_INDEX	XPAR_PSU_IPI_1_BUFFER_INDEX
+#define  XPAR_XIPIPSU_1_INT_ID	XPAR_PSU_IPI_1_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_2 */
+#define  XPAR_XIPIPSU_2_DEVICE_ID	XPAR_PSU_IPI_2_DEVICE_ID
+#define  XPAR_XIPIPSU_2_BASE_ADDRESS	XPAR_PSU_IPI_2_BASE_ADDRESS
+#define  XPAR_XIPIPSU_2_BIT_MASK	XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPSU_2_BUFFER_INDEX	XPAR_PSU_IPI_2_BUFFER_INDEX
+#define  XPAR_XIPIPSU_2_INT_ID	XPAR_PSU_IPI_2_INT_ID
+
 #define  XPAR_XIPIPSU_NUM_TARGETS  11
 
 #define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001
@@ -695,15 +719,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -715,14 +755,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -1010,14 +1054,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1026,13 +1070,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
@@ -101,5 +101,117 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
 				XPAR_PSU_IPI_10_BUFFER_INDEX
 			}
 		}
+	},
+
+	{
+		XPAR_PSU_IPI_1_DEVICE_ID,
+		XPAR_PSU_IPI_1_BASE_ADDRESS,
+		XPAR_PSU_IPI_1_BIT_MASK,
+		XPAR_PSU_IPI_1_BUFFER_INDEX,
+		XPAR_PSU_IPI_1_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	},
+
+	{
+		XPAR_PSU_IPI_2_DEVICE_ID,
+		XPAR_PSU_IPI_2_BASE_ADDRESS,
+		XPAR_PSU_IPI_2_BIT_MASK,
+		XPAR_PSU_IPI_2_BUFFER_INDEX,
+		XPAR_PSU_IPI_2_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
 	}
 };

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c

@@ -496,6 +496,23 @@ void vFullDemoTickHook( void )
 
 	/* Call the code that 'gives' a task notification from an ISR. */
 	xNotifyTaskFromISR();
+
+	/* Test flop alignment in interrupts - calling printf from an interrupt
+	is BAD! */
+	#if( configASSERT_DEFINED == 1 )
+	{
+	char cBuf[ 20 ];
+	UBaseType_t uxSavedInterruptStatus;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			sprintf( cBuf, "%1.3f", 1.234 );
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		configASSERT( strcmp( cBuf, "1.234" ) == 0 );
+	}
+	#endif /* configASSERT_DEFINED */
 }
 
 

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject

@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="org.eclipse.cdt.core.default.config.750804140">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.887738538">
-			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.750804140" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.887738538" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
 				<externalSettings/>
 				<extensions/>
 			</storageModule>

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
 	<name>RTOSDemo_R5_bsp</name>
-	<comment>Created by SDK v2016.1</comment>
+	<comment>Created by SDK v2016.4</comment>
 	<projects>
 	</projects>
 	<buildSpec>

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile

@@ -21,11 +21,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
 
 %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
 	@echo "Running Make include in $(subst /make.include,,$@)"
-	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 %/make.libs: include
 	@echo "Running Make libs in $(subst /make.libs,,$@)"
-	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 clean:
 	rm -f ${PROCESSOR}/lib/libxil.a

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h

@@ -13,6 +13,9 @@
 
 /******************************************************************/
 
+ /* Definition for PSS REF CLK FREQUENCY */
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U
+
 #include "xparameters_ps.h"
 
 /******************************************************************/
@@ -27,6 +30,10 @@
 
 /******************************************************************/
 
+
+/* Number of Fabric Resets */
+#define XPAR_NUM_FABRIC_RESETS 1
+
 #define STDIN_BASEADDRESS 0xFF000000
 #define STDOUT_BASEADDRESS 0xFF000000
 
@@ -260,6 +267,28 @@
 #define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0
 
 
+/******************************************************************/
+
+/* Definitions for driver DDRCPSU */
+#define XPAR_XDDRCPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DDRC_0 */
+#define XPAR_PSU_DDRC_0_DEVICE_ID 0
+#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
+#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
+#define XPAR_PSU_DDRC_0_HAS_ECC 0
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_DDRC_0 */
+#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
+#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
+#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002
+
+
 /******************************************************************/
 
 /* Definitions for driver EMACPS */
@@ -270,12 +299,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -285,12 +314,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -336,11 +365,6 @@
 #define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
 
 
-/* Definitions for peripheral PSU_BBRAM_0 */
-#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000
-#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF
-
-
 /* Definitions for peripheral PSU_CCI_GPV */
 #define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
 #define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
@@ -406,11 +430,6 @@
 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
 
 
-/* Definitions for peripheral PSU_DDRC_0 */
-#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000
-#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF
-
-
 /* Definitions for peripheral PSU_DP */
 #define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000
 #define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF
@@ -456,11 +475,6 @@
 #define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
 
 
-/* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
-
-
 /* Definitions for peripheral PSU_IOU_SCNTR */
 #define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
 #define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
@@ -516,11 +530,6 @@
 #define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF
 
 
-/* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
@@ -541,6 +550,11 @@
 #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF
 
 
+/* Definitions for peripheral PSU_PCIE_LOW */
+#define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000
+#define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF
+
+
 /* Definitions for peripheral PSU_PMU_GLOBAL_0 */
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
@@ -551,44 +565,19 @@
 #define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
 
 
-/* Definitions for peripheral PSU_PMU_RAM */
-#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000
-#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF
-
-
 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
 
 
 /* Definitions for peripheral PSU_R5_0_ATCM */
-#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000
+#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000
-#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF
+#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF
 
 
 /* Definitions for peripheral PSU_R5_0_BTCM */
-#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000
+#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000
-#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF
+#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_ATCM */
-#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000
-#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_BTCM */
-#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000
-#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF
 
 
 /* Definitions for peripheral PSU_R5_DDR_0 */
@@ -598,7 +587,7 @@
 
 /* Definitions for peripheral PSU_R5_TCM_RAM_0 */
 #define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000
+#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
 
 
 /* Definitions for peripheral PSU_RPU */
@@ -636,11 +625,6 @@
 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
 
 
-/* Definitions for peripheral PSU_USB_0 */
-#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000
-#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF
-
-
 /******************************************************************/
 
 /* Definitions for driver GPIOPS */
@@ -754,15 +738,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -774,14 +774,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -858,6 +862,9 @@
 #define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_PSU_SD_1_HAS_CD 1
 #define XPAR_PSU_SD_1_HAS_WP 1
+#define XPAR_PSU_SD_1_BUS_WIDTH 4
+#define XPAR_PSU_SD_1_MIO_BANK 1
+#define XPAR_PSU_SD_1_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -869,6 +876,9 @@
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_XSDPS_0_HAS_CD 1
 #define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 4
+#define XPAR_XSDPS_0_MIO_BANK 1
+#define XPAR_XSDPS_0_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -1060,6 +1070,25 @@
 #define XPAR_XUARTPS_1_HAS_MODEM 0
 
 
+/******************************************************************/
+
+/* Definitions for driver USBPSU */
+#define XPAR_XUSBPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_USB_0 */
+#define XPAR_PSU_USB_0_DEVICE_ID 0
+#define XPAR_PSU_USB_0_BASEADDR 0xFE200000
+#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_USB_0 */
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID
+#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
+#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF
+
+
 /******************************************************************/
 
 /* Definitions for driver WDTPS */
@@ -1069,14 +1098,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1085,13 +1114,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c

@@ -166,7 +166,7 @@ s32 XCanPs_SelfTest(XCanPs *InstancePtr)
 	for (Index = 0U; Index < 8U; Index++) {
 		if(*FramePtr != 0U) {
 			*FramePtr = (u8)Index;
-			*FramePtr++;
+			FramePtr++;
 		}
 	}
 

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015-2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -51,12 +51,18 @@
 * 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
 *       kvn    08/18/15 Modified Makefile according to compiler changes.
 * 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
 *
 * </pre>
 *
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
 
 #include <xil_types.h>
 #include <xpseudo_asm.h>
@@ -177,5 +183,6 @@ static INLINE u32 XCoresightPs_DccGetStatus(void)
 	}
 #endif
 	return Status;
+#endif
 }
 /** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h

@@ -55,16 +55,20 @@
 * 1.00  kvn    02/14/15 First release
 * 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
 *       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
 *
 * </pre>
 *
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
-
+#ifndef __MICROBLAZE__
 #include <xil_types.h>
 
 void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
 
 u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
 /** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c

@@ -46,6 +46,8 @@
 * Ver   Who     Date     Changes
 * ----- ------  -------- ---------------------------------------------------
 * 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
 * </pre>
 *
 ******************************************************************************/
@@ -152,8 +154,12 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 	}
 	/* Invalidating cache memory */
 	else {
+#if defined(__aarch64__)
 		Xil_DCacheInvalidateRange(Addr, Size <<
 					(u32)(XCSUDMA_SIZE_SHIFT));
+#else
+		Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
+#endif
 	}
 
 	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h

@@ -97,6 +97,8 @@
 * Ver   Who     Date     Changes
 * ----- ------  -------- -----------------------------------------------------
 * 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
 * </pre>
 *
 ******************************************************************************/

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile

@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrcpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ddrcpsu"
+
+xddrcpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrcpsu_includes
+
+xddrcpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h

@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddcrpsu.h
+ * @addtogroup ddrcpsu_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	ssc   04/28/16 First Release.
+ * 1.1  adk   04/08/16 Export DDR freq to xparameters.h file.
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRCPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRCPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRCPS_H_ */
+/** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -54,6 +54,7 @@
 * 						 in XIicPs_Reset.
 *				12/06/14 Implemented Repeated start feature.
 *				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn		05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -228,7 +229,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
 	 * Reset the settings in config register and clear the FIFOs.
 	 */
 	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
+			  (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
 
 	/*
 	 * Read, then write the interrupt status to make sure there are no
@@ -242,7 +243,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
 	/*
 	 * Restore the interrupt state.
 	 */
-	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
 	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
 			  XIICPS_IER_OFFSET, IntrMaskReg);
 

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -183,6 +183,7 @@
 *			01/31/15 Modified the code according to MISRAC 2012 Compliant.
 *			02/18/15 Implemented larger data transfer using repeated start
 *					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -62,6 +62,7 @@
 *			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
 *			 02/18/15 Implemented larger data transfer using repeated start
 *					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -106,6 +107,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 		 u16 SlaveAddr)
 {
 	u32 BaseAddr;
+	u32 Platform = XGetPlatform_Info();
 
 	/*
 	 * Assert validates the input arguments.
@@ -147,6 +149,16 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	 */
 	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
 
+	/* Clear the Hold bit in ZYNQ if receive byte count is less than
+	 * the FIFO depth to get the completion interrupt properly.
+	 */
+	if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+				(u32)(~XIICPS_CR_HOLD_MASK));
+	}
+
 }
 
 /*****************************************************************************/
@@ -182,10 +194,8 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	BaseAddr = InstancePtr->Config.BaseAddress;
 	InstancePtr->RecvBufferPtr = MsgPtr;
 	InstancePtr->RecvByteCount = ByteCount;
-	InstancePtr->CurrByteCount = ByteCount;
 	InstancePtr->SendBufferPtr = NULL;
 	InstancePtr->IsSend = 0;
-	InstancePtr->UpdateTxSize = 0;
 
 	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
 		((InstancePtr->IsRepeatedStart) !=0))
@@ -203,14 +213,16 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	 * Setup the transfer size register so the slave knows how much
 	 * to send to us.
 	 */
-	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+	if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
 		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
 				XIICPS_MAX_TRANSFER_SIZE);
 		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
 		InstancePtr->UpdateTxSize = 1;
 	}else {
+		InstancePtr->CurrByteCount = ByteCount;
 		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
 			 (u32)ByteCount);
+		InstancePtr->UpdateTxSize = 0;
 	}
 
 	XIicPs_EnableInterrupts(BaseAddr,
@@ -251,8 +263,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	u32 StatusReg;
 	u32 BaseAddr;
 	u32 Intrs;
-	u32 Value;
+	_Bool Value;
-	s32 Status;
 
 	/*
 	 * Assert validates the input arguments.
@@ -260,7 +271,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(MsgPtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+	Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
 
 	BaseAddr = InstancePtr->Config.BaseAddress;
 	InstancePtr->SendBufferPtr = MsgPtr;
@@ -302,7 +313,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	 */
 	Value = ((InstancePtr->SendByteCount > (s32)0) &&
 		((IntrStatusReg & Intrs) == (u32)0U));
-	while (Value != (u32)0x00U) {
+	while (Value != FALSE) {
 		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
 
 		/*
@@ -374,14 +385,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	u32 Intrs;
 	u32 StatusReg;
 	u32 BaseAddr;
-	s32 BytesToRecv;
-	s32 BytesToRead;
-	s32 TransSize;
-	s32 Tmp = 0;
-	u32 Status_Rcv;
-	u32 Status;
 	s32 Result;
-	s32 IsHold = 0;
+	s32 IsHold;
 	s32 UpdateTxSize = 0;
 	s32 ByteCountVar = ByteCount;
 	u32 Platform;
@@ -407,6 +412,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
 						(u32)XIICPS_CR_HOLD_MASK);
 		IsHold = 1;
+	} else {
+		IsHold = 0;
 	}
 
 	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
@@ -423,7 +430,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	 * Set up the transfer size register so the slave knows how much
 	 * to send to us.
 	 */
-	if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
+	if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
 		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
 				XIICPS_MAX_TRANSFER_SIZE);
 		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
@@ -460,18 +467,18 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 			XIicPs_RecvByte(InstancePtr);
 		    ByteCountVar --;
 
-			if (Platform == XPLAT_ZYNQ) {
+			if (Platform == (u32)XPLAT_ZYNQ) {
 			    if ((UpdateTxSize != 0) &&
-				    ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
 				    break;
 				}
 			}
 
 			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
 		}
-		if (Platform == XPLAT_ZYNQ) {
+		if (Platform == (u32)XPLAT_ZYNQ) {
 			if ((UpdateTxSize != 0) &&
-				((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
 			    /*  wait while fifo is full */
 			    while (XIicPs_ReadReg(BaseAddr,
 				    XIICPS_TRANS_SIZE_OFFSET) !=
@@ -479,7 +486,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				}
 
 				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -507,7 +514,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
 
 				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -755,17 +762,17 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 			XIicPs_RecvByte(InstancePtr);
 			ByteCnt--;
 
-			if (Platform == XPLAT_ZYNQ) {
+			if (Platform == (u32)XPLAT_ZYNQ) {
 			    if ((InstancePtr->UpdateTxSize != 0) &&
-				    ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
 				    break;
 				}
 			}
 		}
 
-		if (Platform == XPLAT_ZYNQ) {
+		if (Platform == (u32)XPLAT_ZYNQ) {
 			if ((InstancePtr->UpdateTxSize != 0) &&
-				((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
+				(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
 				/* wait while fifo is full */
 				while (XIicPs_ReadReg(BaseAddr,
 					XIICPS_TRANS_SIZE_OFFSET) !=
@@ -773,7 +780,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 				}
 
 				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -798,11 +805,11 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
 				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
 
-				SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
 				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
 
 				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -910,7 +917,6 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
 {
 	u32 ControlReg;
 	u32 BaseAddr;
-	u32 EnabledIntr = 0x0U;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 
@@ -935,11 +941,9 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
 
 	if (Role == RECVING_ROLE) {
 		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
-		EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
 	}else {
 		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
 	}
-	EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
 
 	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
 

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -55,6 +55,7 @@
 * 2.3	sk	10/07/14 Repeated start feature removed.
 * 3.0	sk	12/06/14 Implemented Repeated start feature.
 *			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -135,7 +136,7 @@ s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
 	 * The hold bit in CR will be written by driver when the next transfer
 	 * is initiated.
 	 */
-	if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
+	if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
 		InstancePtr->IsRepeatedStart = 1;
 		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
 	}
@@ -349,8 +350,8 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
 	u32 ControlReg;
 	u32 CalcDivA;
 	u32 CalcDivB;
-	u32 BestDivA = 0;
+	u32 BestDivA;
-	u32 BestDivB = 0;
+	u32 BestDivB;
 	u32 FsclHzVar = FsclHz;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -379,12 +380,12 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
 	 * If frequency 100KHz is selected, 90KHz should be set.
 	 * This is due to a hardware limitation.
 	 */
-	if(FsclHzVar > 384600U) {
+	if(FsclHzVar > (u32)384600U) {
-		FsclHzVar = 384600U;
+		FsclHzVar = (u32)384600U;
 	}
 
-	if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
+	if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
-		FsclHzVar = 90000U;
+		FsclHzVar = (u32)90000U;
 	}
 
 	/*

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,7 @@
 * 1.00a jz  01/30/10 First release
 * 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
 * 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -210,7 +211,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 	s32 BytesToSend;
 	s32 Error = 0;
 	s32 Status = (s32)XST_SUCCESS;
-	u32 Value;
+	_Bool Value;
+	_Bool Result;
 
 	/*
 	 * Assert validates the input arguments.
@@ -227,8 +229,9 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 	 * Use RXRW bit in status register to wait master to start a read.
 	 */
 	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
+	Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
-				((!Error) != 0)) {
+			(Error == 0));
+	while (Result != FALSE) {
 
 		/*
 		 * If master tries to send us data, it is an error.
@@ -238,6 +241,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 		}
 
 		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+				(Error == 0));
 	}
 
 	if (Error != 0) {
@@ -255,8 +260,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 		 * there are no errors.
 		 */
 		Value = (InstancePtr->SendByteCount > (s32)0) &&
-						((!Error) != 0);
+						((Error == 0));
-		while (Value != (u32)0x00U) {
+		while (Value != FALSE) {
 
 			/*
 			 * Find out how many can be sent.
@@ -276,7 +281,7 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 			 * Wait for master to read the data out of fifo.
 			 */
 			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
-							((!Error) != 0)) {
+							(Error == 0)) {
 
 				/*
 				 * If master terminates the transfer before all data is
@@ -296,8 +301,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 				StatusReg = XIicPs_ReadReg(BaseAddr,
 						XIICPS_SR_OFFSET);
 			}
-			Value = (InstancePtr->SendByteCount > (s32)0U) &&
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
-							((!Error) != 0);
+							(Error == 0));
 		}
 	}
 	if (Error != 0) {
@@ -551,7 +556,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
 	/*
 	 * Signal application if there are any events.
 	 */
-	if (0U != StatusEvent) {
+	if ((u32)0U != StatusEvent) {
 		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
 					   StatusEvent);
 	}

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -47,6 +47,7 @@
 * 1.00	mjr	03/15/15	First Release
 * 2.0	mjr	01/22/16	Fixed response buffer address
 *                               calculation. CR# 932582.
+* 2.1	kvn	05/05/16	Modified code for MISRA-C:2012 Compliance
 * </pre>
 *
 *****************************************************************************/
@@ -85,7 +86,7 @@ XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
 
 	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
 
-	for (Index = 0; Index < CfgPtr->TargetCount; Index++) {
+	for (Index = 0U; Index < CfgPtr->TargetCount; Index++) {
 		InstancePtr->Config.TargetList[Index].Mask =
 				CfgPtr->TargetList[Index].Mask;
 		InstancePtr->Config.TargetList[Index].BufferIndex =
@@ -167,7 +168,7 @@ XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	PollCount = 0;
+	PollCount = 0U;
 	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
 	do {
 		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
@@ -202,10 +203,10 @@ static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
 	u32 BufferIndex;
 	u32 Index;
 	/* Init Index with an invalid value */
-	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1;
+	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1U;
 
 	/*Search for CPU in the List */
-	for (Index = 0; Index < InstancePtr->Config.TargetCount; Index++) {
+	for (Index = 0U; Index < InstancePtr->Config.TargetCount; Index++) {
 		/*If we find the CPU , then set the Index and break the loop*/
 		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
 			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
@@ -276,29 +277,29 @@ static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
  * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
  * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
  * @param 	MsgLength is the length of the buffer/message
- * @param 	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ * @param 	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
  *
  * @return	XST_SUCCESS if successful
  * 			XST_FAILURE if an error occurred
  */
 
-XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
 		u32 MsgLength, u8 BufferType)
 {
 	u32 *BufferPtr;
 	u32 Index;
-	u32 Status;
+	XStatus Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(MsgPtr != NULL);
 	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
 
-	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, TargetMask,
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, SrcCpuMask,
 			InstancePtr->Config.BitMask, BufferType);
 	if (BufferPtr != NULL) {
 		/* Copy the IPI Buffer contents into Users's Buffer*/
-		for (Index = 0; Index < MsgLength; Index++) {
+		for (Index = 0U; Index < MsgLength; Index++) {
 			MsgPtr[Index] = BufferPtr[Index];
 		}
 		Status = XST_SUCCESS;
@@ -317,18 +318,18 @@ XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
  * @param	DestCpuMask is the Device Mask for the destination CPU
  * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
  * @param	MsgLength is the length of the buffer/message
- * @param	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ * @param	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
  *
  * @return	XST_SUCCESS if successful
  * 			XST_FAILURE if an error occurred
  */
 
-XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
 		u32 MsgLength, u8 BufferType)
 {
 	u32 *BufferPtr;
 	u32 Index;
-	u32 Status;
+	XStatus Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -336,10 +337,10 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
 	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
 
 	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
-			InstancePtr->Config.BitMask, TargetMask, BufferType);
+			InstancePtr->Config.BitMask, DestCpuMask, BufferType);
 	if (BufferPtr != NULL) {
 		/* Copy the Message to IPI Buffer */
-		for (Index = 0; Index < MsgLength; Index++) {
+		for (Index = 0U; Index < MsgLength; Index++) {
 			BufferPtr[Index] = MsgPtr[Index];
 		}
 		Status = XST_SUCCESS;

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -272,10 +272,10 @@ XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
 		u32 TimeOutCount);
 
 XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
+		u32 MsgLength, u8 BufferType);
 
 XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
+		u32 MsgLength, u8 BufferType);
 
 #endif /* XIPIPSU_H_ */
 /** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -43,6 +43,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------.
 * 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
 *
 * </pre>
 *
@@ -54,7 +55,7 @@
 /* Message RAM related params */
 #define XIPIPSU_MSG_RAM_BASE 0xFF990000U
 #define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
-#define XIPIPSU_MAX_BUFF_INDEX	7
+#define XIPIPSU_MAX_BUFF_INDEX	7U
 
 /* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
 #define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------
 * 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
 * </pre>
 *
 ******************************************************************************/
@@ -76,9 +77,9 @@ extern XIpiPsu_Config XIpiPsu_ConfigTable[];
 XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
 {
 	XIpiPsu_Config *CfgPtr = NULL;
-	int Index;
+	u32 Index;
 
-	for (Index = 0; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
+	for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
 		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
 			CfgPtr = &XIpiPsu_ConfigTable[Index];
 			break;

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c

@@ -52,6 +52,14 @@
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
 *       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
 *                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Changed XQspiPsu_Select to support GQSPI and LQSPI
+*		     selection.
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+* 1.3	nsk 09/16/16 Update PollData and PollTimeout support for dual
+*	             parallel configurations, modified XQspiPsu_PollData()
+*	             and XQspiPsu_Create_PollConfigData()
 *
 * </pre>
 *
@@ -83,6 +91,10 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
 static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 			XQspiPsu_Msg *Msg, s32 Size);
+static inline void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
 
 /************************** Variable Definitions *****************************/
 
@@ -137,7 +149,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
 		InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
 		InstancePtr->StatusHandler = StubStatusHandler;
 		InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
-
+		InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
 		/* Other instance variable initializations */
 		InstancePtr->SendBufferPtr = NULL;
 		InstancePtr->RecvBufferPtr = NULL;
@@ -152,7 +164,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
 		InstancePtr->IsManualstart = TRUE;
 
 		/* Select QSPIPSU */
-		XQspiPsu_Select(InstancePtr);
+		XQspiPsu_Select(InstancePtr, XQSPIPSU_SEL_GQSPI_MASK);
 
 		/*
 		 * Reset the QSPIPSU device to get it into its initial state. It is
@@ -343,12 +355,10 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
 s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 				u32 NumMsg)
 {
-	u32 StatusReg;
+
-	u32 ConfigReg;
 	s32 Index;
-	u32 QspiPsuStatusReg, DmaStatusReg;
+	u32 QspiPsuStatusReg;
 	u32 BaseAddress;
-	s32 Status;
 	s32 RxThr;
 	u32 IOPending = (u32)FALSE;
 
@@ -391,6 +401,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
 
 		if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 				XQspiPsu_ReadReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET) |
@@ -484,6 +497,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
 
 	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
 				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
@@ -526,11 +542,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 				u32 NumMsg)
 {
-	u32 StatusReg;
+
-	u32 ConfigReg;
 	s32 Index;
 	u32 BaseAddress;
-	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -543,6 +557,10 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		return (s32)XST_DEVICE_BUSY;
 	}
 
+	if (Msg[0].Flags & XQSPIPSU_MSG_FLAG_POLL) {
+		InstancePtr->IsBusy = TRUE;
+		XQspiPsu_PollData(InstancePtr, Msg);
+	} else {
 		/* Check for ByteCount upper limit - 2^28 for DMA */
 		for (Index = 0; Index < (s32)NumMsg; Index++) {
 			if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
@@ -574,6 +592,9 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 	XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
 
 	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
 				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
@@ -589,7 +610,7 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
 				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
 	}
-
+	}
 	return XST_SUCCESS;
 }
 
@@ -636,8 +657,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 		XQspiPsu_WriteReg(BaseAddress,
 			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
 	}
-	if (((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE) ||
+	if (((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
-		((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
 		/* Call status handler to indicate error */
 		InstancePtr->StatusHandler(InstancePtr->StatusRef,
 					XST_SPI_COMMAND_ERROR, 0);
@@ -681,6 +701,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
 						MsgCnt);
 				if(InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 					XQspiPsu_WriteReg(BaseAddress,
 						XQSPIPSU_CFG_OFFSET,
 						XQspiPsu_ReadReg(BaseAddress,
@@ -727,6 +750,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 	if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
 		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
 		((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) == FALSE) &&
 		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
 		MsgCnt += 1;
 		DeltaMsgCnt = 1U;
@@ -754,6 +778,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
 
 			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET,
 					XQspiPsu_ReadReg(BaseAddress,
@@ -769,6 +796,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
 
 			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET,
 					XQspiPsu_ReadReg(BaseAddress,
@@ -800,7 +830,34 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 						XST_SPI_TRANSFER_DONE, 0);
 		}
 	}
+	if ((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) != FALSE){
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK){
+			 /*
+			  * Read data from RXFIFO, since when data from the flash device
+			  * (status data) matched with configured value in poll_cfg, then
+			  * controller writes the matched data into RXFIFO.
+			  */
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
 
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+			InstancePtr->StatusHandler(InstancePtr->StatusRef, XST_SPI_POLL_DONE, 0);
+
+			InstancePtr->IsBusy = FALSE;
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+		 }
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK){
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_FLASH_TIMEOUT_ERROR, 0);
+		 }
+	}
 	return XST_SUCCESS;
 }
 
@@ -892,6 +949,11 @@ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
 static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
 {
 	u32 Mask;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectSpiMode\r\n");
+#endif
+
 	switch (SpiMode) {
 		case XQSPIPSU_SELECT_MODE_DUALSPI:
 			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
@@ -906,6 +968,9 @@ static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
 			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
 			break;
 	}
+#ifdef DEBUG
+	xil_printf("\nSPIMode is %08x\r\n", SpiMode);
+#endif
 
 	return Mask;
 }
@@ -1014,6 +1079,10 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
 
 	Xil_AssertVoid(InstancePtr != NULL);
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_FillTxFifo\r\n");
+#endif
+
 	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
 		if (InstancePtr->TxBytes >= 4) {
 			(void)memcpy(&Data, Msg->TxBfrPtr, 4);
@@ -1028,6 +1097,9 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
 		}
 		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				XQSPIPSU_TXD_OFFSET, Data);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
 
 	}
 	if (InstancePtr->TxBytes < 0) {
@@ -1104,6 +1176,10 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
 {
 	u32 GenFifoEntry;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n");
+#endif
+
 	GenFifoEntry = 0x0U;
 	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
 	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
@@ -1114,7 +1190,9 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
 	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
 			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
 	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
-
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 }
@@ -1144,6 +1222,10 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	u32 TempCount;
 	u32 ImmData;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryData\r\n");
+#endif
+
 	BaseAddress = InstancePtr->Config.BaseAddress;
 
 	GenFifoEntry = 0x0U;
@@ -1177,6 +1259,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
 		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 		GenFifoEntry |= Msg[Index].ByteCount;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
 				GenFifoEntry);
 	} else {
@@ -1190,6 +1275,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 			if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
 				GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 				GenFifoEntry |= Exponent;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_GEN_FIFO_OFFSET,
 					GenFifoEntry);
@@ -1203,6 +1291,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 		if ((ImmData & 0xFFU) != FALSE) {
 			GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 			GenFifoEntry |= ImmData & 0xFFU;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 			XQspiPsu_WriteReg(BaseAddress,
 				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 		}
@@ -1212,6 +1303,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
 			((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
 		GenFifoEntry = 0x0U;
+#ifdef DEBUG
+	xil_printf("\nDummy FifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 		XQspiPsu_WriteReg(BaseAddress,
 				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 	}
@@ -1233,6 +1327,10 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
 {
 	u32 GenFifoEntry;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n");
+#endif
+
 	GenFifoEntry = 0x0U;
 	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
 	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
@@ -1242,7 +1340,9 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
 	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
 			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
 	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
-
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 }
@@ -1267,12 +1367,19 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 	s32 Count = 0;
 	u32 Data;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_ReadRxFifo\r\n");
+#endif
+
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(Msg != NULL);
 
 	while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
 		Data = XQspiPsu_ReadReg(InstancePtr->
 				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
 		if (InstancePtr->RxBytes >= 4) {
 			(void)memcpy(Msg->RxBfrPtr, &Data, 4);
 			InstancePtr->RxBytes -= 4;
@@ -1287,4 +1394,121 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 		}
 	}
 }
+
+/*****************************************************************************/
+/**
+*
+* This function enables the polling functionality of controller
+*
+* @param	QspiPsuPtr is a pointer to the XQspiPsu instance.
+*
+* @param	Statuscommand is the status command which send by controller.
+*
+* @param	FlashMsg is a pointer to the structure containing transfer data
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr, XQspiPsu_Msg *FlashMsg)
+{
+
+	u32 GenFifoEntry ;
+	u32 Value;
+
+	Xil_AssertVoid(QspiPsuPtr != NULL);
+	Xil_AssertVoid(FlashMsg != NULL );
+
+	Value = XQspiPsu_Create_PollConfigData(QspiPsuPtr, FlashMsg);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_POLL_CFG_OFFSET, Value);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_P_TO_OFFSET, FlashMsg->PollTimeout);
+
+	XQspiPsu_Enable(QspiPsuPtr);
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_TX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= (u32)FlashMsg->PollStatusCmd;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				(XQSPIPSU_CFG_START_GEN_FIFO_MASK
+				| XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK));
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry = (u32)XQSPIPSU_GENFIFO_POLL;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_RX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	if (((FlashMsg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE)
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	else
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+
+	QspiPsuPtr->Msg = FlashMsg;
+	QspiPsuPtr->NumMsg = (s32)1;
+	QspiPsuPtr->MsgCnt = 0;
+
+	Value = XQspiPsu_ReadReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+	Value |= (XQSPIPSU_CFG_START_GEN_FIFO_MASK |
+			XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK |
+			XQSPIPSU_CFG_EN_POLL_TO_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			Value);
+
+	/* Enable interrupts */
+	Value = ((u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+		(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+		(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
+			Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function creates Poll config register data to write
+*
+* @param	BusMask is mask to enable/disable upper/lower data bus masks.
+*
+* @param	DataBusMask is Data bus mask value during poll operation.
+*
+* @param	Data is the poll data value to write into config regsiter.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg)
+{
+	u32 ConfigData = 0;
+
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_UPPER)
+		ConfigData = XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT;
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_LOWER)
+		ConfigData |= XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT;
+	ConfigData |= ((FlashMsg->PollBusMask << XQSPIPSU_POLL_CFG_MASK_EN_SHIFT)
+			& XQSPIPSU_POLL_CFG_MASK_EN_MASK);
+	ConfigData |= ((FlashMsg->PollData << XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT)
+		          & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
+	return ConfigData;
+}
 /** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h

@@ -95,6 +95,23 @@
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
 *       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
 *                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Added LQSPI support
+*		     Modified XQspiPsu_Select() macro in xqspipsu.h
+*		     Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
+*		     Added required macros in xqspipsu_hw.h
+*		     Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable in
+*		     xqspipsu_options.c
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+*		     Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
+*		     Added XQspiPsu_Create_PollConfigData and
+*		     XQspiPsu_PollData() functions in xqspipsu.c
+* 1.3	nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
+*	             configuration. Updated XQspiPsu_PollData() and
+*	             XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
+*                    and also modified the polldata example
 *
 * </pre>
 *
@@ -143,6 +160,10 @@ typedef struct {
 	u32 ByteCount;
 	u32 BusWidth;
 	u32 Flags;
+	u8 PollData;
+	u32 PollTimeout;
+	u8 PollStatusCmd;
+	u8 PollBusMask;
 } XQspiPsu_Msg;
 
 /**
@@ -207,6 +228,7 @@ typedef struct {
 #define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U
 #define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U
 #define XQSPIPSU_MANUAL_START_OPTION	0x8U
+#define XQSPIPSU_LQSPI_MODE_OPTION	0x20U
 
 #define XQSPIPSU_GENFIFO_EXP_START	0x100U
 
@@ -226,17 +248,25 @@ typedef struct {
 #define XQSPIPSU_CONNECTION_MODE_STACKED	1U
 #define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U
 
+/*QSPI Frequencies*/
+#define XQSPIPSU_FREQ_40MHZ 40000000
+#define XQSPIPSU_FREQ_100MHZ 100000000
+#define XQSPIPSU_FREQ_150MHZ 150000000
+
 /* Add more flags as required */
 #define XQSPIPSU_MSG_FLAG_STRIPE	0x1U
 #define XQSPIPSU_MSG_FLAG_RX		0x2U
 #define XQSPIPSU_MSG_FLAG_TX		0x4U
+#define XQSPIPSU_MSG_FLAG_POLL		0x8U
 
-#define XQspiPsu_Select(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
+#define XQspiPsu_Select(InstancePtr, Mask)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask)
 
 #define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
 
 #define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
 
+#define XQspiPsu_GetLqspiConfigReg(InstancePtr)   XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET)
+
 /************************** Function Prototypes ******************************/
 
 /* Initialization and reset */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h

@@ -47,6 +47,8 @@
 * 1.0   hk  08/21/14 First release
 *       hk  03/18/15 Add DMA status register masks required.
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.2	nsk 07/01/16 Added LQSPI supported Masks
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
 *
 * </pre>
 *
@@ -91,6 +93,7 @@ extern "C" {
  * Register: XQSPIPSU_CFG
  */
 #define XQSPIPSU_CFG_OFFSET    0X00000000U
+#define XQSPIPSU_LQSPI_CR_OFFSET    0X000000A0U
 
 #define XQSPIPSU_CFG_MODE_EN_SHIFT   30
 #define XQSPIPSU_CFG_MODE_EN_WIDTH   2
@@ -129,6 +132,22 @@ extern "C" {
 #define XQSPIPSU_CFG_CLK_POL_WIDTH   1
 #define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
 
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_LQSPI_CR_OFFSET	0X000000A0U
+#define XQSPIPSU_LQSPI_CR_LINEAR_MASK     0x80000000 /**< LQSPI mode enable */
+#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK    0x40000000 /**< Both memories or one */
+#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK    0x20000000 /**< Seperate memory bus */
+#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK     0x10000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK     0x01000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK    0x02000000 /**< Enable mode bits */
+#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK    0x01000000 /**< Mode on */
+#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+                                                         or quad I/O */
+#define XQSPIPS_LQSPI_CR_INST_MASK       0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE       0x80000003 /**< Default LQSPI CR value */
+#define XQSPIPS_LQSPI_CFG_RST_STATE       0x800238C1 /**< Default LQSPI CFG value */
 /**
  * Register: XQSPIPSU_ISR
  */
@@ -406,7 +425,8 @@ extern "C" {
 
 #define XQSPIPSU_SEL_SHIFT   0
 #define XQSPIPSU_SEL_WIDTH   1
-#define XQSPIPSU_SEL_MASK    0X00000001U
+#define XQSPIPSU_SEL_LQSPI_MASK    0X0U
+#define XQSPIPSU_SEL_GQSPI_MASK    0X00000001U
 
 /**
  * Register: XQSPIPSU_FIFO_CTRL
@@ -792,6 +812,23 @@ extern "C" {
 #define XQSPIPSU_GENFIFO_STRIPE		0x40000U
 #define XQSPIPSU_GENFIFO_POLL		0x80000U
 
+/*QSPI Data delay register*/
+#define XQSPIPSU_DATA_DLY_ADJ_OFFSET    0X000000F8U
+
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT   31
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH   1
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK    0X80000000U
+
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT   28
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH   3
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK    0X70000000U
+
+/* Tapdelay Bypass register*/
+#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
+
 /***************** Macros (Inline Functions) Definitions *********************/
 
 #define XQspiPsu_In32 Xil_In32

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c

@@ -47,6 +47,10 @@
 * 1.0   hk  08/21/14 First release
 *       sk  03/13/15 Added IO mode support.
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
 *
 * </pre>
 *
@@ -62,8 +66,23 @@
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
+#if defined (ARMR5) || (__aarch64__)
+#define TAPDLY_BYPASS_VALVE_40MHZ 0x01
+#define TAPDLY_BYPASS_VALVE_100MHZ 0x01
+#define USE_DLY_LPBK  0x01
+#define USE_DATA_DLY_ADJ 0x01
+#define DATA_DLY_ADJ_DLY 0X02
+#define LPBK_DLY_ADJ_DLY0 0X02
+#endif
+
 /************************** Function Prototypes ******************************/
 
+#if defined (ARMR5) || (__aarch64__)
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay);
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler);
+#endif
+
 /************************** Variable Definitions *****************************/
 
 /*
@@ -80,6 +99,7 @@ static OptionsMap OptionsTable[] = {
 	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
 	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
 	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
+	{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},
 };
 
 #define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
@@ -127,7 +147,8 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 
 		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
 					      XQSPIPSU_CFG_OFFSET);
-
+		QspiPsuOptions = Options & XQSPIPSU_LQSPI_MODE_OPTION;
+		Options &= ~XQSPIPSU_LQSPI_MODE_OPTION;
 		/*
 		 * Loop through the options table, turning the option on
 		 * depending on whether the bit is set in the incoming options flag.
@@ -136,9 +157,12 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 			if ((Options & OptionsTable[Index].Option) != FALSE) {
 				/* Turn it on */
 				ConfigReg |= OptionsTable[Index].Mask;
-			}
+			} else {
+                /* Turn it off */
+                ConfigReg &= ~(OptionsTable[Index].Mask);
         }
 
+		}
 		/*
 		 * Now write the control register. Leave it to the upper layers
 		 * to restart the device.
@@ -149,6 +173,21 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
 			InstancePtr->IsManualstart = TRUE;
 		}
+		/*
+		 * Check for the LQSPI configuration options.
+		 */
+		ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET);
+
+			if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) {
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE);
+			/* Enable the QSPI controller */
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK);
+		}
+		 else {
+			ConfigReg &= ~(XQSPIPSU_LQSPI_CR_LINEAR_MASK);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET, ConfigReg);
+		}
 
 		Status = XST_SUCCESS;
 	}
@@ -183,7 +222,6 @@ s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
 {
 	u32 ConfigReg;
 	u32 Index;
-	u32 QspiPsuOptions;
 	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -270,6 +308,119 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
 	return OptionsFlag;
 }
 
+#if defined (ARMR5) || (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This function sets the Tapdelay values for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Tapdelay.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	TapdelayBypss contains the IOU_TAPDLY_BYPASS register value.
+* @param	LPBKDelay contains the GQSPI_LPBK_DLY_ADJ register value.
+* @param	Datadelay contains the QSPI_DATA_DLY_ADJ register value.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting TapDelay.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = XST_DEVICE_BUSY;
+	} else {
+		XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET,
+				TapdelayBypass);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_DATA_DLY_ADJ_OFFSET,Datadelay);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Tapdelay.
+*
+* @note		None.
+*
+******************************************************************************/
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 FreqDiv, Divider, Tapdelay, LBkModeReg, delayReg;
+	s32 Status;
+
+	Divider = (1 << (Prescaler+1));
+
+	FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
+	Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR,
+					IOU_TAPDLY_BYPASS_OFFSET);
+
+	Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK);
+
+	LBkModeReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET);
+
+	LBkModeReg = (LBkModeReg &
+			(~(XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK)));
+
+	delayReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_DATA_DLY_ADJ_OFFSET);
+
+	delayReg = (delayReg &
+			(~(XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK))) &
+			(delayReg & (~( XQSPIPSU_DATA_DLY_ADJ_DLY_MASK)));
+
+	if(FreqDiv < XQSPIPSU_FREQ_40MHZ){
+		Tapdelay = Tapdelay |
+				(TAPDLY_BYPASS_VALVE_40MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_100MHZ) {
+		Tapdelay = Tapdelay | (TAPDLY_BYPASS_VALVE_100MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
+		delayReg = delayReg |
+				(USE_DATA_DLY_ADJ  << XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT) |
+				(DATA_DLY_ADJ_DLY  << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK  <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT ) |
+				(LPBK_DLY_ADJ_DLY0  << XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT);
+	}
+	Status = XQspi_Set_TapDelay(InstancePtr, Tapdelay, LBkModeReg, delayReg);
+
+	return Status;
+}
+#endif
+
 /*****************************************************************************/
 /**
 *
@@ -282,6 +433,7 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_DEVICE_IS_STARTED if the device is already started.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
 *		It must be stopped to re-initialize.
 *
 * @note		None.
@@ -319,7 +471,11 @@ s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
 		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				  XQSPIPSU_CFG_OFFSET, ConfigReg);
 
+#if defined (ARMR5) || (__aarch64__)
+		Status = XQspipsu_Calculate_Tapdelay(InstancePtr,Prescaler);
+#else
 		Status = XST_SUCCESS;
+#endif
 	}
 
 	return Status;
@@ -351,6 +507,10 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
 {
 	Xil_AssertVoid(InstancePtr != NULL);
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectFlash\r\n");
+#endif
+
 	/*
 	 * Bus and CS lines selected here will be updated in the instance and
 	 * used for subsequent GENFIFO entries during transfer.
@@ -389,6 +549,11 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
 			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
 			break;
 	}
+#ifdef DEBUG
+	xil_printf("\nGenFifoCS is %08x and GenFifoBus is %08x\r\n",
+				InstancePtr->GenFifoCS, InstancePtr->GenFifoBus);
+#endif
+
 }
 
 /*****************************************************************************/
@@ -416,6 +581,10 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
 	u32 ConfigReg;
 	s32 Status;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SetReadMode\r\n");
+#endif
+
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -444,6 +613,9 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
 
 		Status = XST_SUCCESS;
 	}
+#ifdef DEBUG
+	xil_printf("\nRead Mode is %08x\r\n", InstancePtr->ReadMode);
+#endif
 	return Status;
 }
 /** @} */

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c

@@ -52,6 +52,7 @@
 *                       switching when vcc_psaux is not available.
 * 1.2          02/15/16 Corrected Calibration mask and Fractional
 *                       mask in CalculateCalibration API.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -59,6 +60,7 @@
 /***************************** Include Files *********************************/
 
 #include "xrtcpsu.h"
+#include "xrtcpsu_hw.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -139,6 +141,10 @@ s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
 	/* Indicate the component is now ready to use. */
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
+	/* Clear TimeUpdated and CurrTimeUpdated */
+	InstancePtr->TimeUpdated = 0;
+	InstancePtr->CurrTimeUpdated = 0;
+
 	Status = XST_SUCCESS;
 	return Status;
 }
@@ -166,6 +172,90 @@ static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event)
 	Xil_AssertVoidAlways();
 }
 
+/****************************************************************************/
+/**
+*
+* This function sets the RTC time by writing into rtc write register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Time that should be updated into RTC write register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time)
+{
+	/* Set the calibration value in calibration register, so that
+	 * next Second is triggered exactly at 1 sec period
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
+							InstancePtr->CalibrationValue);
+	/* clear the RTC secs interrupt from status register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+								XRTC_INT_STS_SECS_MASK);
+	InstancePtr->CurrTimeUpdated = 0;
+	/* Update the flag before setting the time */
+	InstancePtr->TimeUpdated = 1;
+	/* Since RTC takes 1 sec to update the time into current time register, write
+	 * load time + 1sec into the set time register.
+	 */
+	XRtcPsu_WriteSetTime(InstancePtr, Time + 1);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the current RTC time.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	RTC Current time.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+{
+	u32 Status, IntMask, CurrTime;
+
+	IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET);
+
+	if((IntMask & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* We come here if interrupts are disabled */
+		Status = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET);
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(Status & XRTC_INT_STS_SECS_MASK) == (u32)0) {
+			/* Give the previous written time */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if((InstancePtr->TimeUpdated == (u32)1) &&
+				((Status & XRTC_INT_STS_SECS_MASK) == (u32)1)) {
+				InstancePtr->TimeUpdated = (u32)0;
+			}
+
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	} else {
+		/* We come here if interrupts are enabled */
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(InstancePtr->CurrTimeUpdated == (u32)0)) {
+			/* Give the previous written time -1 sec */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if(InstancePtr->TimeUpdated == (u32)1)
+				InstancePtr->TimeUpdated = (u32)0;
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	}
+	return CurrTime;
+}
+
 /****************************************************************************/
 /**
 *

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h

@@ -100,6 +100,7 @@
 * 1.00  kvn    04/21/15 First release
 * 1.1   kvn    09/25/15 Modify control register to enable battery
 *                       switching when vcc_psaux is not available.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -179,6 +180,8 @@ typedef struct {
 	u32 CalibrationValue;
 	XRtcPsu_Handler Handler;
 	void *CallBackRef;			/**< Callback reference for event handler */
+	u32 TimeUpdated;
+	u32 CurrTimeUpdated;
 } XRtcPsu;
 
 /**
@@ -217,7 +220,7 @@ typedef struct {
 * 		void XRtcPsu_SetTime(XRtcPsu *InstancePtr, u32 Time)
 *
 *****************************************************************************/
-#define XRtcPsu_SetTime(InstancePtr,Time) \
+#define XRtcPsu_WriteSetTime(InstancePtr,Time) \
 	XRtcPsu_WriteReg(((InstancePtr)->RtcConfig.BaseAddr + \
 				XRTC_SET_TIME_WR_OFFSET),(Time))
 
@@ -264,10 +267,10 @@ typedef struct {
 * @return	Current Time. This current time will be in seconds.
 *
 * @note		C-Style signature:
-* 		u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+* 		u32 XRtcPsu_ReadCurrentTime(XRtcPsu *InstancePtr)
 *
 *****************************************************************************/
-#define XRtcPsu_GetCurrentTime(InstancePtr) \
+#define XRtcPsu_ReadCurrentTime(InstancePtr) \
 	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CUR_TIME_OFFSET)
 
 /****************************************************************************/
@@ -368,6 +371,8 @@ void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
 		u32 CrystalOscFreq);
 u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr);
 u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr);
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr);
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time);
 
 /* interrupt functions in xrtcpsu_intr.c */
 void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask);

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c

@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights

FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c

@@ -44,6 +44,8 @@
 * Ver   Who    Date	Changes
 * ----- -----  -------- -----------------------------------------------
 * 1.00  kvn    04/21/15 First release
+* 1.3   vak    04/25/16 Changed the XRtcPsu_InterruptHandler() for updating RTC
+*                       read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -219,6 +221,14 @@ void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr)
 
 	/* Seconds interrupt */
 	if((IsrStatus & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* Set the CurrTimeUpdated flag to 1 */
+		InstancePtr->CurrTimeUpdated = 1;
+
+		if(InstancePtr->TimeUpdated == (u32)1) {
+			/* Clear the TimeUpdated */
+			InstancePtr->TimeUpdated = (u32)0;
+		}
+
 		/*
 		 * Call the application handler to indicate that there is an
 		 * seconds interrupt. If the application cares about this seconds