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Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

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Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
This commit is contained in:
Richard Barry 2017-01-19 04:11:21 +00:00
parent 6ffaa6f018
commit 992a3c8c71
266 changed files with 8242 additions and 2072 deletions
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8
FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
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@ -128,16 +128,16 @@ FreeRTOS_IRQ_Handler
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use.
; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned?
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler
PUSH {r0-r3, lr}
; Call the interrupt handler. r4 is pushed to maintain alignment.
PUSH {r0-r4, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r3, lr}
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i