Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.

FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c

@@ -136,12 +136,18 @@ context. */
 #define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portEL3							( ( StackType_t ) 0x0c )
 #define portSP_ELx						( ( StackType_t ) 0x01 )
 #define portSP_EL0						( ( StackType_t ) 0x00 )
 
-/* At the time of writing, the BSP only supports EL3. */
-#define portINITIAL_PSTATE				( portEL3 | portSP_EL0 )
+#if GUEST
+	#define portEL1						( ( StackType_t ) 0x04 )
+	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
+#else
+	#define portEL3						( ( StackType_t ) 0x0c )
+	/* At the time of writing, the BSP only supports EL3. */
+	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
+#endif
+
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
 point is zero. */
@@ -329,7 +335,9 @@ uint32_t ulAPSR;
 
 		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
 		value. */
-		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
 
 		/* Restore the clobbered interrupt priority register to its original
 		value. */
@@ -341,9 +349,13 @@ uint32_t ulAPSR;
 	/* At the time of writing, the BSP only supports EL3. */
 	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
 	ulAPSR &= portAPSR_MODE_BITS_MASK;
+#if GUEST
+	configASSERT( ulAPSR == portEL1 );
+	if( ulAPSR == portEL1 )
+#else
 	configASSERT( ulAPSR == portEL3 );
-
 	if( ulAPSR == portEL3 )
+#endif
 	{
 		/* Only continue if the binary point value is set to its lowest possible
 		setting.  See the comments in vPortValidateInterruptPriority() below for
@@ -423,7 +435,11 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
 	/* Must be the lowest possible priority. */
-	configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	#if( !QEMU )
+	{
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	}
+	#endif
 
 	/* Interrupts should not be enabled before this point. */
 	#if( configASSERT_DEFINED == 1 )

FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S

@@ -111,10 +111,14 @@
 	STP 	X30, XZR, [SP, #-0x10]!
 
 	/* Save the SPSR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
-
 	/* Save the ELR. */
 	MRS		X2, ELR_EL3
+#endif
 
 	STP 	X2, X3, [SP, #-0x10]!
 
@@ -217,11 +221,17 @@
 1:
 	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
 
+#if GUEST
+	/* Restore the SPSR. */
+	MSR		SPSR_EL1, X3
+	/* Restore the ELR. */
+	MSR		ELR_EL1, X2
+#else
 	/* Restore the SPSR. */
 	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
-
 	/* Restore the ELR. */
 	MSR		ELR_EL3, X2
+#endif
 
 	LDP 	X30, XZR, [SP], #0x10
 	LDP 	X28, X29, [SP], #0x10
@@ -256,10 +266,19 @@
 FreeRTOS_SWI_Handler:
 	/* Save the context of the current task and select a new task to run. */
 	portSAVE_CONTEXT
-
+#if GUEST
+	MRS		X0, ESR_EL1
+#else
 	MRS		X0, ESR_EL3
+#endif
+
 	LSR		X1, X0, #26
-	CMP		X1, #0x17 /* 0x17 = SMC instruction. */
+
+#if GUEST
+	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
+#else
+	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
+#endif
 	B.NE	FreeRTOS_Abort
 	BL 		vTaskSwitchContext
 
@@ -279,7 +298,11 @@ vPortRestoreTaskContext:
 
 	/* Install the FreeRTOS interrupt handlers. */
 	LDR		X1, =freertos_vector_base
+#if GUEST
+	MSR		VBAR_EL1, X1
+#else
 	MSR		VBAR_EL3, X1
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -307,8 +330,13 @@ FreeRTOS_IRQ_Handler:
 	STP		X29, X30, [SP, #-0x10]!
 
 	/* Save the SPSR and ELR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
 	MRS		X2, ELR_EL3
+#endif
 	STP 	X2, X3, [SP, #-0x10]!
 
 	/* Increment the interrupt nesting counter. */
@@ -365,8 +393,13 @@ FreeRTOS_IRQ_Handler:
 
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -390,8 +423,13 @@ FreeRTOS_IRQ_Handler:
 Exit_IRQ_No_Context_Switch:
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 

FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h

@@ -128,8 +128,11 @@ extern uint64_t ullPortYieldRequired;			\
 }
 
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SMC 0" )
-
+#if GUEST
+	#define portYIELD() __asm volatile ( "SVC 0" )
+#else
+	#define portYIELD() __asm volatile ( "SMC 0" )
+#endif
 /*-----------------------------------------------------------
  * Critical section control
  *----------------------------------------------------------*/