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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-01 08:54:14 -04:00
Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise). Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
This commit is contained in:
Richard Barry
parent
6ffaa6f018
commit
992a3c8c71
266 changed files with 8242 additions and 2072 deletions
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@ -136,12 +136,18 @@ context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portEL3 ( ( StackType_t ) 0x0c )
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#define portSP_ELx ( ( StackType_t ) 0x01 )
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#define portSP_EL0 ( ( StackType_t ) 0x00 )
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/* At the time of writing, the BSP only supports EL3. */
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#define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
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#if GUEST
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#define portEL1 ( ( StackType_t ) 0x04 )
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#define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
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#else
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#define portEL3 ( ( StackType_t ) 0x0c )
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/* At the time of writing, the BSP only supports EL3. */
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#define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
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#endif
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/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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point is zero. */
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@ -329,7 +335,9 @@ uint32_t ulAPSR;
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/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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value. */
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configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
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/* Restore the clobbered interrupt priority register to its original
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value. */
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@ -341,9 +349,13 @@ uint32_t ulAPSR;
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/* At the time of writing, the BSP only supports EL3. */
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__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
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ulAPSR &= portAPSR_MODE_BITS_MASK;
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#if GUEST
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configASSERT( ulAPSR == portEL1 );
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if( ulAPSR == portEL1 )
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#else
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configASSERT( ulAPSR == portEL3 );
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if( ulAPSR == portEL3 )
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#endif
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{
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/* Only continue if the binary point value is set to its lowest possible
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setting. See the comments in vPortValidateInterruptPriority() below for
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@ -423,7 +435,11 @@ void vPortExitCritical( void )
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void FreeRTOS_Tick_Handler( void )
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{
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/* Must be the lowest possible priority. */
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configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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#if( !QEMU )
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{
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configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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}
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#endif
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/* Interrupts should not be enabled before this point. */
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#if( configASSERT_DEFINED == 1 )
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@ -111,10 +111,14 @@
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STP X30, XZR, [SP, #-0x10]!
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/* Save the SPSR. */
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#if GUEST
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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/* Save the ELR. */
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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@ -217,11 +221,17 @@
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1:
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LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
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#if GUEST
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/* Restore the SPSR. */
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MSR SPSR_EL1, X3
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/* Restore the ELR. */
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MSR ELR_EL1, X2
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#else
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/* Restore the SPSR. */
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MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
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/* Restore the ELR. */
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MSR ELR_EL3, X2
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#endif
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LDP X30, XZR, [SP], #0x10
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LDP X28, X29, [SP], #0x10
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@ -256,10 +266,19 @@
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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#if GUEST
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MRS X0, ESR_EL1
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#else
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MRS X0, ESR_EL3
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#endif
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LSR X1, X0, #26
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CMP X1, #0x17 /* 0x17 = SMC instruction. */
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#if GUEST
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CMP X1, #0x15 /* 0x15 = SVC instruction. */
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#else
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CMP X1, #0x17 /* 0x17 = SMC instruction. */
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#endif
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B.NE FreeRTOS_Abort
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BL vTaskSwitchContext
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@ -279,7 +298,11 @@ vPortRestoreTaskContext:
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/* Install the FreeRTOS interrupt handlers. */
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LDR X1, =freertos_vector_base
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#if GUEST
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MSR VBAR_EL1, X1
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#else
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MSR VBAR_EL3, X1
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#endif
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DSB SY
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ISB SY
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@ -307,8 +330,13 @@ FreeRTOS_IRQ_Handler:
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STP X29, X30, [SP, #-0x10]!
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/* Save the SPSR and ELR. */
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#if GUEST
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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/* Increment the interrupt nesting counter. */
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@ -365,8 +393,13 @@ FreeRTOS_IRQ_Handler:
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if GUEST
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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@ -390,8 +423,13 @@ FreeRTOS_IRQ_Handler:
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Exit_IRQ_No_Context_Switch:
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if GUEST
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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@ -128,8 +128,11 @@ extern uint64_t ullPortYieldRequired; \
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}
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#define portYIELD() __asm volatile ( "SMC 0" )
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#if GUEST
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#define portYIELD() __asm volatile ( "SVC 0" )
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#else
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#define portYIELD() __asm volatile ( "SMC 0" )
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#endif
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/*-----------------------------------------------------------
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* Critical section control
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*----------------------------------------------------------*/
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@ -475,7 +475,7 @@ void xPortSysTickHandler( void )
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__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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{
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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TickType_t xModifiableIdleTime;
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/* Make sure the SysTick reload value does not overflow the counter. */
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@ -551,18 +551,21 @@ void xPortSysTickHandler( void )
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}
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configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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/* Stop SysTick. Again, the time the SysTick is stopped for is
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accounted for as best it can be, but using the tickless mode will
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inevitably result in some tiny drift of the time maintained by the
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kernel with respect to calendar time. */
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ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
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portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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/* Re-enable interrupts - see comments above the cpsid instruction()
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above. */
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__asm volatile( "cpsie i" );
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/* Disable the SysTick clock without reading the
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portNVIC_SYSTICK_CTRL_REG register to ensure the
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portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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/* Determine if the SysTick clock has already counted to zero and
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been set back to the current reload value (the reload back being
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correct for the entire expected idle time) or if the SysTick is yet
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to count to zero (in which case an interrupt other than the SysTick
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must have brought the system out of sleep mode). */
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if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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{
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uint32_t ulCalculatedLoadValue;
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@ -230,16 +230,17 @@ FreeRTOS_IRQ_Handler:
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LDR r0, [r2]
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/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
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future use. */
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future use. _RB_ Is this ever needed provided the start of the stack is
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alligned on an 8-byte boundary? */
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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/* Call the interrupt handler. */
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PUSH {r0-r3, lr}
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PUSH {r0-r4, lr}
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LDR r1, vApplicationIRQHandlerConst
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BLX r1
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POP {r0-r3, lr}
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POP {r0-r4, lr}
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ADD sp, sp, r2
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CPSID i
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@ -128,16 +128,16 @@ FreeRTOS_IRQ_Handler
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LDR r0, [r2]
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; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
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; future use.
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; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned?
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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; Call the interrupt handler
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PUSH {r0-r3, lr}
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; Call the interrupt handler. r4 is pushed to maintain alignment.
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PUSH {r0-r4, lr}
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LDR r1, =vApplicationIRQHandler
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BLX r1
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POP {r0-r3, lr}
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POP {r0-r4, lr}
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ADD sp, sp, r2
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CPSID i
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