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Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

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Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
This commit is contained in:
Richard Barry 2017-01-19 04:11:21 +00:00
parent 6ffaa6f018
commit 992a3c8c71
266 changed files with 8242 additions and 2072 deletions
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FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
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@ -116,7 +116,7 @@
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<entry excluding="src/printf-stdarg.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata|src/platform.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>