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Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

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Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
This commit is contained in:
Richard Barry 2017-01-19 04:11:21 +00:00
parent 6ffaa6f018
commit 992a3c8c71
266 changed files with 8242 additions and 2072 deletions
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9
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
View file

@ -20,7 +20,7 @@
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53" id="xilinx.arm.a53.target.gnu.base.debug.565045804" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.a53.target.gnu.base.debug"/>
<builder buildPath="${workspace_loc:/RTOSDemo_A53}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.a53.toolchain.builder.debug.1503003921" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.a53.toolchain.builder.debug"/>
<tool id="xilinx.gnu.arm.a53.c.toolchain.assembler.debug.1142300561" name="ARM A53 gcc assembler" superClass="xilinx.gnu.arm.a53.c.toolchain.assembler.debug">
<option id="xilinx.gnu.both.assembler.option.flags.139020974" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
<option id="xilinx.gnu.both.assembler.option.flags.139020974" name="Assembler Flags" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
<inputType id="xilinx.gnu.assembler.input.478741574" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.arm.a53.c.toolchain.compiler.debug.587400676" name="ARM A53 gcc compiler" superClass="xilinx.gnu.arm.a53.c.toolchain.compiler.debug">
@ -29,14 +29,15 @@
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1218722002" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../RTOSDemo_A53_bsp/psu_cortexa53_0/include"/>
</option>
<option id="xilinx.gnu.compiler.dircategory.includes.959905810" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
<option id="xilinx.gnu.compiler.dircategory.includes.959905810" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CA53_64_BIT}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
</option>
<option id="xilinx.gnu.compiler.misc.other.1651312713" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
<option id="xilinx.gnu.compiler.misc.other.1651312713" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
<option id="xilinx.gnu.compiler.symbols.defined.890730491" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols"/>
<inputType id="xilinx.gnu.arm.a53.c.compiler.input.1725216366" name="C source files" superClass="xilinx.gnu.arm.a53.c.compiler.input"/>
</tool>
<tool id="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug.986847379" name="ARM A53 g++ compiler" superClass="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug">
@ -55,6 +56,7 @@
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.210457854" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other" valueType="stringList"/>
<inputType id="xilinx.gnu.linker.input.294386883" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@ -164,4 +166,5 @@
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>

58
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
View file

@ -288,64 +288,6 @@ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
}
/*-----------------------------------------------------------*/
void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )
{
/* The compiler used during development seems to err unless these volatiles are
included at -O3 optimisation. */
volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;
size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
if( pvDest != pvSource )
{
for( x = 0; x < xBytes; x++ )
{
pcDest[ x ] = pcSource[ x ];
}
}
return pvDest;
}
/*-----------------------------------------------------------*/
void *memset( void *pvDest, int iValue, size_t xBytes )
{
/* The compiler used during development seems to err unless these volatiles are
included at -O3 optimisation. */
volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;
volatile size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
for( x = 0; x < xBytes; x++ )
{
pcDest[ x ] = ( unsigned char ) iValue;
}
return pvDest;
}
/*-----------------------------------------------------------*/
int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes )
{
const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;
volatile size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
for( x = 0; x < xBytes; x++ )
{
if( pucMem1[ x ] != pucMem2[ x ] )
{
break;
}
}
return xBytes - x;
}
/*-----------------------------------------------------------*/
void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
{
xil_printf( "ASSERT! Line %lu of file %s\r\n", ulLineNumber, pcFileName );

102
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
View file

@ -260,12 +260,12 @@
#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
/******************************************************************/
@ -275,12 +275,12 @@
#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
/******************************************************************/
@ -452,8 +452,6 @@
/* Definitions for peripheral PSU_IOU_S */
#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
/* Definitions for peripheral PSU_IOU_SCNTR */
@ -512,8 +510,6 @@
/* Definitions for peripheral PSU_OCM_RAM_1 */
#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PSU_OCM_XMPU_CFG */
@ -651,7 +647,7 @@
/******************************************************************/
#define XPAR_XIPIPSU_NUM_INSTANCES 1
#define XPAR_XIPIPSU_NUM_INSTANCES 3
/* Parameter definitions for peripheral psu_ipi_0 */
#define XPAR_PSU_IPI_0_DEVICE_ID 0
@ -660,6 +656,20 @@
#define XPAR_PSU_IPI_0_BUFFER_INDEX 2
#define XPAR_PSU_IPI_0_INT_ID 67
/* Parameter definitions for peripheral psu_ipi_1 */
#define XPAR_PSU_IPI_1_DEVICE_ID 1
#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000
#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100
#define XPAR_PSU_IPI_1_BUFFER_INDEX 0
#define XPAR_PSU_IPI_1_INT_ID 65
/* Parameter definitions for peripheral psu_ipi_2 */
#define XPAR_PSU_IPI_2_DEVICE_ID 2
#define XPAR_PSU_IPI_2_BASE_ADDRESS 0xFF320000
#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200
#define XPAR_PSU_IPI_2_BUFFER_INDEX 1
#define XPAR_PSU_IPI_2_INT_ID 66
/* Canonical definitions for peripheral psu_ipi_0 */
#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_0_DEVICE_ID
#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_0_BASE_ADDRESS
@ -667,6 +677,20 @@
#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_0_BUFFER_INDEX
#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_0_INT_ID
/* Canonical definitions for peripheral psu_ipi_1 */
#define XPAR_XIPIPSU_1_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID
#define XPAR_XIPIPSU_1_BASE_ADDRESS XPAR_PSU_IPI_1_BASE_ADDRESS
#define XPAR_XIPIPSU_1_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPSU_1_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX
#define XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_1_INT_ID
/* Canonical definitions for peripheral psu_ipi_2 */
#define XPAR_XIPIPSU_2_DEVICE_ID XPAR_PSU_IPI_2_DEVICE_ID
#define XPAR_XIPIPSU_2_BASE_ADDRESS XPAR_PSU_IPI_2_BASE_ADDRESS
#define XPAR_XIPIPSU_2_BIT_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPSU_2_BUFFER_INDEX XPAR_PSU_IPI_2_BUFFER_INDEX
#define XPAR_XIPIPSU_2_INT_ID XPAR_PSU_IPI_2_INT_ID
#define XPAR_XIPIPSU_NUM_TARGETS 11
#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001
@ -695,15 +719,31 @@
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1
@ -715,14 +755,18 @@
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 1
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 2
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_3_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 3
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_4_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 4
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK XPAR_PSU_IPI_5_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX 5
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK XPAR_PSU_IPI_6_BIT_MASK
#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX 6
/* Definitions for driver QSPIPSU */
#define XPAR_XQSPIPSU_NUM_INSTANCES 1
@ -1010,14 +1054,14 @@
#define XPAR_PSU_WDT_0_DEVICE_ID 0
#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
/* Definitions for peripheral PSU_WDT_1 */
#define XPAR_PSU_WDT_1_DEVICE_ID 1
#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
/******************************************************************/
@ -1026,13 +1070,13 @@
#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
#define XPAR_XWDTPS_0_BASEADDR 0xFF150000
#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
/* Canonical definitions for peripheral PSU_WDT_1 */
#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
/******************************************************************/

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

114
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -101,5 +101,117 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
XPAR_PSU_IPI_10_BUFFER_INDEX
}
}
},
{
XPAR_PSU_IPI_1_DEVICE_ID,
XPAR_PSU_IPI_1_BASE_ADDRESS,
XPAR_PSU_IPI_1_BIT_MASK,
XPAR_PSU_IPI_1_BUFFER_INDEX,
XPAR_PSU_IPI_1_INT_ID,
XPAR_XIPIPSU_NUM_TARGETS,
{
{
XPAR_PSU_IPI_0_BIT_MASK,
XPAR_PSU_IPI_0_BUFFER_INDEX
},
{
XPAR_PSU_IPI_1_BIT_MASK,
XPAR_PSU_IPI_1_BUFFER_INDEX
},
{
XPAR_PSU_IPI_2_BIT_MASK,
XPAR_PSU_IPI_2_BUFFER_INDEX
},
{
XPAR_PSU_IPI_3_BIT_MASK,
XPAR_PSU_IPI_3_BUFFER_INDEX
},
{
XPAR_PSU_IPI_4_BIT_MASK,
XPAR_PSU_IPI_4_BUFFER_INDEX
},
{
XPAR_PSU_IPI_5_BIT_MASK,
XPAR_PSU_IPI_5_BUFFER_INDEX
},
{
XPAR_PSU_IPI_6_BIT_MASK,
XPAR_PSU_IPI_6_BUFFER_INDEX
},
{
XPAR_PSU_IPI_7_BIT_MASK,
XPAR_PSU_IPI_7_BUFFER_INDEX
},
{
XPAR_PSU_IPI_8_BIT_MASK,
XPAR_PSU_IPI_8_BUFFER_INDEX
},
{
XPAR_PSU_IPI_9_BIT_MASK,
XPAR_PSU_IPI_9_BUFFER_INDEX
},
{
XPAR_PSU_IPI_10_BIT_MASK,
XPAR_PSU_IPI_10_BUFFER_INDEX
}
}
},
{
XPAR_PSU_IPI_2_DEVICE_ID,
XPAR_PSU_IPI_2_BASE_ADDRESS,
XPAR_PSU_IPI_2_BIT_MASK,
XPAR_PSU_IPI_2_BUFFER_INDEX,
XPAR_PSU_IPI_2_INT_ID,
XPAR_XIPIPSU_NUM_TARGETS,
{
{
XPAR_PSU_IPI_0_BIT_MASK,
XPAR_PSU_IPI_0_BUFFER_INDEX
},
{
XPAR_PSU_IPI_1_BIT_MASK,
XPAR_PSU_IPI_1_BUFFER_INDEX
},
{
XPAR_PSU_IPI_2_BIT_MASK,
XPAR_PSU_IPI_2_BUFFER_INDEX
},
{
XPAR_PSU_IPI_3_BIT_MASK,
XPAR_PSU_IPI_3_BUFFER_INDEX
},
{
XPAR_PSU_IPI_4_BIT_MASK,
XPAR_PSU_IPI_4_BUFFER_INDEX
},
{
XPAR_PSU_IPI_5_BIT_MASK,
XPAR_PSU_IPI_5_BUFFER_INDEX
},
{
XPAR_PSU_IPI_6_BIT_MASK,
XPAR_PSU_IPI_6_BUFFER_INDEX
},
{
XPAR_PSU_IPI_7_BIT_MASK,
XPAR_PSU_IPI_7_BUFFER_INDEX
},
{
XPAR_PSU_IPI_8_BIT_MASK,
XPAR_PSU_IPI_8_BUFFER_INDEX
},
{
XPAR_PSU_IPI_9_BIT_MASK,
XPAR_PSU_IPI_9_BUFFER_INDEX
},
{
XPAR_PSU_IPI_10_BIT_MASK,
XPAR_PSU_IPI_10_BUFFER_INDEX
}
}
}
};

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights

2
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights