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Update to V4.5.0 files and directory structure.
This commit is contained in:
Richard Barry
parent
1362bebfdc
commit
98a9959a44
758 changed files with 53177 additions and 3139 deletions
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@ -1,5 +1,5 @@
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/*
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FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
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FreeRTOS.org V4.5.0 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS distribution.
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@ -34,7 +34,7 @@
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ST STR91x ARM7
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* Implementation of functions defined in portable.h for the ST STR91x ARM9
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* port.
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*----------------------------------------------------------*/
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@ -43,22 +43,54 @@
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/* Standard includes. */
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#include <stdlib.h>
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#include <assert.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configUSE_WATCHDOG_TICK
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#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
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#endif
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/* Constants required to setup the initial stack. */
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#ifndef _RUN_TASK_IN_ARM_MODE_
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#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
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#else
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#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#endif
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#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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#ifndef abs
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#define abs(x) ((x)>0 ? (x) : -(x))
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#endif
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/**
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* Toggle a led using the following algorithm:
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* if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
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* {
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* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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* }
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* else
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* {
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* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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* }
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*
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*/
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#define TOGGLE_LED(port,pin) \
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if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
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{ \
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(port)->DR[(pin) <<2] = 0x00; \
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} \
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else \
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{ \
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(port)->DR[(pin) <<2] = (pin); \
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}
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/*-----------------------------------------------------------*/
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@ -73,12 +105,16 @@ unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;
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/* Tick interrupt routines for cooperative and preemptive operation
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respectively. The preemptive version is not defined as __irq as it is called
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from an asm wrapper function. */
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__arm __irq void vPortNonPreemptiveTick( void );
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void WDG_IRQHandler( void );
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/* VIC interrupt default handler. */
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static void prvDefaultHandler( void );
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#if configUSE_WATCHDOG_TICK == 0
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/* Used to update the OCR timer register */
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static u16 s_nPulseLength;
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#endif
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/*-----------------------------------------------------------*/
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/*
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@ -174,90 +210,189 @@ void vPortEndScheduler( void )
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/* This function is called from an asm wrapper, so does not require the __irq
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keyword. */
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void WDG_IRQHandler( void )
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{
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/* Increment the tick counter. */
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vTaskIncrementTick();
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#if configUSE_WATCHDOG_TICK == 1
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#if configUSE_PREEMPTION == 1
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/* The new tick value might unblock a task. Ensure the highest task that
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is ready to execute is the task that will execute when the tick ISR
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exits. */
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vTaskSwitchContext();
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#endif
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/* Clear the interrupt in the watchdog. */
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WDG->SR &= ~0x0001;
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}
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/*-----------------------------------------------------------*/
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#ifndef abs
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#define abs(x) ((x)>0 ? (x) : -(x))
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#endif
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static void prvFindFactors(u32 n, u16 *a, u32 *b)
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{
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/* This function is copied from the ST STR7 library and is
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copyright STMicroelectronics. Reproduced with permission. */
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u32 b0;
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u16 a0;
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long err, err_min=n;
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*a = a0 = ((n-1)/65536ul) + 1;
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*b = b0 = n / *a;
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for (; *a <= 256; (*a)++)
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static void prvFindFactors(u32 n, u16 *a, u32 *b)
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{
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*b = n / *a;
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err = (long)*a * (long)*b - (long)n;
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if (abs(err) > (*a / 2))
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/* This function is copied from the ST STR7 library and is
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copyright STMicroelectronics. Reproduced with permission. */
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u32 b0;
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u16 a0;
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long err, err_min=n;
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*a = a0 = ((n-1)/65536ul) + 1;
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*b = b0 = n / *a;
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for (; *a <= 256; (*a)++)
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{
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(*b)++;
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*b = n / *a;
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err = (long)*a * (long)*b - (long)n;
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if (abs(err) > (*a / 2))
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{
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(*b)++;
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err = (long)*a * (long)*b - (long)n;
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}
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if (abs(err) < abs(err_min))
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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if (err == 0) break;
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}
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}
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if (abs(err) < abs(err_min))
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*a = a0;
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*b = b0;
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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WDG_InitTypeDef xWdg;
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unsigned portSHORT a;
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unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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/* Configure the watchdog as a free running timer that generates a
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periodic interrupt. */
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SCU_APBPeriphClockConfig( __WDG, ENABLE );
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WDG_DeInit();
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WDG_StructInit(&xWdg);
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prvFindFactors( n, &a, &b );
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xWdg.WDG_Prescaler = a - 1;
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xWdg.WDG_Preload = b - 1;
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WDG_Init( &xWdg );
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WDG_ITConfig(ENABLE);
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/* Configure the VIC for the WDG interrupt. */
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VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
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VIC_ITCmd( WDG_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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WDG_Cmd(ENABLE);
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}
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/*-----------------------------------------------------------*/
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void WDG_IRQHandler( void )
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{
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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if (err == 0) break;
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/* Increment the tick counter. */
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vTaskIncrementTick();
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#if configUSE_PREEMPTION == 1
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{
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/* The new tick value might unblock a task. Ensure the highest task that
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is ready to execute is the task that will execute when the tick ISR
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exits. */
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vTaskSwitchContext();
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}
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#endif /* configUSE_PREEMPTION. */
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/* Clear the interrupt in the watchdog. */
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WDG->SR &= ~0x0001;
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}
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}
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*a = a0;
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*b = b0;
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}
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/*-----------------------------------------------------------*/
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#else
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static void prvSetupTimerInterrupt( void )
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{
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WDG_InitTypeDef xWdg;
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unsigned portSHORT a;
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unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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static void prvFindFactors(u32 n, u8 *a, u16 *b)
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{
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/* This function is copied from the ST STR7 library and is
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copyright STMicroelectronics. Reproduced with permission. */
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u16 b0;
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u8 a0;
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long err, err_min=n;
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*a = a0 = ((n-1)/256) + 1;
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*b = b0 = n / *a;
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for (; *a <= 256; (*a)++)
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{
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*b = n / *a;
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err = (long)*a * (long)*b - (long)n;
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if (abs(err) > (*a / 2))
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{
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(*b)++;
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err = (long)*a * (long)*b - (long)n;
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}
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if (abs(err) < abs(err_min))
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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if (err == 0) break;
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}
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}
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*a = a0;
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*b = b0;
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}
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/*-----------------------------------------------------------*/
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/* Configure the watchdog as a free running timer that generates a
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periodic interrupt. */
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static void prvSetupTimerInterrupt( void )
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{
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unsigned portCHAR a;
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unsigned portSHORT b;
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unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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TIM_InitTypeDef timer;
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SCU_APBPeriphClockConfig( __TIM23, ENABLE );
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TIM_DeInit(TIM2);
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TIM_StructInit(&timer);
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prvFindFactors( n, &a, &b );
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timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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timer.TIM_OC1_Modes = TIM_TIMING;
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timer.TIM_Clock_Source = TIM_CLK_APB;
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timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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timer.TIM_Prescaler = a-1;
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timer.TIM_Pulse_Level_1 = TIM_HIGH;
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timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
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TIM_Init (TIM2, &timer);
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TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
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/* Configure the VIC for the WDG interrupt. */
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VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
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VIC_ITCmd( TIM2_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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TIM_CounterCmd(TIM2, TIM_CLEAR);
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TIM_CounterCmd(TIM2, TIM_START);
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}
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/*-----------------------------------------------------------*/
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SCU_APBPeriphClockConfig( __WDG, ENABLE );
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WDG_DeInit();
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WDG_StructInit(&xWdg);
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prvFindFactors( n, &a, &b );
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xWdg.WDG_Prescaler = a - 1;
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xWdg.WDG_Preload = b - 1;
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WDG_Init( &xWdg );
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WDG_ITConfig(ENABLE);
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/* Configure the VIC for the WDG interrupt. */
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VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
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VIC_ITCmd( WDG_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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WDG_Cmd(ENABLE);
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}
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void TIM2_IRQHandler( void )
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{
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/* Reset the timer counter to avioid overflow. */
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TIM2->OC1R += s_nPulseLength;
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/* Increment the tick counter. */
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vTaskIncrementTick();
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#if configUSE_PREEMPTION == 1
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{
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/* The new tick value might unblock a task. Ensure the highest task that
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is ready to execute is the task that will execute when the tick ISR
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exits. */
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vTaskSwitchContext();
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}
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#endif
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/* Clear the interrupt in the watchdog. */
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TIM2->SR &= ~TIM_FLAG_OC1;
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}
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#endif /* USE_WATCHDOG_TICK */
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/*-----------------------------------------------------------*/
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