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Update to V4.5.0 files and directory structure.
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Richard Barry
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758 changed files with 53177 additions and 3139 deletions
281
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c
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Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c
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/*
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FreeRTOS.org V4.5.0 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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/* Kernel includes. */
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#include "FreeRTOS.h"
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#include "Semphr.h"
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#include "task.h"
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/* Demo includes. */
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#include "EMAC.h"
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/* uIP includes. */
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#include "uip.h"
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/* Hardware library includes. */
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#include "hw_types.h"
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#include "hw_memmap.h"
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#include "hw_ints.h"
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#include "hw_ethernet.h"
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#include "ethernet.h"
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#include "interrupt.h"
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#define emacNUM_RX_BUFFERS 5
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#define emacFRAM_SIZE_BYTES 2
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#define macNEGOTIATE_DELAY 2000
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#define macWAIT_SEND_TIME ( 10 )
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/* The task that handles the MAC peripheral. This is created at a high
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priority and is effectively a deferred interrupt handler. The peripheral
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handling is deferred to a task to prevent the entire FIFO having to be read
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from within an ISR. */
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void vMACHandleTask( void *pvParameters );
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/*-----------------------------------------------------------*/
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/* The semaphore used to wake the uIP task when data arrives. */
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xSemaphoreHandle xEMACSemaphore = NULL;
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/* The semaphore used to wake the interrupt handler task. The peripheral
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is processed at the task level to prevent the need to read the entire FIFO from
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within the ISR itself. */
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xSemaphoreHandle xMACInterruptSemaphore = NULL;
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/* The buffer used by the uIP stack. In this case the pointer is used to
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point to one of the Rx buffers. */
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unsigned portCHAR *uip_buf;
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/* Buffers into which Rx data is placed. */
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static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ];
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/* The length of the data within each of the Rx buffers. */
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static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ];
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/* Used to keep a track of the number of bytes to transmit. */
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static unsigned portLONG ulNextTxSpace;
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/*-----------------------------------------------------------*/
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portBASE_TYPE vInitEMAC( void )
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{
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unsigned long ulTemp;
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portBASE_TYPE xReturn;
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/* Ensure all interrupts are disabled. */
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EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
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/* Clear any interrupts that were already pending. */
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ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
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EthernetIntClear( ETH_BASE, ulTemp );
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/* Initialise the MAC and connect. */
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EthernetInit( ETH_BASE );
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EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );
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EthernetEnable( ETH_BASE );
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/* Mark each Rx buffer as empty. */
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for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )
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{
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ulRxLength[ ulTemp ] = 0;
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}
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/* Create the queue and task used to defer the MAC processing to the
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task level. */
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vSemaphoreCreateBinary( xMACInterruptSemaphore );
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xSemaphoreTake( xMACInterruptSemaphore, 0 );
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xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
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vTaskDelay( macNEGOTIATE_DELAY );
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/* We are only interested in Rx interrupts. */
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IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );
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IntEnable( INT_ETH );
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EthernetIntEnable(ETH_BASE, ETH_INT_RX);
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
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{
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static unsigned long ulNextRxBuffer = 0;
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unsigned int iLen;
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iLen = ulRxLength[ ulNextRxBuffer ];
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if( iLen != 0 )
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{
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/* Leave room for the size at the start of the buffer. */
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uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
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ulRxLength[ ulNextRxBuffer ] = 0;
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ulNextRxBuffer++;
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if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
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{
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ulNextRxBuffer = 0;
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}
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}
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return iLen;
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}
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/*-----------------------------------------------------------*/
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void vInitialiseSend( void )
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{
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/* Set the index to the first byte to send - skipping over the size
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bytes. */
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ulNextTxSpace = 2;
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}
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/*-----------------------------------------------------------*/
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void vIncrementTxLength( unsigned portLONG ulLength )
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{
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ulNextTxSpace += ulLength;
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}
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/*-----------------------------------------------------------*/
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void vSendBufferToMAC( void )
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{
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unsigned long *pulSource;
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unsigned portSHORT * pus;
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unsigned portLONG ulNextWord;
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/* Locate the data to be send. */
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pus = ( unsigned portSHORT * ) uip_buf;
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/* Add in the size of the data. */
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pus--;
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*pus = ulNextTxSpace;
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/* Wait for data to be sent if there is no space immediately. */
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while( !EthernetSpaceAvail( ETH_BASE ) )
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{
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vTaskDelay( macWAIT_SEND_TIME );
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}
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pulSource = ( unsigned portLONG * ) pus;
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for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) )
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{
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HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;
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pulSource++;
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}
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/* Go. */
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HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;
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}
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/*-----------------------------------------------------------*/
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void vEMAC_ISR( void )
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{
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portBASE_TYPE xSwitchRequired = pdFALSE;
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unsigned portLONG ulTemp;
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/* Clear the interrupt. */
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ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
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EthernetIntClear( ETH_BASE, ulTemp );
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/* Was it an Rx interrupt? */
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if( ulTemp & ETH_INT_RX )
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{
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xSwitchRequired = pdTRUE;
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xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE );
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EthernetIntDisable( ETH_BASE, ETH_INT_RX );
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}
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/* Switch to the uIP task. */
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portEND_SWITCHING_ISR( xSwitchRequired );
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}
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/*-----------------------------------------------------------*/
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void vMACHandleTask( void *pvParameters )
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{
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unsigned long ulLen = 0, i;
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unsigned portLONG ulLength, ulInt;
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unsigned long *pulBuffer;
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static unsigned portLONG ulNextRxBuffer = 0;
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portBASE_TYPE xSwitchRequired = pdFALSE;
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for( ;; )
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{
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/* Wait for something to do. */
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xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );
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while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )
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{
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ulLength = HWREG( ETH_BASE + MAC_O_DATA );
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/* Leave room at the start of the buffer for the size. */
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pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
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*pulBuffer = ( ulLength >> 16 );
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/* Get the size of the data. */
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pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] );
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ulLength &= 0xFFFF;
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if( ulLength > 4 )
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{
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ulLength -= 4;
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if( ulLength >= UIP_BUFSIZE )
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{
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/* The data won't fit in our buffer. Ensure we don't
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try to write into the buffer. */
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ulLength = 0;
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}
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/* Read out the data into our buffer. */
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for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) )
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{
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*pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );
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pulBuffer++;
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}
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/* Store the length of the data into the separate array. */
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ulRxLength[ ulNextRxBuffer ] = ulLength;
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/* Use the next buffer the next time through. */
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ulNextRxBuffer++;
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if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
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{
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ulNextRxBuffer = 0;
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}
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/* Ensure the uIP task is not blocked as data has arrived. */
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xSemaphoreGive( xEMACSemaphore );
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}
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}
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EthernetIntEnable( ETH_BASE, ETH_INT_RX );
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}
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}
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