mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-06 14:17:41 -04:00
Feature: SMP (#278)
* Add XMOS XCore ports Some minor modifications are also made to the kernel to support the XCore compiler's automatic stack size calculation. * Update kernel to support SMP The XMOS XCore ports are also updated to support SMP. * Fix compiler warnings in xcore ports The port set and clear interrupt mask from ISR macros were removed from the ports so that the default macros found in FreeRTOS.h are used instead. The default macros do not result in warnings when they are used. * Remove inline function from timers.h Inline function converted to macro. This should now build when optimizations are off and inlining is disabled. * Fix compiler warnings in xcore ports and tasks.c * fixed documentation for ulTaskNotifyTake() and ulTaskNotifyTakeIndexed() * spelling fixes for tasks.c Co-authored-by: Michael Bruno <mikeb@xmos.com>
This commit is contained in:
Joseph Julicher
GitHub
parent
cafae476e4
commit
989bc332b2
509 changed files with 176869 additions and 174380 deletions
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@ -1,214 +1,214 @@
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
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* this software and associated documentation files (the "Software"), to deal in
|
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* the Software without restriction, including without limitation the rights to
|
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 132
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#ifdef __LANGUAGE_ASSEMBLY__
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/******************************************************************/
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.macro portSAVE_CONTEXT
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/* Make room for the context. First save the current status so it can be
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manipulated, and the cause and EPC registers so their original values are
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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maintain the values of these registers across the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Prepare to enable interrupts above the current priority.
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k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
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srl k0, k0, 0xa
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/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
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ins k1, k0, 10, 7
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/* Sets CP0.Status.IPL = CP0.Cause.RIPL
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Copy the MSB of the IPL, but it would be an error if it was set anyway. */
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srl k0, k0, 0x7
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/* MSB of IPL is bit[18] of CP0.Status */
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ins k1, k0, 18, 1
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/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
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b[3]=Rsvd, b[2]=ERL, b[1]=EXL
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Setting EXL=0 allows higher priority interrupts
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to preempt this handler */
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, (k0)
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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the system stack is already being used. */
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bne s6, zero, 1f
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nop
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, (sp)
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/* Increment and save the nesting count. */
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1: addiu s6, s6, 1
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sw s6, 0(k0)
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. No other s registers need be
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saved. */
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sw ra, 120(s5) /* Return address (RA=R31) */
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sw s8, 116(s5) /* Frame Pointer (FP=R30) */
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sw t9, 112(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t6, 100(s5)
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sw t5, 96(s5)
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sw t4, 92(s5)
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sw t3, 88(s5)
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sw t2, 84(s5)
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sw t1, 80(s5)
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sw t0, 76(s5)
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sw a3, 72(s5)
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sw a2, 68(s5)
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sw a1, 64(s5)
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sw a0, 60(s5)
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sw v1, 56(s5)
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sw v0, 52(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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sw $1, 16(s5)
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/* MEC14xx does not have DSP, removed 7 words */
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mfhi s6
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sw s6, 12(s5)
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mflo s6
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sw s6, 8(s5)
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Save the stack pointer. */
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la s6, uxSavedTaskStackPointer
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sw s5, (s6)
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1:
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.endm
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/******************************************************************/
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.macro portRESTORE_CONTEXT
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/* Restore the stack pointer from the TCB. This is only done if the
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nesting count is 1. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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la s6, uxSavedTaskStackPointer
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lw s5, (s6)
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/* Restore the context.
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MCHP MEC14xx does not include DSP */
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1:
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lw s6, 8(s5)
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mtlo s6
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lw s6, 12(s5)
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mthi s6
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lw $1, 16(s5)
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/* s6 is loaded as it was used as a scratch register and therefore saved
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as part of the interrupt context. */
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lw s6, 44(s5)
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lw v0, 52(s5)
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lw v1, 56(s5)
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lw a0, 60(s5)
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lw a1, 64(s5)
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lw a2, 68(s5)
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lw a3, 72(s5)
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lw t0, 76(s5)
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lw t1, 80(s5)
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lw t2, 84(s5)
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lw t3, 88(s5)
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lw t4, 92(s5)
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lw t5, 96(s5)
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lw t6, 100(s5)
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lw t7, 104(s5)
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lw t8, 108(s5)
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lw t9, 112(s5)
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lw s8, 116(s5)
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lw ra, 120(s5)
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/* Protect access to the k registers, and others. */
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di
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ehb
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/* Decrement the nesting count. */
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la k0, uxInterruptNesting
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lw k1, (k0)
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addiu k1, k1, -1
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sw k1, 0(k0)
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k0, _CP0_STATUS
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mtc0 k1, _CP0_EPC
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ehb
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eret
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nop
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.endm
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#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
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* this software and associated documentation files (the "Software"), to deal in
|
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* the Software without restriction, including without limitation the rights to
|
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
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*
|
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* The above copyright notice and this permission notice shall be included in all
|
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 132
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#ifdef __LANGUAGE_ASSEMBLY__
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/******************************************************************/
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.macro portSAVE_CONTEXT
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/* Make room for the context. First save the current status so it can be
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manipulated, and the cause and EPC registers so their original values are
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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maintain the values of these registers across the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Prepare to enable interrupts above the current priority.
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k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
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srl k0, k0, 0xa
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/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
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ins k1, k0, 10, 7
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/* Sets CP0.Status.IPL = CP0.Cause.RIPL
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Copy the MSB of the IPL, but it would be an error if it was set anyway. */
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srl k0, k0, 0x7
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/* MSB of IPL is bit[18] of CP0.Status */
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ins k1, k0, 18, 1
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/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
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b[3]=Rsvd, b[2]=ERL, b[1]=EXL
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Setting EXL=0 allows higher priority interrupts
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to preempt this handler */
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, (k0)
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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the system stack is already being used. */
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bne s6, zero, 1f
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nop
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, (sp)
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/* Increment and save the nesting count. */
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1: addiu s6, s6, 1
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sw s6, 0(k0)
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. No other s registers need be
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saved. */
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sw ra, 120(s5) /* Return address (RA=R31) */
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sw s8, 116(s5) /* Frame Pointer (FP=R30) */
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sw t9, 112(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t6, 100(s5)
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sw t5, 96(s5)
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sw t4, 92(s5)
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sw t3, 88(s5)
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sw t2, 84(s5)
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sw t1, 80(s5)
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sw t0, 76(s5)
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sw a3, 72(s5)
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sw a2, 68(s5)
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sw a1, 64(s5)
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sw a0, 60(s5)
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sw v1, 56(s5)
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sw v0, 52(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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sw $1, 16(s5)
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/* MEC14xx does not have DSP, removed 7 words */
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mfhi s6
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sw s6, 12(s5)
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mflo s6
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sw s6, 8(s5)
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Save the stack pointer. */
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la s6, uxSavedTaskStackPointer
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sw s5, (s6)
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1:
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.endm
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/******************************************************************/
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.macro portRESTORE_CONTEXT
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/* Restore the stack pointer from the TCB. This is only done if the
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nesting count is 1. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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la s6, uxSavedTaskStackPointer
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lw s5, (s6)
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|
||||
/* Restore the context.
|
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MCHP MEC14xx does not include DSP */
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1:
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lw s6, 8(s5)
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mtlo s6
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lw s6, 12(s5)
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mthi s6
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lw $1, 16(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
as part of the interrupt context. */
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
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lw a0, 60(s5)
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lw a1, 64(s5)
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lw a2, 68(s5)
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lw a3, 72(s5)
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lw t0, 76(s5)
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||||
lw t1, 80(s5)
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||||
lw t2, 84(s5)
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||||
lw t3, 88(s5)
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lw t4, 92(s5)
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lw t5, 96(s5)
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lw t6, 100(s5)
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lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
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lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
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lw k1, (k0)
|
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addiu k1, k1, -1
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sw k1, 0(k0)
|
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|
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lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
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|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
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||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.endm
|
||||
|
||||
#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,345 +1,345 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Microchip includes. */
|
||||
#include <xc.h>
|
||||
#include <cp0defs.h>
|
||||
|
||||
#if !defined(__MEC__)
|
||||
#error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
|
||||
#endif
|
||||
|
||||
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#endif
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/* MEC14xx RTOS Timer MMCR's. */
|
||||
#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
|
||||
#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
|
||||
|
||||
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
|
||||
peripheral space. */
|
||||
#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
|
||||
#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
|
||||
|
||||
/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
|
||||
|
||||
/*
|
||||
By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
can override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
behaviour for the specified interrupt vector.
|
||||
3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
handler.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Used to catch tasks that attempt to return from their implementing function.
|
||||
*/
|
||||
static void prvTaskExitError( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
UBaseType_t uxSavedTaskStackPointer = 0;
|
||||
|
||||
/* The stack used by interrupt service routines that cause a context switch. */
|
||||
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static __inline uint32_t prvDisableInterrupt( void )
|
||||
{
|
||||
uint32_t prev_state;
|
||||
|
||||
__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
|
||||
return prev_state;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Setup a timer for a regular tick. This function uses the RTOS timer.
|
||||
* The function is declared weak so an application writer can use a different
|
||||
* timer by redefining this implementation. If a different timer is used then
|
||||
* configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
|
||||
* ensure the RTOS provided tick interrupt handler is installed on the correct
|
||||
* vector number.
|
||||
*/
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
/* MEC14xx RTOS Timer whose input clock is 32KHz. */
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
|
||||
configASSERT( ulPreload != 0UL );
|
||||
|
||||
/* Configure the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0ul;
|
||||
portMMCR_RTMR_PRELOAD = ulPreload;
|
||||
|
||||
/* Configure interrupts from the RTOS timer. */
|
||||
portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
|
||||
/* Enable the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0x0Fu;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
|
||||
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
ulCause = ulPortGetCP0Cause();
|
||||
ulCause |= ( 1ul << 8UL );
|
||||
vPortSetCP0Cause( ulCause );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
prvDisableInterrupt();
|
||||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
||||
{
|
||||
vPortSetCP0Status( uxSavedStatusRegister );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Microchip includes. */
|
||||
#include <xc.h>
|
||||
#include <cp0defs.h>
|
||||
|
||||
#if !defined(__MEC__)
|
||||
#error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
|
||||
#endif
|
||||
|
||||
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#endif
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/* MEC14xx RTOS Timer MMCR's. */
|
||||
#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
|
||||
#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
|
||||
|
||||
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
|
||||
peripheral space. */
|
||||
#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
|
||||
#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
|
||||
|
||||
/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
|
||||
|
||||
/*
|
||||
By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
can override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
behaviour for the specified interrupt vector.
|
||||
3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
handler.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Used to catch tasks that attempt to return from their implementing function.
|
||||
*/
|
||||
static void prvTaskExitError( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
UBaseType_t uxSavedTaskStackPointer = 0;
|
||||
|
||||
/* The stack used by interrupt service routines that cause a context switch. */
|
||||
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static __inline uint32_t prvDisableInterrupt( void )
|
||||
{
|
||||
uint32_t prev_state;
|
||||
|
||||
__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
|
||||
return prev_state;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Setup a timer for a regular tick. This function uses the RTOS timer.
|
||||
* The function is declared weak so an application writer can use a different
|
||||
* timer by redefining this implementation. If a different timer is used then
|
||||
* configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
|
||||
* ensure the RTOS provided tick interrupt handler is installed on the correct
|
||||
* vector number.
|
||||
*/
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
/* MEC14xx RTOS Timer whose input clock is 32KHz. */
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
|
||||
configASSERT( ulPreload != 0UL );
|
||||
|
||||
/* Configure the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0ul;
|
||||
portMMCR_RTMR_PRELOAD = ulPreload;
|
||||
|
||||
/* Configure interrupts from the RTOS timer. */
|
||||
portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
|
||||
/* Enable the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0x0Fu;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
|
||||
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
ulCause = ulPortGetCP0Cause();
|
||||
ulCause |= ( 1ul << 8UL );
|
||||
vPortSetCP0Cause( ulCause );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
prvDisableInterrupt();
|
||||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
||||
{
|
||||
vPortSetCP0Status( uxSavedStatusRegister );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,348 +1,348 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOSConfig.h"
|
||||
#include "ISR_Support.h"
|
||||
|
||||
/* Microchip includes. */
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern vPortIncrementTick
|
||||
.extern xISRStackTop
|
||||
|
||||
PORT_CPP_JTVIC_BASE = 0xBFFFC000
|
||||
PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
|
||||
|
||||
.global vPortStartFirstTask .text
|
||||
.global vPortYieldISR .text
|
||||
.global vPortTickInterruptHandler .text
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/***************************************************************
|
||||
* The following is needed to locate the
|
||||
* vPortTickInterruptHandler function into the correct vector
|
||||
* MEC14xx - This ISR will only be used if HW timers' interrupts
|
||||
* in GIRQ23 are disaggregated.
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
.set micromips
|
||||
|
||||
.section .text, code
|
||||
.ent vPortTickInterruptHandler
|
||||
|
||||
#if configTIMERS_DISAGGREGATED_ISRS == 0
|
||||
|
||||
.globl girq23_isr
|
||||
|
||||
girq23_isr:
|
||||
vPortTickInterruptHandler:
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal girq23_handler
|
||||
nop
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortTickInterruptHandler
|
||||
|
||||
#else
|
||||
|
||||
.globl girq23_b4
|
||||
|
||||
girq23_b4:
|
||||
vPortTickInterruptHandler:
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal vPortIncrementTick
|
||||
nop
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortTickInterruptHandler
|
||||
|
||||
#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.section .text, code
|
||||
.ent vPortStartFirstTask
|
||||
|
||||
vPortStartFirstTask:
|
||||
|
||||
/* Simply restore the context of the highest priority task that has
|
||||
been created so far. */
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortStartFirstTask
|
||||
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* The following is needed to locate the vPortYieldISR function into the correct
|
||||
* vector.
|
||||
***************************************************************/
|
||||
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.section .text, code
|
||||
|
||||
.global vPortYieldISR
|
||||
|
||||
|
||||
#if configCPU_DISAGGREGATED_ISRS == 0
|
||||
.global girq24_isr
|
||||
.ent girq24_isr
|
||||
girq24_isr:
|
||||
la k0, PORT_CPP_JTVIC_BASE
|
||||
lw k0, 0x10C(k0)
|
||||
andi k1, k0, 0x2
|
||||
bgtz k1, vPortYieldISR
|
||||
nop
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal girq24_b_0_2
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end girq24_isr
|
||||
|
||||
#else
|
||||
.global girq24_b1
|
||||
girq24_b1:
|
||||
#endif
|
||||
.ent vPortYieldISR
|
||||
vPortYieldISR:
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
manipulated, and the cause and EPC registers so thier original values
|
||||
are captured. */
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Prepare to re-enable interrupts above the kernel priority. */
|
||||
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
|
||||
ins k1, zero, 18, 1 /* Clear IPL bit 7 */
|
||||
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
|
||||
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
|
||||
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
|
||||
/* Swap to the system stack. This is not conditional on the nesting
|
||||
count as this interrupt is always the lowest priority and therefore
|
||||
the nesting is always 0. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, (sp)
|
||||
|
||||
/* Set the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
addiu s6, zero, 1
|
||||
sw s6, 0(k0)
|
||||
|
||||
/* s6 holds the EPC value, this is saved with the rest of the context
|
||||
after interrupts are enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s7, 48(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
/* s5 and s6 has already been saved. */
|
||||
sw s4, 36(s5)
|
||||
sw s3, 32(s5)
|
||||
sw s2, 28(s5)
|
||||
sw s1, 24(s5)
|
||||
sw s0, 20(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* s7 is used as a scratch register as this should always be saved acro ss
|
||||
nesting interrupts. */
|
||||
mfhi s7
|
||||
sw s7, 12(s5)
|
||||
mflo s7
|
||||
sw s7, 8(s5)
|
||||
|
||||
/* Save the stack pointer to the task. */
|
||||
la s7, pxCurrentTCB
|
||||
lw s7, (s7)
|
||||
sw s5, (s7)
|
||||
|
||||
/* Set the interrupt mask to the max priority that can use the API.
|
||||
The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
|
||||
which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
|
||||
ever raise the IPL value and never lower it. */
|
||||
di
|
||||
ehb
|
||||
mfc0 s7, _CP0_STATUS
|
||||
ins s7, zero, 10, 7
|
||||
ins s7, zero, 18, 1
|
||||
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
|
||||
|
||||
/* This mtc0 re-enables interrupts, but only above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
mtc0 s6, _CP0_STATUS
|
||||
ehb
|
||||
|
||||
/* Clear the software interrupt in the core. */
|
||||
mfc0 s6, _CP0_CAUSE
|
||||
ins s6, zero, 8, 1
|
||||
mtc0 s6, _CP0_CAUSE
|
||||
ehb
|
||||
|
||||
/* Clear the interrupt in the interrupt controller.
|
||||
MEC14xx GIRQ24 Source bit[1] = 1 to clear */
|
||||
la s6, PORT_CCP_JTVIC_GIRQ24_SRC
|
||||
addiu s4, zero, 2
|
||||
sw s4, (s6)
|
||||
jal vTaskSwitchContext
|
||||
nop
|
||||
|
||||
/* Clear the interrupt mask again. The saved status value is still in s7 */
|
||||
mtc0 s7, _CP0_STATUS
|
||||
ehb
|
||||
|
||||
/* Restore the stack pointer from the TCB. */
|
||||
la s0, pxCurrentTCB
|
||||
lw s0, (s0)
|
||||
lw s5, (s0)
|
||||
|
||||
/* Restore the rest of the context. */
|
||||
lw s0, 8(s5)
|
||||
mtlo s0
|
||||
lw s0, 12(s5)
|
||||
mthi s0
|
||||
|
||||
lw $1, 16(s5)
|
||||
lw s0, 20(s5)
|
||||
lw s1, 24(s5)
|
||||
lw s2, 28(s5)
|
||||
lw s3, 32(s5)
|
||||
lw s4, 36(s5)
|
||||
|
||||
/* s5 is loaded later. */
|
||||
lw s6, 44(s5)
|
||||
lw s7, 48(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Set nesting back to zero. As the lowest priority interrupt this
|
||||
interrupt cannot have nested. */
|
||||
la k0, uxInterruptNesting
|
||||
sw zero, 0(k0)
|
||||
|
||||
/* Switch back to use the real stack pointer. */
|
||||
add sp, zero, s5
|
||||
|
||||
/* Restore the real s5 value. */
|
||||
lw s5, 40(sp)
|
||||
|
||||
/* Pop the status and epc values. */
|
||||
lw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
lw k0, portEPC_STACK_LOCATION(sp)
|
||||
|
||||
/* Remove stack frame. */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mtc0 k1, _CP0_STATUS
|
||||
mtc0 k0, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.end vPortYieldISR
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOSConfig.h"
|
||||
#include "ISR_Support.h"
|
||||
|
||||
/* Microchip includes. */
|
||||
#include <xc.h>
|
||||
#include <sys/asm.h>
|
||||
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern vPortIncrementTick
|
||||
.extern xISRStackTop
|
||||
|
||||
PORT_CPP_JTVIC_BASE = 0xBFFFC000
|
||||
PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
|
||||
|
||||
.global vPortStartFirstTask .text
|
||||
.global vPortYieldISR .text
|
||||
.global vPortTickInterruptHandler .text
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/***************************************************************
|
||||
* The following is needed to locate the
|
||||
* vPortTickInterruptHandler function into the correct vector
|
||||
* MEC14xx - This ISR will only be used if HW timers' interrupts
|
||||
* in GIRQ23 are disaggregated.
|
||||
*
|
||||
***************************************************************/
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
.set micromips
|
||||
|
||||
.section .text, code
|
||||
.ent vPortTickInterruptHandler
|
||||
|
||||
#if configTIMERS_DISAGGREGATED_ISRS == 0
|
||||
|
||||
.globl girq23_isr
|
||||
|
||||
girq23_isr:
|
||||
vPortTickInterruptHandler:
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal girq23_handler
|
||||
nop
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortTickInterruptHandler
|
||||
|
||||
#else
|
||||
|
||||
.globl girq23_b4
|
||||
|
||||
girq23_b4:
|
||||
vPortTickInterruptHandler:
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal vPortIncrementTick
|
||||
nop
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortTickInterruptHandler
|
||||
|
||||
#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.section .text, code
|
||||
.ent vPortStartFirstTask
|
||||
|
||||
vPortStartFirstTask:
|
||||
|
||||
/* Simply restore the context of the highest priority task that has
|
||||
been created so far. */
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end vPortStartFirstTask
|
||||
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/***************************************************************
|
||||
* The following is needed to locate the vPortYieldISR function into the correct
|
||||
* vector.
|
||||
***************************************************************/
|
||||
|
||||
.set micromips
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.section .text, code
|
||||
|
||||
.global vPortYieldISR
|
||||
|
||||
|
||||
#if configCPU_DISAGGREGATED_ISRS == 0
|
||||
.global girq24_isr
|
||||
.ent girq24_isr
|
||||
girq24_isr:
|
||||
la k0, PORT_CPP_JTVIC_BASE
|
||||
lw k0, 0x10C(k0)
|
||||
andi k1, k0, 0x2
|
||||
bgtz k1, vPortYieldISR
|
||||
nop
|
||||
|
||||
portSAVE_CONTEXT
|
||||
|
||||
jal girq24_b_0_2
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.end girq24_isr
|
||||
|
||||
#else
|
||||
.global girq24_b1
|
||||
girq24_b1:
|
||||
#endif
|
||||
.ent vPortYieldISR
|
||||
vPortYieldISR:
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
manipulated, and the cause and EPC registers so thier original values
|
||||
are captured. */
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Prepare to re-enable interrupts above the kernel priority. */
|
||||
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
|
||||
ins k1, zero, 18, 1 /* Clear IPL bit 7 */
|
||||
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
|
||||
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
|
||||
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
|
||||
/* Swap to the system stack. This is not conditional on the nesting
|
||||
count as this interrupt is always the lowest priority and therefore
|
||||
the nesting is always 0. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, (sp)
|
||||
|
||||
/* Set the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
addiu s6, zero, 1
|
||||
sw s6, 0(k0)
|
||||
|
||||
/* s6 holds the EPC value, this is saved with the rest of the context
|
||||
after interrupts are enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s7, 48(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
/* s5 and s6 has already been saved. */
|
||||
sw s4, 36(s5)
|
||||
sw s3, 32(s5)
|
||||
sw s2, 28(s5)
|
||||
sw s1, 24(s5)
|
||||
sw s0, 20(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* s7 is used as a scratch register as this should always be saved acro ss
|
||||
nesting interrupts. */
|
||||
mfhi s7
|
||||
sw s7, 12(s5)
|
||||
mflo s7
|
||||
sw s7, 8(s5)
|
||||
|
||||
/* Save the stack pointer to the task. */
|
||||
la s7, pxCurrentTCB
|
||||
lw s7, (s7)
|
||||
sw s5, (s7)
|
||||
|
||||
/* Set the interrupt mask to the max priority that can use the API.
|
||||
The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
|
||||
which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
|
||||
ever raise the IPL value and never lower it. */
|
||||
di
|
||||
ehb
|
||||
mfc0 s7, _CP0_STATUS
|
||||
ins s7, zero, 10, 7
|
||||
ins s7, zero, 18, 1
|
||||
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
|
||||
|
||||
/* This mtc0 re-enables interrupts, but only above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
mtc0 s6, _CP0_STATUS
|
||||
ehb
|
||||
|
||||
/* Clear the software interrupt in the core. */
|
||||
mfc0 s6, _CP0_CAUSE
|
||||
ins s6, zero, 8, 1
|
||||
mtc0 s6, _CP0_CAUSE
|
||||
ehb
|
||||
|
||||
/* Clear the interrupt in the interrupt controller.
|
||||
MEC14xx GIRQ24 Source bit[1] = 1 to clear */
|
||||
la s6, PORT_CCP_JTVIC_GIRQ24_SRC
|
||||
addiu s4, zero, 2
|
||||
sw s4, (s6)
|
||||
jal vTaskSwitchContext
|
||||
nop
|
||||
|
||||
/* Clear the interrupt mask again. The saved status value is still in s7 */
|
||||
mtc0 s7, _CP0_STATUS
|
||||
ehb
|
||||
|
||||
/* Restore the stack pointer from the TCB. */
|
||||
la s0, pxCurrentTCB
|
||||
lw s0, (s0)
|
||||
lw s5, (s0)
|
||||
|
||||
/* Restore the rest of the context. */
|
||||
lw s0, 8(s5)
|
||||
mtlo s0
|
||||
lw s0, 12(s5)
|
||||
mthi s0
|
||||
|
||||
lw $1, 16(s5)
|
||||
lw s0, 20(s5)
|
||||
lw s1, 24(s5)
|
||||
lw s2, 28(s5)
|
||||
lw s3, 32(s5)
|
||||
lw s4, 36(s5)
|
||||
|
||||
/* s5 is loaded later. */
|
||||
lw s6, 44(s5)
|
||||
lw s7, 48(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Set nesting back to zero. As the lowest priority interrupt this
|
||||
interrupt cannot have nested. */
|
||||
la k0, uxInterruptNesting
|
||||
sw zero, 0(k0)
|
||||
|
||||
/* Switch back to use the real stack pointer. */
|
||||
add sp, zero, s5
|
||||
|
||||
/* Restore the real s5 value. */
|
||||
lw s5, 40(sp)
|
||||
|
||||
/* Pop the status and epc values. */
|
||||
lw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
lw k0, portEPC_STACK_LOCATION(sp)
|
||||
|
||||
/* Remove stack frame. */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mtc0 k1, _CP0_STATUS
|
||||
mtc0 k0, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.end vPortYieldISR
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,252 +1,252 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* Interrupt priority conversion */
|
||||
#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
|
||||
#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Status( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Status( uint32_t new_status)
|
||||
{
|
||||
( void ) new_status;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_status ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Cause( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Cause( uint32_t new_cause )
|
||||
{
|
||||
( void ) new_cause;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_cause ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* Interrupt priority conversion */
|
||||
#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
|
||||
#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Status( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Status( uint32_t new_status)
|
||||
{
|
||||
( void ) new_status;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_status ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Cause( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Cause( uint32_t new_cause )
|
||||
{
|
||||
( void ) new_cause;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_cause ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue