mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-05 13:53:50 -04:00
Feature: SMP (#278)
* Add XMOS XCore ports Some minor modifications are also made to the kernel to support the XCore compiler's automatic stack size calculation. * Update kernel to support SMP The XMOS XCore ports are also updated to support SMP. * Fix compiler warnings in xcore ports The port set and clear interrupt mask from ISR macros were removed from the ports so that the default macros found in FreeRTOS.h are used instead. The default macros do not result in warnings when they are used. * Remove inline function from timers.h Inline function converted to macro. This should now build when optimizations are off and inlining is disabled. * Fix compiler warnings in xcore ports and tasks.c * fixed documentation for ulTaskNotifyTake() and ulTaskNotifyTakeIndexed() * spelling fixes for tasks.c Co-authored-by: Michael Bruno <mikeb@xmos.com>
This commit is contained in:
Joseph Julicher
GitHub
parent
cafae476e4
commit
989bc332b2
509 changed files with 176869 additions and 174380 deletions
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@ -1,173 +1,173 @@
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* System Includes. */
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#include <tc1782.h>
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#include <machine/intrinsics.h>
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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||||
*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#endif
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/*---------------------------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 4
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#define portNOP() __asm volatile( " nop " )
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#define portCRITICAL_NESTING_IN_TCB 1
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#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
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/*---------------------------------------------------------------------------*/
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typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
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/* Define away the instruction from the Restore Context Macro. */
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#define portPRIVILEGE_BIT 0x0UL
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#define portCCPN_MASK ( 0x000000FFUL )
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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/*---------------------------------------------------------------------------*/
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/* CSA Manipulation. */
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#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
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#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
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/*---------------------------------------------------------------------------*/
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#define portYIELD() _syscall( 0 )
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/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
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#define portSYSCALL_TASK_YIELD 0
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#define portSYSCALL_RAISE_PRIORITY 1
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/*---------------------------------------------------------------------------*/
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/* Critical section management. */
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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#define portDISABLE_INTERRUPTS() { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Clear ICR.CCPN to allow all interrupt priorities. */
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#define portENABLE_INTERRUPTS() { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set ICR.CCPN to uxSavedMaskValue. */
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
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extern uint32_t uxPortSetInterruptMaskFromISR( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
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/* Pend a priority 1 interrupt, which will take care of the context switch. */
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#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); }
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/*---------------------------------------------------------------------------*/
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/* Task function macros as described on the FreeRTOS.org WEB site. */
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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/*---------------------------------------------------------------------------*/
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/*
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* Port specific clean up macro required to free the CSAs that were consumed by
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* a task that has since been deleted.
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*/
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void vPortReclaimCSA( uint32_t *pxTCB );
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#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
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#ifdef __cplusplus
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}
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#endif
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#endif /* PORTMACRO_H */
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* System Includes. */
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#include <tc1782.h>
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#include <machine/intrinsics.h>
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#endif
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/*---------------------------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 4
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#define portNOP() __asm volatile( " nop " )
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#define portCRITICAL_NESTING_IN_TCB 1
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#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
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/*---------------------------------------------------------------------------*/
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typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
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/* Define away the instruction from the Restore Context Macro. */
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#define portPRIVILEGE_BIT 0x0UL
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#define portCCPN_MASK ( 0x000000FFUL )
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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/*---------------------------------------------------------------------------*/
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/* CSA Manipulation. */
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#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
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#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
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/*---------------------------------------------------------------------------*/
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#define portYIELD() _syscall( 0 )
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/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
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#define portSYSCALL_TASK_YIELD 0
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#define portSYSCALL_RAISE_PRIORITY 1
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/*---------------------------------------------------------------------------*/
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/* Critical section management. */
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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#define portDISABLE_INTERRUPTS() { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Clear ICR.CCPN to allow all interrupt priorities. */
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#define portENABLE_INTERRUPTS() { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set ICR.CCPN to uxSavedMaskValue. */
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
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uint32_t ulICR; \
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_disable(); \
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ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
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extern uint32_t uxPortSetInterruptMaskFromISR( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
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/* Pend a priority 1 interrupt, which will take care of the context switch. */
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#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); }
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|
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/*---------------------------------------------------------------------------*/
|
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|
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/* Task function macros as described on the FreeRTOS.org WEB site. */
|
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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/*---------------------------------------------------------------------------*/
|
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|
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/*
|
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* Port specific clean up macro required to free the CSAs that were consumed by
|
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* a task that has since been deleted.
|
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*/
|
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void vPortReclaimCSA( uint32_t *pxTCB );
|
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#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
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|
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#ifdef __cplusplus
|
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}
|
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#endif
|
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|
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#endif /* PORTMACRO_H */
|
||||
|
|
|
|||
|
|
@ -1,281 +1,281 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Machine includes */
|
||||
#include <tc1782.h>
|
||||
#include <machine/intrinsics.h>
|
||||
#include <machine/cint.h>
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* This reference is required by the Save/Restore Context Macros.
|
||||
*/
|
||||
extern volatile uint32_t *pxCurrentTCB;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* This file contains base definitions for all of the possible traps in the system.
|
||||
* It is suggested to provide implementations for all of the traps but for
|
||||
* the time being they simply trigger a DEBUG instruction so that it is easy
|
||||
* to see what caused a particular trap.
|
||||
*
|
||||
* Trap Class 6, the SYSCALL, is used exclusively by the operating system.
|
||||
*/
|
||||
|
||||
/* The Trap Classes. */
|
||||
#define portMMU_TRAP 0
|
||||
#define portIPT_TRAP 1
|
||||
#define portIE_TRAP 2
|
||||
#define portCM_TRAP 3
|
||||
#define portSBP_TRAP 4
|
||||
#define portASSERT_TRAP 5
|
||||
#define portNMI_TRAP 7
|
||||
|
||||
/* MMU Trap Identifications. */
|
||||
#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
|
||||
#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
|
||||
|
||||
/* Internal Protection Trap Identifications. */
|
||||
#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_READ 2
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
|
||||
|
||||
/* Instruction Error Trap Identifications. */
|
||||
#define portTIN_IE_ILLEGAL_OPCODE 1
|
||||
#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
|
||||
#define portTIN_IE_INVALID_OPERAND 3
|
||||
#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
|
||||
#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
|
||||
|
||||
/* Context Management Trap Identifications. */
|
||||
#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
|
||||
#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
|
||||
#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
|
||||
#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
|
||||
#define portTIN_CM_CALL_STACK_UNDERFLOW 5
|
||||
#define portTIN_CM_CONTEXT_TYPE 6
|
||||
#define portTIN_CM_NESTING_ERROR 7
|
||||
|
||||
/* System Bus and Peripherals Trap Identifications. */
|
||||
#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
|
||||
#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
|
||||
#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
|
||||
#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
|
||||
#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
|
||||
#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
|
||||
|
||||
/* Assertion Trap Identifications. */
|
||||
#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
|
||||
#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
|
||||
|
||||
/* Non-maskable Interrupt Trap Identifications. */
|
||||
#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vTrapInstallHandlers( void )
|
||||
{
|
||||
if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vMMUTrap( int iTrapIdentification )
|
||||
{
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
|
||||
case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vInternalProtectionTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_IPT_PRIVILIGED_INSTRUCTION:
|
||||
/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_READ:
|
||||
/* Load word using invalid address. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_WRITE:
|
||||
/* Store Word using invalid address. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
|
||||
/* PC jumped to an address outside of the valid range. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
|
||||
/* Access to a peripheral denied at current execution level. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
|
||||
/* NULL Pointer. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
|
||||
/* Tried to modify a global address pointer register. */
|
||||
|
||||
default:
|
||||
|
||||
pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vInstructionErrorTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_IE_ILLEGAL_OPCODE:
|
||||
case portTIN_IE_UNIMPLEMENTED_OPCODE:
|
||||
case portTIN_IE_INVALID_OPERAND:
|
||||
case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
|
||||
case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vContextManagementTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
|
||||
case portTIN_CM_CALL_DEPTH_OVERFLOW:
|
||||
case portTIN_CM_CALL_DEPTH_UNDEFLOW:
|
||||
case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
|
||||
case portTIN_CM_CALL_STACK_UNDERFLOW:
|
||||
case portTIN_CM_CONTEXT_TYPE:
|
||||
case portTIN_CM_NESTING_ERROR:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
|
||||
case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vAssertionTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
|
||||
case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vNonMaskableInterruptTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_NMI_NON_MASKABLE_INTERRUPT:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Machine includes */
|
||||
#include <tc1782.h>
|
||||
#include <machine/intrinsics.h>
|
||||
#include <machine/cint.h>
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* This reference is required by the Save/Restore Context Macros.
|
||||
*/
|
||||
extern volatile uint32_t *pxCurrentTCB;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* This file contains base definitions for all of the possible traps in the system.
|
||||
* It is suggested to provide implementations for all of the traps but for
|
||||
* the time being they simply trigger a DEBUG instruction so that it is easy
|
||||
* to see what caused a particular trap.
|
||||
*
|
||||
* Trap Class 6, the SYSCALL, is used exclusively by the operating system.
|
||||
*/
|
||||
|
||||
/* The Trap Classes. */
|
||||
#define portMMU_TRAP 0
|
||||
#define portIPT_TRAP 1
|
||||
#define portIE_TRAP 2
|
||||
#define portCM_TRAP 3
|
||||
#define portSBP_TRAP 4
|
||||
#define portASSERT_TRAP 5
|
||||
#define portNMI_TRAP 7
|
||||
|
||||
/* MMU Trap Identifications. */
|
||||
#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
|
||||
#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
|
||||
|
||||
/* Internal Protection Trap Identifications. */
|
||||
#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_READ 2
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
|
||||
#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
|
||||
|
||||
/* Instruction Error Trap Identifications. */
|
||||
#define portTIN_IE_ILLEGAL_OPCODE 1
|
||||
#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
|
||||
#define portTIN_IE_INVALID_OPERAND 3
|
||||
#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
|
||||
#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
|
||||
|
||||
/* Context Management Trap Identifications. */
|
||||
#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
|
||||
#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
|
||||
#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
|
||||
#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
|
||||
#define portTIN_CM_CALL_STACK_UNDERFLOW 5
|
||||
#define portTIN_CM_CONTEXT_TYPE 6
|
||||
#define portTIN_CM_NESTING_ERROR 7
|
||||
|
||||
/* System Bus and Peripherals Trap Identifications. */
|
||||
#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
|
||||
#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
|
||||
#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
|
||||
#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
|
||||
#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
|
||||
#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
|
||||
|
||||
/* Assertion Trap Identifications. */
|
||||
#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
|
||||
#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
|
||||
|
||||
/* Non-maskable Interrupt Trap Identifications. */
|
||||
#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vTrapInstallHandlers( void )
|
||||
{
|
||||
if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
|
||||
if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
|
||||
{
|
||||
_debug();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vMMUTrap( int iTrapIdentification )
|
||||
{
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
|
||||
case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vInternalProtectionTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_IPT_PRIVILIGED_INSTRUCTION:
|
||||
/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_READ:
|
||||
/* Load word using invalid address. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_WRITE:
|
||||
/* Store Word using invalid address. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
|
||||
/* PC jumped to an address outside of the valid range. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
|
||||
/* Access to a peripheral denied at current execution level. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
|
||||
/* NULL Pointer. */
|
||||
|
||||
case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
|
||||
/* Tried to modify a global address pointer register. */
|
||||
|
||||
default:
|
||||
|
||||
pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vInstructionErrorTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_IE_ILLEGAL_OPCODE:
|
||||
case portTIN_IE_UNIMPLEMENTED_OPCODE:
|
||||
case portTIN_IE_INVALID_OPERAND:
|
||||
case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
|
||||
case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vContextManagementTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
|
||||
case portTIN_CM_CALL_DEPTH_OVERFLOW:
|
||||
case portTIN_CM_CALL_DEPTH_UNDEFLOW:
|
||||
case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
|
||||
case portTIN_CM_CALL_STACK_UNDERFLOW:
|
||||
case portTIN_CM_CONTEXT_TYPE:
|
||||
case portTIN_CM_NESTING_ERROR:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
|
||||
case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
|
||||
case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vAssertionTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
|
||||
case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
void vNonMaskableInterruptTrap( int iTrapIdentification )
|
||||
{
|
||||
/* Deliberate fall through to default. */
|
||||
switch( iTrapIdentification )
|
||||
{
|
||||
case portTIN_NMI_NON_MASKABLE_INTERRUPT:
|
||||
default:
|
||||
_debug();
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue