Merge branch 'main' into ARM_CRx_MPU

This commit is contained in:
Soren Ptak 2024-01-03 11:07:48 -05:00 committed by GitHub
commit 96ab824bb9
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 40 additions and 13 deletions

View file

@ -698,6 +698,7 @@ TXUBR
TXVC TXVC
TXVDIS TXVDIS
UDCP UDCP
uncrustify
UNDADD UNDADD
UNRE UNRE
URAD URAD
@ -713,6 +714,10 @@ VDDCORE
VECT VECT
VECTACTIVE VECTACTIVE
VECTKEY VECTKEY
visualisation
vldmdbeq
vldmia
vldmiaeq
VMSRNE VMSRNE
VPOPNE VPOPNE
VPUSHNE VPUSHNE

View file

@ -509,12 +509,36 @@
#endif /* configUSE_TIMERS */ #endif /* configUSE_TIMERS */
#ifndef portHAS_NESTED_INTERRUPTS
#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) && defined( portCLEAR_INTERRUPT_MASK_FROM_ISR )
#define portHAS_NESTED_INTERRUPTS 1
#else
#define portHAS_NESTED_INTERRUPTS 0
#endif
#endif
#ifndef portSET_INTERRUPT_MASK_FROM_ISR #ifndef portSET_INTERRUPT_MASK_FROM_ISR
#define portSET_INTERRUPT_MASK_FROM_ISR() 0 #if ( portHAS_NESTED_INTERRUPTS == 1 )
#error portSET_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
#else
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#endif
#else
#if ( portHAS_NESTED_INTERRUPTS == 0 )
#error portSET_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
#endif
#endif #endif
#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR #ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue ) #if ( portHAS_NESTED_INTERRUPTS == 1 )
#error portCLEAR_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
#else
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue )
#endif
#else
#if ( portHAS_NESTED_INTERRUPTS == 0 )
#error portCLEAR_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
#endif
#endif #endif
#ifndef portCLEAN_UP_TCB #ifndef portCLEAN_UP_TCB

View file

@ -33,6 +33,14 @@
* This file implements atomic functions by disabling interrupts globally. * This file implements atomic functions by disabling interrupts globally.
* Implementations with architecture specific atomic instructions can be * Implementations with architecture specific atomic instructions can be
* provided under each compiler directory. * provided under each compiler directory.
*
* The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
* can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
* support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
* atomic interface must not be used in ISRs on FreeRTOS ports that do not
* support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
* because ISRs on these ports cannot be interrupted and therefore, do not need
* atomics in ISRs.
*/ */
#ifndef ATOMIC_H #ifndef ATOMIC_H
@ -59,7 +67,7 @@
* ATOMIC_ENTER_CRITICAL(). * ATOMIC_ENTER_CRITICAL().
* *
*/ */
#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) #if ( portHAS_NESTED_INTERRUPTS == 1 )
/* Nested interrupt scheme is supported in this port. */ /* Nested interrupt scheme is supported in this port. */
#define ATOMIC_ENTER_CRITICAL() \ #define ATOMIC_ENTER_CRITICAL() \

View file

@ -81,7 +81,6 @@ add_library(freertos_kernel_port STATIC
# ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>: $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:
ThirdParty/GCC/RP2040/idle_task_static_memory.c
ThirdParty/GCC/RP2040/port.c> ThirdParty/GCC/RP2040/port.c>
# ARMv7-M ports for GCC # ARMv7-M ports for GCC

View file

@ -111,9 +111,6 @@ extern void vTaskSwitchContext( void );
/* Critical section management. */ /* Critical section management. */
#define portCRITICAL_NESTING_IN_TCB 0 #define portCRITICAL_NESTING_IN_TCB 0
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
#define portDISABLE_INTERRUPTS() __asm volatile ( "csrc mstatus, 8" ) #define portDISABLE_INTERRUPTS() __asm volatile ( "csrc mstatus, 8" )
#define portENABLE_INTERRUPTS() __asm volatile ( "csrs mstatus, 8" ) #define portENABLE_INTERRUPTS() __asm volatile ( "csrs mstatus, 8" )

View file

@ -113,9 +113,6 @@ extern void vTaskSwitchContext( void );
/* Critical section management. */ /* Critical section management. */
#define portCRITICAL_NESTING_IN_TCB 0 #define portCRITICAL_NESTING_IN_TCB 0
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
#define portDISABLE_INTERRUPTS() __disable_interrupt() #define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt() #define portENABLE_INTERRUPTS() __enable_interrupt()

View file

@ -139,9 +139,6 @@
#define portSET_INTERRUPT_MASK() rtos_interrupt_mask_all() #define portSET_INTERRUPT_MASK() rtos_interrupt_mask_all()
#define portCLEAR_INTERRUPT_MASK( ulState ) rtos_interrupt_mask_set( ulState ) #define portCLEAR_INTERRUPT_MASK( ulState ) rtos_interrupt_mask_set( ulState )
#define portSET_INTERRUPT_MASK_FROM_ISR() ( 0 )
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( ( void ) x )
/* /*
* Will enable interrupts if ulState is non-zero. * Will enable interrupts if ulState is non-zero.
*/ */