mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-01 11:53:53 -04:00
Updated ESP32 port-layer to ESP-IDF v4.4.2 (#572)
* Xtensa_ESP32: Added esp-idf v4.4.2 specific changes * Xtensa_ESP32: Updated SPDX license identifiers
This commit is contained in:
Laukik Hase
GitHub
parent
195a351ec7
commit
963abe6c48
15 changed files with 854 additions and 1096 deletions
134
portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
vendored
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134
portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
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@ -0,0 +1,134 @@
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/*
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* SPDX-FileCopyrightText: 2022 Amazon.com, Inc. or its affiliates
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software. If you wish to use our Amazon
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* FreeRTOS name, please do so in a fair use way that does not cause confusion.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_XTENSA_H
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#define FREERTOS_CONFIG_XTENSA_H
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#include "sdkconfig.h"
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/* enable use of optimized task selection by the scheduler */
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#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION)
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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#endif
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#define XT_USE_THREAD_SAFE_CLIB 0
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#undef XT_USE_SWPRI
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#if CONFIG_FREERTOS_CORETIMER_0
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#define XT_TIMER_INDEX 0
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#elif CONFIG_FREERTOS_CORETIMER_1
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#define XT_TIMER_INDEX 1
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#endif
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#ifndef __ASSEMBLER__
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/**
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* This function is defined to provide a deprecation warning whenever
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* XT_CLOCK_FREQ macro is used.
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* Update the code to use esp_clk_cpu_freq function instead.
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* @return current CPU clock frequency, in Hz
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*/
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int xt_clock_freq(void) __attribute__((deprecated));
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#define XT_CLOCK_FREQ (xt_clock_freq())
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#endif // __ASSEMBLER__
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/* Required for configuration-dependent settings */
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#include <xtensa_config.h>
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/* configASSERT behaviour */
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#ifndef __ASSEMBLER__
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#include <assert.h>
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#include "esp_rom_sys.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#endif
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#endif // __ASSEMBLER__
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// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro
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// configASSERT_DEFINED remains unset (meaning some warnings are avoided)
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#ifdef configASSERT
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#undef configASSERT
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#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
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#define configASSERT(a) if (unlikely(!(a))) { \
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esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
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__FUNCTION__); \
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}
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#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT)
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#define configASSERT(a) assert(a)
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#endif
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#endif
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#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
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#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
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#else
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#define UNTESTED_FUNCTION()
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#endif
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#define configXT_BOARD 1 /* Board mode */
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#define configXT_SIMULATOR 0
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/* The maximum interrupt priority from which FreeRTOS.org API functions can
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be called. Only API functions that end in ...FromISR() can be used within
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interrupts. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL
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/* Stack alignment, architecture specifc. Must be a power of two. */
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#define configSTACK_ALIGNMENT 16
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/* The Xtensa port uses a separate interrupt stack. Adjust the stack size
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* to suit the needs of your specific application.
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* Size needs to be aligned to the stack increment, since the location of
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* the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE.
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*/
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#ifndef configISR_STACK_SIZE
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#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1)))
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#endif
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#ifndef __ASSEMBLER__
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#if CONFIG_APPTRACE_SV_ENABLE
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extern uint32_t port_switch_flag[];
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#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_])
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#else
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#define os_task_switch_is_pended(_cpu_) (false)
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#endif
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#endif
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#endif // FREERTOS_CONFIG_XTENSA_H
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20
portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h
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20
portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h
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@ -0,0 +1,20 @@
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/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Set up the SysTick interrupt
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*/
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void vPortSetupTimer(void);
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#ifdef __cplusplus
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}
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#endif
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@ -74,12 +74,20 @@
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#include <xtensa/config/core.h>
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#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
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#include <xtensa/xtruntime.h>
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#include "soc/spinlock.h"
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#include "esp_timer.h" /* required for FreeRTOS run time stats */
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#include "esp_system.h"
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#include "esp_idf_version.h"
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#include "esp_heap_caps.h"
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/* TODO: Resolve build warnings generated due to this header inclusion */
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#include "hal/cpu_hal.h"
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#include <esp_heap_caps.h>
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/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
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#include <limits.h>
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#include <xtensa/xtensa_api.h>
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#include "soc/cpu.h"
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#include "soc/soc_memory_layout.h"
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#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
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#include "soc/compare_set.h"
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@ -127,54 +135,12 @@
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#include "esp_attr.h"
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/* "mux" data structure (spinlock) */
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typedef struct
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{
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/* owner field values:
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* 0 - Uninitialized (invalid)
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* portMUX_FREE_VAL - Mux is free, can be locked by either CPU
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* CORE_ID_REGVAL_PRO / CORE_ID_REGVAL_APP - Mux is locked to the particular core
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*
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* Any value other than portMUX_FREE_VAL, CORE_ID_REGVAL_PRO, CORE_ID_REGVAL_APP indicates corruption
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*/
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uint32_t owner;
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/* count field:
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* If mux is unlocked, count should be zero.
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* If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
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*/
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uint32_t count;
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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const char * lastLockedFn;
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int lastLockedLine;
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#endif
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} portMUX_TYPE;
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#define portMUX_FREE_VAL 0xB33FFFFF
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/* Special constants for vPortCPUAcquireMutexTimeout() */
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#define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */
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#define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */
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/* Keep this in sync with the portMUX_TYPE struct definition please. */
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#ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
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#define portMUX_INITIALIZER_UNLOCKED \
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{ \
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.owner = portMUX_FREE_VAL, \
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.count = 0, \
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}
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#else
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#define portMUX_INITIALIZER_UNLOCKED \
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{ \
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.owner = portMUX_FREE_VAL, \
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.count = 0, \
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.lastLockedFn = "(never locked)", \
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.lastLockedLine = -1 \
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}
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#endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */
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#define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
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void vPortAssertIfInISR();
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typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */
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#define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */
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#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */
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#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
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#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
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#define portMUX_INITIALIZE(mux) spinlock_initialize(mux) /*< Initialize a spinlock to its unlocked state */
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#define portCRITICAL_NESTING_IN_TCB 1
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@ -200,7 +166,7 @@
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* This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
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* will break this scheme.
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*
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* Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning
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* Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vPortEnterCritical, meaning
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* that either function can be called both from ISR as well as task context. This is not standard FreeRTOS
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* behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
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*/
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@ -255,6 +221,8 @@
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} \
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} while( 0 )
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#define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
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void vPortAssertIfInISR(void);
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/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
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/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
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/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */
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/* They can be called from interrupts too. */
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/* WARNING: Only applies to current CPU. See notes above. */
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static inline unsigned portENTER_CRITICAL_NESTED()
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static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void )
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{
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unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
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UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
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portbenchmarkINTERRUPT_DISABLE();
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return state;
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return prev_int_level;
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}
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static inline void __attribute__( ( always_inline ) ) vPortClearInterruptMaskFromISR( UBaseType_t prev_level )
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{
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portbenchmarkINTERRUPT_RESTORE( prev_level );
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XTOS_RESTORE_JUST_INTLEVEL( prev_level );
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}
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#define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
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/* These FreeRTOS versions are similar to the nested versions above */
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#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state )
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#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( prev_level ) vPortClearInterruptMaskFromISR( prev_level )
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/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
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/*the stack memory to always be internal. */
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@ -352,7 +324,7 @@
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#else
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static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
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{
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#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
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#if defined(CONFIG_SPIRAM)
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compare_and_set_extram(addr, compare, set);
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#endif
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}
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@ -374,18 +346,47 @@
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#ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
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/* Coarse resolution time (us) */
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#define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time()
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#define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t )esp_timer_get_time(); } while( 0 )
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#endif
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/* Kernel utilities. */
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void vPortYield( void );
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void vPortEvaluateYieldFromISR( int argc, ... );
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void _frxt_setup_switch( void );
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#define portYIELD() vPortYield()
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#define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); }
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/* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with,
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* or without arguments. The macro counts only 0 or 1 arguments.
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*
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* In the future, we want to switch to C++20. We also want to become compatible with clang.
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* Hence, we provide two versions of the following macros which are using variadic arguments.
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* The first one is using the GNU extension ##__VA_ARGS__. The second one is using the C++20 feature __VA_OPT__(,).
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* This allows users to compile their code with standard C++20 enabled instead of the GNU extension.
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* Below C++20, we haven't found any good alternative to using ##__VA_ARGS__.
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*/
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#if defined( __cplusplus ) && ( __cplusplus > 201703L )
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#define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(,) __VA_ARGS__, 1 , 0 )
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#else
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#define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0, ##__VA_ARGS__, 1, 0 )
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#endif
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#define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count
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static inline uint32_t xPortGetCoreID();
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_Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" );
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_Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" );
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#define portYIELD() vPortYield()
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/* The macro below could be used when passing a single argument, or without any argument,
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* it was developed to support both usages of portYIELD inside of an ISR. Any other usage form
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* might result in undesired behaviour
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*/
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#if defined( __cplusplus ) && ( __cplusplus > 201703L )
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#define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__( , ) __VA_ARGS__ )
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#else
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#define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ##__VA_ARGS__ )
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#endif
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static inline BaseType_t xPortGetCoreID();
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/*-----------------------------------------------------------*/
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@ -428,10 +429,11 @@
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#endif
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void vApplicationSleep( TickType_t xExpectedIdleTime );
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void vPortSetStackWatchpoint( void* pxStackStart );
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#define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
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void _xt_coproc_release( volatile void * coproc_sa_base );
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/*-----------------------------------------------------------*/
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#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
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@ -458,10 +460,6 @@
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/*-----------------------------------------------------------*/
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void _xt_coproc_release( volatile void * coproc_sa_base );
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/*
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* Map to the memory management routines required for the port.
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*
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@ -520,20 +518,31 @@
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#endif
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/* Multi-core: get current core ID */
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static inline uint32_t IRAM_ATTR xPortGetCoreID()
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static inline BaseType_t IRAM_ATTR xPortGetCoreID()
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{
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int id;
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asm (
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"rsr.prid %0\n"
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" extui %0,%0,13,1"
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: "=r" ( id ) );
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return id;
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return ( uint32_t )cpu_hal_get_core_id();
|
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}
|
||||
|
||||
/* Get tick rate per second */
|
||||
uint32_t xPortGetTickRateHz( void );
|
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|
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static inline bool IRAM_ATTR xPortCanYield(void)
|
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{
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uint32_t ps_reg = 0;
|
||||
|
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//Get the current value of PS (processor status) register
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RSR(PS, ps_reg);
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||||
|
||||
/*
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||||
* intlevel = (ps_reg & 0xf);
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||||
* excm = (ps_reg >> 4) & 0x1;
|
||||
* CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
|
||||
* However, just return true, only intlevel is zero.
|
||||
*/
|
||||
|
||||
return ((ps_reg & PS_INTLEVEL_MASK) == 0);
|
||||
}
|
||||
|
||||
/* porttrace */
|
||||
#if configUSE_TRACE_FACILITY_2
|
||||
#include "porttrace.h"
|
||||
|
|
|
|||
|
|
@ -27,113 +27,4 @@
|
|||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* Xtensa-specific API for RTOS ports.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __XTENSA_API_H__
|
||||
#define __XTENSA_API_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#include "xtensa_context.h"
|
||||
|
||||
|
||||
/* Typedef for C-callable interrupt handler function */
|
||||
typedef void (* xt_handler)( void * );
|
||||
|
||||
/* Typedef for C-callable exception handler function */
|
||||
typedef void (* xt_exc_handler)( XtExcFrame * );
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to set a handler for the specified exception. The handler
|
||||
* will be installed on the core that calls this function.
|
||||
*
|
||||
* n - Exception number (type)
|
||||
* f - Handler function address, NULL to uninstall handler.
|
||||
*
|
||||
* The handler will be passed a pointer to the exception frame, which is created
|
||||
* on the stack of the thread that caused the exception.
|
||||
*
|
||||
* If the handler returns, the thread context will be restored and the faulting
|
||||
* instruction will be retried. Any values in the exception frame that are
|
||||
* modified by the handler will be restored as part of the context. For details
|
||||
* of the exception frame structure see xtensa_context.h.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
extern xt_exc_handler xt_set_exception_handler( int n,
|
||||
xt_exc_handler f );
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to set a handler for the specified interrupt. The handler
|
||||
* will be installed on the core that calls this function.
|
||||
*
|
||||
* n - Interrupt number.
|
||||
* f - Handler function address, NULL to uninstall handler.
|
||||
* arg - Argument to be passed to handler.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
extern xt_handler xt_set_interrupt_handler( int n,
|
||||
xt_handler f,
|
||||
void * arg );
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to enable the specified interrupts on the core that runs
|
||||
* this code.
|
||||
*
|
||||
* mask - Bit mask of interrupts to be enabled.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
extern void xt_ints_on( unsigned int mask );
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to disable the specified interrupts on the core that runs
|
||||
* this code.
|
||||
*
|
||||
* mask - Bit mask of interrupts to be disabled.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
extern void xt_ints_off( unsigned int mask );
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to set the specified (s/w) interrupt.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void xt_set_intset( unsigned int arg )
|
||||
{
|
||||
xthal_set_intset( arg );
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to clear the specified (s/w or edge-triggered)
|
||||
* interrupt.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void xt_set_intclear( unsigned int arg )
|
||||
{
|
||||
xthal_set_intclear( arg );
|
||||
}
|
||||
|
||||
/*
|
||||
* -------------------------------------------------------------------------------
|
||||
* Call this function to get handler's argument for the specified interrupt.
|
||||
*
|
||||
* n - Interrupt number.
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
extern void * xt_get_interrupt_handler_arg( int n );
|
||||
|
||||
#endif /* __XTENSA_API_H__ */
|
||||
#include <xtensa/xtensa_api.h>
|
||||
|
|
|
|||
|
|
@ -27,373 +27,4 @@
|
|||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
|
||||
XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
|
||||
|
||||
This header contains definitions and macros for use primarily by Xtensa
|
||||
RTOS assembly coded source files. It includes and uses the Xtensa hardware
|
||||
abstraction layer (HAL) to deal with config specifics. It may also be
|
||||
included in C source files.
|
||||
|
||||
!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
|
||||
|
||||
NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef XTENSA_CONTEXT_H
|
||||
#define XTENSA_CONTEXT_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#include <xtensa/coreasm.h>
|
||||
#endif
|
||||
|
||||
#include <xtensa/config/tie.h>
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
#include <xtensa/xtruntime-frames.h>
|
||||
#include <esp_idf_version.h>
|
||||
|
||||
|
||||
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
|
||||
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
Macros that help define structures for both C and assembler.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef STRUCT_BEGIN
|
||||
#undef STRUCT_BEGIN
|
||||
#undef STRUCT_FIELD
|
||||
#undef STRUCT_AFIELD
|
||||
#undef STRUCT_END
|
||||
#endif
|
||||
|
||||
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
|
||||
|
||||
#define STRUCT_BEGIN .pushsection .text; .struct 0
|
||||
#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
|
||||
#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
|
||||
#define STRUCT_END(sname) sname##Size:; .popsection
|
||||
|
||||
#else
|
||||
|
||||
#define STRUCT_BEGIN typedef struct {
|
||||
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
|
||||
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
|
||||
#define STRUCT_END(sname) } sname;
|
||||
|
||||
#endif //_ASMLANGUAGE || __ASSEMBLER__
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
|
||||
|
||||
A stack frame of this structure is allocated for any interrupt or exception.
|
||||
It goes on the current stack. If the RTOS has a system stack for handling
|
||||
interrupts, every thread stack must allow space for just one interrupt stack
|
||||
frame, then nested interrupt stack frames go on the system stack.
|
||||
|
||||
The frame includes basic registers (explicit) and "extra" registers introduced
|
||||
by user TIE or the use of the MAC16 option in the user's Xtensa config.
|
||||
The frame size is minimized by omitting regs not applicable to user's config.
|
||||
|
||||
For Windowed ABI, this stack frame includes the interruptee's base save area,
|
||||
another base save area to manage gcc nested functions, and a little temporary
|
||||
space to help manage the spilling of the register windows.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
STRUCT_BEGIN
|
||||
STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
|
||||
STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
|
||||
STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
|
||||
STRUCT_FIELD (long, 4, XT_STK_A0, a0)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
|
||||
STRUCT_FIELD (long, 4, XT_STK_A2, a2)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A3, a3)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A4, a4)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A5, a5)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A6, a6)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A7, a7)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A8, a8)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A9, a9)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A10, a10)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A11, a11)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A12, a12)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A13, a13)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A14, a14)
|
||||
STRUCT_FIELD (long, 4, XT_STK_A15, a15)
|
||||
STRUCT_FIELD (long, 4, XT_STK_SAR, sar)
|
||||
STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
|
||||
STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
|
||||
#if XCHAL_HAVE_LOOPS
|
||||
STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
|
||||
STRUCT_FIELD (long, 4, XT_STK_LEND, lend)
|
||||
STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
|
||||
#endif
|
||||
#ifndef __XTENSA_CALL0_ABI__
|
||||
/* Temporary space for saving stuff during window spill */
|
||||
STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)
|
||||
STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)
|
||||
STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)
|
||||
#endif
|
||||
#ifdef XT_USE_SWPRI
|
||||
/* Storage for virtual priority mask */
|
||||
STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)
|
||||
#endif
|
||||
#ifdef XT_USE_OVLY
|
||||
/* Storage for overlay state */
|
||||
STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)
|
||||
#endif
|
||||
STRUCT_END(XtExcFrame)
|
||||
|
||||
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
|
||||
#define XT_STK_NEXT1 XtExcFrameSize
|
||||
#else
|
||||
#define XT_STK_NEXT1 sizeof(XtExcFrame)
|
||||
#endif
|
||||
|
||||
/* Allocate extra storage if needed */
|
||||
#if XCHAL_EXTRA_SA_SIZE != 0
|
||||
|
||||
#if XCHAL_EXTRA_SA_ALIGN <= 16
|
||||
#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
|
||||
#else
|
||||
/* If need more alignment than stack, add space for dynamic alignment */
|
||||
#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
|
||||
#endif
|
||||
#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
|
||||
|
||||
#else
|
||||
|
||||
#define XT_STK_NEXT2 XT_STK_NEXT1
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
This is the frame size. Add space for 4 registers (interruptee's base save
|
||||
area) and some space for gcc nested functions if any.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
SOLICITED STACK FRAME FOR A THREAD
|
||||
|
||||
A stack frame of this structure is allocated whenever a thread enters the
|
||||
RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
|
||||
It goes on the current thread's stack.
|
||||
|
||||
The solicited frame only includes registers that are required to be preserved
|
||||
by the callee according to the compiler's ABI conventions, some space to save
|
||||
the return address for returning to the caller, and the caller's PS register.
|
||||
|
||||
For Windowed ABI, this stack frame includes the caller's base save area.
|
||||
|
||||
Note on XT_SOL_EXIT field:
|
||||
It is necessary to distinguish a solicited from an interrupt stack frame.
|
||||
This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
|
||||
always at the same offset (0). It can be written with a code (usually 0)
|
||||
to distinguish a solicted frame from an interrupt frame. An RTOS port may
|
||||
opt to ignore this field if it has another way of distinguishing frames.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
STRUCT_BEGIN
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
|
||||
#else
|
||||
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
|
||||
#endif
|
||||
STRUCT_END(XtSolFrame)
|
||||
|
||||
/* Size of solicited stack frame */
|
||||
#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
CO-PROCESSOR STATE SAVE AREA FOR A THREAD
|
||||
|
||||
The RTOS must provide an area per thread to save the state of co-processors
|
||||
when that thread does not have control. Co-processors are context-switched
|
||||
lazily (on demand) only when a new thread uses a co-processor instruction,
|
||||
otherwise a thread retains ownership of the co-processor even when it loses
|
||||
control of the processor. An Xtensa co-processor exception is triggered when
|
||||
any co-processor instruction is executed by a thread that is not the owner,
|
||||
and the context switch of that co-processor is then peformed by the handler.
|
||||
Ownership represents which thread's state is currently in the co-processor.
|
||||
|
||||
Co-processors may not be used by interrupt or exception handlers. If an
|
||||
co-processor instruction is executed by an interrupt or exception handler,
|
||||
the co-processor exception handler will trigger a kernel panic and freeze.
|
||||
This restriction is introduced to reduce the overhead of saving and restoring
|
||||
co-processor state (which can be quite large) and in particular remove that
|
||||
overhead from interrupt handlers.
|
||||
|
||||
The co-processor state save area may be in any convenient per-thread location
|
||||
such as in the thread control block or above the thread stack area. It need
|
||||
not be in the interrupt stack frame since interrupts don't use co-processors.
|
||||
|
||||
Along with the save area for each co-processor, two bitmasks with flags per
|
||||
co-processor (laid out as in the CPENABLE reg) help manage context-switching
|
||||
co-processors as efficiently as possible:
|
||||
|
||||
XT_CPENABLE
|
||||
The contents of a non-running thread's CPENABLE register.
|
||||
It represents the co-processors owned (and whose state is still needed)
|
||||
by the thread. When a thread is preempted, its CPENABLE is saved here.
|
||||
When a thread solicits a context-swtich, its CPENABLE is cleared - the
|
||||
compiler has saved the (caller-saved) co-proc state if it needs to.
|
||||
When a non-running thread loses ownership of a CP, its bit is cleared.
|
||||
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
|
||||
Avoids co-processor exceptions when no change of ownership is needed.
|
||||
|
||||
XT_CPSTORED
|
||||
A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether the state of each co-processor is saved in the state
|
||||
save area. When a thread enters the kernel, only the state of co-procs
|
||||
still enabled in CPENABLE is saved. When the co-processor exception
|
||||
handler assigns ownership of a co-processor to a thread, it restores
|
||||
the saved state only if this bit is set, and clears this bit.
|
||||
|
||||
XT_CP_CS_ST
|
||||
A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether callee-saved state is saved in the state save area.
|
||||
Callee-saved state is saved by itself on a solicited context switch,
|
||||
and restored when needed by the coprocessor exception handler.
|
||||
Unsolicited switches will cause the entire coprocessor to be saved
|
||||
when necessary.
|
||||
|
||||
XT_CP_ASA
|
||||
Pointer to the aligned save area. Allows it to be aligned more than
|
||||
the overall save area (which might only be stack-aligned or TCB-aligned).
|
||||
Especially relevant for Xtensa cores configured with a very large data
|
||||
path that requires alignment greater than 16 bytes (ABI stack alignment).
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if XCHAL_CP_NUM > 0
|
||||
|
||||
/* Offsets of each coprocessor save area within the 'aligned save area': */
|
||||
#define XT_CP0_SA 0
|
||||
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
|
||||
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
|
||||
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
|
||||
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
|
||||
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
|
||||
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
|
||||
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
|
||||
#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
|
||||
|
||||
/* Offsets within the overall save area: */
|
||||
#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
|
||||
#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
|
||||
#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
|
||||
#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
|
||||
/* Overall size allows for dynamic alignment: */
|
||||
#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
|
||||
#else
|
||||
#define XT_CP_SIZE 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Macro to get the current core ID. Only uses the reg given as an argument.
|
||||
Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
|
||||
and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
|
||||
bit 13: it's 1 on the APP and 0 on the PRO processor.
|
||||
*/
|
||||
#ifdef __ASSEMBLER__
|
||||
.macro getcoreid reg
|
||||
rsr.prid \reg
|
||||
extui \reg,\reg,13,1
|
||||
.endm
|
||||
#endif
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#define CORE_ID_PRO 0xCDCD
|
||||
#define CORE_ID_APP 0xABAB
|
||||
#else
|
||||
#define CORE_ID_REGVAL_PRO 0xCDCD
|
||||
#define CORE_ID_REGVAL_APP 0xABAB
|
||||
|
||||
/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */
|
||||
#define CORE_ID_PRO CORE_ID_REGVAL_PRO
|
||||
|
||||
/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */
|
||||
#define CORE_ID_APP CORE_ID_REGVAL_APP
|
||||
#endif
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
|
||||
|
||||
Convenient where the frame size requirements are the same for both ABIs.
|
||||
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
|
||||
ENTRY0, RET0 are for frameless functions (no locals, no calls).
|
||||
|
||||
where size = size of stack frame in bytes (must be >0 and aligned to 16).
|
||||
For framed functions the frame is created and the return address saved at
|
||||
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
|
||||
For frameless functions, there is no frame and return address remains in a0.
|
||||
Note: Because CPP macros expand to a single line, macros requiring multi-line
|
||||
expansions are implemented as assembler macros.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
/* Call0 */
|
||||
#define ENTRY(sz) entry1 sz
|
||||
.macro entry1 size=0x10
|
||||
addi sp, sp, -\size
|
||||
s32i a0, sp, 0
|
||||
.endm
|
||||
#define ENTRY0
|
||||
#define RET(sz) ret1 sz
|
||||
.macro ret1 size=0x10
|
||||
l32i a0, sp, 0
|
||||
addi sp, sp, \size
|
||||
ret
|
||||
.endm
|
||||
#define RET0 ret
|
||||
#else
|
||||
/* Windowed */
|
||||
#define ENTRY(sz) entry sp, sz
|
||||
#define ENTRY0 entry sp, 0x10
|
||||
#define RET(sz) retw
|
||||
#define RET0 retw
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* XTENSA_CONTEXT_H */
|
||||
|
||||
#include <xtensa/xtensa_context.h>
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
|
||||
#include "sdkconfig.h"
|
||||
/*
|
||||
* Include any RTOS specific definitions that are needed by this header.
|
||||
*/
|
||||
|
|
@ -154,7 +154,9 @@
|
|||
* RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
|
||||
*/
|
||||
/* void XT_RTOS_TIMER_INT(void) */
|
||||
#define XT_RTOS_TIMER_INT _frxt_timer_int
|
||||
#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
#define XT_RTOS_TIMER_INT _frxt_timer_int
|
||||
#endif
|
||||
#define XT_TICK_PER_SEC configTICK_RATE_HZ
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue