mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2026-02-20 09:05:30 -05:00
Combine the SmartFusion2 starter kit and development kits demos into a single directory.
This commit is contained in:
parent
82995fd4fd
commit
961928b0f9
72 changed files with 22 additions and 120310 deletions
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,22 @@
|
|||
/**************************************************************************
|
||||
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
|
||||
*
|
||||
* Smartfusion2 system configuration.
|
||||
* - Automatically created by Microsemi Libero SoC Sun May 05 13:12:03 2013
|
||||
*
|
||||
* Warning: Do not modify this file, it may lead to unexpected
|
||||
* functional failures in your Microcontroller Subsystem.
|
||||
*/
|
||||
#ifndef SYS_CONFIG_MSS_CLOCKS
|
||||
#define SYS_CONFIG_MSS_CLOCKS
|
||||
|
||||
#define MSS_SYS_M3_CLK_FREQ 50000000u
|
||||
#define MSS_SYS_MDDR_CLK_FREQ 200000000u
|
||||
#define MSS_SYS_APB_0_CLK_FREQ 50000000u
|
||||
#define MSS_SYS_APB_1_CLK_FREQ 50000000u
|
||||
#define MSS_SYS_APB_2_CLK_FREQ 12500000u
|
||||
#define MSS_SYS_FIC_0_CLK_FREQ 50000000u
|
||||
#define MSS_SYS_FIC_1_CLK_FREQ 50000000u
|
||||
#define MSS_SYS_FIC64_CLK_FREQ 50000000u
|
||||
|
||||
#endif /* SYS_CONFIG_MSS_CLOCKS */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/**************************************************************************
|
||||
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
|
||||
*
|
||||
* Smartfusion2 system configuration.
|
||||
* - Automatically created by Microsemi Libero SoC Sun May 05 13:12:03 2013
|
||||
*
|
||||
* Warning: Do not modify this file, it may lead to unexpected
|
||||
* functional failures in your Microcontroller Subsystem.
|
||||
*/
|
||||
#ifndef SYS_CONFIG_MSS_CLOCKS
|
||||
#define SYS_CONFIG_MSS_CLOCKS
|
||||
|
||||
#define MSS_SYS_M3_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_MDDR_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_APB_0_CLK_FREQ 25000000u
|
||||
#define MSS_SYS_APB_1_CLK_FREQ 25000000u
|
||||
#define MSS_SYS_APB_2_CLK_FREQ 25000000u
|
||||
#define MSS_SYS_FIC_0_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_FIC_1_CLK_FREQ 100000000u
|
||||
#define MSS_SYS_FIC64_CLK_FREQ 100000000u
|
||||
|
||||
#endif /* SYS_CONFIG_MSS_CLOCKS */
|
||||
Loading…
Add table
Add a link
Reference in a new issue