mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-11 13:54:16 -04:00
Updated AVR32 demos and added AVR32 UC3B demo.
This commit is contained in:
Richard Barry
parent
45e7e5ac55
commit
94c94d3c0e
164 changed files with 21458 additions and 3994 deletions
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@ -1,5 +1,3 @@
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/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
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/*This file is prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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@ -12,7 +10,7 @@
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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* Support and FAQ: http://support.atmel.no/
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*
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******************************************************************************/
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@ -47,18 +45,10 @@
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#ifndef _COMPILER_H_
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#define _COMPILER_H_
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#if __GNUC__
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# include <avr32/io.h>
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#elif __ICCAVR32__ || __AAVR32__
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# include <avr32/iouc3a0512.h>
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# include <avr32/uc3a0512.h>
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# if __ICCAVR32__
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# include <intrinsics.h>
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# endif
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#else
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# error Unknown compiler
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#include <avr32/io.h>
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#if __ICCAVR32__
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# include <intrinsics.h>
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#endif
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#include "preprocessor.h"
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@ -69,6 +59,22 @@
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#include <stddef.h>
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#include <stdlib.h>
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#if __ICCAVR32__
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/*! \name Compiler Keywords
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*
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* Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
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*/
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//! @{
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#define __asm__ asm
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#define __inline__ inline
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#define __volatile__
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//! @}
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#endif
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/*! \name Usual Types
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*/
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//! @{
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@ -85,6 +91,7 @@ typedef float F32; //!< 32-bit floating-point number.
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typedef double F64; //!< 64-bit floating-point number.
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//! @}
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/*! \name Status Types
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*/
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//! @{
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@ -92,19 +99,6 @@ typedef Bool Status_bool_t; //!< Boolean status.
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typedef U8 Status_t; //!< 8-bit-coded status.
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//! @}
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#if __ICCAVR32__
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/*! \name Compiler Keywords
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*
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* Translation of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
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*/
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//! @{
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#define __asm__ asm
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#define __inline__ inline
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#define __volatile__
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//! @}
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#endif
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/*! \name Aliasing Aggregate Types
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*/
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@ -210,6 +204,7 @@ typedef struct
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#endif // __AVR32_ABI_COMPILER__
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//_____ M A C R O S ________________________________________________________
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/*! \name Usual Constants
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@ -233,9 +228,10 @@ typedef struct
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#define SET 1
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//! @}
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#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
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/*! \name Bit-Field Handling Macros
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/*! \name Bit-Field Handling
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*/
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//! @{
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@ -316,6 +312,7 @@ typedef struct
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//! @}
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/*! \brief This macro is used to test fatal errors.
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*
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* The macro tests if the expression is FALSE. If it is, a fatal error is
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@ -332,7 +329,8 @@ typedef struct
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#define Assert(expr)
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#endif
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/*! \name Zero-Bit Counting Macros
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/*! \name Zero-Bit Counting
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*
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* Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
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* applied to constant expressions (values known at compile time), so they are
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@ -372,7 +370,8 @@ typedef struct
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//! @}
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/*! \name Alignment Macros
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/*! \name Alignment
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*/
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//! @{
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@ -424,7 +423,8 @@ typedef struct
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//! @}
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/*! \name Mathematics Macros
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/*! \name Mathematics
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*
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* The same considerations as for clz and ctz apply here but AVR32-GCC does not
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* provide built-in functions to access the assembly instructions abs, min and
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@ -536,6 +536,7 @@ typedef struct
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//! @}
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/*! \brief Calls the routine at address \a addr.
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*
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* It generates a long call opcode.
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@ -558,18 +559,39 @@ typedef struct
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(\
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{\
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__asm__ __volatile__ (\
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"lda.w r8, _start\n\t"\
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"lddpc r9, 1f\n\t"\
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"stm --sp, r8-r9\n\t"\
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"lddpc r9, 3f\n\t"\
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"mfsr r8, %[SR]\n\t"\
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"bfextu r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\
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"cp.w r8, 0b001\n\t"\
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"breq 0f\n\t"\
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"sub r8, pc, $ - 1f\n\t"\
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"pushm r8-r9\n\t"\
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"rete\n"\
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"0:\n\t"\
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"rets\n\t"\
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".balign 4\n"\
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"mtsr %[SR], r9\n"\
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"1:\n\t"\
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"mov r0, 0\n\t"\
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"mov r1, 0\n\t"\
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"mov r2, 0\n\t"\
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"mov r3, 0\n\t"\
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"mov r4, 0\n\t"\
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"mov r5, 0\n\t"\
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"mov r6, 0\n\t"\
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"mov r7, 0\n\t"\
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"mov r8, 0\n\t"\
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"mov r9, 0\n\t"\
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"mov r10, 0\n\t"\
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"mov r11, 0\n\t"\
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"mov r12, 0\n\t"\
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"mov sp, 0\n\t"\
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"stdsp sp[0], sp\n\t"\
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"ldmts sp, sp\n\t"\
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"mov lr, 0\n\t"\
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"lddpc pc, 2f\n\t"\
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".balign 4\n"\
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"2:\n\t"\
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".word _start\n"\
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"3:\n\t"\
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".word %[RESET_SR]"\
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:\
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: [SR] "i" (AVR32_SR),\
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@ -584,81 +606,44 @@ typedef struct
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{\
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extern void *volatile __program_start;\
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__asm__ __volatile__ (\
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"mov r8, LWRD(__program_start)\n\t"\
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"orh r8, HWRD(__program_start)\n\t"\
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"mov r7, LWRD(__program_start)\n\t"\
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"orh r7, HWRD(__program_start)\n\t"\
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"mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
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"orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
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"stm --sp, r8-r9\n\t"\
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"mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\
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"bfextu r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\
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"cp.w r8, 001b\n\t"\
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"breq $ + 4\n\t"\
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"breq $ + 10\n\t"\
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"sub r8, pc, -12\n\t"\
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"pushm r8-r9\n\t"\
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"rete\n\t"\
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"rets"\
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"mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\
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"mov r0, 0\n\t"\
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"mov r1, 0\n\t"\
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"mov r2, 0\n\t"\
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"mov r3, 0\n\t"\
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"mov r4, 0\n\t"\
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"mov r5, 0\n\t"\
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"mov r6, 0\n\t"\
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"st.w r0[4], r7\n\t"\
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"mov r7, 0\n\t"\
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"mov r8, 0\n\t"\
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"mov r9, 0\n\t"\
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"mov r10, 0\n\t"\
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"mov r11, 0\n\t"\
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"mov r12, 0\n\t"\
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"mov sp, 0\n\t"\
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"stdsp sp[0], sp\n\t"\
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"ldmts sp, sp\n\t"\
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"mov lr, 0\n\t"\
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"ld.w pc, lr[4]"\
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);\
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__program_start;\
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}
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}
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#endif
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/*! \name CPU Status Register Macros
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*/
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//! @{
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/*! \brief Disables all exceptions.
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*/
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#if __GNUC__
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#define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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#elif __ICCAVR32__
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#define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))
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#endif
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/*! \brief Enables all exceptions.
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*/
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#if __GNUC__
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#define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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#elif __ICCAVR32__
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#define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))
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#endif
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/*! \brief Disables all interrupts.
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*/
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#if __GNUC__
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#define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));})
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#elif __ICCAVR32__
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#define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}
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#endif
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/*! \brief Enables all interrupts.
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*/
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#if __GNUC__
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#define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
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#elif __ICCAVR32__
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#define Enable_global_interrupt() (__enable_interrupt())
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#endif
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/*! \brief Disables interrupt level \a int_lev.
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*
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* \param int_lev Interrupt level to disable (0 to 3).
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*/
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#if __GNUC__
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#define Disable_interrupt_level(int_lev) ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
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#elif __ICCAVR32__
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#define Disable_interrupt_level(int_lev) {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");}
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#endif
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/*! \brief Enables interrupt level \a int_lev.
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*
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* \param int_lev Interrupt level to enable (0 to 3).
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*/
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#if __GNUC__
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#define Enable_interrupt_level(int_lev) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
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#elif __ICCAVR32__
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#define Enable_interrupt_level(int_lev) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)))
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#endif
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//! @}
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/*! \name System Register Access Macros
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/*! \name System Register Access
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*/
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//! @{
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@ -687,8 +672,88 @@ typedef struct
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//! @}
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/*! \name CPU Status Register Access
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*/
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//! @{
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/*! \brief Tells whether exceptions are globally enabled.
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*
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* \return \c 1 if exceptions are globally enabled, else \c 0.
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*/
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#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))
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/*! \brief Disables exceptions globally.
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*/
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#if __GNUC__
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#define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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#elif __ICCAVR32__
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#define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))
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#endif
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/*! \brief Enables exceptions globally.
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*/
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#if __GNUC__
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#define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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#elif __ICCAVR32__
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#define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))
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#endif
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/*! \brief Tells whether interrupts are globally enabled.
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*
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* \return \c 1 if interrupts are globally enabled, else \c 0.
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*/
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#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))
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/*! \brief Disables interrupts globally.
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*/
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#if __GNUC__
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#define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));})
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#elif __ICCAVR32__
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#define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}
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#endif
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/*! \brief Enables interrupts globally.
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*/
|
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#if __GNUC__
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#define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
|
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#elif __ICCAVR32__
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#define Enable_global_interrupt() (__enable_interrupt())
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#endif
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/*! \brief Tells whether interrupt level \a int_lev is enabled.
|
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*
|
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* \param int_lev Interrupt level (0 to 3).
|
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*
|
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* \return \c 1 if interrupt level \a int_lev is enabled, else \c 0.
|
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*/
|
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#define Is_interrupt_level_enabled(int_lev) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_lev, M_MASK)))
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|
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/*! \brief Disables interrupt level \a int_lev.
|
||||
*
|
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* \param int_lev Interrupt level to disable (0 to 3).
|
||||
*/
|
||||
#if __GNUC__
|
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#define Disable_interrupt_level(int_lev) ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
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#elif __ICCAVR32__
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#define Disable_interrupt_level(int_lev) {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");}
|
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#endif
|
||||
|
||||
/*! \brief Enables interrupt level \a int_lev.
|
||||
*
|
||||
* \param int_lev Interrupt level to enable (0 to 3).
|
||||
*/
|
||||
#if __GNUC__
|
||||
#define Enable_interrupt_level(int_lev) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
|
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#elif __ICCAVR32__
|
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#define Enable_interrupt_level(int_lev) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)))
|
||||
#endif
|
||||
|
||||
//! @}
|
||||
|
||||
#endif // __AVR32_ABI_COMPILER__
|
||||
|
||||
|
||||
//! Boolean evaluating MCU little endianism.
|
||||
#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)
|
||||
#define LITTLE_ENDIAN_MCU FALSE
|
||||
|
|
@ -702,34 +767,39 @@ typedef struct
|
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//! Boolean evaluating MCU big endianism.
|
||||
#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)
|
||||
|
||||
|
||||
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
|
||||
|
||||
/*! \name U16/U32/U64 MCU Endianism Handling Macros
|
||||
/*! \name MCU Endianism Handling
|
||||
*/
|
||||
//! @{
|
||||
|
||||
#if LITTLE_ENDIAN_MCU
|
||||
|
||||
#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
|
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#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
|
||||
|
||||
#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
|
||||
#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
|
||||
#define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.
|
||||
#define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.
|
||||
#define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.
|
||||
#define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.
|
||||
#define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
|
||||
#define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
|
||||
#define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
|
||||
#define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
|
||||
#define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32.
|
||||
#define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32.
|
||||
#define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32.
|
||||
#define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32.
|
||||
|
||||
#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
|
||||
#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
|
||||
#define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.
|
||||
#define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.
|
||||
#define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.
|
||||
#define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.
|
||||
#define MSH3(u64) LSH0(u64) //!< Most significant half-word of 1st rank of \a u64.
|
||||
#define MSH2(u64) LSH1(u64) //!< Most significant half-word of 2nd rank of \a u64.
|
||||
#define MSH1(u64) LSH2(u64) //!< Most significant half-word of 3rd rank of \a u64.
|
||||
#define MSH0(u64) LSH3(u64) //!< Most significant half-word of 4th rank of \a u64.
|
||||
#define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64.
|
||||
#define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64.
|
||||
#define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64.
|
||||
#define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64.
|
||||
#define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.
|
||||
#define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.
|
||||
#define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.
|
||||
|
|
@ -738,37 +808,41 @@ typedef struct
|
|||
#define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.
|
||||
#define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.
|
||||
#define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.
|
||||
#define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 1st rank of \a u64.
|
||||
#define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 2nd rank of \a u64.
|
||||
#define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 3rd rank of \a u64.
|
||||
#define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 4th rank of \a u64.
|
||||
#define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 5th rank of \a u64.
|
||||
#define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 6th rank of \a u64.
|
||||
#define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 7th rank of \a u64.
|
||||
#define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 8th rank of \a u64.
|
||||
#define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64.
|
||||
#define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64.
|
||||
#define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64.
|
||||
#define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64.
|
||||
#define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64.
|
||||
#define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64.
|
||||
#define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64.
|
||||
#define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64.
|
||||
|
||||
#else // BIG_ENDIAN_MCU
|
||||
|
||||
#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.
|
||||
#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.
|
||||
|
||||
#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.
|
||||
#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.
|
||||
#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.
|
||||
#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.
|
||||
#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.
|
||||
#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.
|
||||
#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
|
||||
#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
|
||||
#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
|
||||
#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
|
||||
#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
|
||||
#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
|
||||
#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
|
||||
#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
|
||||
|
||||
#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.
|
||||
#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.
|
||||
#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.
|
||||
#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.
|
||||
#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.
|
||||
#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.
|
||||
#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 1st rank of \a u64.
|
||||
#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 2nd rank of \a u64.
|
||||
#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 3rd rank of \a u64.
|
||||
#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 4th rank of \a u64.
|
||||
#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
|
||||
#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
|
||||
#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
|
||||
#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
|
||||
#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.
|
||||
#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.
|
||||
#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.
|
||||
|
|
@ -777,18 +851,21 @@ typedef struct
|
|||
#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.
|
||||
#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.
|
||||
#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.
|
||||
#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 1st rank of \a u64.
|
||||
#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 2nd rank of \a u64.
|
||||
#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 3rd rank of \a u64.
|
||||
#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 4th rank of \a u64.
|
||||
#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 5th rank of \a u64.
|
||||
#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 6th rank of \a u64.
|
||||
#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 7th rank of \a u64.
|
||||
#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 8th rank of \a u64.
|
||||
#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
|
||||
#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
|
||||
#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
|
||||
#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
|
||||
#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
|
||||
#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
|
||||
#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
|
||||
#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
|
||||
|
||||
#endif
|
||||
|
||||
//! @}
|
||||
|
||||
/*! \name Endianism Conversion Macros
|
||||
|
||||
/*! \name Endianism Conversion
|
||||
*
|
||||
* The same considerations as for clz and ctz apply here but AVR32-GCC's
|
||||
* __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
|
||||
|
|
@ -874,6 +951,35 @@ typedef struct
|
|||
|
||||
//! @}
|
||||
|
||||
|
||||
/*! \name Target Abstraction
|
||||
*/
|
||||
//! @{
|
||||
|
||||
#define _GLOBEXT_ extern //!< extern storage-class specifier.
|
||||
#define _CONST_TYPE_ const //!< const type qualifier.
|
||||
#define _MEM_TYPE_SLOW_ //!< Slow memory type.
|
||||
#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
|
||||
#define _MEM_TYPE_FAST_ //!< Fast memory type.
|
||||
|
||||
typedef U8 Byte; //!< 8-bit unsigned integer.
|
||||
|
||||
#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
|
||||
#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
|
||||
#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
|
||||
#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
|
||||
|
||||
#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
|
||||
#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
|
||||
#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
|
||||
#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
|
||||
#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
|
||||
#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
|
||||
#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
|
||||
#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
|
||||
|
||||
//! @}
|
||||
|
||||
#endif // __AVR32_ABI_COMPILER__
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue