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Updated AVR32 demos and added AVR32 UC3B demo.

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This commit is contained in:
Richard Barry 2007-07-27 07:59:50 +00:00
parent 45e7e5ac55
commit 94c94d3c0e
164 changed files with 21458 additions and 3994 deletions
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4
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.c
View file

@ -6,11 +6,11 @@
* This file defines a useful set of functions for the GPIO.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a PWM module can be used.
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/

29
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h
View file

@ -10,7 +10,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
@ -45,13 +45,7 @@
#ifndef _GPIO_H_
#define _GPIO_H_
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
/*! \name Return Values of the GPIO API
@ -90,8 +84,16 @@ extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables a specific module mode for a pin.
*
* \param pin The pin number.
* \param function The pin function.
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for module pins. E.g., to enable a PWM
* channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM
* channel 3.
* \param function The pin function.\n
* Refer to the product header file `uc3x.h' (where x is the
* part number; e.g. x = a0512) for module pin functions. E.g.,
* to enable a PWM channel output, the pin function can be
* AVR32_PWM_PWM_3_FUNCTION for PWM channel 3.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
@ -106,7 +108,12 @@ extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables the GPIO mode of a pin.
*
* \param pin The pin number.
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for pin definitions. E.g., to enable the
* GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
* AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release
* module pins for GPIO.
*/
extern void gpio_enable_gpio_pin(unsigned int pin);

14
Demo/AVR32_UC3/DRIVERS/INTC/intc.c
View file

@ -10,7 +10,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
@ -42,14 +42,7 @@
*/
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
@ -61,7 +54,7 @@ extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
//! Each line handler table contains a set of pointers to interrupt handlers.
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP];
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
@ -186,6 +179,7 @@ void INTC_init_interrupts(void)
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)
{
// Determine the group of the IRQ.
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so

2
Demo/AVR32_UC3/DRIVERS/INTC/intc.h
View file

@ -10,7 +10,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/

604
Demo/AVR32_UC3/DRIVERS/PM/pm.c
View file

@ -9,7 +9,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
@ -44,297 +44,275 @@
#include "pm.h"
/*! \name PM Writable Bit-Field Registers
*/
//! @{
typedef union
{
unsigned long mcctrl;
avr32_pm_mcctrl_t MCCTRL;
} u_avr32_pm_mcctrl_t;
typedef union
{
unsigned long cksel;
avr32_pm_cksel_t CKSEL;
} u_avr32_pm_cksel_t;
typedef union
{
unsigned long pll;
avr32_pm_pll_t PLL;
} u_avr32_pm_pll_t;
typedef union
{
unsigned long oscctrl0;
avr32_pm_oscctrl0_t OSCCTRL0;
} u_avr32_pm_oscctrl0_t;
typedef union
{
unsigned long oscctrl1;
avr32_pm_oscctrl1_t OSCCTRL1;
} u_avr32_pm_oscctrl1_t;
typedef union
{
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} u_avr32_pm_oscctrl32_t;
typedef union
{
unsigned long ier;
avr32_pm_ier_t IER;
} u_avr32_pm_ier_t;
typedef union
{
unsigned long idr;
avr32_pm_idr_t IDR;
} u_avr32_pm_idr_t;
typedef union
{
unsigned long icr;
avr32_pm_icr_t ICR;
} u_avr32_pm_icr_t;
typedef union
{
unsigned long gcctrl;
avr32_pm_gcctrl_t GCCTRL;
} u_avr32_pm_gcctrl_t;
typedef union
{
unsigned long rccr;
avr32_pm_rccr_t RCCR;
} u_avr32_pm_rccr_t;
typedef union
{
unsigned long bgcr;
avr32_pm_bgcr_t BGCR;
} u_avr32_pm_bgcr_t;
typedef union
{
unsigned long vregcr;
avr32_pm_vregcr_t VREGCR;
} u_avr32_pm_vregcr_t;
typedef union
{
unsigned long bod;
avr32_pm_bod_t BOD;
} u_avr32_pm_bod_t;
//! @}
/*! \brief Sets the mode of the oscillator 0.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
* \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).
*/
static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)
{
// Read
u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
// Modify
u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;
// Write
pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
}
void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
{
union {
unsigned long oscctrl0;
avr32_pm_oscctrl0_t OSCCTRL0;
} oscctrl0 ;
// Read
oscctrl0.oscctrl0 = pm->oscctrl0;
// Modify
oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;
// Write
pm->oscctrl0 = oscctrl0.oscctrl0;
pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
}
void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
{
union {
unsigned long oscctrl0;
avr32_pm_oscctrl0_t OSCCTRL0;
} oscctrl0 ;
// Read
oscctrl0.oscctrl0 = pm->oscctrl0;
// Modify
oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;
// Write
pm->oscctrl0 = oscctrl0.oscctrl0;
pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
}
void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
union {
unsigned long oscctrl0;
avr32_pm_oscctrl0_t OSCCTRL0;
} oscctrl0 ;
// Read register
mcctrl.mcctrl = pm->mcctrl;
oscctrl0.oscctrl0 = pm->oscctrl0;
// Modify
mcctrl.MCCTRL.osc0en = 1;
oscctrl0.OSCCTRL0.startup = startup;
// Write back
pm->oscctrl0 = oscctrl0.oscctrl0;
pm->mcctrl = mcctrl.mcctrl;
while(!pm->ISR.osc0rdy); //For osc output valid
pm_enable_clk0_no_wait(pm, startup);
pm_wait_for_clk0_ready(pm);
}
void pm_disable_clk0(volatile avr32_pm_t *pm)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
// Read register
mcctrl.mcctrl = pm->mcctrl;
// Modify
mcctrl.MCCTRL.osc0en = 0;
// Write back
pm->mcctrl = mcctrl.mcctrl;
pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
}
void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
union {
unsigned long oscctrl0;
avr32_pm_oscctrl0_t OSCCTRL0;
} oscctrl0 ;
// Read register
mcctrl.mcctrl = pm->mcctrl;
oscctrl0.oscctrl0 = pm->oscctrl0;
u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
// Modify
mcctrl.MCCTRL.osc0en = 1;
oscctrl0.OSCCTRL0.startup=startup;
u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
// Write back
pm->mcctrl = mcctrl.mcctrl;
pm->oscctrl0 = oscctrl0.oscctrl0;
pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
}
void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
{
while(!pm->ISR.osc0rdy);
while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
}
/*! \brief Sets the mode of the oscillator 1.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
* \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).
*/
static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)
{
// Read
u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
// Modify
u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;
// Write
pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
}
void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
{
union {
unsigned long oscctrl1;
avr32_pm_oscctrl1_t OSCCTRL1;
} oscctrl1 ;
// Read
oscctrl1.oscctrl1= pm->oscctrl1;
// Modify
oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;
// Write
pm->oscctrl1 = oscctrl1.oscctrl1;
pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
}
void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
{
union {
unsigned long oscctrl1;
avr32_pm_oscctrl1_t OSCCTRL1;
} oscctrl1 ;
// Read
oscctrl1.oscctrl1= pm->oscctrl1;
// Modify
oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;
// Write
pm->oscctrl1 = oscctrl1.oscctrl1;
pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
}
void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
union {
unsigned long oscctrl1;
avr32_pm_oscctrl1_t OSCCTRL1;
} oscctrl1 ;
// Read register
mcctrl.mcctrl = pm->mcctrl;
oscctrl1.oscctrl1 = pm->oscctrl1;
mcctrl.MCCTRL.osc1en = 1;
oscctrl1.OSCCTRL1.startup=startup;
// Write back
pm->oscctrl1 = oscctrl1.oscctrl1;
pm->mcctrl = mcctrl.mcctrl;
while(!pm->ISR.osc1rdy);
pm_enable_clk1_no_wait(pm, startup);
pm_wait_for_clk1_ready(pm);
}
void pm_disable_clk1(volatile avr32_pm_t *pm)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
// Read register
mcctrl.mcctrl = pm->mcctrl;
// Modify
mcctrl.MCCTRL.osc1en = 0;
// Write back
pm->mcctrl = mcctrl.mcctrl;
pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
}
void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
union {
unsigned long oscctrl1;
avr32_pm_oscctrl1_t OSCCTRL1;
} oscctrl1 ;
// Read register
mcctrl.mcctrl = pm->mcctrl;
oscctrl1.oscctrl1 = pm->oscctrl1;
mcctrl.MCCTRL.osc1en = 1;
oscctrl1.OSCCTRL1.startup=startup;
u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
// Modify
u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
// Write back
pm->oscctrl1 = oscctrl1.oscctrl1;
pm->mcctrl = mcctrl.mcctrl;
pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
}
void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
{
while(!pm->ISR.osc1rdy);
while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
}
/*! \brief Sets the mode of the 32-kHz oscillator.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
* \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).
*/
static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)
{
// Read
u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
// Modify
u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;
// Write
pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
}
void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
{
union {
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} u_ctrl;
u_ctrl.oscctrl32 = pm->oscctrl32;
u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;
pm->oscctrl32 = u_ctrl.oscctrl32;
pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
}
void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
{
union {
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} u_ctrl;
u_ctrl.oscctrl32 = pm->oscctrl32;
u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;
pm->oscctrl32 = u_ctrl.oscctrl32;
pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
}
void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} oscctrl32 ;
// Read register
oscctrl32.oscctrl32 = pm->oscctrl32;
// Modify
oscctrl32.OSCCTRL32.osc32en = 1;
oscctrl32.OSCCTRL32.startup=startup;
// Write back
pm->oscctrl32 = oscctrl32.oscctrl32;
while(!pm->ISR.osc32rdy);
pm_enable_clk32_no_wait(pm, startup);
pm_wait_for_clk32_ready(pm);
}
void pm_disable_clk32(volatile avr32_pm_t *pm)
{
// To get rid of a GCC bug
// This makes C code longer, but not ASM
union {
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} oscctrl32 ;
// Read register
oscctrl32.oscctrl32 = pm->oscctrl32;
// Modify
oscctrl32.OSCCTRL32.osc32en = 0;
// Write back
pm->oscctrl32 = oscctrl32.oscctrl32;
pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
}
void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
{
union {
unsigned long oscctrl32;
avr32_pm_oscctrl32_t OSCCTRL32;
} oscctrl32 ;
// Read register
oscctrl32.oscctrl32 = pm->oscctrl32;
u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
// Modify
oscctrl32.OSCCTRL32.osc32en = 1;
oscctrl32.OSCCTRL32.startup=startup;
u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
// Write back
pm->oscctrl32 = oscctrl32.oscctrl32;
pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
}
void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
{
// To get rid of a GCC bug
// This makes C code longer, but not ASM
while(!pm->ISR.osc32rdy);
while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
}
@ -346,29 +324,21 @@ void pm_cksel(volatile avr32_pm_t *pm,
unsigned int hsbdiv,
unsigned int hsbsel)
{
// Force the compiler to generate only one 32 bits access
union {
avr32_pm_cksel_t selval ;
unsigned long uword32;
} cksel;
u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
cksel.uword32 = 0;
u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
cksel.selval.cpudiv = hsbdiv;
cksel.selval.cpusel = hsbsel;
cksel.selval.hsbdiv = hsbdiv;
cksel.selval.hsbsel = hsbsel;
cksel.selval.pbbdiv = pbbdiv;
cksel.selval.pbbsel = pbbsel;
cksel.selval.pbadiv = pbadiv;
cksel.selval.pbasel = pbasel;
pm->cksel = cksel.uword32;
pm->cksel = u_avr32_pm_cksel.cksel;
// Wait for ckrdy bit and then clear it
while(!(pm->ISR.ckrdy));
return;
while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
}
@ -377,42 +347,30 @@ void pm_gc_setup(volatile avr32_pm_t *pm,
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
unsigned int diven,
unsigned int div) {
union {
unsigned long gcctrl;
avr32_pm_gcctrl_t GCCTRL;
} u_gc;
unsigned int div)
{
u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
u_gc.GCCTRL.oscsel = pll_osc;
u_gc.GCCTRL.pllsel = osc_or_pll;
u_gc.GCCTRL.diven = diven;
u_gc.GCCTRL.div = div;
u_gc.GCCTRL.cen = 0; // Disable GC first
pm->gcctrl[gc] = u_gc.gcctrl;
u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
u_avr32_pm_gcctrl.GCCTRL.diven = diven;
u_avr32_pm_gcctrl.GCCTRL.div = div;
pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
}
void pm_gc_enable(volatile avr32_pm_t *pm,
unsigned int gc) {
union {
unsigned long gcctrl;
avr32_pm_gcctrl_t GCCTRL;
} u_gc;
u_gc.gcctrl = pm->gcctrl[gc];
u_gc.GCCTRL.cen = 1;
pm->gcctrl[gc] = u_gc.gcctrl;
unsigned int gc)
{
pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
}
void pm_gc_disable(volatile avr32_pm_t *pm,
unsigned int gc) {
union {
unsigned long gcctrl;
avr32_pm_gcctrl_t GCCTRL;
} u_gc;
u_gc.gcctrl = pm->gcctrl[gc];
u_gc.GCCTRL.cen = 0;
pm->gcctrl[gc] = u_gc.gcctrl;
unsigned int gc)
{
pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
}
@ -421,25 +379,16 @@ void pm_pll_setup(volatile avr32_pm_t *pm,
unsigned int mul,
unsigned int div,
unsigned int osc,
unsigned int lockcount) {
unsigned int lockcount)
{
u_avr32_pm_pll_t u_avr32_pm_pll = {0};
union {
unsigned long pll ;
avr32_pm_pll_t PLL ;
} u_pll;
u_avr32_pm_pll.PLL.pllosc = osc;
u_avr32_pm_pll.PLL.plldiv = div;
u_avr32_pm_pll.PLL.pllmul = mul;
u_avr32_pm_pll.PLL.pllcount = lockcount;
u_pll.pll=0;
u_pll.PLL.pllmul = mul;
u_pll.PLL.plldiv = div;
u_pll.PLL.pllosc = osc;
u_pll.PLL.pllcount = lockcount;
u_pll.PLL.pllopt = 0;
u_pll.PLL.plltest = 0;
(pm->pll)[pll] = u_pll.pll;
pm->pll[pll] = u_avr32_pm_pll.pll;
}
@ -447,53 +396,38 @@ void pm_pll_set_option(volatile avr32_pm_t *pm,
unsigned int pll,
unsigned int pll_freq,
unsigned int pll_div2,
unsigned int pll_wbwdisable) {
union {
unsigned long pll ;
avr32_pm_pll_t PLL ;
} u_pll;
u_pll.pll = (pm->pll)[pll];
u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);
(pm->pll)[pll] = u_pll.pll;
unsigned int pll_wbwdisable)
{
u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
pm->pll[pll] = u_avr32_pm_pll.pll;
}
unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
unsigned int pll) {
return (pm->PLL)[pll].pllopt;
unsigned int pll)
{
return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
}
void pm_pll_enable(volatile avr32_pm_t *pm,
unsigned int pll) {
union {
unsigned long pll ;
avr32_pm_pll_t PLL ;
} u_pll;
u_pll.pll = (pm->pll)[pll];
u_pll.PLL.pllen = 1;
(pm->pll)[pll] = u_pll.pll;
unsigned int pll)
{
pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
}
void pm_pll_disable(volatile avr32_pm_t *pm,
unsigned int pll) {
union {
unsigned long pll ;
avr32_pm_pll_t PLL ;
} u_pll;
u_pll.pll = (pm->pll)[pll];
u_pll.PLL.pllen = 0;
(pm->pll)[pll] = u_pll.pll;
unsigned int pll)
{
pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
}
void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
{
while(!pm->ISR.lock0);
while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
// Bypass the lock signal of the PLL
pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;
@ -502,7 +436,7 @@ void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
{
while(!pm->ISR.lock1);
while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
// Bypass the lock signal of the PLL
pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;
@ -511,16 +445,12 @@ void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
{
union {
avr32_pm_mcctrl_t MCCTRL;
unsigned long mcctrl;
} mcctrl;
// Read
mcctrl.mcctrl = pm->mcctrl;
u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
// Modify
mcctrl.MCCTRL.mcsel = clock;
// Write Back
pm->MCCTRL.mcsel = mcctrl.mcctrl;
u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
// Write back
pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
}
@ -532,77 +462,49 @@ void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int
}
void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {
union {
unsigned long ier ;
avr32_pm_ier_t IER ;
} u_ier;
u_ier.ier = 0;
u_ier.IER.boddet = 1;
pm->ier = u_ier.ier;
void pm_bod_enable_irq(volatile avr32_pm_t *pm)
{
pm->ier = AVR32_PM_IER_BODDET_MASK;
}
void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {
union {
unsigned long idr ;
avr32_pm_idr_t IDR ;
} u_idr;
u_idr.idr = 0;
u_idr.IDR.boddet = 1;
pm->idr = u_idr.idr;
void pm_bod_disable_irq(volatile avr32_pm_t *pm)
{
pm->idr = AVR32_PM_IDR_BODDET_MASK;
}
void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {
union {
unsigned long icr ;
avr32_pm_idr_t ICR ;
} u_icr;
u_icr.icr = 0;
u_icr.ICR.boddet = 1;
pm->icr = u_icr.icr;
void pm_bod_clear_irq(volatile avr32_pm_t *pm)
{
pm->icr = AVR32_PM_ICR_BODDET_MASK;
}
unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {
return pm->ISR.boddet;
unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)
{
return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
}
unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {
return pm->IMR.boddet;
unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)
{
return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
}
unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {
union {
unsigned long bod ;
avr32_pm_bod_t BOD ;
} u_bod;
u_bod.bod = pm->bod;
return (unsigned long) u_bod.BOD.level;
unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)
{
return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
}
void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {
(pm->gplp)[gplp] = value;
void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value)
{
pm->gplp[gplp] = value;
}
unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {
return (pm->gplp)[gplp];
unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp)
{
return pm->gplp[gplp];
}

28
Demo/AVR32_UC3/DRIVERS/PM/pm.h
View file

@ -9,7 +9,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
@ -44,15 +44,7 @@
#ifndef _PM_H_
#define _PM_H_
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
# include <avr32/uc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
@ -70,6 +62,22 @@
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
/*! \brief Gets the MCU reset cause.
*
* \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
*
* \return The MCU reset cause which can be masked with the
* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
{
return pm->rcause;
}
/*!
* \brief This function will enable the external clock mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)

11
Demo/AVR32_UC3/DRIVERS/TC/tc.c
View file

@ -10,7 +10,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
@ -42,14 +42,7 @@
*/
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
#include "compiler.h"
#include "tc.h"

12
Demo/AVR32_UC3/DRIVERS/TC/tc.h
View file

@ -10,7 +10,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
@ -45,17 +45,11 @@
#ifndef _TC_H_
#define _TC_H_
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
//! TC driver functions return value in case of invalid argument(s).
#define TC_INVALID_ARGUMENT -1
#define TC_INVALID_ARGUMENT (-1)
//! Number of timer/counter channels.
#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))

29
Demo/AVR32_UC3/DRIVERS/USART/usart.c
View file

@ -11,7 +11,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
@ -70,9 +70,12 @@ static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a
* wanted baudrate as possible.
*
* \todo manage the FP fractal part to avoid big errors
*
* Baudrate calculation:
* \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or
* \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling.
* \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling or
* \f$ baudrate = \frac{Selected Clock}{CD} \f$ with SYNC bit set to allow high speed.
*
* \param usart Base address of the USART instance.
* \param baudrate Wanted baudrate.
@ -90,20 +93,30 @@ static int usart_set_baudrate(volatile avr32_usart_t *usart, unsigned int baudra
// Baudrate calculation.
if (baudrate < pba_hz / 16)
{
// Use 16x oversampling.
usart->mr &=~ AVR32_USART_MR_OVER_MASK;
cd = pba_hz / (16 * baudrate);
// Use 16x oversampling, clear SYNC bit.
usart->mr &=~ (AVR32_USART_MR_OVER_MASK | AVR32_USART_MR_SYNC_MASK);
cd = (pba_hz + 8 * baudrate) / (16 * baudrate);
if ((cd >65535)) return USART_INVALID_INPUT;
}
else
else if (baudrate < pba_hz / 8)
{
// Use 8x oversampling.
usart->mr |= AVR32_USART_MR_OVER_MASK;
cd = pba_hz / (8 * baudrate);
// clear SYNC bit
usart->mr &=~ AVR32_USART_MR_SYNC_MASK;
cd = (pba_hz + 4 * baudrate) / (8 * baudrate);
if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT;
}
else
{
// set SYNC to 1
usart->mr |= AVR32_USART_MR_SYNC_MASK;
// use PBA/BaudRate
cd = (pba_hz / baudrate);
}
usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
return USART_SUCCESS;
@ -303,8 +316,6 @@ int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *o
return USART_SUCCESS;
}
//! @}

74
Demo/AVR32_UC3/DRIVERS/USART/usart.h
View file

@ -11,7 +11,7 @@
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support email: avr32@atmel.com
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
@ -46,14 +46,7 @@
#ifndef _USART_H_
#define _USART_H_
#if __GNUC__
# include <avr32/io.h>
#elif __ICCAVR32__
# include <avr32/iouc3a0512.h>
#else
# error Unknown compiler
#endif
#include <avr32/io.h>
#include "compiler.h"
@ -97,6 +90,7 @@
#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking.
//! @}
/*! \name Channel Modes
*/
//! @{
@ -171,6 +165,26 @@ typedef struct
int bit_order;
} iso7816_options_t;
//! Input parameters when initializing ISO7816 modes.
typedef struct
{
//! Set the frequency of the SPI clock.
unsigned long baudrate;
//! Number of bits to transmit as a character (5 to 9).
unsigned char charlength;
//! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,
//! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.
unsigned char channelmode;
//! Which SPI mode to use when transmitting.
unsigned char spimode;
} usart_spi_options_t;
//------------------------------------------------------------------------------
/*! \name Initialization Functions
@ -254,8 +268,50 @@ extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t
*/
extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz);
/*! \brief Sets up the USART to use the SPI mode as master.
*
* \param usart Base address of the USART instance.
* \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
*
* \retval USART_SUCCESS Mode successfully initialized.
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
*/
extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);
/*! \brief Sets up the USART to use the SPI mode as slave.
*
* \param usart Base address of the USART instance.
* \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
*
* \retval USART_SUCCESS Mode successfully initialized.
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
*/
extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);
//! @}
//------------------------------------------------------------------------------
/*! \brief Selects slave chip.
*
* \param usart Base address of the USART instance.
*
* \return Status.
* \retval USART_SUCCESS Success.
*/
extern int usart_spi_selectChip(volatile avr32_usart_t *usart);
/*! \brief Unselects slave chip.
*
* \param usart Base address of the USART instance.
*
* \return Status.
* \retval USART_SUCCESS Success.
* \retval USART_FAILURE Time out.
*/
extern int usart_spi_unselectChip(volatile avr32_usart_t *usart);
//------------------------------------------------------------------------------
/*! \name Read and Reset Error Status Bits