mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-01 08:54:14 -04:00
Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
This commit is contained in:
Richard Barry
parent
670d172cfc
commit
92f1699055
19 changed files with 412 additions and 120 deletions
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@ -1,6 +1,6 @@
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/*
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FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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***************************************************************************
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* *
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@ -40,7 +40,7 @@
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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@ -50,17 +50,17 @@
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, training, latest information,
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http://www.FreeRTOS.org - Documentation, training, latest information,
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license and contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool.
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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provide a safety engineered and independently SIL3 certified version under
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provide a safety engineered and independently SIL3 certified version under
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the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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@ -73,7 +73,7 @@ extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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@ -98,13 +98,13 @@ extern "C" {
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typedef unsigned portLONG portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffffffff
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#endif
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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@ -118,10 +118,10 @@ extern void vPortYieldFromISR( void );
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/* Critical section management. */
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/*
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/*
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* Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
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* registers. r0 is clobbered.
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*/
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*/
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#define portSET_INTERRUPT_MASK() \
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__asm volatile \
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( \
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@ -129,10 +129,10 @@ extern void vPortYieldFromISR( void );
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" msr basepri, r0 \n" \
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::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \
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)
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/*
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* Set basepri back to 0 without effective other registers.
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
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* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
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*/
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#define portCLEAR_INTERRUPT_MASK() \
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@ -143,8 +143,8 @@ extern void vPortYieldFromISR( void );
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:::"r0" \
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)
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/* FAQ: Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a
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bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before
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/* FAQ: Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a
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bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before
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disagreeing. */
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
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@ -165,6 +165,33 @@ extern void vPortExitCritical( void );
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#define portNOP()
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Generic helper function. */
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__attribute__( ( always_inline ) ) static unsigned char ucPortCountLeadingZeros( unsigned long ulBitmap )
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{
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unsigned char ucReturn;
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__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
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return ucReturn;
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}
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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#ifdef __cplusplus
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}
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#endif
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@ -170,6 +170,33 @@ portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */
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#define portNOP()
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Generic helper function. */
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__attribute__( ( always_inline ) ) static unsigned char ucPortCountLeadingZeros( ulBitmap )
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{
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unsigned char ucReturn;
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__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
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return ucReturn;
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}
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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#ifdef __cplusplus
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}
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#endif
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@ -40,7 +40,7 @@
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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@ -50,17 +50,17 @@
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, training, latest information,
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http://www.FreeRTOS.org - Documentation, training, latest information,
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license and contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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including FreeRTOS+Trace - an indispensable productivity tool.
|
||||
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||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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||||
the code with commercial support, indemnification, and middleware, under
|
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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||||
the code with commercial support, indemnification, and middleware, under
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||||
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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||||
provide a safety engineered and independently SIL3 certified version under
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||||
provide a safety engineered and independently SIL3 certified version under
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the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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@ -115,6 +115,24 @@ extern void vPortYieldFromISR( void );
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
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/*-----------------------------------------------------------*/
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#include <intrinsics.h>
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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/* Critical section management. */
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@ -128,7 +146,7 @@ extern void vPortClearInterruptMask( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
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@ -115,6 +115,24 @@ extern void vPortYieldFromISR( void );
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
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/*-----------------------------------------------------------*/
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#include <intrinsics.h>
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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/* Critical section management. */
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@ -141,6 +141,25 @@ http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
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#define portNOP()
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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#ifdef __cplusplus
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}
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#endif
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@ -145,6 +145,25 @@ portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */
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#define portNOP()
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if( configMAX_PRIORITIES >= 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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#ifdef __cplusplus
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}
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#endif
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