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Add starting point for IGLOO2 RISV-V demo project.
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/*******************************************************************************
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* Hardware registers access macros.
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*
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* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
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* DEVELOPMENT.
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*
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* These macros are used to access peripheral's registers. They allow access to
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* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
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* be done through these macros in order to ease porting across different
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* processors/bus architectures.
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*
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* Some of these macros also allow to access a specific register field.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#ifndef __HW_REGISTER_MACROS_H
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#define __HW_REGISTER_MACROS_H 1
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/*------------------------------------------------------------------------------
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* 32 bits registers access:
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*/
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#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint32_t) \
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( \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 32 bits memory access:
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*/
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#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
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#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
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/*------------------------------------------------------------------------------
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* 16 bits registers access:
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*/
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#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint16_t) \
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( \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits registers access:
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*/
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#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint8_t) \
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( \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits memory access:
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*/
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#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
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#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
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#endif /* __HW_REGISTER_MACROS_H */
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