mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add starting point for IGLOO2 RISV-V demo project.
This commit is contained in:
Richard Barry
parent
483f4a8c4b
commit
9119e1e0e3
42 changed files with 13068 additions and 0 deletions
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/*******************************************************************************
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#ifndef __CPU_TYPES_H
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#define __CPU_TYPES_H 1
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#include <stdint.h>
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/*------------------------------------------------------------------------------
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*/
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typedef unsigned int size_t;
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/*------------------------------------------------------------------------------
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* addr_t: address type.
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* Used to specify the address of peripherals present in the processor's memory
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* map.
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*/
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typedef unsigned int addr_t;
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/*------------------------------------------------------------------------------
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* psr_t: processor state register.
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* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
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* processor's state between disabling and restoring interrupts.
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*/
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typedef unsigned int psr_t;
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#endif /* __CPU_TYPES_H */
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207
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/hal/hal.h
Normal file
207
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/hal/hal.h
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/***************************************************************************//**
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* Hardware abstraction layer functions.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#ifndef HAL_H_
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#define HAL_H_
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#include "cpu_types.h"
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#include "hw_reg_access.h"
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/***************************************************************************//**
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* Enable all interrupts at the processor level.
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*/
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void HAL_enable_interrupts( void );
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/***************************************************************************//**
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* Disable all interrupts at the processor core level.
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* Return the interrupts enable state before disabling occured so that it can
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* later be restored.
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*/
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psr_t HAL_disable_interrupts( void );
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/***************************************************************************//**
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* Restore the interrupts enable state at the processor core level.
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* This function is normally passed the value returned from a previous call to
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* HAL_disable_interrupts().
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*/
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void HAL_restore_interrupts( psr_t saved_psr );
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/***************************************************************************//**
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*/
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#define FIELD_OFFSET(FIELD_NAME) (FIELD_NAME##_OFFSET)
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#define FIELD_SHIFT(FIELD_NAME) (FIELD_NAME##_SHIFT)
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#define FIELD_MASK(FIELD_NAME) (FIELD_NAME##_MASK)
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/***************************************************************************//**
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* The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to write. These strings are
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* specified in a header file associated with the peripheral.
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* VALUE: A variable of type uint32_t containing the value to write.
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*/
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#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
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(HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
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/***************************************************************************//**
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* The macro HAL_get_32bit_reg() is used to read the value of a 32 bits wide
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* register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to read. These strings are
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* specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint32_t value.
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*/
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#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
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(HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
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/***************************************************************************//**
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* The macro HAL_set_32bit_reg_field() is used to write a field within a
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* 32 bits wide register. The field written can be one or more bits.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* FIELD_NAME: A string identifying the register field to write. These strings
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* are specified in a header file associated with the peripheral.
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* VALUE: A variable of type uint32_t containing the field value to write.
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*/
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#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
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(HW_set_32bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME),\
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(VALUE)))
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/***************************************************************************//**
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* The macro HAL_get_32bit_reg_field() is used to read a register field from
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* within a 32 bit wide peripheral register. The field can be one or more bits.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* FIELD_NAME: A string identifying the register field to write. These strings
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* are specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint32_t value.
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*/
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#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
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(HW_get_32bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME)))
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/***************************************************************************//**
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* The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to write. These strings are
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* specified in a header file associated with the peripheral.
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* VALUE: A variable of type uint_fast16_t containing the value to write.
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*/
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#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
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(HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
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/***************************************************************************//**
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* The macro HAL_get_16bit_reg() is used to read the value of a 16 bits wide
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* register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to read. These strings are
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* specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint16_t value.
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*/
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#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
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(HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
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/***************************************************************************//**
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* The macro HAL_set_16bit_reg_field() is used to write a field within a
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* 16 bits wide register. The field written can be one or more bits.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* FIELD_NAME: A string identifying the register field to write. These strings
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* are specified in a header file associated with the peripheral.
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* VALUE: A variable of type uint16_t containing the field value to write.
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*/
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#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
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(HW_set_16bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME),\
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(VALUE)))
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/***************************************************************************//**
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* The macro HAL_get_16bit_reg_field() is used to read a register field from
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* within a 8 bit wide peripheral register. The field can be one or more bits.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* FIELD_NAME: A string identifying the register field to write. These strings
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* are specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint16_t value.
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*/
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#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
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(HW_get_16bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME)))
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/***************************************************************************//**
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* The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to write. These strings are
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* specified in a header file associated with the peripheral.
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* VALUE: A variable of type uint_fast8_t containing the value to write.
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*/
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#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
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(HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
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/***************************************************************************//**
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* The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
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* register.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* REG_NAME: A string identifying the register to read. These strings are
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* specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint8_t value.
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*/
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#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
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(HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
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/***************************************************************************//**
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*/
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#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
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(HW_set_8bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME),\
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(VALUE)))
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/***************************************************************************//**
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* The macro HAL_get_8bit_reg_field() is used to read a register field from
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* within a 8 bit wide peripheral register. The field can be one or more bits.
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*
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* BASE_ADDR: A variable of type addr_t specifying the base address of the
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* peripheral containing the register.
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* FIELD_NAME: A string identifying the register field to write. These strings
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* are specified in a header file associated with the peripheral.
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* RETURN: This function-like macro returns a uint8_t value.
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*/
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#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
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(HW_get_8bit_reg_field(\
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(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
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FIELD_SHIFT(FIELD_NAME),\
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FIELD_MASK(FIELD_NAME)))
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#endif /*HAL_H_*/
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/*******************************************************************************
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* (c) Copyright 2008-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#ifndef HAL_ASSERT_HEADER
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#define HAL_ASSERT_HEADER
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#define NDEBUG 1
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#if defined(NDEBUG)
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/***************************************************************************//**
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* HAL_ASSERT() is defined out when the NDEBUG symbol is used.
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******************************************************************************/
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#define HAL_ASSERT(CHECK)
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#else
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/***************************************************************************//**
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* Default behaviour for HAL_ASSERT() macro:
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*------------------------------------------------------------------------------
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The behaviour is toolchain specific and project setting specific.
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******************************************************************************/
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#define HAL_ASSERT(CHECK) ASSERT(CHECK);
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#endif /* NDEBUG */
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#endif /* HAL_ASSERT_HEADER */
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/***************************************************************************//**
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* Legacy interrupt control functions for the Microsemi driver library hardware
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* abstraction layer.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#include "hal.h"
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#include "riscv_hal.h"
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/*------------------------------------------------------------------------------
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*
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*/
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void HAL_enable_interrupts(void) {
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__enable_irq();
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}
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/*------------------------------------------------------------------------------
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*
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*/
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psr_t HAL_disable_interrupts(void) {
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psr_t psr;
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psr = read_csr(mstatus);
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__disable_irq();
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return(psr);
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}
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/*------------------------------------------------------------------------------
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*
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*/
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void HAL_restore_interrupts(psr_t saved_psr) {
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write_csr(mstatus, saved_psr);
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}
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/*******************************************************************************
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* Hardware registers access macros.
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*
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* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
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* DEVELOPMENT.
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*
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* These macros are used to access peripheral's registers. They allow access to
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* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
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* be done through these macros in order to ease porting across different
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* processors/bus architectures.
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*
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* Some of these macros also allow to access a specific register field.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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#ifndef __HW_REGISTER_MACROS_H
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#define __HW_REGISTER_MACROS_H 1
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/*------------------------------------------------------------------------------
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* 32 bits registers access:
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*/
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#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint32_t) \
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( \
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(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 32 bits memory access:
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*/
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#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
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#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
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/*------------------------------------------------------------------------------
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* 16 bits registers access:
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*/
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#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint16_t) \
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( \
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(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits registers access:
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*/
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#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
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#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
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#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
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( \
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(uint8_t) \
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( \
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(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
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(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
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) \
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)
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#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
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(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
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/*------------------------------------------------------------------------------
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* 8 bits memory access:
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*/
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#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
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#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
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#endif /* __HW_REGISTER_MACROS_H */
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@ -0,0 +1,209 @@
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/***************************************************************************//**
|
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* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
|
||||
*
|
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* Hardware registers access functions.
|
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* The implementation of these function is platform and toolchain specific.
|
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* The functions declared here are implemented using assembler as part of the
|
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* processor/toolchain specific HAL.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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.section .text
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.globl HW_set_32bit_reg
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.globl HW_get_32bit_reg
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.globl HW_set_32bit_reg_field
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.globl HW_get_32bit_reg_field
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.globl HW_set_16bit_reg
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.globl HW_get_16bit_reg
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.globl HW_set_16bit_reg_field
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.globl HW_get_16bit_reg_field
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||||
.globl HW_set_8bit_reg
|
||||
.globl HW_get_8bit_reg
|
||||
.globl HW_set_8bit_reg_field
|
||||
.globl HW_get_8bit_reg_field
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: uint32_t value
|
||||
*/
|
||||
HW_set_32bit_reg:
|
||||
sw a1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* R0: addr_t reg_addr
|
||||
* @return 32 bits value read from the peripheral register.
|
||||
*/
|
||||
HW_get_32bit_reg:
|
||||
lw a0, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint32_t mask
|
||||
* a3: uint32_t value
|
||||
*/
|
||||
HW_set_32bit_reg_field:
|
||||
mv t3, a3
|
||||
sll t3, t3, a1
|
||||
and t3, t3, a2
|
||||
lw t1, 0(a0)
|
||||
mv t2, a2
|
||||
not t2, t2
|
||||
and t1, t1, t2
|
||||
or t1, t1, t3
|
||||
sw t1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_32bit_reg_field is used to read the content of a field out of a
|
||||
* 32 bits wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint32_t mask
|
||||
*
|
||||
* @return 32 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
HW_get_32bit_reg_field:
|
||||
lw a0, 0(a0)
|
||||
and a0, a0, a2
|
||||
srl a0, a0, a1
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: uint_fast16_t value
|
||||
*/
|
||||
HW_set_16bit_reg:
|
||||
sh a1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* @return 16 bits value read from the peripheral register.
|
||||
*/
|
||||
HW_get_16bit_reg:
|
||||
lh a0, (a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint_fast16_t mask
|
||||
* a3: uint_fast16_t value
|
||||
* @param value Value to be written in the specified field.
|
||||
*/
|
||||
HW_set_16bit_reg_field:
|
||||
mv t3, a3
|
||||
sll t3, t3, a1
|
||||
and t3, t3, a2
|
||||
lh t1, 0(a0)
|
||||
mv t2, a2
|
||||
not t2, t2
|
||||
and t1, t1, t2
|
||||
or t1, t1, t3
|
||||
sh t1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_16bit_reg_field is used to read the content of a field from a
|
||||
* 16 bits wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint_fast16_t mask
|
||||
*
|
||||
* @return 16 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
HW_get_16bit_reg_field:
|
||||
lh a0, 0(a0)
|
||||
and a0, a0, a2
|
||||
srl a0, a0, a1
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: uint_fast8_t value
|
||||
*/
|
||||
HW_set_8bit_reg:
|
||||
sb a1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* @return 8 bits value read from the peripheral register.
|
||||
*/
|
||||
HW_get_8bit_reg:
|
||||
lb a0, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr,
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint_fast8_t mask
|
||||
* a3: uint_fast8_t value
|
||||
*/
|
||||
HW_set_8bit_reg_field:
|
||||
mv t3, a3
|
||||
sll t3, t3, a1
|
||||
and t3, t3, a2
|
||||
lb t1, 0(a0)
|
||||
mv t2, a2
|
||||
not t2, t2
|
||||
and t1, t1, t2
|
||||
or t1, t1, t3
|
||||
sb t1, 0(a0)
|
||||
ret
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_8bit_reg_field is used to read the content of a field from a
|
||||
* 8 bits wide peripheral register.
|
||||
*
|
||||
* a0: addr_t reg_addr
|
||||
* a1: int_fast8_t shift
|
||||
* a2: uint_fast8_t mask
|
||||
*
|
||||
* @return 8 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
HW_get_8bit_reg_field:
|
||||
lb a0, 0(a0)
|
||||
and a0, a0, a2
|
||||
srl a0, a0, a1
|
||||
ret
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
/***************************************************************************//**
|
||||
* (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
|
||||
*
|
||||
* Hardware registers access functions.
|
||||
* The implementation of these function is platform and toolchain specific.
|
||||
* The functions declared here are implemented using assembler as part of the
|
||||
* processor/toolchain specific HAL.
|
||||
*
|
||||
* SVN $Revision: 9661 $
|
||||
* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
|
||||
*/
|
||||
#ifndef HW_REG_ACCESS
|
||||
#define HW_REG_ACCESS
|
||||
|
||||
#include "cpu_types.h"
|
||||
/***************************************************************************//**
|
||||
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* write.
|
||||
* @param value Value to be written into the peripheral register.
|
||||
*/
|
||||
void
|
||||
HW_set_32bit_reg
|
||||
(
|
||||
addr_t reg_addr,
|
||||
uint32_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @return 32 bits value read from the peripheral register.
|
||||
*/
|
||||
uint32_t
|
||||
HW_get_32bit_reg
|
||||
(
|
||||
addr_t reg_addr
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* be written.
|
||||
* @param shift Bit offset of the register field to be read within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
* @param value Value to be written in the specified field.
|
||||
*/
|
||||
void
|
||||
HW_set_32bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint32_t mask,
|
||||
uint32_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_32bit_reg_field is used to read the content of a field out of a
|
||||
* 32 bits wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @param shift Bit offset of the register field to be written within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
*
|
||||
* @return 32 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
uint32_t
|
||||
HW_get_32bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint32_t mask
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* write.
|
||||
* @param value Value to be written into the peripheral register.
|
||||
*/
|
||||
void
|
||||
HW_set_16bit_reg
|
||||
(
|
||||
addr_t reg_addr,
|
||||
uint_fast16_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @return 16 bits value read from the peripheral register.
|
||||
*/
|
||||
uint16_t
|
||||
HW_get_16bit_reg
|
||||
(
|
||||
addr_t reg_addr
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* be written.
|
||||
* @param shift Bit offset of the register field to be read within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
* @param value Value to be written in the specified field.
|
||||
*/
|
||||
void HW_set_16bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint_fast16_t mask,
|
||||
uint_fast16_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_16bit_reg_field is used to read the content of a field from a
|
||||
* 16 bits wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @param shift Bit offset of the register field to be written within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
*
|
||||
* @return 16 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
uint16_t HW_get_16bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint_fast16_t mask
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* write.
|
||||
* @param value Value to be written into the peripheral register.
|
||||
*/
|
||||
void
|
||||
HW_set_8bit_reg
|
||||
(
|
||||
addr_t reg_addr,
|
||||
uint_fast8_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
|
||||
* register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @return 8 bits value read from the peripheral register.
|
||||
*/
|
||||
uint8_t
|
||||
HW_get_8bit_reg
|
||||
(
|
||||
addr_t reg_addr
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
|
||||
* wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* be written.
|
||||
* @param shift Bit offset of the register field to be read within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
* @param value Value to be written in the specified field.
|
||||
*/
|
||||
void HW_set_8bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint_fast8_t mask,
|
||||
uint_fast8_t value
|
||||
);
|
||||
|
||||
/***************************************************************************//**
|
||||
* HW_get_8bit_reg_field is used to read the content of a field from a
|
||||
* 8 bits wide peripheral register.
|
||||
*
|
||||
* @param reg_addr Address in the processor's memory map of the register to
|
||||
* read.
|
||||
* @param shift Bit offset of the register field to be written within the
|
||||
* register.
|
||||
* @param mask Bit mask to be applied to the raw register value to filter
|
||||
* out the other register fields values.
|
||||
*
|
||||
* @return 8 bits value containing the register field value specified
|
||||
* as parameter.
|
||||
*/
|
||||
uint8_t HW_get_8bit_reg_field
|
||||
(
|
||||
addr_t reg_addr,
|
||||
int_fast8_t shift,
|
||||
uint_fast8_t mask
|
||||
);
|
||||
|
||||
#endif /* HW_REG_ACCESS */
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue