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cortex-r82: Minor code improvements
This commit includes minor code improvements to enhance readability and maintainability of the Cortex-R82 port files. Changes include refactoring variable names, optimizing comments, and improving code structure without altering functionality. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
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Ahmed Ismail
parent
3cca1ec00e
commit
8e8d4152e3
3 changed files with 124 additions and 105 deletions
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@ -52,13 +52,13 @@
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/* Variables and functions. */
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#if ( configNUMBER_OF_CORES == 1 )
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.extern pxCurrentTCB
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.extern ullCriticalNesting
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.extern ullPortInterruptNesting
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.extern pxCurrentTCB
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.extern ullCriticalNesting
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.extern ullPortInterruptNesting
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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.extern pxCurrentTCBs
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.extern ullCriticalNestings
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.extern ullPortInterruptNestings
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.extern pxCurrentTCBs
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.extern ullCriticalNestings
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.extern ullPortInterruptNestings
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#endif
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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@ -308,16 +308,16 @@ LDP Q0, Q1, [ SP ], # 0x20
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/* Store user allocated task stack and use ullContext as the SP */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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#else
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X1, [ X0 ]
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ADD X1, X1, #8 /* X1 = X1 + 8, X1 now points to ullTaskUnprivilegedSP in TCB. */
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@ -339,16 +339,16 @@ LDP Q0, Q1, [ SP ], # 0x20
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#endif
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CBNZ X0, 3f /* If task is privileged, skip saving MPU context. */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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#else
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X0, [ X0 ]
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@ -369,8 +369,10 @@ LDP Q0, Q1, [ SP ], # 0x20
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#endif /* #if ( configENABLE_MPU == 1 ) */
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MSR SPSEL, # 0
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/* Save the entire context. */
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saveallgpregisters
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/* Save the SPSR and ELR values. */
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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@ -379,24 +381,25 @@ STP X2, X3, [ SP, # - 0x10 ] !
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/* Save the critical section nesting depth. */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, ullCriticalNesting
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add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */
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adrp X0, ullCriticalNesting
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add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */
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#else
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adrp X0, ullCriticalNestings
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add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */
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/* Calculate per-core index using MPIDR_EL1 for SMP support. */
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MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */
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AND X1, X1, # 0xff /* Extract Aff0 (core ID). */
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LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */
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ADD X0, X0, X1 /* Add offset to base address. */
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adrp X0, ullCriticalNestings
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add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */
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/* Calculate per-core index using MPIDR_EL1 for SMP support. */
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MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */
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AND X1, X1, # 0xff /* Extract Aff0 (core ID). */
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LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */
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ADD X0, X0, X1 /* Add offset to base address. */
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#endif
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LDR X3, [ X0 ]
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/* Save the FPU context indicator. */
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adrp X0, ullPortTaskHasFPUContext
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add X0, X0, :lo12:ullPortTaskHasFPUContext /* X0 = &ullPortTaskHasFPUContext */
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#if configNUMBER_OF_CORES > 1
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#if ( configNUMBER_OF_CORES > 1 )
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ADD X0, X0, X1 /* Add to the base of the FPU array. */
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#endif
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LDR X2, [ X0 ]
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@ -547,16 +550,16 @@ MSR SPSEL, # 1
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STP X8, X9, [ SP, # - 0x10 ] !
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STR X10, [ SP, # - 0x10 ] !
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X8, pxCurrentTCB
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add X8, X8, :lo12:pxCurrentTCB /* X8 = &pxCurrentTCB */
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adrp X8, pxCurrentTCB
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add X8, X8, :lo12:pxCurrentTCB /* X8 = &pxCurrentTCB */
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#else
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adrp X8, pxCurrentTCBs
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add X8, X8, :lo12:pxCurrentTCBs /* X8 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X10, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X10, X10, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X10, X10, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X8, X8, X10 /* Add the offset for the current core's TCB pointer */
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adrp X8, pxCurrentTCBs
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add X8, X8, :lo12:pxCurrentTCBs /* X8 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X10, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X10, X10, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X10, X10, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X8, X8, X10 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X9, [ X8 ]
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MRS X8, SP_EL0
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@ -926,8 +929,8 @@ LDP X0, X1, [SP], #0x10
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portSAVE_CONTEXT
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savefuncontextgpregs
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#if ( configNUMBER_OF_CORES > 1 )
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MRS x0, mpidr_el1
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AND x0, x0, 255
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MRS x0, mpidr_el1
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AND x0, x0, 255
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#endif
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BL vTaskSwitchContext
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restorefuncontextgpregs
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@ -1039,12 +1042,12 @@ ISB SY
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/* Restore the interrupt ID value. */
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LDP X0, X1, [ SP ], # 0x10
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/* End IRQ processing by writing interrupt ID value to the EOI register. */
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MSR ICC_EOIR1_EL1, X0
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/* Restore the critical nesting count. */
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LDP X1, X5, [ SP ], # 0x10
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STR X1, [ X5 ]
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/* Has interrupt nesting unwound? */
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@ -1095,8 +1098,8 @@ restoreallgpregisters
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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#if configNUMBER_OF_CORES > 1
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MRS x0, mpidr_el1
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AND x0, x0, 255
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MRS x0, mpidr_el1
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AND x0, x0, 255
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#endif
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savefuncontextgpregs
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BL vTaskSwitchContext
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@ -1116,7 +1119,7 @@ ISB SY
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restorefloatregisters
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restoreallgpregisters
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ERET
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ERET
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/******************************************************************************
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* If the application provides an implementation of vApplicationIRQHandler(),
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