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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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armv8-m: Remove redundant constant pools (#1035)
Currently in Armv8-M GCC/ArmClang ports, constant pool is used to define literals needed for `ldr` instructions. However, those constant pools are defined with `.align 4` which increases code size. Instead of defining the constant pool with `.align 4`, let the compiler hanlde the constant pool and the required alignment. Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
Devaraj Ranganna
GitHub
parent
bbc058967b
commit
8d280217cd
15 changed files with 372 additions and 786 deletions
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@ -56,11 +56,11 @@
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" .syntax unified \n"
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" \n"
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" program_mpu_first_task: \n"
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" ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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@ -68,34 +68,34 @@
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
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" movs r3, #5 \n" /* r3 = 5. */
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" str r3, [r1] \n" /* Program RNR = 5. */
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" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
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" movs r3, #6 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 6. */
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" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
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" movs r3, #7 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 7. */
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" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
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" \n"
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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@ -103,7 +103,7 @@
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" restore_context_first_task: \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
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" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
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" \n"
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@ -137,13 +137,6 @@
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" restore_context_done_first_task: \n"
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" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
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" bx lr \n"
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" \n"
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" .align 4 \n"
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" pxCurrentTCBConst2: .word pxCurrentTCB \n"
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" xMPUCTRLConst2: .word 0xe000ed94 \n"
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" xMAIR0Const2: .word 0xe000edc0 \n"
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" xRNRConst2: .word 0xe000ed98 \n"
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" xRBARConst2: .word 0xe000ed9c \n"
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);
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}
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@ -155,7 +148,7 @@
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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@ -169,9 +162,6 @@
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" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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" isb \n"
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" bx r2 \n" /* Finally, branch to EXC_RETURN. */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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);
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}
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@ -193,8 +183,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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" running_privileged: \n"
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" movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n" /* Return. */
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" \n"
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" .align 4 \n"
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::: "r0", "r1", "memory"
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);
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}
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@ -238,7 +226,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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(
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" .syntax unified \n"
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" \n"
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" ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
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" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
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" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
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@ -247,9 +235,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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" isb \n"
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" svc %0 \n" /* System call to start the first task. */
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" nop \n"
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" \n"
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" .align 4 \n"
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"xVTORConst: .word 0xe000ed08 \n"
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::"i" ( portSVC_START_SCHEDULER ) : "memory"
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);
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}
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@ -290,7 +275,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
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" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
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" mrs r2, psp \n" /* r2 = PSP. */
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@ -325,11 +310,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" cpsie i \n"
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" \n"
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" program_mpu: \n"
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" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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@ -337,34 +322,34 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
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" movs r3, #5 \n" /* r3 = 5. */
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" str r3, [r1] \n" /* Program RNR = 5. */
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" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
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" movs r3, #6 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 6. */
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" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
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" movs r3, #7 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 7. */
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" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
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" \n"
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" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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@ -372,7 +357,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" restore_context: \n"
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" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
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" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
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" \n"
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@ -406,13 +391,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" restore_context_done: \n"
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" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
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" bx lr \n"
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" \n"
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" .align 4 \n"
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" pxCurrentTCBConst: .word pxCurrentTCB \n"
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" xMPUCTRLConst: .word 0xe000ed94 \n"
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" xMAIR0Const: .word 0xe000edc0 \n"
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" xRNRConst: .word 0xe000ed98 \n"
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" xRBARConst: .word 0xe000ed9c \n"
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);
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}
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@ -425,7 +403,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" .syntax unified \n"
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" \n"
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" mrs r0, psp \n" /* Read PSP in r0. */
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" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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" subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
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" str r0, [r1] \n" /* Save the new top of stack in TCB. */
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@ -446,7 +424,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" bl vTaskSwitchContext \n"
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" cpsie i \n"
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" \n"
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" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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" \n"
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@ -463,9 +441,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
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#endif
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" bx r3 \n"
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst: .word pxCurrentTCB \n"
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);
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}
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@ -528,15 +503,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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" tst r0, r1 \n"
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" beq stacking_used_msp \n"
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" mrs r0, psp \n"
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" ldr r2, svchandler_address_const \n"
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" ldr r2, =vPortSVCHandler_C \n"
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" bx r2 \n"
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" stacking_used_msp: \n"
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" mrs r0, msp \n"
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" ldr r2, svchandler_address_const \n"
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" ldr r2, =vPortSVCHandler_C \n"
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" bx r2 \n"
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" \n"
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" .align 4 \n"
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"svchandler_address_const: .word vPortSVCHandler_C \n"
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);
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}
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