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Revert Portable/MPLAB Formatting (#883)
* Revert the formatting PR * Fix spelling mistakes --------- Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
Soren Ptak
GitHub
parent
2dfc5142f4
commit
8d1da77d0d
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@ -27,32 +27,32 @@
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*/
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/*
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* Changes between V1.2.4 and V1.2.5
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*
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Changes between V1.2.4 and V1.2.5
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+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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+ interrupt flag setting. Using the two bits defined within
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+ portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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+ before the test was performed.
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+
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+ Changes from V1.2.5
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+
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interrupt flag setting. Using the two bits defined within
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portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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before the test was performed.
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Changes from V1.2.5
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+ Set the interrupt vector address to 0x08. Previously it was at the
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+ incorrect address for compatibility mode of 0x18.
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+
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+ Changes from V2.1.1
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+
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incorrect address for compatibility mode of 0x18.
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Changes from V2.1.1
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+ PCLATU and PCLATH are now saved as part of the context. This allows
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+ function pointers to be used within tasks. Thanks to Javier Espeche
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+ for the enhancement.
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+
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+ Changes from V2.3.1
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+
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function pointers to be used within tasks. Thanks to Javier Espeche
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for the enhancement.
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Changes from V2.3.1
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+ TABLAT is now saved as part of the task context.
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+
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+ Changes from V3.2.0
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+
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Changes from V3.2.0
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+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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+ value and does not write to the register.
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value and does not write to the register.
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*/
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/* Scheduler include files. */
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@ -70,24 +70,24 @@
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#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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/* Initial interrupt enable state for newly created tasks. This value is
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* copied into INTCON when a task switches in for the first time. */
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copied into INTCON when a task switches in for the first time. */
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#define portINITAL_INTERRUPT_STATE 0xc0
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/* Just the bit within INTCON for the global interrupt flag. */
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#define portGLOBAL_INTERRUPT_FLAG 0x80
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/* Constant used for context switch macro when we require the interrupt
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* enable state to be unchanged when the interrupted task is switched back in. */
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enable state to be unchanged when the interrupted task is switched back in. */
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#define portINTERRUPTS_UNCHANGED 0x00
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/* Some memory areas get saved as part of the task context. These memory
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* area's get used by the compiler for temporary storage, especially when
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* performing mathematical operations, or when using 32bit data types. This
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* constant defines the size of memory area which must be saved. */
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area's get used by the compiler for temporary storage, especially when
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performing mathematical operations, or when using 32bit data types. This
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constant defines the size of memory area which must be saved. */
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#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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/* We require the address of the pxCurrentTCB variable, but don't want to know
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* any details of its type. */
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any details of its type. */
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typedef void TCB_t;
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extern volatile TCB_t * volatile pxCurrentTCB;
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@ -136,7 +136,7 @@ static void prvLowInterrupt( void );
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*
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* The compiler uses some locations at the bottom of the memory for temporary
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* storage during math and other computations. This is especially true if
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* 32bit data types are used (as they are by the scheduler). The .tmpdata
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* 32bit data types are utilized (as they are by the scheduler). The .tmpdata
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* and MATH_DATA sections have to be stored in there entirety as part of a task
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* context. This macro stores from data address 0x00 to
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* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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@ -148,11 +148,11 @@ static void prvLowInterrupt( void );
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{ \
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_asm \
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/* Save the status and WREG registers first, as these will get modified \
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* by the operations below. */ \
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by the operations below. */ \
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MOVFF WREG, PREINC1 \
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MOVFF STATUS, PREINC1 \
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/* Save the INTCON register with the appropriate bits forced if \
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* necessary - as described above. */ \
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necessary - as described above. */ \
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MOVFF INTCON, WREG \
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IORLW ucForcedInterruptFlags \
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MOVFF WREG, PREINC1 \
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@ -201,7 +201,7 @@ static void prvLowInterrupt( void );
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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/* Store the hardware stack pointer in a temp register before we \
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* modify it. */ \
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modify it. */ \
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MOVFF STKPTR, FSR0L \
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_endasm \
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\
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@ -218,7 +218,7 @@ static void prvLowInterrupt( void );
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\
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_asm \
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/* Store the number of addresses on the hardware stack (from the \
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* temporary register). */ \
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temporary register). */ \
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MOVFF FSR0L, PREINC1 \
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MOVF PREINC1, 1, 0 \
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_endasm \
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@ -245,12 +245,12 @@ static void prvLowInterrupt( void );
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MOVFF pxCurrentTCB + 1, FSR0H \
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\
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/* De-reference FSR0 to set the address it holds into FSR1. \
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* (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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MOVFF POSTINC0, FSR1L \
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MOVFF POSTINC0, FSR1H \
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\
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/* How many return addresses are there on the hardware stack? Discard \
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* the first byte as we are pointing to the next free space. */ \
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the first byte as we are pointing to the next free space. */ \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, FSR0L \
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_endasm \
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@ -310,13 +310,13 @@ static void prvLowInterrupt( void );
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MOVFF POSTDEC1, FSR2L \
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MOVFF POSTDEC1, BSR \
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/* The next byte is the INTCON register. Read this into WREG as some \
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* manipulation is required. */ \
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manipulation is required. */ \
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MOVFF POSTDEC1, WREG \
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_endasm \
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\
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/* From the INTCON register, only the interrupt enable bits form part \
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* of the tasks context. It is perfectly legitimate for another task to \
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* have modified any other bits. We therefore only restore the top two bits. \
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of the tasks context. It is perfectly legitimate for another task to \
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have modified any other bits. We therefore only restore the top two bits. \
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*/ \
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if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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{ \
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@ -333,7 +333,7 @@ static void prvLowInterrupt( void );
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MOVFF POSTDEC1, STATUS \
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MOVFF POSTDEC1, WREG \
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/* Return without effecting interrupts. The context may have \
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* been saved from a critical region. */ \
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been saved from a critical region. */ \
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RETURN 0 \
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_endasm \
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} \
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@ -343,15 +343,13 @@ static void prvLowInterrupt( void );
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint32_t ulAddress;
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uint8_t ucBlock;
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/* Place a few bytes of known values on the bottom of the stack.
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* This is just useful for debugging. */
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This is just useful for debugging. */
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*pxTopOfStack = 0x11;
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pxTopOfStack++;
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@ -362,10 +360,10 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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/* Simulate how the stack would look after a call to vPortYield() generated
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* by the compiler.
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*
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* First store the function parameters. This is where the task will expect to
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* find them when it starts running. */
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by the compiler.
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First store the function parameters. This is where the task will expect to
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find them when it starts running. */
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ulAddress = ( uint32_t ) pvParameters;
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*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
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pxTopOfStack++;
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@ -375,9 +373,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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pxTopOfStack++;
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/* Next we just leave a space. When a context is saved the stack pointer
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* is incremented before it is used so as not to corrupt whatever the stack
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* pointer is actually pointing to. This is especially necessary during
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* function epilogue code generated by the compiler. */
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is incremented before it is used so as not to corrupt whatever the stack
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pointer is actually pointing to. This is especially necessary during
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function epilogue code generated by the compiler. */
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*pxTopOfStack = 0x44;
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pxTopOfStack++;
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@ -447,7 +445,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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pxTopOfStack++;
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/* The only function return address so far is the address of the
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* task. */
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task. */
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ulAddress = ( uint32_t ) pxCode;
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/* TOS low. */
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@ -465,7 +463,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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pxTopOfStack++;
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/* Store the number of return addresses on the hardware stack - so far only
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* the address of the task entry point. */
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the address of the task entry point. */
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*pxTopOfStack = ( StackType_t ) 1;
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pxTopOfStack++;
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@ -492,8 +490,8 @@ BaseType_t xPortStartScheduler( void )
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the scheduler for the PIC port will get stopped
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* once running. If required disable the tick interrupt here, then return
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* to xPortStartScheduler(). */
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once running. If required disable the tick interrupt here, then return
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to xPortStartScheduler(). */
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}
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/*-----------------------------------------------------------*/
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@ -505,7 +503,7 @@ void vPortEndScheduler( void )
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void vPortYield( void )
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{
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/* This can get called with interrupts either enabled or disabled. We
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* will save the INTCON register with the interrupt enable bits unmodified. */
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will save the INTCON register with the interrupt enable bits unmodified. */
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portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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/* Switch to the highest priority task that is ready to run. */
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@ -562,7 +560,7 @@ static void prvLowInterrupt( void )
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static void prvTickISR( void )
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{
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/* Interrupts must have been enabled for the ISR to fire, so we have to
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* save the context with interrupts enabled. */
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save the context with interrupts enabled. */
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portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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PIR1bits.CCP1IF = 0;
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@ -587,11 +585,11 @@ static void prvSetupTimerInterrupt( void )
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uint8_t ucByte;
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/* Interrupts are disabled when this function is called.
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*
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* Setup CCP1 to provide the tick interrupt using a compare match on timer
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* 1.
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*
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* Clear the time count then setup timer. */
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Setup CCP1 to provide the tick interrupt using a compare match on timer
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1.
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Clear the time count then setup timer. */
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TMR1H = ( uint8_t ) 0x00;
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TMR1L = ( uint8_t ) 0x00;
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@ -608,10 +606,10 @@ static void prvSetupTimerInterrupt( void )
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PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
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/* We are only going to use the global interrupt bit, so set the peripheral
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* bit to true. */
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bit to true. */
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INTCONbits.GIEL = portBIT_SET;
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/* Provided library function for setting up the timer that will produce the
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* tick. */
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tick. */
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OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
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}
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@ -75,16 +75,14 @@ typedef unsigned char UBaseType_t;
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#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
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/* Push the INTCON register onto the stack, then disable interrupts. */
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#define portENTER_CRITICAL() \
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POSTINC1 = INTCON; \
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#define portENTER_CRITICAL() POSTINC1 = INTCON; \
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INTCONbits.GIEH = 0;
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/* Retrieve the INTCON register from the stack, and enable interrupts
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* if they were saved as being enabled. Don't modify any other bits
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* within the INTCON register as these may have legitimately have been
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* modified within the critical region. */
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#define portEXIT_CRITICAL() \
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_asm \
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if they were saved as being enabled. Don't modify any other bits
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within the INTCON register as these may have legitimately have been
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modified within the critical region. */
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#define portEXIT_CRITICAL() _asm \
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MOVF POSTDEC1, 1, 0 \
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_endasm \
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if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
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@ -109,8 +107,7 @@ extern void vPortYield( void );
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#endif
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#define portNOP() \
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_asm \
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#define portNOP() _asm \
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NOP \
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_endasm
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@ -27,8 +27,8 @@
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*/
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/*
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* Changes from V4.2.1
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*
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Changes from V4.2.1
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+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
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*/
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@ -46,13 +46,13 @@
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#define portINITIAL_SR 0
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/* Defined for backward compatability with project created prior to
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* FreeRTOS.org V4.3.0. */
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FreeRTOS.org V4.3.0. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 1
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#endif
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/* Use _T1Interrupt as the interrupt handler name if the application writer has
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* not provided their own. */
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not provided their own. */
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#ifndef configTICK_INTERRUPT_HANDLER
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#define configTICK_INTERRUPT_HANDLER _T1Interrupt
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#endif /* configTICK_INTERRUPT_HANDLER */
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@ -149,7 +149,7 @@ UBaseType_t uxCriticalNesting = 0xef;
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#error Unrecognised device selected
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/* Note: dsPIC parts with EDS are not supported as there is no easy way to
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* recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
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recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
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#endif
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/*
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@ -160,9 +160,7 @@ void vApplicationSetupTickTimerInterrupt( void );
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint16_t usCode;
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UBaseType_t i;
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@ -199,19 +197,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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0x1010, /* DOSTARTH */
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0x1110, /* DOENDL */
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0x1212, /* DOENDH */
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#endif /* if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
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#endif
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};
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/* Setup the stack as if a yield had occurred.
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*
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* Save the low bytes of the program counter. */
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Save the low bytes of the program counter. */
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usCode = ( uint16_t ) pxCode;
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*pxTopOfStack = ( StackType_t ) usCode;
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pxTopOfStack++;
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/* Save the high byte of the program counter. This will always be zero
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* here as it is passed in a 16bit pointer. If the address is greater than
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* 16 bits then the pointer will point to a jump table. */
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here as it is passed in a 16bit pointer. If the address is greater than
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16 bits then the pointer will point to a jump table. */
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*pxTopOfStack = ( StackType_t ) 0;
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pxTopOfStack++;
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@ -269,7 +267,7 @@ BaseType_t xPortStartScheduler( void )
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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* Artificially force an assert. */
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Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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@ -316,7 +314,6 @@ void vPortExitCritical( void )
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{
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configASSERT( uxCriticalNesting );
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uxCriticalNesting--;
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if( uxCriticalNesting == 0 )
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{
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portENABLE_INTERRUPTS();
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|
|
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@ -63,7 +63,6 @@ typedef unsigned short UBaseType_t;
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#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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/* 16-bit tick type on a 16-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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@ -85,8 +84,8 @@ typedef unsigned short UBaseType_t;
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#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
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#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 )
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/* Note that exiting a critical section will set the IPL bits to 0, no
|
||||
* matter what their value was prior to entering the critical section. */
|
||||
/* Note that exiting a critical sectino will set the IPL bits to 0, no matter
|
||||
what their value was prior to entering the critical section. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
|
|
@ -95,8 +94,7 @@ extern void vPortExitCritical( void );
|
|||
|
||||
/* Task utilities. */
|
||||
extern void vPortYield( void );
|
||||
#define portYIELD() \
|
||||
asm volatile ( "CALL _vPortYield \n" \
|
||||
#define portYIELD() asm volatile ( "CALL _vPortYield \n" \
|
||||
"NOP " );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,36 +38,36 @@
|
|||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
* maintain the values of these registers across the ISR. */
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Prepare to enable interrupts above the current priority.
|
||||
* k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
|
||||
k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
|
||||
srl k0, k0, 0xa
|
||||
|
||||
/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
|
||||
ins k1, k0, 10, 7
|
||||
|
||||
/* Sets CP0.Status.IPL = CP0.Cause.RIPL
|
||||
* Copy the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
Copy the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
srl k0, k0, 0x7
|
||||
|
||||
/* MSB of IPL is bit[18] of CP0.Status */
|
||||
ins k1, k0, 18, 1
|
||||
|
||||
/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
|
||||
* b[3]=Rsvd, b[2]=ERL, b[1]=EXL
|
||||
* Setting EXL=0 allows higher priority interrupts
|
||||
* to preempt this handler */
|
||||
b[3]=Rsvd, b[2]=ERL, b[1]=EXL
|
||||
Setting EXL=0 allows higher priority interrupts
|
||||
to preempt this handler */
|
||||
ins k1, zero, 1, 4
|
||||
|
||||
|
||||
|
|
@ -79,7 +79,7 @@
|
|||
lw s6, (k0)
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
|
|
@ -98,8 +98,8 @@
|
|||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5) /* Return address (RA=R31) */
|
||||
sw s8, 116(s5) /* Frame Pointer (FP=R30) */
|
||||
sw t9, 112(s5)
|
||||
|
|
@ -144,7 +144,7 @@
|
|||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
|
|
@ -154,7 +154,7 @@
|
|||
lw s5, (s6)
|
||||
|
||||
/* Restore the context.
|
||||
* MCHP MEC14xx does not include DSP */
|
||||
MCHP MEC14xx does not include DSP */
|
||||
1:
|
||||
lw s6, 8(s5)
|
||||
mtlo s6
|
||||
|
|
@ -163,7 +163,7 @@
|
|||
lw $1, 16(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
as part of the interrupt context. */
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
|
|
@ -198,7 +198,7 @@
|
|||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@
|
|||
#define portEXL_BIT ( 0x00000002 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/* MEC14xx RTOS Timer MMCR's. */
|
||||
|
|
@ -59,7 +59,7 @@
|
|||
#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
|
||||
|
||||
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
|
||||
* peripheral space. */
|
||||
peripheral space. */
|
||||
#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
|
||||
#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
|
||||
|
|
@ -74,17 +74,17 @@
|
|||
#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
* can override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
* behaviour for the specified interrupt vector.
|
||||
* 3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
* handler.
|
||||
By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
can override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
behaviour for the specified interrupt vector.
|
||||
3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
handler.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
|
|
@ -96,8 +96,8 @@
|
|||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
* in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
|
|
@ -105,27 +105,25 @@
|
|||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
|
@ -141,7 +139,7 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
|
|
@ -151,7 +149,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
|
|||
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. */
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -159,9 +157,7 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
|
@ -196,7 +192,6 @@ static __inline uint32_t prvDisableInterrupt( void )
|
|||
uint32_t prev_state;
|
||||
|
||||
__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
|
||||
|
||||
return prev_state;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -204,17 +199,14 @@ static __inline uint32_t prvDisableInterrupt( void )
|
|||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -251,7 +243,7 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
|||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -272,7 +264,7 @@ BaseType_t xPortStartScheduler( void )
|
|||
portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
|
||||
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
* priority */
|
||||
priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
|
||||
|
|
@ -280,18 +272,18 @@ BaseType_t xPortStartScheduler( void )
|
|||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
* by the time we get here. */
|
||||
by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
* location is loaded into uxSavedTaskStackPointer. */
|
||||
location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
|
|
@ -331,11 +323,11 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
|||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
|
|
|
|||
|
|
@ -77,9 +77,8 @@ typedef unsigned long UBaseType_t;
|
|||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
* never have higher IPL bits set anyway. */
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
|
|
@ -142,13 +141,13 @@ static inline void vPortSetCP0Cause( uint32_t new_cause )
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
|
|
|
|||
|
|
@ -36,14 +36,14 @@
|
|||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
* maintain the values of these registers across the ISR. */
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
|
@ -61,7 +61,7 @@ la k0, uxInterruptNesting
|
|||
lw s6, (k0)
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
|
|
@ -80,8 +80,8 @@ mfc0 s6, _CP0_EPC
|
|||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
|
|
@ -126,7 +126,7 @@ sw s5, ( s6 )
|
|||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
|
|
@ -141,9 +141,8 @@ mtlo s6
|
|||
lw s6, 12(s5)
|
||||
mthi s6
|
||||
lw $1, 16(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
as part of the interrupt context. */
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
|
|
@ -178,7 +177,7 @@ lw k0, portSTATUS_STACK_LOCATION( s5 )
|
|||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
|
|
|||
|
|
@ -51,25 +51,25 @@
|
|||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. */
|
||||
the first task is being restored. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
* override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
* to generate the tick interrupt. For example, when timer 1 is used then
|
||||
* configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
* configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
* 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
* timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
* used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
* IFS0CLR = _IFS0_T1IF_MASK.
|
||||
By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
to generate the tick interrupt. For example, when timer 1 is used then
|
||||
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
|
|
@ -81,8 +81,8 @@
|
|||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
* debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
|
|
@ -90,27 +90,25 @@
|
|||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
|
@ -142,7 +140,7 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
|
|
@ -152,7 +150,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
|
|||
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. */
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -160,9 +158,7 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure 8 byte alignment is maintained when the context is popped from
|
||||
* stack. The size of the context is 33 words (132 bytes). */
|
||||
|
|
@ -197,17 +193,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -243,7 +236,7 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
|||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -272,18 +265,18 @@ BaseType_t xPortStartScheduler( void )
|
|||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
* disabled by the time we get here. */
|
||||
disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
* Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
|
|
@ -318,13 +311,12 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
|||
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ typedef unsigned long UBaseType_t;
|
|||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#else
|
||||
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
|
||||
|
|
@ -88,13 +88,13 @@ typedef unsigned long UBaseType_t;
|
|||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
|
||||
/******************************************************************/
|
||||
.macro portSAVE_FPU_REGS offset, base
|
||||
|
||||
/* Macro to assist with saving just the FPU registers to the
|
||||
* specified address and base offset,
|
||||
* offset is a constant, base is the base pointer register */
|
||||
|
|
@ -79,7 +78,6 @@ sdc1 $f0, \ offset + 0 ( \ base )
|
|||
|
||||
/******************************************************************/
|
||||
.macro portLOAD_FPU_REGS offset, base
|
||||
|
||||
/* Macro to assist with loading just the FPU registers from the
|
||||
* specified address and base offset, offset is a constant,
|
||||
* base is the base pointer register */
|
||||
|
|
@ -123,16 +121,15 @@ ldc1 $f31, \ offset + 248 ( \ base )
|
|||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
/* Test if we are already using the system stack. Only tasks may use the
|
||||
* FPU so if we are already in a nested interrupt then the FPU context does
|
||||
* not require saving. */
|
||||
FPU so if we are already in a nested interrupt then the FPU context does
|
||||
not require saving. */
|
||||
la k1, uxInterruptNesting
|
||||
lw k1, 0(k1)
|
||||
bne k1, zero, 2f
|
||||
|
|
@ -152,12 +149,12 @@ addiu sp, sp, -portCONTEXT_SIZE
|
|||
sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
|
||||
|
||||
2:
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
#endif
|
||||
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
|
||||
* should maintain the values of these registers across the ISR. */
|
||||
should maintain the values of these registers across the ISR. */
|
||||
sw s7, 48(sp)
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
|
|
@ -178,7 +175,7 @@ la k0, uxInterruptNesting
|
|||
lw s6, (k0)
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
|
|
@ -197,8 +194,8 @@ mfc0 s6, _CP0_EPC
|
|||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
|
|
@ -221,7 +218,7 @@ sw s6, portEPC_STACK_LOCATION( s5 )
|
|||
sw $1, 16(s5)
|
||||
|
||||
/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
|
||||
* scratch register. */
|
||||
scratch register. */
|
||||
mfhi s6, $ac1
|
||||
sw s6, 128(s5)
|
||||
mflo s6, $ac1
|
||||
|
|
@ -259,6 +256,7 @@ sw s6, 8 ( s5 )
|
|||
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the FPU registers. */
|
||||
portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
|
|
@ -267,7 +265,7 @@ sw s6, 8 ( s5 )
|
|||
sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
|
||||
|
||||
1:
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
#endif
|
||||
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
|
|
@ -286,7 +284,7 @@ sw s5, ( s6 )
|
|||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
|
|
@ -300,13 +298,14 @@ lw s5, ( s6 )
|
|||
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Restore the FPU registers. */
|
||||
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
/* Restore the FPU status register. */
|
||||
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
|
||||
ctc1 s6, $f31
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
#endif
|
||||
|
||||
1:
|
||||
|
||||
|
|
@ -337,7 +336,7 @@ mthi s6, $ac0
|
|||
lw $1, 16(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
as part of the interrupt context. */
|
||||
lw s7, 48(s5)
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
|
|
@ -388,7 +387,7 @@ sw k1, 0 ( k0 )
|
|||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
|
|
@ -402,21 +401,21 @@ sw k1, 0 ( k0 )
|
|||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
2: /* Adjust the stack pointer */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
#else
|
||||
|
||||
/* Restore the frame when there is no hardware FP support. */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@
|
|||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. */
|
||||
the first task is being restored. */
|
||||
#if ( __mips_hard_float == 1 )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
|
||||
#else
|
||||
|
|
@ -72,26 +72,26 @@
|
|||
#endif
|
||||
|
||||
/* The initial value to store into the FPU status and control register. This is
|
||||
* only used on parts that support a hardware FPU. */
|
||||
only used on parts that support a hardware FPU. */
|
||||
#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
|
||||
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
* override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
* to generate the tick interrupt. For example, when timer 1 is used then
|
||||
* configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
* configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
* 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
* timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
* used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
* IFS0CLR = _IFS0_T1IF_MASK.
|
||||
By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
to generate the tick interrupt. For example, when timer 1 is used then
|
||||
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
|
|
@ -103,8 +103,8 @@
|
|||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
* debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
|
|
@ -112,27 +112,25 @@
|
|||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
|
@ -147,7 +145,7 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
|
|
@ -157,13 +155,13 @@ UBaseType_t uxSavedTaskStackPointer = 0;
|
|||
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
* is required to allow double word floating point stack pushes generated by the
|
||||
* compiler. */
|
||||
the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
is required to allow double word floating point stack pushes generated by the
|
||||
compiler. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
|
||||
|
||||
/* Saved as part of the task context. Set to pdFALSE if the task does not
|
||||
* require an FPU context. */
|
||||
require an FPU context. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
uint32_t ulTaskHasFPUContext = 0;
|
||||
#endif
|
||||
|
|
@ -173,9 +171,7 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure 8 byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
|
@ -214,17 +210,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -260,7 +253,7 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
|||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -289,18 +282,18 @@ BaseType_t xPortStartScheduler( void )
|
|||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
* disabled by the time we get here. */
|
||||
disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
* Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
|
|
@ -335,13 +328,12 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
|||
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
|
|
@ -366,7 +358,7 @@ void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
|||
vPortInitialiseFPSCR(portINITIAL_FPSCR);
|
||||
|
||||
/* A task is registering the fact that it needs a FPU context. Set the
|
||||
* FPU flag (saved as part of the task context). */
|
||||
FPU flag (saved as part of the task context). */
|
||||
ulTaskHasFPUContext = pdTRUE;
|
||||
|
||||
portEXIT_CRITICAL();
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ typedef unsigned long UBaseType_t;
|
|||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#else
|
||||
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
|
||||
|
|
@ -84,20 +84,19 @@ typedef unsigned long UBaseType_t;
|
|||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
* never have higher IPL bits set anyway. */
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
|
|
|
|||
Loading…
Reference in a new issue