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Revert Portable/MPLAB Formatting (#883)
* Revert the formatting PR * Fix spelling mistakes --------- Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
Soren Ptak
GitHub
parent
2dfc5142f4
commit
8d1da77d0d
13 changed files with 1648 additions and 1686 deletions
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@ -28,406 +28,405 @@
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 160
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#define portEPC_STACK_LOCATION 152
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#define portSTATUS_STACK_LOCATION 156
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#define portFPCSR_STACK_LOCATION 0
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#define portTASK_HAS_FPU_STACK_LOCATION 0
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#define portFPU_CONTEXT_SIZE 264
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#define portCONTEXT_SIZE 160
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#define portEPC_STACK_LOCATION 152
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#define portSTATUS_STACK_LOCATION 156
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#define portFPCSR_STACK_LOCATION 0
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#define portTASK_HAS_FPU_STACK_LOCATION 0
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#define portFPU_CONTEXT_SIZE 264
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/******************************************************************/
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.macro portSAVE_FPU_REGS offset, base
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.macro portSAVE_FPU_REGS offset, base
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/* Macro to assist with saving just the FPU registers to the
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* specified address and base offset,
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* offset is a constant, base is the base pointer register */
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/* Macro to assist with saving just the FPU registers to the
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* specified address and base offset,
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* offset is a constant, base is the base pointer register */
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sdc1 $f31, \offset + 248(\base)
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sdc1 $f30, \offset + 240(\base)
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sdc1 $f29, \offset + 232(\base)
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sdc1 $f28, \offset + 224(\base)
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sdc1 $f27, \offset + 216(\base)
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sdc1 $f26, \offset + 208(\base)
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sdc1 $f25, \offset + 200(\base)
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sdc1 $f24, \offset + 192(\base)
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sdc1 $f23, \offset + 184(\base)
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sdc1 $f22, \offset + 176(\base)
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sdc1 $f21, \offset + 168(\base)
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sdc1 $f20, \offset + 160(\base)
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sdc1 $f19, \offset + 152(\base)
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sdc1 $f18, \offset + 144(\base)
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sdc1 $f17, \offset + 136(\base)
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sdc1 $f16, \offset + 128(\base)
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sdc1 $f15, \offset + 120(\base)
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sdc1 $f14, \offset + 112(\base)
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sdc1 $f13, \offset + 104(\base)
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sdc1 $f12, \offset + 96(\base)
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sdc1 $f11, \offset + 88(\base)
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sdc1 $f10, \offset + 80(\base)
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sdc1 $f9, \offset + 72(\base)
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sdc1 $f8, \offset + 64(\base)
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sdc1 $f7, \offset + 56(\base)
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sdc1 $f6, \offset + 48(\base)
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sdc1 $f5, \offset + 40(\base)
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sdc1 $f4, \offset + 32(\base)
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sdc1 $f3, \offset + 24(\base)
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sdc1 $f2, \offset + 16(\base)
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sdc1 $f1, \offset + 8(\base)
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sdc1 $f0, \offset + 0(\base)
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sdc1 $f31, \ offset + 248 ( \ base )
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sdc1 $f30, \ offset + 240 ( \ base )
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sdc1 $f29, \ offset + 232 ( \ base )
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sdc1 $f28, \ offset + 224 ( \ base )
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sdc1 $f27, \ offset + 216 ( \ base )
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sdc1 $f26, \ offset + 208 ( \ base )
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sdc1 $f25, \ offset + 200 ( \ base )
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sdc1 $f24, \ offset + 192 ( \ base )
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sdc1 $f23, \ offset + 184 ( \ base )
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sdc1 $f22, \ offset + 176 ( \ base )
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sdc1 $f21, \ offset + 168 ( \ base )
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sdc1 $f20, \ offset + 160 ( \ base )
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sdc1 $f19, \ offset + 152 ( \ base )
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sdc1 $f18, \ offset + 144 ( \ base )
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sdc1 $f17, \ offset + 136 ( \ base )
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sdc1 $f16, \ offset + 128 ( \ base )
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sdc1 $f15, \ offset + 120 ( \ base )
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sdc1 $f14, \ offset + 112 ( \ base )
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sdc1 $f13, \ offset + 104 ( \ base )
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sdc1 $f12, \ offset + 96 ( \ base )
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sdc1 $f11, \ offset + 88 ( \ base )
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sdc1 $f10, \ offset + 80 ( \ base )
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sdc1 $f9, \ offset + 72 ( \ base )
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sdc1 $f8, \ offset + 64 ( \ base )
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sdc1 $f7, \ offset + 56 ( \ base )
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sdc1 $f6, \ offset + 48 ( \ base )
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sdc1 $f5, \ offset + 40 ( \ base )
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sdc1 $f4, \ offset + 32 ( \ base )
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sdc1 $f3, \ offset + 24 ( \ base )
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sdc1 $f2, \ offset + 16 ( \ base )
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sdc1 $f1, \ offset + 8 ( \ base )
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sdc1 $f0, \ offset + 0 ( \ base )
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.endm
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.endm
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/******************************************************************/
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.macro portLOAD_FPU_REGS offset, base
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.macro portLOAD_FPU_REGS offset, base
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/* Macro to assist with loading just the FPU registers from the
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* specified address and base offset, offset is a constant,
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* base is the base pointer register */
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/* Macro to assist with loading just the FPU registers from the
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* specified address and base offset, offset is a constant,
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* base is the base pointer register */
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ldc1 $f0, \offset + 0(\base)
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ldc1 $f1, \offset + 8(\base)
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ldc1 $f2, \offset + 16(\base)
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ldc1 $f3, \offset + 24(\base)
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ldc1 $f4, \offset + 32(\base)
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ldc1 $f5, \offset + 40(\base)
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ldc1 $f6, \offset + 48(\base)
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ldc1 $f7, \offset + 56(\base)
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ldc1 $f8, \offset + 64(\base)
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ldc1 $f9, \offset + 72(\base)
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ldc1 $f10, \offset + 80(\base)
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ldc1 $f11, \offset + 88(\base)
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ldc1 $f12, \offset + 96(\base)
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ldc1 $f13, \offset + 104(\base)
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ldc1 $f14, \offset + 112(\base)
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ldc1 $f15, \offset + 120(\base)
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ldc1 $f16, \offset + 128(\base)
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ldc1 $f17, \offset + 136(\base)
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ldc1 $f18, \offset + 144(\base)
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ldc1 $f19, \offset + 152(\base)
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ldc1 $f20, \offset + 160(\base)
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ldc1 $f21, \offset + 168(\base)
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ldc1 $f22, \offset + 176(\base)
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ldc1 $f23, \offset + 184(\base)
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ldc1 $f24, \offset + 192(\base)
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ldc1 $f25, \offset + 200(\base)
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ldc1 $f26, \offset + 208(\base)
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ldc1 $f27, \offset + 216(\base)
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ldc1 $f28, \offset + 224(\base)
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ldc1 $f29, \offset + 232(\base)
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ldc1 $f30, \offset + 240(\base)
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ldc1 $f31, \offset + 248(\base)
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ldc1 $f0, \ offset + 0 ( \ base )
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ldc1 $f1, \ offset + 8 ( \ base )
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ldc1 $f2, \ offset + 16 ( \ base )
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ldc1 $f3, \ offset + 24 ( \ base )
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ldc1 $f4, \ offset + 32 ( \ base )
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ldc1 $f5, \ offset + 40 ( \ base )
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ldc1 $f6, \ offset + 48 ( \ base )
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ldc1 $f7, \ offset + 56 ( \ base )
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ldc1 $f8, \ offset + 64 ( \ base )
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ldc1 $f9, \ offset + 72 ( \ base )
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ldc1 $f10, \ offset + 80 ( \ base )
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ldc1 $f11, \ offset + 88 ( \ base )
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ldc1 $f12, \ offset + 96 ( \ base )
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ldc1 $f13, \ offset + 104 ( \ base )
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ldc1 $f14, \ offset + 112 ( \ base )
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ldc1 $f15, \ offset + 120 ( \ base )
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ldc1 $f16, \ offset + 128 ( \ base )
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ldc1 $f17, \ offset + 136 ( \ base )
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ldc1 $f18, \ offset + 144 ( \ base )
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ldc1 $f19, \ offset + 152 ( \ base )
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ldc1 $f20, \ offset + 160 ( \ base )
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ldc1 $f21, \ offset + 168 ( \ base )
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ldc1 $f22, \ offset + 176 ( \ base )
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ldc1 $f23, \ offset + 184 ( \ base )
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ldc1 $f24, \ offset + 192 ( \ base )
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ldc1 $f25, \ offset + 200 ( \ base )
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ldc1 $f26, \ offset + 208 ( \ base )
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ldc1 $f27, \ offset + 216 ( \ base )
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ldc1 $f28, \ offset + 224 ( \ base )
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ldc1 $f29, \ offset + 232 ( \ base )
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ldc1 $f30, \ offset + 240 ( \ base )
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ldc1 $f31, \ offset + 248 ( \ base )
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.endm
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.endm
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/******************************************************************/
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.macro portSAVE_CONTEXT
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.macro portSAVE_CONTEXT
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/* Make room for the context. First save the current status so it can be
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* manipulated, and the cause and EPC registers so their original values are
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* captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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/* Make room for the context. First save the current status so it can be
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manipulated, and the cause and EPC registers so their original values are
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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/* Test if we are already using the system stack. Only tasks may use the
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FPU so if we are already in a nested interrupt then the FPU context does
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not require saving. */
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la k1, uxInterruptNesting
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lw k1, 0(k1)
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bne k1, zero, 2f
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nop
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/* Test if we are already using the system stack. Only tasks may use the
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* FPU so if we are already in a nested interrupt then the FPU context does
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* not require saving. */
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la k1, uxInterruptNesting
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lw k1, 0 ( k1 )
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bne k1, zero, 2f
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/* Test if the current task needs the FPU context saving. */
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la k1, ulTaskHasFPUContext
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lw k1, 0(k1)
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beq k1, zero, 1f
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nop
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/* Adjust the stack to account for the additional FPU context.*/
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addiu sp, sp, -portFPU_CONTEXT_SIZE
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1:
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/* Save the ulTaskHasFPUContext flag. */
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sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
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2:
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#endif
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mfc0 k1, _CP0_STATUS
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/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
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should maintain the values of these registers across the ISR. */
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sw s7, 48(sp)
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Prepare to enable interrupts above the current priority. */
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srl k0, k0, 0xa
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ins k1, k0, 10, 7
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srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
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ins k1, k0, 18, 1
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, (k0)
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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the system stack is already being used. */
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bne s6, zero, 1f
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nop
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/* Test if the current task needs the FPU context saving. */
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la k1, ulTaskHasFPUContext
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lw k1, 0 ( k1 )
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beq k1, zero, 1f
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, (sp)
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/* Increment and save the nesting count. */
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1: addiu s6, s6, 1
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sw s6, 0(k0)
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. No other s registers need be
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saved. */
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sw ra, 120(s5)
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sw s8, 116(s5)
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sw t9, 112(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t6, 100(s5)
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sw t5, 96(s5)
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sw t4, 92(s5)
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sw t3, 88(s5)
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sw t2, 84(s5)
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sw t1, 80(s5)
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sw t0, 76(s5)
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sw a3, 72(s5)
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sw a2, 68(s5)
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sw a1, 64(s5)
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sw a0, 60(s5)
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sw v1, 56(s5)
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sw v0, 52(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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sw $1, 16(s5)
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/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
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scratch register. */
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mfhi s6, $ac1
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sw s6, 128(s5)
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mflo s6, $ac1
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sw s6, 124(s5)
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mfhi s6, $ac2
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sw s6, 136(s5)
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mflo s6, $ac2
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sw s6, 132(s5)
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mfhi s6, $ac3
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sw s6, 144(s5)
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mflo s6, $ac3
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sw s6, 140(s5)
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/* Save the DSP Control register */
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rddsp s6
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sw s6, 148(s5)
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/* ac0 is done separately to match the MX port. */
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mfhi s6, $ac0
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sw s6, 12(s5)
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mflo s6, $ac0
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sw s6, 8(s5)
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/* Save the FPU context if the nesting count was zero. */
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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la s6, uxInterruptNesting
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lw s6, 0(s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Test if the current task needs the FPU context saving. */
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lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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beq s6, zero, 1f
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nop
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/* Save the FPU registers. */
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portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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/* Save the FPU status register */
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cfc1 s6, $f31
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sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
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1:
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#endif
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Adjust the stack to account for the additional FPU context.*/
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addiu sp, sp, -portFPU_CONTEXT_SIZE
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1 :
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/* Save the ulTaskHasFPUContext flag. */
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sw k1, portTASK_HAS_FPU_STACK_LOCATION( sp )
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2 :
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#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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mfc0 k1, _CP0_STATUS
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/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
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* should maintain the values of these registers across the ISR. */
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sw s7, 48 ( sp )
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sw s6, 44 ( sp )
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sw s5, 40 ( sp )
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sw k1, portSTATUS_STACK_LOCATION( sp )
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/* Prepare to enable interrupts above the current priority. */
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srl k0, k0, 0xa
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ins k1, k0, 10, 7
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srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
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ins k1, k0, 18, 1
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, ( k0 )
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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* the system stack is already being used. */
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bne s6, zero, 1f
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nop
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, ( sp )
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/* Increment and save the nesting count. */
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1 : addiu s6, s6, 1
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sw s6, 0 ( k0 )
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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* here as it now contains the EPC value. No other s registers need be
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* saved. */
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sw ra, 120 ( s5 )
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sw s8, 116 ( s5 )
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sw t9, 112 ( s5 )
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sw t8, 108 ( s5 )
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sw t7, 104 ( s5 )
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sw t6, 100 ( s5 )
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sw t5, 96 ( s5 )
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sw t4, 92 ( s5 )
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sw t3, 88 ( s5 )
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sw t2, 84 ( s5 )
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sw t1, 80 ( s5 )
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sw t0, 76 ( s5 )
|
||||
sw a3, 72 ( s5 )
|
||||
sw a2, 68 ( s5 )
|
||||
sw a1, 64 ( s5 )
|
||||
sw a0, 60 ( s5 )
|
||||
sw v1, 56 ( s5 )
|
||||
sw v0, 52 ( s5 )
|
||||
sw s6, portEPC_STACK_LOCATION( s5 )
|
||||
sw $1, 16 ( s5 )
|
||||
|
||||
/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
|
||||
* scratch register. */
|
||||
mfhi s6, $ac1
|
||||
sw s6, 128 ( s5 )
|
||||
mflo s6, $ac1
|
||||
sw s6, 124 ( s5 )
|
||||
|
||||
mfhi s6, $ac2
|
||||
sw s6, 136 ( s5 )
|
||||
mflo s6, $ac2
|
||||
sw s6, 132 ( s5 )
|
||||
|
||||
mfhi s6, $ac3
|
||||
sw s6, 144 ( s5 )
|
||||
mflo s6, $ac3
|
||||
sw s6, 140 ( s5 )
|
||||
|
||||
/* Save the DSP Control register */
|
||||
rddsp s6
|
||||
sw s6, 148 ( s5 )
|
||||
|
||||
/* ac0 is done separately to match the MX port. */
|
||||
mfhi s6, $ac0
|
||||
sw s6, 12 ( s5 )
|
||||
mflo s6, $ac0
|
||||
sw s6, 8 ( s5 )
|
||||
|
||||
/* Save the FPU context if the nesting count was zero. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, 0 ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Test if the current task needs the FPU context saving. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
/* Save the FPU registers. */
|
||||
portSAVE_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
/* Save the FPU status register */
|
||||
cfc1 s6, $f31
|
||||
sw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
|
||||
|
||||
1 :
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, ( s6 )
|
||||
1 :
|
||||
.endm
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, (s6)
|
||||
1:
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portRESTORE_CONTEXT
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, ( s6 )
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* Restore the FPU context if required. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
|
||||
beq s6, zero, 1f
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Restore the FPU registers. */
|
||||
portLOAD_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, (s6)
|
||||
|
||||
/* Restore the FPU status register. */
|
||||
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
|
||||
ctc1 s6, $f31
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* Restore the FPU context if required. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
|
||||
1 :
|
||||
/* Restore the FPU registers. */
|
||||
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
/* Restore the context. */
|
||||
lw s6, 128 ( s5 )
|
||||
mthi s6, $ac1
|
||||
lw s6, 124 ( s5 )
|
||||
mtlo s6, $ac1
|
||||
/* Restore the FPU status register. */
|
||||
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
|
||||
ctc1 s6, $f31
|
||||
#endif
|
||||
|
||||
lw s6, 136 ( s5 )
|
||||
mthi s6, $ac2
|
||||
lw s6, 132 ( s5 )
|
||||
mtlo s6, $ac2
|
||||
1:
|
||||
|
||||
lw s6, 144 ( s5 )
|
||||
mthi s6, $ac3
|
||||
lw s6, 140 ( s5 )
|
||||
mtlo s6, $ac3
|
||||
/* Restore the context. */
|
||||
lw s6, 128(s5)
|
||||
mthi s6, $ac1
|
||||
lw s6, 124(s5)
|
||||
mtlo s6, $ac1
|
||||
|
||||
/* Restore DSPControl. */
|
||||
lw s6, 148 ( s5 )
|
||||
wrdsp s6
|
||||
lw s6, 136(s5)
|
||||
mthi s6, $ac2
|
||||
lw s6, 132(s5)
|
||||
mtlo s6, $ac2
|
||||
|
||||
lw s6, 8 ( s5 )
|
||||
mtlo s6, $ac0
|
||||
lw s6, 12 ( s5 )
|
||||
mthi s6, $ac0
|
||||
lw $1, 16 ( s5 )
|
||||
lw s6, 144(s5)
|
||||
mthi s6, $ac3
|
||||
lw s6, 140(s5)
|
||||
mtlo s6, $ac3
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
lw s7, 48 ( s5 )
|
||||
lw s6, 44 ( s5 )
|
||||
lw v0, 52 ( s5 )
|
||||
lw v1, 56 ( s5 )
|
||||
lw a0, 60 ( s5 )
|
||||
lw a1, 64 ( s5 )
|
||||
lw a2, 68 ( s5 )
|
||||
lw a3, 72 ( s5 )
|
||||
lw t0, 76 ( s5 )
|
||||
lw t1, 80 ( s5 )
|
||||
lw t2, 84 ( s5 )
|
||||
lw t3, 88 ( s5 )
|
||||
lw t4, 92 ( s5 )
|
||||
lw t5, 96 ( s5 )
|
||||
lw t6, 100 ( s5 )
|
||||
lw t7, 104 ( s5 )
|
||||
lw t8, 108 ( s5 )
|
||||
lw t9, 112 ( s5 )
|
||||
lw s8, 116 ( s5 )
|
||||
lw ra, 120 ( s5 )
|
||||
/* Restore DSPControl. */
|
||||
lw s6, 148(s5)
|
||||
wrdsp s6
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
lw s6, 8(s5)
|
||||
mtlo s6, $ac0
|
||||
lw s6, 12(s5)
|
||||
mthi s6, $ac0
|
||||
lw $1, 16(s5)
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, ( k0 )
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0 ( k0 )
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
as part of the interrupt context. */
|
||||
lw s7, 48(s5)
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* If the nesting count is now zero then the FPU context may be restored. */
|
||||
bne k1, zero, 1f
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, (k0)
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0(k0)
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* If the nesting count is now zero then the FPU context may be restored. */
|
||||
bne k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* Restore the value of ulTaskHasFPUContext */
|
||||
la k0, ulTaskHasFPUContext
|
||||
lw k1, 0(s5)
|
||||
sw k1, 0(k0)
|
||||
|
||||
/* If the task does not have an FPU context then adjust the stack normally. */
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
/* Adjust the stack pointer to remove the FPU context */
|
||||
addiu sp, sp, portFPU_CONTEXT_SIZE
|
||||
beq zero, zero, 2f
|
||||
nop
|
||||
|
||||
1: /* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
2: /* Adjust the stack pointer */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#else
|
||||
|
||||
/* Restore the frame when there is no hardware FP support. */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
/* Restore the value of ulTaskHasFPUContext */
|
||||
la k0, ulTaskHasFPUContext
|
||||
lw k1, 0 ( s5 )
|
||||
sw k1, 0 ( k0 )
|
||||
|
||||
/* If the task does not have an FPU context then adjust the stack normally. */
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
|
||||
/* Adjust the stack pointer to remove the FPU context */
|
||||
addiu sp, sp, portFPU_CONTEXT_SIZE
|
||||
beq zero, zero, 2f
|
||||
nop
|
||||
|
||||
1 : /* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
|
||||
2 : /* Adjust the stack pointer */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
|
||||
/* Restore the frame when there is no hardware FP support. */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.endm
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@
|
|||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MZ port.
|
||||
*----------------------------------------------------------*/
|
||||
* Implementation of functions defined in portable.h for the PIC32MZ port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Microchip specific headers. */
|
||||
#include <xc.h>
|
||||
|
|
@ -40,62 +40,62 @@
|
|||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#if !defined( __PIC32MZ__ )
|
||||
#if !defined(__PIC32MZ__)
|
||||
#error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings.
|
||||
#endif
|
||||
|
||||
#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#endif
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
|
||||
#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
|
||||
#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
|
||||
#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
|
||||
#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
|
||||
|
||||
/* Bits within the CAUSE register. */
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. */
|
||||
the first task is being restored. */
|
||||
#if ( __mips_hard_float == 1 )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
|
||||
#else
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
|
||||
#endif
|
||||
|
||||
/* The initial value to store into the FPU status and control register. This is
|
||||
* only used on parts that support a hardware FPU. */
|
||||
#define portINITIAL_FPSCR ( 0x1000000 ) /* High perf on denormal ops */
|
||||
only used on parts that support a hardware FPU. */
|
||||
#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
|
||||
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
* override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
* to generate the tick interrupt. For example, when timer 1 is used then
|
||||
* configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
* configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
* 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
* timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
* used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
* IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
to generate the tick interrupt. For example, when timer 1 is used then
|
||||
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
|
|
@ -103,36 +103,34 @@
|
|||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
* debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
|
@ -147,23 +145,23 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
UBaseType_t uxSavedTaskStackPointer = 0;
|
||||
|
||||
/* The stack used by interrupt service routines that cause a context switch. */
|
||||
__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
* is required to allow double word floating point stack pushes generated by the
|
||||
* compiler. */
|
||||
the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
is required to allow double word floating point stack pushes generated by the
|
||||
compiler. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
|
||||
|
||||
/* Saved as part of the task context. Set to pdFALSE if the task does not
|
||||
* require an FPU context. */
|
||||
require an FPU context. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
uint32_t ulTaskHasFPUContext = 0;
|
||||
#endif
|
||||
|
|
@ -173,39 +171,37 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure 8 byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
|
||||
*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00000000; /* DSPControl */
|
||||
pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
|
||||
*pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
|
||||
pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pdFALSE; /*by default disable FPU context save on parts with FPU */
|
||||
*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
|
|
@ -214,17 +210,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -237,9 +230,9 @@ static void prvTaskExitError( void )
|
|||
* vector number. When Timer 1 is used the vector number is defined as
|
||||
* _TIMER_1_VECTOR.
|
||||
*/
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1UL;
|
||||
const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
|
||||
|
||||
T1CON = 0x0000;
|
||||
T1CONbits.TCKPS = portPRESCALE_BITS;
|
||||
|
|
@ -257,18 +250,18 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void * pxCurrentTCB;
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
|
|
@ -289,18 +282,18 @@ BaseType_t xPortStartScheduler( void )
|
|||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
* disabled by the time we get here. */
|
||||
disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
* Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
|
|
@ -309,7 +302,7 @@ BaseType_t xPortStartScheduler( void )
|
|||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
UBaseType_t uxSavedStatus;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
|
|
@ -331,17 +324,16 @@ void vPortIncrementTick( void )
|
|||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
|
|
@ -356,17 +348,17 @@ void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
|||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
void vPortTaskUsesFPU( void )
|
||||
void vPortTaskUsesFPU(void)
|
||||
{
|
||||
extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
|
||||
extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
|
||||
|
||||
portENTER_CRITICAL();
|
||||
|
||||
/* Initialise the floating point status register. */
|
||||
vPortInitialiseFPSCR( portINITIAL_FPSCR );
|
||||
vPortInitialiseFPSCR(portINITIAL_FPSCR);
|
||||
|
||||
/* A task is registering the fact that it needs a FPU context. Set the
|
||||
* FPU flag (saved as part of the task context). */
|
||||
FPU flag (saved as part of the task context). */
|
||||
ulTaskHasFPUContext = pdTRUE;
|
||||
|
||||
portEXIT_CRITICAL();
|
||||
|
|
|
|||
|
|
@ -49,103 +49,102 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#else
|
||||
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
* never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
#error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
|
||||
|
|
@ -153,27 +152,27 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
|||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
void vPortTaskUsesFPU( void );
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
#endif
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
|
|
@ -181,26 +180,26 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
|||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue