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fix typos in comments: interace -> interface, swtich -> switch (#1022)

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Fix typos in comments: interace -> interface, swtich -> switch.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
This commit is contained in:
Florian La Roche 2024-04-09 02:50:55 +02:00 committed by GitHub
parent 8c49c54987
commit 8afb3a5b82
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GPG key ID: B5690EEEBB952194
12 changed files with 15 additions and 15 deletions
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2
portable/GCC/ARM_AARCH64/README.md
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@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
application processors. application processors.
* ARM_AARCH64 * ARM_AARCH64
* Memory mapped interace to access Arm GIC registers * Memory mapped interface to access Arm GIC registers

2
portable/GCC/ARM_AARCH64_SRE/README.md
View file

@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
application processors. application processors.
* ARM_AARCH64_SRE * ARM_AARCH64_SRE
* System Register interace to access Arm GIC registers * System Register interface to access Arm GIC registers

4
portable/GCC/ARM_CA53_64_BIT/README.md
View file

@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
Arm Cortex-A53 processor. Arm Cortex-A53 processor.
* ARM_CA53_64_BIT * ARM_CA53_64_BIT
* Memory mapped interace to access Arm GIC registers * Memory mapped interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64`.
**NOTE** **NOTE**
This port uses memory mapped interace to access Arm GIC registers. This port uses memory mapped interface to access Arm GIC registers.

4
portable/GCC/ARM_CA53_64_BIT_SRE/README.md
View file

@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
Arm Cortex-A53 processor. Arm Cortex-A53 processor.
* ARM_CA53_64_BIT_SRE * ARM_CA53_64_BIT_SRE
* System Register interace to access Arm GIC registers * System Register interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64_SRE`.
**NOTE** **NOTE**
This port uses System Register interace to access Arm GIC registers. This port uses System Register interface to access Arm GIC registers.

2
portable/GCC/ARM_CA9/portASM.S
View file

@ -246,7 +246,7 @@ exit_without_switch:
MOVS PC, LR MOVS PC, LR
switch_before_exit: switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending /* A context switch is to be performed. Clear the context switch pending
flag. */ flag. */
MOV r0, #0 MOV r0, #0
STR r0, [r1] STR r0, [r1]

2
portable/GCC/ARM_CR5/portASM.S
View file

@ -242,7 +242,7 @@ exit_without_switch:
MOVS PC, LR MOVS PC, LR
switch_before_exit: switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending /* A context switch is to be performed. Clear the context switch pending
flag. */ flag. */
MOV r0, #0 MOV r0, #0
STR r0, [r1] STR r0, [r1]

4
portable/GCC/ARM_CRx_MPU/portASM.S
View file

@ -446,7 +446,7 @@ FreeRTOS_IRQ_Handler:
* ulPortInterruptNesting. */ * ulPortInterruptNesting. */
STR R1, [R0] STR R1, [R0]
/* Context swtich is only performed when interrupt nesting count is 0. */ /* Context switch is only performed when interrupt nesting count is 0. */
CMP R1, #0 CMP R1, #0
BNE exit_without_switch BNE exit_without_switch
@ -464,7 +464,7 @@ exit_without_switch:
RFE SP! RFE SP!
switch_before_exit: switch_before_exit:
/* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds /* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds
* the address of ulPortYieldRequired. */ * the address of ulPortYieldRequired. */
MOV R0, #0 MOV R0, #0
STR R0, [R1] STR R0, [R1]

2
portable/GCC/ARM_CRx_No_GIC/portASM.S
View file

@ -223,7 +223,7 @@ exit_without_switch:
MOVS PC, LR MOVS PC, LR
switch_before_exit: switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending /* A context switch is to be performed. Clear the context switch pending
flag. */ flag. */
MOV r0, #0 MOV r0, #0
STR r0, [r1] STR r0, [r1]

2
portable/IAR/ARM_CRx_No_GIC/portASM.s
View file

@ -215,7 +215,7 @@ exit_without_switch:
MOVS PC, LR MOVS PC, LR
switch_before_exit: switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending /* A context switch is to be performed. Clear the context switch pending
flag. */ flag. */
MOV r0, #0 MOV r0, #0
STR r0, [r1] STR r0, [r1]

2
portable/RVDS/ARM_CA9/portASM.s
View file

@ -143,7 +143,7 @@ exit_without_switch
MOVS PC, LR MOVS PC, LR
switch_before_exit switch_before_exit
; A context swtich is to be performed. Clear the context switch pending ; A context switch is to be performed. Clear the context switch pending
; flag. ; flag.
MOV r0, #0 MOV r0, #0
STR r0, [r1] STR r0, [r1]

2
portable/ThirdParty/CDK/T-HEAD_CK802/port.c vendored
View file

@ -32,7 +32,7 @@ extern void vPortStartTask( void );
* will be set to 0 prior to the first task being started. */ * will be set to 0 prior to the first task being started. */
portLONG ulCriticalNesting = 0x9999UL; portLONG ulCriticalNesting = 0x9999UL;
/* Used to record one tack want to swtich task after enter critical area, we need know it /* Used to record one tack want to switch task after enter critical area, we need know it
* and implement task switch after exit critical area */ * and implement task switch after exit critical area */
portLONG pendsvflag = 0; portLONG pendsvflag = 0;

2
portable/ThirdParty/XCC/Xtensa/xtensa_context.h vendored
View file

@ -254,7 +254,7 @@ STRUCT_END(XtSolFrame)
The contents of a non-running thread's CPENABLE register. The contents of a non-running thread's CPENABLE register.
It represents the co-processors owned (and whose state is still needed) It represents the co-processors owned (and whose state is still needed)
by the thread. When a thread is preempted, its CPENABLE is saved here. by the thread. When a thread is preempted, its CPENABLE is saved here.
When a thread solicits a context-swtich, its CPENABLE is cleared - the When a thread solicits a context-switch, its CPENABLE is cleared - the
compiler has saved the (caller-saved) co-proc state if it needs to. compiler has saved the (caller-saved) co-proc state if it needs to.
When a non-running thread loses ownership of a CP, its bit is cleared. When a non-running thread loses ownership of a CP, its bit is cleared.
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.