len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-19 17:48:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

fix typos in comments: interace -> interface, swtich -> switch (#1022)

Browse source 
Fix typos in comments: interace -> interface, swtich -> switch.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
This commit is contained in:
Florian La Roche 2024-04-09 02:50:55 +02:00 • committed by GitHub
parent 8c49c54987
commit 8afb3a5b82
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
12 changed files with 15 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

2
portable/GCC/ARM_AARCH64/README.md
View file

@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
application processors.
* ARM_AARCH64
* Memory mapped interace to access Arm GIC registers
* Memory mapped interface to access Arm GIC registers

2
portable/GCC/ARM_AARCH64_SRE/README.md
View file

@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
application processors.
* ARM_AARCH64_SRE
* System Register interace to access Arm GIC registers
* System Register interface to access Arm GIC registers

4
portable/GCC/ARM_CA53_64_BIT/README.md
View file

@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
Arm Cortex-A53 processor.
* ARM_CA53_64_BIT
* Memory mapped interace to access Arm GIC registers
* Memory mapped interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64`.
**NOTE**
This port uses memory mapped interace to access Arm GIC registers.
This port uses memory mapped interface to access Arm GIC registers.

4
portable/GCC/ARM_CA53_64_BIT_SRE/README.md
View file

@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
Arm Cortex-A53 processor.
* ARM_CA53_64_BIT_SRE
* System Register interace to access Arm GIC registers
* System Register interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64_SRE`.
**NOTE**
This port uses System Register interace to access Arm GIC registers.
This port uses System Register interface to access Arm GIC registers.

2
portable/GCC/ARM_CA9/portASM.S
View file

@ -246,7 +246,7 @@ exit_without_switch:
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
/* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]

2
portable/GCC/ARM_CR5/portASM.S
View file

@ -242,7 +242,7 @@ exit_without_switch:
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
/* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]

4
portable/GCC/ARM_CRx_MPU/portASM.S
View file

@ -446,7 +446,7 @@ FreeRTOS_IRQ_Handler:
* ulPortInterruptNesting. */
STR R1, [R0]
/* Context swtich is only performed when interrupt nesting count is 0. */
/* Context switch is only performed when interrupt nesting count is 0. */
CMP R1, #0
BNE exit_without_switch
@ -464,7 +464,7 @@ exit_without_switch:
RFE SP!
switch_before_exit:
/* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds
/* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds
* the address of ulPortYieldRequired. */
MOV R0, #0
STR R0, [R1]

2
portable/GCC/ARM_CRx_No_GIC/portASM.S
View file

@ -223,7 +223,7 @@ exit_without_switch:
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
/* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]