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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Make the parameters to vPortDefineHeapRegions() const.
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated). Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
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@ -381,7 +381,7 @@ typedef struct HeapRegion
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* terminated by a HeapRegions_t structure that has a size of 0. The region
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* with the lowest start address must appear first in the array.
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*/
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void vPortDefineHeapRegions( HeapRegion_t *pxHeapRegions );
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void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions );
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/*
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@ -424,14 +424,14 @@ uint8_t *puc;
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}
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/*-----------------------------------------------------------*/
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void vPortDefineHeapRegions( HeapRegion_t *pxHeapRegions )
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void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
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{
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BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
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uint8_t *pucAlignedHeap;
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size_t xTotalRegionSize, xTotalHeapSize = 0;
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BaseType_t xDefinedRegions = 0;
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uint32_t ulAddress;
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HeapRegion_t *pxHeapRegion;
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const HeapRegion_t *pxHeapRegion;
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/* Can only call once! */
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configASSERT( pxEnd == NULL );
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@ -110,6 +110,9 @@ is defined. */
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#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0x1FUL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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@ -268,11 +271,13 @@ __asm void prvStartFirstTask( void )
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msr msp, r0
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/* Globally enable interrupts. */
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cpsie i
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cpsie f
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dsb
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isb
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/* Call SVC to start the first task. */
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svc 0
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nop
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nop
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}
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/*-----------------------------------------------------------*/
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@ -370,6 +375,16 @@ void vPortEnterCritical( void )
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uxCriticalNesting++;
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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/* This is not the interrupt safe version of the enter critical function so
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assert() if it is being called from an interrupt context. Only API
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functions that end in "FromISR" can be used in an interrupt. Only assert if
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the critical nesting count is 1 to protect against recursive calls if the
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assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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}
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/*-----------------------------------------------------------*/
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@ -123,6 +123,9 @@ is defined. */
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#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0x1FUL )
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/* Constants required to manipulate the VFP. */
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#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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@ -290,11 +293,13 @@ __asm void prvStartFirstTask( void )
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msr msp, r0
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/* Globally enable interrupts. */
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cpsie i
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cpsie f
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dsb
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isb
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/* Call SVC to start the first task. */
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svc 0
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nop
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nop
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}
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/*-----------------------------------------------------------*/
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@ -414,6 +419,16 @@ void vPortEnterCritical( void )
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uxCriticalNesting++;
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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/* This is not the interrupt safe version of the enter critical function so
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assert() if it is being called from an interrupt context. Only API
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functions that end in "FromISR" can be used in an interrupt. Only assert if
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the critical nesting count is 1 to protect against recursive calls if the
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assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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}
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/*-----------------------------------------------------------*/
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@ -695,6 +695,14 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
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mtCOVERAGE_TEST_MARKER();
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}
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}
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else if( xYieldRequired != pdFALSE )
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{
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/* This path is a special case that will only get
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executed if the task was holding multiple mutexes and
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the mutexes were given back in an order that is
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different to that in which they were taken. */
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queueYIELD_IF_USING_PREEMPTION();
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}
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else
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{
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mtCOVERAGE_TEST_MARKER();
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