mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 04:13:54 -04:00
FreeRTOS source:
+ Added Renesas RXv2 port for IAR. Demo apps: + Demo/Rename the CORTEX_R4F_T_GCC_IAR_ARM directory to just Rename the CORTEX_R4F_T_GCC_IAR. + Add IAR project for the RX113. + Add RX231 e2studio projects for the RX231.
This commit is contained in:
Richard Barry
parent
27ff871a37
commit
87243e4a16
225 changed files with 427176 additions and 220 deletions
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@ -71,7 +71,14 @@
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#define FREERTOS_CONFIG_H
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/* Renesas hardware definition header. */
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#include "iodefine.h"
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#ifdef __ICCRX__
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#include <iorx71m.h>
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#include <machine.h>
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#endif
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#ifdef __GNUC__
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#include "iodefine.h"
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#endif
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/*-----------------------------------------------------------
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* Application specific definitions.
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@ -128,7 +135,7 @@ kernel is doing. */
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/* The peripheral used to generate the tick interrupt is configured as part of
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the application code. This constant should be set to the vector number of the
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peripheral chosen. As supplied this is CMT0. */
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#define configTICK_VECTOR _CMT0_CMI0
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#define configTICK_VECTOR 28 /*vect _CMT0_CMI0*/
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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@ -68,9 +68,9 @@
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*/
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/*
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* This file contains the non-portable and therefore RX62N specific parts of
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* the IntQueue standard demo task - namely the configuration of the timers
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* that generate the interrupts and the interrupt entry points.
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* This file contains the non-portable and therefore RX specific parts of the
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* IntQueue standard demo task - namely the configuration of the timers that
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* generate the interrupts and the interrupt entry points.
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*/
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/* Scheduler includes. */
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@ -81,23 +81,8 @@
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Hardware specifics. */
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#include "iodefine.h"
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#define IPR_PERIB_INTB128 128
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#define IPR_PERIB_INTB129 129
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#define IER_PERIB_INTB128 0x10
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#define IER_PERIB_INTB129 0x10
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#define IEN_PERIB_INTB128 IEN0
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#define IEN_PERIB_INTB129 IEN1
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#define IR_PERIB_INTB128 128
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#define IR_PERIB_INTB129 129
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void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2301UL )
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void vInitialiseTimerForIntQueueTest( void )
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{
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@ -107,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void )
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/* Give write access. */
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SYSTEM.PRCR.WORD = 0xa502;
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/* Cascade two 8bit timer channels to generate the interrupts.
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/* Cascade two 8bit timer channels to generate the interrupts.
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8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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utilised for this test. */
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@ -130,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void )
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/* 16 bit operation ( count from timer 1,2 ). */
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TMR0.TCCR.BIT.CSS = 3;
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TMR2.TCCR.BIT.CSS = 3;
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/* Use PCLK as the input. */
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TMR1.TCCR.BIT.CSS = 1;
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TMR3.TCCR.BIT.CSS = 1;
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/* Divide PCLK by 8. */
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TMR1.TCCR.BIT.CKS = 2;
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TMR3.TCCR.BIT.CKS = 2;
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@ -143,11 +128,9 @@ void vInitialiseTimerForIntQueueTest( void )
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set
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priority above the kernel's priority, but below the max syscall
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priority. */
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ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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/* Set priority and enable interrupt. */
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ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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IEN( PERIB, INTB128 ) = 1;
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/* Ensure that the flag is set to 0, otherwise the interrupt will not be
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@ -155,8 +138,8 @@ void vInitialiseTimerForIntQueueTest( void )
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IR( PERIB, INTB128 ) = 0;
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/* Do the same for TMR2, but to vector 129. */
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ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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IEN( PERIB, INTB129 ) = 1;
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IR( PERIB, INTB129 ) = 0;
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}
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@ -164,25 +147,49 @@ void vInitialiseTimerForIntQueueTest( void )
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}
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/*-----------------------------------------------------------*/
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/* On vector 128. */
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void vIntQTimerISR0( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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#ifdef __GNUC__
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void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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void vIntQTimerISR0( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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void vIntQTimerISR1( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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#endif /* __GNUC__ */
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/*-----------------------------------------------------------*/
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#ifdef __ICCRX__
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#pragma vector = VECT_PERIB_INTB128
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__interrupt void vT0_1InterruptHandler( void )
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{
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__enable_interrupt();
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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/* On vector 129. */
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void vIntQTimerISR1( void )
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#pragma vector = VECT_PERIB_INTB129
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__interrupt void vT2_3InterruptHandler( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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__enable_interrupt();
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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#endif /* __ICCRX__ */
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@ -0,0 +1,304 @@
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/*
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FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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***************************************************************************
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>>! NOTE: The modification to the GPL is included to allow you to !<<
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>>! distribute a combined work that includes FreeRTOS without being !<<
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>>! obliged to provide the source code for proprietary components !<<
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>>! outside of the FreeRTOS kernel. !<<
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***************************************************************************
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available on the following
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link: http://www.freertos.org/a00114.html
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that is more than just the market leader, it *
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* is the industry's de facto standard. *
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* *
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* Help yourself get started quickly while simultaneously helping *
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* to support the FreeRTOS project by purchasing a FreeRTOS *
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* tutorial book, reference manual, or both: *
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* http://www.FreeRTOS.org/Documentation *
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* *
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***************************************************************************
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http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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the FAQ page "My application does not run, what could be wrong?". Have you
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defined configASSERT()?
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http://www.FreeRTOS.org/support - In return for receiving this top quality
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embedded software for free we request you assist our global community by
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participating in the support forum.
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http://www.FreeRTOS.org/training - Investing in training allows your team to
|
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be as productive as possible as early as possible. Now you can receive
|
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FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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Ltd, and the world's leading authority on the world's leading RTOS.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
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http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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licenses offer ticketed support, indemnification and commercial middleware.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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1 tab == 4 spaces!
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*/
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PUBLIC _vRegTest1Implementation
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PUBLIC _vRegTest2Implementation
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EXTERN _ulRegTest1LoopCounter
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EXTERN _ulRegTest2LoopCounter
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RSEG CODE:CODE(4)
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/* This function is explained in the comments at the top of main.c. */
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_vRegTest1Implementation:
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;/* Put a known value in the guard byte of the accumulators. */
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MOV.L #10, R1
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MVTACGU R1, A0
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MOV.L #20, R1
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MVTACGU R1, A1
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/* Put a known value in each register. */
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MOV #1, R1
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MOV #2, R2
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MOV #3, R3
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MOV #4, R4
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MOV #5, R5
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MOV #6, R6
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MOV #7, R7
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MOV #8, R8
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MOV #9, R9
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MOV #10, R10
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MOV #11, R11
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MOV #12, R12
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MOV #13, R13
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MOV #14, R14
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MOV #15, R15
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;/* Put a known value in the hi and low of the accumulators. */
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MVTACHI R1, A0
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MVTACLO R2, A0
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MVTACHI R3, A1
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MVTACLO R4, A1
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/* Loop, checking each itteration that each register still contains the
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expected value. */
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TestLoop1:
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/* Push the registers that are going to get clobbered. */
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PUSHM R14-R15
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/* Increment the loop counter to show this task is still getting CPU time. */
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MOV #_ulRegTest1LoopCounter, R14
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MOV [ R14 ], R15
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ADD #1, R15
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MOV R15, [ R14 ]
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/* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */
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MOV #1, R14
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MOV #0872E0H, R15
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MOV.B R14, [R15]
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NOP
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NOP
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;/* Check accumulators. */
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MVFACHI #0, A0, R15
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CMP #1, R15
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BNE RegTest1Error
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MVFACLO #0, A0, R15
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CMP #2, R15
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BNE RegTest1Error
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MVFACGU #0, A0, R15
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CMP #10, R15
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BNE RegTest1Error
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MVFACHI #0, A1, R15
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CMP #3, R15
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BNE RegTest1Error
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MVFACLO #0, A1, R15
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CMP #4, R15
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BNE RegTest1Error
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MVFACGU #0, A1, R15
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CMP #20, R15
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BNE RegTest1Error
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/* Restore the clobbered registers. */
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POPM R14-R15
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/* Now compare each register to ensure it still contains the value that was
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set before this loop was entered. */
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CMP #1, R1
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BNE RegTest1Error
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CMP #2, R2
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BNE RegTest1Error
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CMP #3, R3
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BNE RegTest1Error
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CMP #4, R4
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BNE RegTest1Error
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CMP #5, R5
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BNE RegTest1Error
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CMP #6, R6
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BNE RegTest1Error
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CMP #7, R7
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BNE RegTest1Error
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CMP #8, R8
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BNE RegTest1Error
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CMP #9, R9
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BNE RegTest1Error
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CMP #10, R10
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BNE RegTest1Error
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CMP #11, R11
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BNE RegTest1Error
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CMP #12, R12
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BNE RegTest1Error
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CMP #13, R13
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BNE RegTest1Error
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CMP #14, R14
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BNE RegTest1Error
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CMP #15, R15
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BNE RegTest1Error
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/* All comparisons passed, start a new itteratio of this loop. */
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BRA TestLoop1
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RegTest1Error:
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/* A compare failed, just loop here so the loop counter stops incrementing
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- causing the check task to indicate the error. */
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BRA RegTest1Error
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/*-----------------------------------------------------------*/
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/* This function is explained in the comments at the top of main.c. */
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_vRegTest2Implementation:
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;/* Put a known value in the guard byte of the accumulators. */
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MOV.L #1H, R1
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MVTACGU R1, A0
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MOV.L #2H, R1
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MVTACGU R1, A1
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/* Put a known value in each register. */
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MOV #10H, R1
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MOV #20H, R2
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MOV #30H, R3
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MOV #40H, R4
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MOV #50H, R5
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MOV #60H, R6
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MOV #70H, R7
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MOV #80H, R8
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MOV #90H, R9
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MOV #100H, R10
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MOV #110H, R11
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MOV #120H, R12
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MOV #130H, R13
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MOV #140H, R14
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MOV #150H, R15
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;/* Put a known value in the hi and low of the accumulators. */
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MVTACHI R1, A0
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MVTACLO R2, A0
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MVTACHI R3, A1
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MVTACLO R4, A1
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/* Loop, checking each itteration that each register still contains the
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expected value. */
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TestLoop2:
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/* Push the registers that are going to get clobbered. */
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PUSHM R14-R15
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/* Increment the loop counter to show this task is still getting CPU time. */
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MOV #_ulRegTest2LoopCounter, R14
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MOV [ R14 ], R15
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ADD #1, R15
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MOV R15, [ R14 ]
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;/* Check accumulators. */
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MVFACHI #0, A0, R15
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CMP #10H, R15
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BNE RegTest1Error
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MVFACLO #0, A0, R15
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CMP #20H, R15
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BNE RegTest1Error
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MVFACGU #0, A0, R15
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CMP #1H, R15
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BNE RegTest1Error
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MVFACHI #0, A1, R15
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CMP #30H, R15
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BNE RegTest1Error
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MVFACLO #0, A1, R15
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CMP #40H, R15
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BNE RegTest1Error
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MVFACGU #0, A1, R15
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CMP #2H, R15
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BNE RegTest1Error
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/* Restore the clobbered registers. */
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POPM R14-R15
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/* Now compare each register to ensure it still contains the value that was
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set before this loop was entered. */
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CMP #10H, R1
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BNE RegTest2Error
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CMP #20H, R2
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BNE RegTest2Error
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CMP #30H, R3
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BNE RegTest2Error
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CMP #40H, R4
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BNE RegTest2Error
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CMP #50H, R5
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BNE RegTest2Error
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CMP #60H, R6
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BNE RegTest2Error
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CMP #70H, R7
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BNE RegTest2Error
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CMP #80H, R8
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BNE RegTest2Error
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CMP #90H, R9
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BNE RegTest2Error
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CMP #100H, R10
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BNE RegTest2Error
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CMP #110H, R11
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BNE RegTest2Error
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CMP #120H, R12
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BNE RegTest2Error
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CMP #130H, R13
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BNE RegTest2Error
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CMP #140H, R14
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BNE RegTest2Error
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||||
CMP #150H, R15
|
||||
BNE RegTest2Error
|
||||
|
||||
/* All comparisons passed, start a new itteratio of this loop. */
|
||||
BRA TestLoop2
|
||||
|
||||
RegTest2Error:
|
||||
/* A compare failed, just loop here so the loop counter stops incrementing
|
||||
- causing the check task to indicate the error. */
|
||||
BRA RegTest2Error
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PRIORITY_DEFINITIONS_H
|
||||
#define PRIORITY_DEFINITIONS_H
|
||||
|
||||
#ifndef __IASMRX__
|
||||
#error This file is only intended to be included from the FreeRTOS IAR port layer assembly file.
|
||||
#endif
|
||||
|
||||
/* The interrupt priority used by the kernel itself for the tick interrupt and
|
||||
the pended interrupt. This would normally be the lowest priority. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 1
|
||||
|
||||
/* The maximum interrupt priority from which FreeRTOS API calls can be made.
|
||||
Interrupts that use a priority above this will not be effected by anything the
|
||||
kernel is doing. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
|
||||
|
||||
#endif /* PRIORITY_DEFINITIONS_H */
|
||||
|
|
@ -2,15 +2,15 @@
|
|||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
|
|
@ -30,8 +30,14 @@
|
|||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "../iodefine.h"
|
||||
//_RB_#include <machine.h>
|
||||
#ifdef __ICCRX__
|
||||
#include <iorx71m.h>
|
||||
#include <machine.h>
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#include "iodefine.h"
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
|
|
@ -66,7 +72,7 @@ Macro definitions
|
|||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
#ifndef __TYPEDEF__
|
||||
#ifndef _STD_USING_INT_TYPES
|
||||
#if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT )
|
||||
#define _SYS_INT_TYPES_H
|
||||
#ifndef _STD_USING_BIT_TYPES
|
||||
#ifndef __int8_t_defined
|
||||
|
|
|
|||
|
|
@ -2,15 +2,15 @@
|
|||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
|
|
@ -78,11 +78,11 @@ void R_SCI7_Create(void)
|
|||
SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;
|
||||
|
||||
/* Set control registers */
|
||||
SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE |
|
||||
SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE |
|
||||
_00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;
|
||||
SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST |
|
||||
SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST |
|
||||
_10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT;
|
||||
SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK |
|
||||
SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK |
|
||||
_00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE;
|
||||
|
||||
/* Set bitrate */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,241 @@
|
|||
/*Adapted for IAR Embedded Workbench*/
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2013, 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_sci_user.c
|
||||
* Version : Code Generator for RX64M V1.00.01.01 [09 May 2014]
|
||||
* Device(s) : R5F571MLCxFC
|
||||
* Tool-Chain : IAR Embedded Workbench
|
||||
* Description : This file implements device driver for SCI module.
|
||||
* Creation Date: 30/06/2014
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_sci.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "rskrx71mdef.h"
|
||||
//_RB_#include "r_cg_cmt.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */
|
||||
extern uint16_t g_sci7_tx_count; /* SCI7 send data number */
|
||||
extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */
|
||||
extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */
|
||||
extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
/* Global used to receive a character from the PC terminal */
|
||||
uint8_t g_rx_char;
|
||||
|
||||
/* Flag used to control transmission to PC terminal */
|
||||
volatile uint8_t g_tx_flag = FALSE;
|
||||
|
||||
/* Flag used locally to detect transmission complete */
|
||||
static volatile uint8_t sci7_txdone;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_transmit_interrupt
|
||||
* Description : None
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
#pragma vector=VECT(SCI7,TXI7)
|
||||
__interrupt static void r_sci7_transmit_interrupt(void)
|
||||
{
|
||||
if (g_sci7_tx_count > 0U)
|
||||
{
|
||||
SCI7.TDR = *gp_sci7_tx_address;
|
||||
gp_sci7_tx_address++;
|
||||
g_sci7_tx_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCI7.SCR.BIT.TIE = 0U;
|
||||
SCI7.SCR.BIT.TEIE = 1U;
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_transmitend_interrupt
|
||||
* Description : This function is TEI7 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_sci7_transmitend_interrupt(void)
|
||||
{
|
||||
MPC.P90PFS.BYTE = 0x00U;
|
||||
PORT9.PMR.BYTE &= 0xFEU;
|
||||
SCI7.SCR.BIT.TIE = 0U;
|
||||
SCI7.SCR.BIT.TE = 0U;
|
||||
SCI7.SCR.BIT.TEIE = 0U;
|
||||
|
||||
r_sci7_callback_transmitend();
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_receive_interrupt
|
||||
* Description : None
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
#pragma vector=VECT(SCI7,RXI7)
|
||||
__interrupt static void r_sci7_receive_interrupt(void)
|
||||
{
|
||||
if (g_sci7_rx_length > g_sci7_rx_count)
|
||||
{
|
||||
*gp_sci7_rx_address = SCI7.RDR;
|
||||
gp_sci7_rx_address++;
|
||||
g_sci7_rx_count++;
|
||||
|
||||
if (g_sci7_rx_length <= g_sci7_rx_count)
|
||||
{
|
||||
r_sci7_callback_receiveend();
|
||||
}
|
||||
}
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_receiveerror_interrupt
|
||||
* Description : This function is ERI7 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_sci7_receiveerror_interrupt(void)
|
||||
{
|
||||
uint8_t err_type;
|
||||
|
||||
r_sci7_callback_receiveerror();
|
||||
|
||||
/* Clear overrun, framing and parity error flags */
|
||||
err_type = SCI7.SSR.BYTE;
|
||||
err_type &= 0xC7U;
|
||||
err_type |= 0xC0U;
|
||||
SCI7.SSR.BYTE = err_type;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_callback_transmitend
|
||||
* Description : This function is a callback function when SCI7 finishes transmission.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_sci7_callback_transmitend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
sci7_txdone = TRUE;
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_callback_receiveend
|
||||
* Description : This function is a callback function when SCI7 finishes reception.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_sci7_callback_receiveend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* Check the contents of g_rx_char */
|
||||
if ('z' == g_rx_char)
|
||||
{
|
||||
/* Stop the timer used to control transmission to PC terminal*/
|
||||
// R_CMT1_Stop();
|
||||
|
||||
/* Turn off LED0 and turn on LED1 to indicate serial transmission
|
||||
inactive */
|
||||
LED0 = LED_OFF;
|
||||
LED1 = LED_ON;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Start the timer used to control transmission to PC terminal*/
|
||||
//_RB_ R_CMT1_Start();
|
||||
|
||||
/* Turn on LED0 and turn off LED1 to indicate serial transmission
|
||||
active */
|
||||
LED0 = LED_ON;
|
||||
LED1 = LED_OFF;
|
||||
}
|
||||
|
||||
/* Set up SCI7 receive buffer again */
|
||||
R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1);
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_sci7_callback_receiveerror
|
||||
* Description : This function is a callback function when SCI7 reception encounters error.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_sci7_callback_receiveerror(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCI7_AsyncTransmit
|
||||
* Description : This function sends SCI7 data and waits for the transmit end flag.
|
||||
* Arguments : tx_buf -
|
||||
* transfer buffer pointer
|
||||
* tx_num -
|
||||
* buffer size
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
/* clear the flag before initiating a new transmission */
|
||||
sci7_txdone = FALSE;
|
||||
|
||||
/* Send the data using the API */
|
||||
status = R_SCI7_Serial_Send(tx_buf, tx_num);
|
||||
|
||||
/* Wait for the transmit end flag */
|
||||
while (FALSE == sci7_txdone)
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
return (status);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* End of function R_SCI7_AsyncTransmit
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -248,6 +248,23 @@ const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500
|
|||
/* Reneable register protection. */
|
||||
SYSTEM.PRCR.WORD = ulDisableRegisterWrite;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __ICCRX__
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
/* Called from the C start up code when compiled with IAR. */
|
||||
#pragma diag_suppress = Pm011
|
||||
int __low_level_init(void)
|
||||
#pragma diag_default = Pm011
|
||||
{
|
||||
extern void R_Systeminit( void );
|
||||
|
||||
__disable_interrupt();
|
||||
R_Systeminit();
|
||||
|
||||
return (int)(1U);
|
||||
}
|
||||
|
||||
#endif /* __ICCRX__ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue