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Style: Revert uncrustify for portable directories (#122)

Browse source 
* Style: revert uncrustify portable directories

* Style: Uncrustify Some Portable files

Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
This commit is contained in:
alfred gedeon 2020-08-17 10:51:02 -07:00 committed by GitHub
parent a6da1cd0ce
commit 86653e2a1f
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273 changed files with 64802 additions and 65931 deletions
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10
portable/ARMv8M/non_secure/port.c
View file

@ -22,7 +22,6 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@ -876,7 +875,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
}
}
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
@ -889,6 +888,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;

52
portable/BCC/16BitDOS/Flsh186/port.c
View file

@ -26,16 +26,16 @@
*/
/*
* Changes from V1.00:
*
Changes from V1.00:
+ Call to taskYIELD() from within tick ISR has been replaced by the more
+ efficient portSWITCH_CONTEXT().
efficient portSWITCH_CONTEXT().
+ ISR function definitions renamed to include the prv prefix.
+
+ Changes from V2.6.1
+
Changes from V2.6.1
+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
macro to be consistent with the later ports.
*/
/*-----------------------------------------------------------
@ -68,16 +68,14 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
static void prvExitFunction( void );
/* The ISR used depends on whether the preemptive or cooperative scheduler
* is being used. */
is being used. */
#if( configUSE_PREEMPTION == 1 )
/* Tick service routine used by the scheduler when preemptive scheduling is
* being used. */
being used. */
static void __interrupt __far prvPreemptiveTick( void );
#else
/* Tick service routine used by the scheduler when cooperative scheduling is
* being used. */
being used. */
static void __interrupt __far prvNonPreemptiveTick( void );
#endif
@ -90,8 +88,8 @@ static void __interrupt __far prvYieldProcessor( void );
static BaseType_t xSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual
* context switches. This is then used to restore the original routine during
* prvExitFunction(). */
context switches. This is then used to restore the original routine during
prvExitFunction(). */
static void ( __interrupt __far *pxOldSwitchISR )();
/* Used to restore the original DOS context when the scheduler is ended. */
@ -105,11 +103,11 @@ BaseType_t xPortStartScheduler( void )
/* This is called with interrupts already disabled. */
/* Remember what was on the interrupts we are going to use
* so we can put them back later if required. */
so we can put them back later if required. */
pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
/* Put our manual switch (yield) function on a known
* vector. */
vector. */
_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
#if( configUSE_PREEMPTION == 1 )
@ -145,7 +143,7 @@ BaseType_t xPortStartScheduler( void )
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative scheduler
* is being used. */
is being used. */
#if( configUSE_PREEMPTION == 1 )
static void __interrupt __far prvPreemptiveTick( void )
{
@ -159,15 +157,15 @@ BaseType_t xPortStartScheduler( void )
/* Reset the PIC ready for the next time. */
portRESET_PIC();
}
#else /* if ( configUSE_PREEMPTION == 1 ) */
#else
static void __interrupt __far prvNonPreemptiveTick( void )
{
/* Same as preemptive tick, but the cooperative scheduler is being used
* so we don't have to switch in the context of the next task. */
so we don't have to switch in the context of the next task. */
xTaskIncrementTick();
portRESET_PIC();
}
#endif /* if ( configUSE_PREEMPTION == 1 ) */
#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
@ -180,8 +178,8 @@ static void __interrupt __far prvYieldProcessor( void )
void vPortEndScheduler( void )
{
/* Jump back to the processor state prior to starting the
* scheduler. This means we are not going to be using a
* task stack frame so the task can be deleted. */
scheduler. This means we are not going to be using a
task stack frame so the task can be deleted. */
longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
@ -192,19 +190,18 @@ static void prvExitFunction( void )
uint16_t usTimer0Control;
/* Interrupts should be disabled here anyway - but no
* harm in making sure. */
harm in making sure. */
portDISABLE_INTERRUPTS();
if( xSchedulerRunning == pdTRUE )
{
/* Put back the switch interrupt routines that was in place
* before the scheduler started. */
before the scheduler started. */
_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
}
/* Disable the timer used for the tick to ensure the scheduler is
* not called before restoring interrupts. There was previously nothing
* on this timer so there is no old ISR to restore. */
not called before restoring interrupts. There was previously nothing
on this timer so there is no old ISR to restore. */
portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
/* Restart the DOS tick. */
@ -244,3 +241,4 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz )
/*lint +e950 */

4
portable/BCC/16BitDOS/Flsh186/prtmacro.h
View file

@ -61,8 +61,7 @@ typedef unsigned short UBaseType_t;
/*-----------------------------------------------------------*/
/* Critical section handling. */
#define portENTER_CRITICAL() \
__asm{ pushf } \
#define portENTER_CRITICAL() __asm{ pushf } \
__asm{ cli } \
#define portEXIT_CRITICAL() __asm{ popf }
@ -95,3 +94,4 @@ typedef unsigned short UBaseType_t;
#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
#endif /* PORTMACRO_H */

70
portable/BCC/16BitDOS/PC/port.c
View file

@ -26,15 +26,15 @@
*/
/*
* Changes from V2.6.1
*
Changes from V2.6.1
+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
+
+ Changes from V4.0.1
+
macro to be consistent with the later ports.
Changes from V4.0.1
+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+ its proper value when the scheduler exits.
its proper value when the scheduler exits.
*/
#include <stdlib.h>
@ -61,21 +61,19 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
static void prvExitFunction( void );
/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
* directly. We chain to the DOS tick as close as possible to the standard DOS
* tick rate. */
directly. We chain to the DOS tick as close as possible to the standard DOS
tick rate. */
static void prvPortResetPIC( void );
/* The ISR used depends on whether the preemptive or cooperative
* scheduler is being used. */
scheduler is being used. */
#if( configUSE_PREEMPTION == 1 )
/* Tick service routine used by the scheduler when preemptive scheduling is
* being used. */
being used. */
static void __interrupt __far prvPreemptiveTick( void );
#else
/* Tick service routine used by the scheduler when cooperative scheduling is
* being used. */
being used. */
static void __interrupt __far prvNonPreemptiveTick( void );
#endif
@ -83,7 +81,7 @@ static void prvPortResetPIC( void );
static void __interrupt __far prvYieldProcessor( void );
/* Set the tick frequency back so the floppy drive works correctly when the
* scheduler exits. */
scheduler exits. */
static void prvSetTickFrequencyDefault( void );
/*lint -e956 File scopes necessary here. */
@ -113,7 +111,7 @@ BaseType_t xPortStartScheduler( void )
/* This is called with interrupts already disabled. */
/* Remember what was on the interrupts we are going to use
* so we can put them back later if required. */
so we can put them back later if required. */
pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@ -121,15 +119,15 @@ BaseType_t xPortStartScheduler( void )
prvSetTickFrequency( configTICK_RATE_HZ );
/* Put our manual switch (yield) function on a known
* vector. */
vector. */
_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
/* Put the old tick on a different interrupt number so we can
* call it when we want. */
call it when we want. */
_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
/* The ISR used depends on whether the preemptive or cooperative
* scheduler is being used. */
scheduler is being used. */
#if( configUSE_PREEMPTION == 1 )
{
/* Put our tick switch function on the timer interrupt. */
@ -143,8 +141,8 @@ BaseType_t xPortStartScheduler( void )
#endif
/* Setup a counter that is used to call the DOS interrupt as close
* to it's original frequency as can be achieved given our chosen tick
* frequency. */
to it's original frequency as can be achieved given our chosen tick
frequency. */
sDOSTickCounter = portTICKS_PER_DOS_TICK;
/* Clean up function if we want to return to DOS. */
@ -166,7 +164,7 @@ BaseType_t xPortStartScheduler( void )
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative
* scheduler is being used. */
scheduler is being used. */
#if( configUSE_PREEMPTION == 1 )
static void __interrupt __far prvPreemptiveTick( void )
{
@ -180,15 +178,15 @@ BaseType_t xPortStartScheduler( void )
/* Reset the PIC ready for the next time. */
prvPortResetPIC();
}
#else /* if ( configUSE_PREEMPTION == 1 ) */
#else
static void __interrupt __far prvNonPreemptiveTick( void )
{
/* Same as preemptive tick, but the cooperative scheduler is being used
* so we don't have to switch in the context of the next task. */
so we don't have to switch in the context of the next task. */
xTaskIncrementTick();
prvPortResetPIC();
}
#endif /* if ( configUSE_PREEMPTION == 1 ) */
#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
@ -201,22 +199,19 @@ static void __interrupt __far prvYieldProcessor( void )
static void prvPortResetPIC( void )
{
/* We are going to call the DOS tick interrupt at as close a
* frequency to the normal DOS tick as possible. */
frequency to the normal DOS tick as possible. */
/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
--sDOSTickCounter;
if( sDOSTickCounter <= 0 )
{
sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
__asm {
int portSWITCH_INT_NUMBER + 1
};
__asm{ int portSWITCH_INT_NUMBER + 1 };
}
else
{
/* Reset the PIC as the DOS tick is not being called to
* do it. */
do it. */
__asm
{
mov al, 20H
@ -229,8 +224,8 @@ static void prvPortResetPIC( void )
void vPortEndScheduler( void )
{
/* Jump back to the processor state prior to starting the
* scheduler. This means we are not going to be using a
* task stack frame so the task can be deleted. */
scheduler. This means we are not going to be using a
task stack frame so the task can be deleted. */
longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
@ -240,9 +235,8 @@ static void prvExitFunction( void )
void ( __interrupt __far *pxOriginalTickISR )();
/* Interrupts should be disabled here anyway - but no
* harm in making sure. */
harm in making sure. */
portDISABLE_INTERRUPTS();
if( xSchedulerRunning == pdTRUE )
{
/* Set the DOS tick back onto the timer ticker. */
@ -251,13 +245,12 @@ static void prvExitFunction( void )
prvSetTickFrequencyDefault();
/* Put back the switch interrupt routines that was in place
* before the scheduler started. */
before the scheduler started. */
_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
}
/* The tick timer is back how DOS wants it. We can re-enable
* interrupts without the scheduler being called. */
interrupts without the scheduler being called. */
portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
@ -292,3 +285,4 @@ static void prvSetTickFrequencyDefault( void )
/*lint +e950 */

4
portable/BCC/16BitDOS/PC/prtmacro.h
View file

@ -61,8 +61,7 @@ typedef unsigned short UBaseType_t;
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portENTER_CRITICAL() \
__asm{ pushf } \
#define portENTER_CRITICAL() __asm{ pushf } \
__asm{ cli } \
#define portEXIT_CRITICAL() __asm{ popf }
@ -95,3 +94,4 @@ typedef unsigned short UBaseType_t;
#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
#endif /* PORTMACRO_H */

11
portable/BCC/16BitDOS/common/portasm.h
View file

@ -47,10 +47,10 @@ void portSWITCH_CONTEXT( void );
void portFIRST_CONTEXT( void );
/* There are slightly different versions depending on whether you are building
* to include debugger information. If debugger information is used then there
* are a couple of extra bytes left of the ISR stack (presumably for use by the
* debugger). The true stack pointer is then stored in the bp register. We add
* 2 to the stack pointer to remove the extra bytes before we restore our context. */
to include debugger information. If debugger information is used then there
are a couple of extra bytes left of the ISR stack (presumably for use by the
debugger). The true stack pointer is then stored in the bp register. We add
2 to the stack pointer to remove the extra bytes before we restore our context. */
#define portSWITCH_CONTEXT() \
asm { mov ax, seg pxCurrentTCB } \
@ -83,4 +83,5 @@ void portFIRST_CONTEXT( void );
__asm { iret }
#endif /* ifndef PORT_ASM_H */
#endif

33
portable/BCC/16BitDOS/common/portcomn.c
View file

@ -26,14 +26,14 @@
*/
/*
* Changes from V1.00:
*
Changes from V1.00:
+ pxPortInitialiseStack() now initialises the stack of new tasks to the
+ same format used by the compiler. This allows the compiler generated
+ interrupt mechanism to be used for context switches.
+
+ Changes from V2.6.1
+
same format used by the compiler. This allows the compiler generated
interrupt mechanism to be used for context switches.
Changes from V2.6.1
+ Move usPortCheckFreeStackSpace() to tasks.c.
*/
@ -45,14 +45,12 @@
/*-----------------------------------------------------------*/
/* See header file for description. */
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t DS_Reg = 0;
/* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging. */
This is just useful for debugging. */
*pxTopOfStack = 0x1111;
pxTopOfStack--;
@ -69,8 +67,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* We are going to start the scheduler using a return from interrupt
* instruction to load the program counter, so first there would be the
* function call with parameters preamble. */
instruction to load the program counter, so first there would be the
function call with parameters preamble. */
*pxTopOfStack = FP_SEG( pvParameters );
pxTopOfStack--;
@ -90,8 +88,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The remaining registers would be pushed on the stack by our context
* switch function. These are loaded with values simply to make debugging
* easier. */
switch function. These are loaded with values simply to make debugging
easier. */
*pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@ -104,9 +102,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* We need the true data segment. */
__asm {
MOV DS_Reg, DS
};
__asm{ MOV DS_Reg, DS };
*pxTopOfStack = DS_Reg; /* DS */
pxTopOfStack--;
@ -121,3 +117,4 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
return pxTopOfStack;
}
/*-----------------------------------------------------------*/

41
portable/CCS/ARM_Cortex-R4/port.c
View file

@ -57,7 +57,7 @@ uint32_t ulCriticalNesting = 9999;
#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
/* The number of words on the stack frame between the saved Top Of Stack and
* R0 (in which the parameters are passed. */
R0 (in which the parameters are passed. */
#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
/*-----------------------------------------------------------*/
@ -68,7 +68,7 @@ extern void vPortStartFirstTask( void );
/*-----------------------------------------------------------*/
/* Saved as part of the task context. Set to pdFALSE if the task does not
* require an FPU context. */
require an FPU context. */
uint32_t ulTaskHasFPUContext = 0;
/*-----------------------------------------------------------*/
@ -77,9 +77,7 @@ uint32_t ulTaskHasFPUContext = 0;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
@ -93,11 +91,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
#endif
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which is the start of the as
* the task has not executed yet. The offset is added to make the return
* address appear as it would within an IRQ ISR. */
the task has not executed yet. The offset is added to make the return
address appear as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -133,11 +131,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
pxTopOfStack--;
}
#else /* ifdef portPRELOAD_TASK_REGISTERS */
#else
{
pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
}
#endif /* ifdef portPRELOAD_TASK_REGISTERS */
#endif
/* Function parameters are passed in R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
@ -157,8 +155,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The last thing on the stack is the tasks ulUsingFPU value, which by
* default is set to indicate that the stack frame does not include FPU
* registers. */
default is set to indicate that the stack frame does not include FPU
registers. */
*pxTopOfStack = pdFALSE;
}
#endif
@ -209,7 +207,7 @@ BaseType_t xPortStartScheduler( void )
ulCriticalNesting = 0;
/* Start the first task. This is done from portASM.asm as ARM mode must be
* used. */
used. */
vPortStartFirstTask();
/* Should not get here! */
@ -223,7 +221,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler(void)
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -238,11 +236,11 @@ void vPortEndScheduler( void )
portRTI_INTFLAG_REG = 0x00000001;
/* Increment the tick count - this may make a delaying task ready
* to run - but a context switch is not performed. */
to run - but a context switch is not performed. */
xTaskIncrementTick();
}
#else /* if configUSE_PREEMPTION == 0 */
#else
/*
**************************************************************************
@ -253,7 +251,7 @@ void vPortEndScheduler( void )
*/
void vPortPreemptiveTick( void );
#endif /* if configUSE_PREEMPTION == 0 */
#endif
/*-----------------------------------------------------------*/
@ -266,8 +264,8 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -284,7 +282,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == 0 )
{
/* Enable interrupts as per portENABLE_INTERRUPTS(). */
@ -301,7 +299,7 @@ void vPortExitCritical( void )
extern void vPortInitialiseFPSCR( void );
/* A task is registering the fact that it needs an FPU context. Set the
* FPU flag (saved as part of the task context. */
FPU flag (saved as part of the task context. */
ulTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
@ -311,3 +309,4 @@ void vPortExitCritical( void )
#endif /* __TI_VFP_SUPPORT__ */
/*-----------------------------------------------------------*/

3
portable/CCS/ARM_Cortex-R4/portmacro.h
View file

@ -59,7 +59,7 @@ typedef unsigned long UBaseType_t;
#define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
@ -114,3 +114,4 @@ extern void vPortYield( void );
#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#endif /* __PORTMACRO_H__ */

55
portable/CCS/MSP430X/data_model.h
View file

@ -1,29 +1,29 @@
;/*
* ; * FreeRTOS Kernel V10.3.1
* ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* ; *
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
* ; * this software and associated documentation files (the "Software"), to deal in
* ; * the Software without restriction, including without limitation the rights to
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* ; * the Software, and to permit persons to whom the Software is furnished to do so,
* ; * subject to the following conditions:
* ; *
* ; * The above copyright notice and this permission notice shall be included in all
* ; * copies or substantial portions of the Software.
* ; *
* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* ; *
* ; * http://www.FreeRTOS.org
* ; * http://aws.amazon.com/freertos
* ; *
* ; * 1 tab == 4 spaces!
* ; */
; * FreeRTOS Kernel V10.3.1
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * http://www.FreeRTOS.org
; * http://aws.amazon.com/freertos
; *
; * 1 tab == 4 spaces!
; */
.if $DEFINED( __LARGE_DATA_MODEL__ )
.define "pushm.a", pushm_x
@ -46,3 +46,8 @@
.define "call", call_x
.define "ret", ret_x
.endif

50
portable/CCS/MSP430X/port.c
View file

@ -34,24 +34,24 @@
*----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
* not the MCLK. */
not the MCLK. */
#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
* any details of its type. */
any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
* time a critical section is entered the count is incremented. Each time a
* critical section is exited the count is decremented - with interrupts only
* being re-enabled if the count is zero.
*
* usCriticalNesting will get set to zero when the scheduler starts, but must
* not be initialised to zero as this will cause problems during the startup
* sequence. */
time a critical section is entered the count is incremented. Each time a
critical section is exited the count is decremented - with interrupts only
being re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as this will cause problems during the startup
sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@ -69,27 +69,25 @@ void vPortSetupTimerInterrupt( void );
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint16_t *pusTopOfStack;
uint32_t *pulTopOfStack, ulTemp;
/*
* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging and can be included if required.
*
Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging and can be included if required.
*pxTopOfStack = ( StackType_t ) 0x1111;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x2222;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x3333;
* pxTopOfStack--;
pxTopOfStack--;
*/
/* Data types are need either 16 bits or 32 bits depending on the data
* and code model used. */
and code model used. */
if( sizeof( pxCode ) == sizeof( uint16_t ) )
{
pusTopOfStack = ( uint16_t * ) pxTopOfStack;
@ -138,19 +136,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x4444;
pxTopOfStack--;
#else /* ifdef PRELOAD_REGISTER_VALUES */
#else
pxTopOfStack -= 3;
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack -= 9;
#endif /* ifdef PRELOAD_REGISTER_VALUES */
#endif
/* A variable is used to keep track of the critical section nesting.
* This variable has to be stored as part of the task context and is
* initially set to zero. */
This variable has to be stored as part of the task context and is
initially set to zero. */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack we have generated so this can
* be stored in the task control block for the task. */
be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -158,7 +156,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
void vPortEndScheduler( void )
{
/* It is unlikely that the MSP430 port will get stopped. If required simply
* disable the tick interrupt here. */
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@ -185,3 +183,5 @@ interrupt void vTickISREntry( void )
vPortCooperativeTickISR();
#endif
}

3
portable/CCS/MSP430X/portmacro.h
View file

@ -136,7 +136,8 @@ extern void vTaskSwitchContext( void );
void vApplicationSetupTimerInterrupt( void );
/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
* run time stats information is to be displayed. */
run time stats information is to be displayed. */
#define portLU_PRINTF_SPECIFIER_REQUIRED
#endif /* PORTMACRO_H */

20
portable/CodeWarrior/ColdFire_V1/port.c
View file

@ -45,20 +45,17 @@ asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
static void prvSetupTimerInterrupt( void );
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
* will be set to 0 prior to the first task being started. */
will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t ulOriginalA5;
__asm {
MOVE.L A5, ulOriginalA5
};
__asm{ MOVE.L A5, ulOriginalA5 };
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
@ -109,7 +106,7 @@ static void prvSetupTimerInterrupt( void )
RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
/* Enable the RTC to generate interrupts - interrupts are already disabled
* when this code executes. */
when this code executes. */
RTCSC_RTIE = 1;
}
/*-----------------------------------------------------------*/
@ -125,20 +122,19 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
* critical section being entered. */
critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( INTC_FRC == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -146,7 +142,6 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
@ -185,3 +180,4 @@ void interrupt VectorNumber_Vrtc vPortTickISR( void )
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}

4
portable/CodeWarrior/ColdFire_V1/portmacro.h
View file

@ -101,8 +101,7 @@
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
if( xSwitchRequired != pdFALSE ) \
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
{ \
portYIELD(); \
}
@ -113,3 +112,4 @@
#endif
#endif /* PORTMACRO_H */

13
portable/CodeWarrior/ColdFire_V2/port.c
View file

@ -36,7 +36,7 @@
#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
* will be set to 0 prior to the first task being started. */
will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
@ -57,9 +57,7 @@ static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack--;
@ -108,20 +106,19 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
* critical section being entered. */
critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( MCF_INTC0_INTFRCH == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -129,7 +126,6 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
@ -148,3 +144,4 @@ void vPortYieldHandler( void )
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
/*-----------------------------------------------------------*/

4
portable/CodeWarrior/ColdFire_V2/portmacro.h
View file

@ -100,8 +100,7 @@
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
if( xSwitchRequired != pdFALSE ) \
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
{ \
portYIELD(); \
}
@ -112,3 +111,4 @@
#endif
#endif /* PORTMACRO_H */

60
portable/CodeWarrior/HCS12/port.c
View file

@ -42,7 +42,7 @@
static void prvSetupTimerInterrupt( void );
/* Interrupt service routines have to be in non-banked memory - as does the
* scheduler startup function. */
scheduler startup function. */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
/* Manual context switch function. This is the SWI ISR. */
@ -52,19 +52,19 @@ void interrupt vPortYield( void );
void interrupt vPortTickInterrupt( void );
/* Simply called by xPortStartScheduler(). xPortStartScheduler() does not
* start the scheduler directly because the header file containing the
* xPortStartScheduler() prototype is part of the common kernel code, and
* therefore cannot use the CODE_SEG pragma. */
start the scheduler directly because the header file containing the
xPortStartScheduler() prototype is part of the common kernel code, and
therefore cannot use the CODE_SEG pragma. */
static BaseType_t xBankedStartScheduler( void );
#pragma CODE_SEG DEFAULT
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
* critical section should not be left (i.e. interrupts should not be re-enabled)
* until the nesting depth reaches 0. This variable simply tracks the nesting
* depth. Each task maintains it's own critical nesting depth variable so
* uxCriticalNesting is saved and restored from the task stack during a context
* switch. */
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
volatile UBaseType_t uxCriticalNesting = 0xff;
/*-----------------------------------------------------------*/
@ -72,27 +72,25 @@ volatile UBaseType_t uxCriticalNesting = 0xff;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/*
* Place a few bytes of known values on the bottom of the stack.
* This can be uncommented to provide useful stack markers when debugging.
*
Place a few bytes of known values on the bottom of the stack.
This can be uncommented to provide useful stack markers when debugging.
*pxTopOfStack = ( StackType_t ) 0x11;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x22;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x33;
* pxTopOfStack--;
pxTopOfStack--;
*/
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. In this case the stack as
* expected by the HCS12 RTI instruction. */
expected by the portRESTORE_CONTEXT() macro. In this case the stack as
expected by the HCS12 RTI instruction. */
/* The address of the task function is placed in the stack byte at a time. */
@ -124,7 +122,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* CCR: Note that when the task starts interrupts will be enabled since
* "I" bit of CCR is cleared */
"I" bit of CCR is cleared */
*pxTopOfStack = ( StackType_t ) 0x00;
pxTopOfStack--;
@ -135,7 +133,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
#endif
/* Finally the critical nesting depth is initialised with 0 (not within
* a critical section). */
a critical section). */
*pxTopOfStack = ( StackType_t ) 0x00;
return pxTopOfStack;
@ -158,10 +156,10 @@ static void prvSetupTimerInterrupt( void )
BaseType_t xPortStartScheduler( void )
{
/* xPortStartScheduler() does not start the scheduler directly because
* the header file containing the xPortStartScheduler() prototype is part
* of the common kernel code, and therefore cannot use the CODE_SEG pragma.
* Instead it simply calls the locally defined xBankedStartScheduler() -
* which does use the CODE_SEG pragma. */
the header file containing the xPortStartScheduler() prototype is part
of the common kernel code, and therefore cannot use the CODE_SEG pragma.
Instead it simply calls the locally defined xBankedStartScheduler() -
which does use the CODE_SEG pragma. */
return xBankedStartScheduler();
}
@ -172,7 +170,7 @@ BaseType_t xPortStartScheduler( void )
static BaseType_t xBankedStartScheduler( void )
{
/* Configure the timer that will generate the RTOS tick. Interrupts are
* disabled when this function is called. */
disabled when this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task. */
@ -223,15 +221,17 @@ void interrupt vPortTickInterrupt( void )
TFLG1 = 1;
/* Restore the context of a task - which may be a different task
* to that interrupted. */
to that interrupted. */
portRESTORE_CONTEXT();
}
#else /* if configUSE_PREEMPTION == 1 */
#else
{
xTaskIncrementTick();
TFLG1 = 1;
}
#endif /* if configUSE_PREEMPTION == 1 */
#endif
}
#pragma CODE_SEG DEFAULT

6
portable/CodeWarrior/HCS12/portmacro.h
View file

@ -117,7 +117,6 @@ typedef unsigned char UBaseType_t;
*/
#ifdef BANKED_MODEL
/*
* Load the stack pointer for the task, then pull the critical nesting
* count and PPAGE register from the stack. The remains of the
@ -153,7 +152,7 @@ typedef unsigned char UBaseType_t;
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#else /* ifdef BANKED_MODEL */
#else
/*
* These macros are as per the BANKED versions above, but without saving
@ -181,7 +180,7 @@ typedef unsigned char UBaseType_t;
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#endif /* ifdef BANKED_MODEL */
#endif
/*
* Utility macro to call macros above in correct order in order to perform a
@ -200,3 +199,4 @@ typedef unsigned char UBaseType_t;
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */

39
portable/GCC/ARM7_AT91FR40008/port.c
View file

@ -73,24 +73,22 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
* is not really required. */
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -124,12 +122,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R0. */
R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
* system mode, with interrupts enabled. */
system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
@ -142,9 +140,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -154,7 +152,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -168,7 +166,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -192,8 +190,8 @@ static void prvSetupTimerInterrupt( void )
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Store interrupt handler function address in tick timer vector register...
* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
#if configUSE_PREEMPTION == 1
{
extern void ( vPreemptiveTick )( void );
@ -210,8 +208,8 @@ static void prvSetupTimerInterrupt( void )
AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
/* Enable the tick timer interrupt...
*
* First at timer level */
First at timer level */
portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
/* Then at the AIC level. */
@ -221,14 +219,14 @@ static void prvSetupTimerInterrupt( void )
if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
{
/* The tick rate is fast enough for us to use the faster timer input
* clock (main clock / 2). */
clock (main clock / 2). */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
}
else
{
/* We must use a slower timer input clock (main clock / 8) because the
* tick rate is too slow for the faster input clock. */
tick rate is too slow for the faster input clock. */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
}
@ -237,3 +235,4 @@ static void prvSetupTimerInterrupt( void )
portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
}
/*-----------------------------------------------------------*/

35
portable/GCC/ARM7_AT91FR40008/portISR.c
View file

@ -33,10 +33,10 @@
*----------------------------------------------------------*/
/*
* Changes from V3.2.4
*
Changes from V3.2.4
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
than each line having its own asm block.
*/
@ -66,7 +66,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
* called from ARM mode. */
called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -82,8 +82,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -105,7 +105,7 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick. */
simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
void vNonPreemptiveTick( void )
{
@ -123,7 +123,7 @@ void vPortYieldProcessor( void )
#else /* else preemption is turned on */
/* The preemptive scheduler is defined as "naked" as the full context is
* saved on entry as part of the context switch. */
saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__((naked));
void vPreemptiveTick( void )
{
@ -131,14 +131,14 @@ void vPortYieldProcessor( void )
portSAVE_CONTEXT();
/* WARNING - Do not use local (stack) variables here. Use globals
* if you must! */
if you must! */
static volatile uint32_t ulDummy;
/* Clear tick timer interrupt indication. */
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Increment the RTOS tick count, then look for the highest priority
* task that is ready to run. */
task that is ready to run. */
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
@ -151,7 +151,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
/*-----------------------------------------------------------*/
/*
@ -190,9 +190,9 @@ void vPortYieldProcessor( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -204,8 +204,8 @@ void vPortEnterCritical( void )
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -217,7 +217,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
@ -230,3 +230,4 @@ void vPortExitCritical( void )
}
}
}

33
portable/GCC/ARM7_AT91FR40008/portmacro.h
View file

@ -26,26 +26,26 @@
*/
/*
* Changes from V3.2.3
*
Changes from V3.2.3
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
Changes from V3.2.4
+ Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
than each line having its own asm block.
Changes from V4.5.0
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H
@ -252,3 +252,4 @@
#endif
#endif /* PORTMACRO_H */

5270
portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
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File diff suppressed because it is too large Load diff

10779
portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
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File diff suppressed because it is too large Load diff

91
portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
View file

@ -1,50 +1,51 @@
/** ---------------------------------------------------------------------------- */
/** ATMEL Microcontroller Software Support - ROUSSET - */
/** ---------------------------------------------------------------------------- */
/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/** ---------------------------------------------------------------------------- */
/** File Name : lib_AT91SAM7X256.h */
/** Object : AT91SAM7X256 inlined functions */
/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
/** */
/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
/** ---------------------------------------------------------------------------- */
//* ----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//* ----------------------------------------------------------------------------
//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//* ----------------------------------------------------------------------------
//* File Name : lib_AT91SAM7X256.h
//* Object : AT91SAM7X256 inlined functions
//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
//*
//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
//* ----------------------------------------------------------------------------
#include "AT91SAM7X256.h"
/**---------------------------------------------------------------------------- */
/** \fn AT91F_AIC_ConfigureIt */
/** \brief Interrupt Handler Initialization */
/**---------------------------------------------------------------------------- */
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------

4920
portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
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File diff suppressed because it is too large Load diff

37
portable/GCC/ARM7_AT91SAM7S/port.c
View file

@ -82,24 +82,22 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
* is not really required. */
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -133,12 +131,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R0. */
R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
* system mode, with interrupts enabled. */
system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
@ -151,9 +149,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -163,7 +161,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -177,7 +175,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -189,20 +187,27 @@ static void prvSetupTimerInterrupt( void )
AT91PS_PITC pxPIT = AT91C_BASE_PITC;
/* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
* on whether the preemptive or cooperative scheduler is being used. */
on whether the preemptive or cooperative scheduler is being used. */
#if configUSE_PREEMPTION == 0
extern void ( vNonPreemptiveTick ) ( void );
AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
#else
extern void ( vPreemptiveTick )( void );
AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
#endif
/* Configure the PIT period. */
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
/* Enable the interrupt. Global interrupts are disables at this point so
* this is safe. */
this is safe. */
AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
}
/*-----------------------------------------------------------*/

37
portable/GCC/ARM7_AT91SAM7S/portISR.c
View file

@ -33,10 +33,10 @@
*----------------------------------------------------------*/
/*
* Changes from V3.2.4
*
Changes from V3.2.4
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
than each line having its own asm block.
*/
/* Scheduler includes. */
@ -68,7 +68,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
* called from ARM mode. */
called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -84,8 +84,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -107,15 +107,15 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick. */
simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
void vNonPreemptiveTick( void )
{
uint32_t ulDummy;
/* Increment the tick count - which may wake some tasks but as the
* preemptive scheduler is not being used any woken task is not given
* processor time no matter what its priority. */
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
xTaskIncrementTick();
/* Clear the PIT interrupt. */
@ -125,10 +125,10 @@ void vPortYieldProcessor( void )
AT91C_BASE_AIC->AIC_EOICR = ulDummy;
}
#else /* if configUSE_PREEMPTION == 0 */
#else
/* The preemptive scheduler is defined as "naked" as the full context is
* saved on entry as part of the context switch. */
saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__((naked));
void vPreemptiveTick( void )
{
@ -148,7 +148,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
/*-----------------------------------------------------------*/
/*
@ -184,9 +184,9 @@ void vPortEnableInterruptsFromThumb( void )
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -198,8 +198,8 @@ void vPortEnterCritical( void )
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -211,7 +211,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
@ -224,3 +224,4 @@ void vPortExitCritical( void )
}
}
}

33
portable/GCC/ARM7_AT91SAM7S/portmacro.h
View file

@ -26,26 +26,26 @@
*/
/*
* Changes from V3.2.3
*
Changes from V3.2.3
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
Changes from V3.2.4
+ Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
than each line having its own asm block.
Changes from V4.5.0
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H
@ -246,3 +246,4 @@
#endif
#endif /* PORTMACRO_H */

38
portable/GCC/ARM7_LPC2000/port.c
View file

@ -78,24 +78,22 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
* is not really required. */
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -129,12 +127,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R0. */
R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
* system mode, with interrupts enabled. */
system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@ -146,9 +144,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -158,7 +156,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -172,7 +170,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -182,18 +180,17 @@ void vPortEndScheduler( void )
static void prvSetupTimerInterrupt( void )
{
uint32_t ulCompareMatch;
extern void ( vTickISR )( void );
/* A 1ms tick does not require the use of the timer prescale. This is
* defaulted to zero but can be used if necessary. */
defaulted to zero but can be used if necessary. */
T0_PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
* in a warning - hence the #if. */
in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@ -209,13 +206,16 @@ static void prvSetupTimerInterrupt( void )
VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
/* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
scheduler is being used. */
VICVectAddr0 = ( int32_t ) vTickISR;
VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
/* Start the timer - interrupts are disabled when this function is called
* so it is okay to do this here. */
so it is okay to do this here. */
T0_TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

44
portable/GCC/ARM7_LPC2000/portISR.c
View file

@ -33,21 +33,21 @@
*----------------------------------------------------------*/
/*
* Changes from V2.5.2
*
Changes from V2.5.2
+ The critical section management functions have been changed. These no
+ longer modify the stack and are safe to use at all optimisation levels.
+ The functions are now also the same for both ARM and THUMB modes.
+
+ Changes from V2.6.0
+
longer modify the stack and are safe to use at all optimisation levels.
The functions are now also the same for both ARM and THUMB modes.
Changes from V2.6.0
+ Removed the 'static' from the definition of vNonPreemptiveTick() to
+ allow the demo to link when using the cooperative scheduler.
+
+ Changes from V3.2.4
+
allow the demo to link when using the cooperative scheduler.
Changes from V3.2.4
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
than each line having its own asm block.
*/
@ -77,7 +77,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
* called from ARM mode. */
called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -93,8 +93,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -118,7 +118,7 @@ void vTickISR( void )
portSAVE_CONTEXT();
/* Increment the RTOS tick count, then look for the highest priority
* task that is ready to run. */
task that is ready to run. */
__asm volatile
(
" bl xTaskIncrementTick \t\n" \
@ -173,9 +173,9 @@ void vTickISR( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -187,8 +187,8 @@ void vPortEnterCritical( void )
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -200,7 +200,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

1
portable/GCC/ARM7_LPC2000/portmacro.h
View file

@ -223,3 +223,4 @@
#endif
#endif /* PORTMACRO_H */

37
portable/GCC/ARM7_LPC23xx/port.c
View file

@ -78,24 +78,22 @@ extern void vPortISRStartFirstTask( void );
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
* is not really required. */
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -129,12 +127,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R0. */
R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The last thing onto the stack is the status register, which is set for
* system mode, with interrupts enabled. */
system mode, with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@ -146,9 +144,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Some optimisation levels use the stack differently to others. This
* means the interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
means the interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
return pxTopOfStack;
@ -158,7 +156,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -172,7 +170,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -188,14 +186,14 @@ static void prvSetupTimerInterrupt( void )
T0CTCR = 0; /* Timer mode */
/* A 1ms tick does not require the use of the timer prescale. This is
* defaulted to zero but can be used if necessary. */
defaulted to zero but can be used if necessary. */
T0PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
* in a warning - hence the #if. */
in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@ -210,7 +208,7 @@ static void prvSetupTimerInterrupt( void )
VICIntEnable = 0x00000010;
/* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
scheduler is being used. */
#if configUSE_PREEMPTION == 1
{
extern void ( vPreemptiveTick )( void );
@ -226,7 +224,10 @@ static void prvSetupTimerInterrupt( void )
VICVectCntl4 = 1;
/* Start the timer - interrupts are disabled when this function is called
* so it is okay to do this here. */
so it is okay to do this here. */
T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

28
portable/GCC/ARM7_LPC23xx/portISR.c
View file

@ -59,7 +59,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
* called from ARM mode. */
called from ARM mode. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@ -75,8 +75,8 @@ void vPortISRStartFirstTask( void )
void vPortYieldProcessor( void )
{
/* Within an IRQ ISR the link register has an offset from the true return
* address, but an SWI ISR does not. Add the offset manually so the same
* ISR return code can be used in both cases. */
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
@ -99,7 +99,7 @@ void vPortYieldProcessor( void )
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick. */
simply increment the system tick. */
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
void vNonPreemptiveTick( void )
{
@ -108,10 +108,10 @@ void vPortYieldProcessor( void )
VICVectAddr = portCLEAR_VIC_INTERRUPT;
}
#else /* if configUSE_PREEMPTION == 0 */
#else
/* The preemptive scheduler is defined as "naked" as the full context is
* saved on entry as part of the context switch. */
saved on entry as part of the context switch. */
void vPreemptiveTick( void ) __attribute__((naked));
void vPreemptiveTick( void )
{
@ -119,7 +119,7 @@ void vPortYieldProcessor( void )
portSAVE_CONTEXT();
/* Increment the RTOS tick count, then look for the highest priority
* task that is ready to run. */
task that is ready to run. */
__asm volatile
(
" bl xTaskIncrementTick \t\n" \
@ -137,7 +137,7 @@ void vPortYieldProcessor( void )
portRESTORE_CONTEXT();
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
/*-----------------------------------------------------------*/
/*
@ -176,9 +176,9 @@ void vPortYieldProcessor( void )
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
@ -190,8 +190,8 @@ void vPortEnterCritical( void )
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
@ -203,7 +203,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */

33
portable/GCC/ARM7_LPC23xx/portmacro.h
View file

@ -26,26 +26,26 @@
*/
/*
* Changes from V3.2.3
*
Changes from V3.2.3
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
Changes from V3.2.4
+ Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
than each line having its own asm block.
Changes from V4.5.0
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H
@ -246,3 +246,4 @@
#endif
#endif /* PORTMACRO_H */

153
portable/GCC/ARM_CA53_64_BIT/port.c
View file

@ -33,23 +33,23 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
#error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
@ -73,24 +73,24 @@
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
* portmacro.h. */
portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
* this value. */
this value. */
#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
* (but the lowest) interrupt priority. */
(but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -108,7 +108,7 @@
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
* point is zero. */
point is zero. */
#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
@ -143,21 +143,21 @@ extern void vPortRestoreTaskContext( void );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
volatile uint64_t ullCriticalNesting = 9999ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
* then floating point context must be saved and restored for the task. */
then floating point context must be saved and restored for the task. */
uint64_t ullPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint64_t ullPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
if the nesting depth is 0. */
uint64_t ullPortInterruptNesting = 0;
/* Used in the ASM code. */
@ -171,12 +171,10 @@ __attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First all the general purpose registers. */
pxTopOfStack--;
@ -252,13 +250,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
* enabled. */
enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
* the floating point hardware must call vPortTaskUsesFPU() before executing
* any floating point instructions. */
the floating point hardware must call vPortTaskUsesFPU() before executing
any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@ -276,12 +274,12 @@ BaseType_t xPortStartScheduler( void )
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
*
* Save the interrupt priority value that is about to be clobbered. */
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
* all possible bits. */
all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
@ -294,13 +292,13 @@ BaseType_t xPortStartScheduler( void )
}
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
* value. */
value. */
configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
* value. */
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
}
#endif /* conifgASSERT_DEFINED */
@ -313,25 +311,23 @@ BaseType_t xPortStartScheduler( void )
#if defined( GUEST )
#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
configASSERT( ulAPSR == portEL1 );
if( ulAPSR == portEL1 )
#else
configASSERT( ulAPSR == portEL3 );
if( ulAPSR == portEL3 )
#endif
{
/* Only continue if the binary point value is set to its lowest possible
* setting. See the comments in vPortValidateInterruptPriority() below for
* more information. */
setting. See the comments in vPortValidateInterruptPriority() below for
more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
{
/* Interrupts are turned off in the CPU itself to ensure a tick does
* not execute while the scheduler is being started. Interrupts are
* automatically turned back on in the CPU when the first task starts
* executing. */
not execute while the scheduler is being started. Interrupts are
automatically turned back on in the CPU when the first task starts
executing. */
portDISABLE_INTERRUPTS();
/* Start the timer that generates the tick ISR. */
@ -349,7 +345,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( ullCriticalNesting == 1000ULL );
}
/*-----------------------------------------------------------*/
@ -360,15 +356,15 @@ void vPortEnterCritical( void )
uxPortSetInterruptMask();
/* Now interrupts are disabled ullCriticalNesting can be accessed
* directly. Increment ullCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ullCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ullCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( ullCriticalNesting == 1ULL )
{
configASSERT( ullPortInterruptNesting == 0 );
@ -381,15 +377,15 @@ void vPortExitCritical( void )
if( ullCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
* exited. */
exited. */
ullCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
* priorities must be re-enabled. */
priorities must be re-enabled. */
if( ullCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
* should be unmasked. */
should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@ -416,10 +412,10 @@ void FreeRTOS_Tick_Handler( void )
#endif /* configASSERT_DEFINED */
/* Set interrupt mask before altering scheduler structures. The tick
* handler runs at the lowest priority, so interrupts cannot already be masked,
* so there is no need to save and restore the current mask value. It is
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
* updated. */
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. It is
necessary to turn off interrupts in the CPU itself while the ICCPMR is being
updated. */
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb sy \n"
"isb sy \n" ::: "memory" );
@ -442,11 +438,11 @@ void FreeRTOS_Tick_Handler( void )
void vPortTaskUsesFPU( void )
{
/* A task is registering the fact that it needs an FPU context. Set the
* FPU flag (which is saved as part of the task context). */
FPU flag (which is saved as part of the task context). */
ullPortTaskHasFPUContext = pdTRUE;
/* Consider initialising the FPSR here - but probably not necessary in
* AArch64. */
AArch64. */
}
/*-----------------------------------------------------------*/
@ -464,9 +460,8 @@ UBaseType_t uxPortSetInterruptMask( void )
uint32_t ulReturn;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
* updated. */
updated. */
portDISABLE_INTERRUPTS();
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@ -479,7 +474,6 @@ UBaseType_t uxPortSetInterruptMask( void )
__asm volatile ( "dsb sy \n"
"isb sy \n" ::: "memory" );
}
portENABLE_INTERRUPTS();
return ulReturn;
@ -491,33 +485,34 @@ UBaseType_t uxPortSetInterruptMask( void )
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
* an interrupt that has been assigned a priority above
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
* function. ISR safe FreeRTOS API functions must *only* be called
* from interrupts that have been assigned a priority at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* Numerically low interrupt priority numbers represent logically high
* interrupt priorities, therefore the priority of the interrupt must
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible. */
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible. */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
* that define each interrupt's priority to be split between bits that
* define the interrupt's pre-emption priority bits and bits that define
* the interrupt's sub-priority. For simplicity all bits must be defined
* to be pre-emption priority bits. The following assertion will fail if
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority. For simplicity all bits must be defined
to be pre-emption priority bits. The following assertion will fail if
this is not the case (if some bits represent a sub-priority).
The priority grouping is configured by the GIC's binary point register
(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/

20
portable/GCC/ARM_CA53_64_BIT/portmacro.h
View file

@ -59,7 +59,7 @@
#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -91,7 +91,6 @@
#else
#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
#endif
/*-----------------------------------------------------------
* Critical section control
*----------------------------------------------------------*/
@ -114,7 +113,7 @@
/* These macros do not globally disable/enable interrupts. They do mask off
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
@ -123,17 +122,17 @@
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not required for this port but included in case common demo code that uses these
* macros is used. */
not required for this port but included in case common demo code that uses these
macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
* handler for whichever peripheral is used to generate the RTOS tick. */
handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
* before any floating point instructions are executed. */
before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -171,7 +170,7 @@
/* The number of bits to shift for an interrupt priority is dependent on the
* number of bits implemented by the interrupt controller. */
number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
#define portPRIORITY_SHIFT 4
#define portMAX_BINARY_POINT_VALUE 3
@ -187,9 +186,9 @@
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#else
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#endif
/* Interrupt controller access addresses. */
#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
@ -209,3 +208,4 @@
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */

199
portable/GCC/ARM_CA9/port.c
View file

@ -33,23 +33,23 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
#error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
@ -73,24 +73,24 @@
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
* portmacro.h. */
portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
* this value. */
this value. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
* (but the lowest) interrupt priority. */
(but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -100,19 +100,19 @@
#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
* point is zero. */
point is zero. */
#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
* mode. */
mode. */
#define portAPSR_USER_MODE ( 0x10 )
/* The critical section macros only mask interrupts up to an application
* determined priority level. Sometimes it is necessary to turn interrupt off in
* the CPU itself before modifying certain hardware registers. */
determined priority level. Sometimes it is necessary to turn interrupt off in
the CPU itself before modifying certain hardware registers. */
#define portCPU_IRQ_DISABLE() \
__asm volatile ( "CPSID i" ::: "memory" ); \
__asm volatile ( "DSB" ); \
@ -139,8 +139,8 @@
#define portBIT_0_SET ( ( uint8_t ) 0x01 )
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
@ -148,7 +148,7 @@
#endif
/* The space on the stack required to hold the FPU registers. This is 32 64-bit
* registers, plus a 32-bit status register. */
registers, plus a 32-bit status register. */
#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
/*-----------------------------------------------------------*/
@ -188,21 +188,21 @@ void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak )
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
* a floating point context must be saved and restored for the task. */
a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file. */
@ -216,16 +216,14 @@ __attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro.
*
* The fist real value on the stack is the status register, which is set for
* system mode, with interrupts enabled. A few NULLs are added first to ensure
* GDB does not try decoding a non-existent return address. */
expected by the portRESTORE_CONTEXT() macro.
The fist real value on the stack is the status register, which is set for
system mode, with interrupts enabled. A few NULLs are added first to ensure
GDB does not try decoding a non-existent return address. */
*pxTopOfStack = ( StackType_t ) NULL;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL;
@ -277,21 +275,21 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
* enabled. */
enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
#if( configUSE_TASK_FPU_SUPPORT == 1 )
{
/* The task will start without a floating point context. A task that
* uses the floating point hardware must call vPortTaskUsesFPU() before
* executing any floating point instructions. */
uses the floating point hardware must call vPortTaskUsesFPU() before
executing any floating point instructions. */
pxTopOfStack--;
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
}
#elif( configUSE_TASK_FPU_SUPPORT == 2 )
{
/* The task will start with a floating point context. Leave enough
* space for the registers - and ensure they are initialised to 0. */
space for the registers - and ensure they are initialised to 0. */
pxTopOfStack -= portFPU_REGISTER_WORDS;
memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
@ -299,11 +297,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = pdTRUE;
ulPortTaskHasFPUContext = pdTRUE;
}
#else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
#else
{
#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
}
#endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
#endif
return pxTopOfStack;
}
@ -312,17 +310,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ; ; )
{
}
for( ;; );
}
/*-----------------------------------------------------------*/
@ -337,12 +332,12 @@ BaseType_t xPortStartScheduler( void )
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
*
* Save the interrupt priority value that is about to be clobbered. */
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
* all possible bits. */
all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
@ -355,18 +350,18 @@ BaseType_t xPortStartScheduler( void )
}
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
* value. */
value. */
configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
* value. */
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
}
#endif /* conifgASSERT_DEFINED */
/* Only continue if the CPU is not in User mode. The CPU must be in a
* Privileged mode for the scheduler to start. */
Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
@ -374,16 +369,16 @@ BaseType_t xPortStartScheduler( void )
if( ulAPSR != portAPSR_USER_MODE )
{
/* Only continue if the binary point value is set to its lowest possible
* setting. See the comments in vPortValidateInterruptPriority() below for
* more information. */
setting. See the comments in vPortValidateInterruptPriority() below for
more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
{
/* Interrupts are turned off in the CPU itself to ensure tick does
* not execute while the scheduler is being started. Interrupts are
* automatically turned back on in the CPU when the first task starts
* executing. */
not execute while the scheduler is being started. Interrupts are
automatically turned back on in the CPU when the first task starts
executing. */
portCPU_IRQ_DISABLE();
/* Start the timer that generates the tick ISR. */
@ -395,10 +390,10 @@ BaseType_t xPortStartScheduler( void )
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
* a non-privileged mode or the binary point register was not set to its lowest
* possible value. prvTaskExitError() is referenced to prevent a compiler
* warning about it being defined but not referenced in the case that the user
* defines their own exit address. */
a non-privileged mode or the binary point register was not set to its lowest
possible value. prvTaskExitError() is referenced to prevent a compiler
warning about it being defined but not referenced in the case that the user
defines their own exit address. */
( void ) prvTaskExitError;
return 0;
}
@ -407,7 +402,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -418,15 +413,15 @@ void vPortEnterCritical( void )
ulPortSetInterruptMask();
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@ -439,15 +434,15 @@ void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
* exited. */
exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
* priorities must be re-enabled. */
priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
* should be unmasked. */
should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@ -457,10 +452,10 @@ void vPortExitCritical( void )
void FreeRTOS_Tick_Handler( void )
{
/* Set interrupt mask before altering scheduler structures. The tick
* handler runs at the lowest priority, so interrupts cannot already be masked,
* so there is no need to save and restore the current mask value. It is
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
* updated. */
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. It is
necessary to turn off interrupts in the CPU itself while the ICCPMR is being
updated. */
portCPU_IRQ_DISABLE();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb \n"
@ -486,7 +481,7 @@ void FreeRTOS_Tick_Handler( void )
uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
* FPU flag (which is saved as part of the task context). */
FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
@ -510,9 +505,8 @@ uint32_t ulPortSetInterruptMask( void )
uint32_t ulReturn;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
* updated. */
updated. */
portCPU_IRQ_DISABLE();
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@ -525,7 +519,6 @@ uint32_t ulPortSetInterruptMask( void )
__asm volatile ( "dsb \n"
"isb \n" ::: "memory" );
}
portCPU_IRQ_ENABLE();
return ulReturn;
@ -537,31 +530,31 @@ uint32_t ulPortSetInterruptMask( void )
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
* an interrupt that has been assigned a priority above
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
* function. ISR safe FreeRTOS API functions must *only* be called
* from interrupts that have been assigned a priority at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* Numerically low interrupt priority numbers represent logically high
* interrupt priorities, therefore the priority of the interrupt must
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible. */
an interrupt that has been assigned a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
function. ISR safe FreeRTOS API functions must *only* be called
from interrupts that have been assigned a priority at or below
configMAX_SYSCALL_INTERRUPT_PRIORITY.
Numerically low interrupt priority numbers represent logically high
interrupt priorities, therefore the priority of the interrupt must
be set to a value equal to or numerically *higher* than
configMAX_SYSCALL_INTERRUPT_PRIORITY.
FreeRTOS maintains separate thread and ISR API functions to ensure
interrupt entry is as fast and simple as possible. */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
* that define each interrupt's priority to be split between bits that
* define the interrupt's pre-emption priority bits and bits that define
* the interrupt's sub-priority. For simplicity all bits must be defined
* to be pre-emption priority bits. The following assertion will fail if
* this is not the case (if some bits represent a sub-priority).
*
* The priority grouping is configured by the GIC's binary point register
* (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
* possible value (which may be above 0). */
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority. For simplicity all bits must be defined
to be pre-emption priority bits. The following assertion will fail if
this is not the case (if some bits represent a sub-priority).
The priority grouping is configured by the GIC's binary point register
(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}

28
portable/GCC/ARM_CA9/portmacro.h
View file

@ -59,7 +59,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -99,7 +99,7 @@
extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
@ -110,26 +110,25 @@
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not required for this port but included in case common demo code that uses these
* macros is used. */
not required for this port but included in case common demo code that uses these
macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
* handler for whichever peripheral is used to generate the RTOS tick. */
handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
* created without an FPU context and must call vPortTaskUsesFPU() to give
* themselves an FPU context before using any FPU instructions. If
* configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
* by default. */
created without an FPU context and must call vPortTaskUsesFPU() to give
themselves an FPU context before using any FPU instructions. If
configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
by default. */
#if( configUSE_TASK_FPU_SUPPORT != 2 )
void vPortTaskUsesFPU( void );
#else
/* Each task has an FPU context already, so define this function away to
* nothing to prevent it being called accidentally. */
nothing to prevent it being called accidentally. */
#define vPortTaskUsesFPU()
#endif
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -168,7 +167,7 @@
/* The number of bits to shift for an interrupt priority is dependent on the
* number of bits implemented by the interrupt controller. */
number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
#define portPRIORITY_SHIFT 4
#define portMAX_BINARY_POINT_VALUE 3
@ -184,9 +183,9 @@
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#else
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#endif
/* Interrupt controller access addresses. */
#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
@ -206,3 +205,4 @@
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */

6
portable/GCC/ARM_CM23/non_secure/port.c
View file

@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;

8
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
View file

@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
}
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;

8
portable/GCC/ARM_CM33/non_secure/port.c
View file

@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
}
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;

8
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
View file

@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
}
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;

9
portable/GCC/ARM_CM4_MPU/portmacro.h
View file

@ -29,9 +29,12 @@
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@ -80,6 +83,7 @@
#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
* Register (RASR). */
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
@ -139,7 +143,7 @@
| | | | | bus. See the table below for the cacheability policy | |
| | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
|
+-----------------------------------------+----------------------------------------+
| AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
+-----------------------------------------+----------------------------------------+
@ -387,8 +391,11 @@
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
#endif
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

5
portable/GCC/ARM_CR5/port.c
View file

@ -149,7 +149,8 @@
/* Adding the necessary stuff in order to be able to determine from C code wheter or not the IRQs are enabled at the processor level (not interrupt controller level) */
#define GET_CPSR() ({u32 rval = 0U; \
#define GET_CPSR() \
( { u32 rval = 0U; \
__asm__ __volatile__ ( \
"mrs %0, cpsr\n"\
: "=r" ( rval ) \
@ -516,7 +517,9 @@ uint32_t ulPortSetInterruptMask( void )
* critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a
* switch of context while already performing a switch context. */
if( !wasIRQDisabled )
{
portCPU_IRQ_ENABLE();
}
return ulReturn;
}

98
portable/GCC/ARM_CRx_No_GIC/port.c
View file

@ -48,14 +48,14 @@
#endif
/* A critical section is exited when the critical section nesting count reaches
* this value. */
this value. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
@ -67,12 +67,12 @@
#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
* mode. */
mode. */
#define portAPSR_USER_MODE ( 0x10 )
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
@ -95,21 +95,21 @@ static void prvTaskExitError( void );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
* variable has to be stored as part of the task context and must be initialised to
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
* a floating point context must be saved and restored for the task. */
a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file to clear an interrupt. */
@ -120,16 +120,14 @@ __attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro.
*
* The fist real value on the stack is the status register, which is set for
* system mode, with interrupts enabled. A few NULLs are added first to ensure
* GDB does not try decoding a non-existent return address. */
expected by the portRESTORE_CONTEXT() macro.
The fist real value on the stack is the status register, which is set for
system mode, with interrupts enabled. A few NULLs are added first to ensure
GDB does not try decoding a non-existent return address. */
*pxTopOfStack = ( StackType_t ) NULL;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL;
@ -181,13 +179,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
* enabled. */
enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
* the floating point hardware must call vPortTaskUsesFPU() before executing
* any floating point instructions. */
the floating point hardware must call vPortTaskUsesFPU() before executing
any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@ -197,17 +195,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ; ; )
{
}
for( ;; );
}
/*-----------------------------------------------------------*/
@ -216,9 +211,8 @@ BaseType_t xPortStartScheduler( void )
uint32_t ulAPSR;
/* Only continue if the CPU is not in User mode. The CPU must be in a
* Privileged mode for the scheduler to start. */
Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
@ -233,10 +227,10 @@ BaseType_t xPortStartScheduler( void )
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
* a non-privileged mode or the binary point register was not set to its lowest
* possible value. prvTaskExitError() is referenced to prevent a compiler
* warning about it being defined but not referenced in the case that the user
* defines their own exit address. */
a non-privileged mode or the binary point register was not set to its lowest
possible value. prvTaskExitError() is referenced to prevent a compiler
warning about it being defined but not referenced in the case that the user
defines their own exit address. */
( void ) prvTaskExitError;
return 0;
}
@ -245,7 +239,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -255,15 +249,15 @@ void vPortEnterCritical( void )
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@ -276,15 +270,15 @@ void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
* exited. */
exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
* priorities must be re-enabled. */
priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
* should be unmasked. */
should be unmasked. */
portENABLE_INTERRUPTS();
}
}
@ -314,10 +308,12 @@ void vPortTaskUsesFPU( void )
uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
* FPU flag (which is saved as part of the task context). */
FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
__asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
}
/*-----------------------------------------------------------*/

20
portable/GCC/ARM_CRx_No_GIC/portmacro.h
View file

@ -59,7 +59,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -85,8 +85,7 @@
}
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
#define portYIELD() \
__asm volatile ( "SWI 0 \n"\
#define portYIELD() __asm volatile ( "SWI 0 \n" \
"ISB " ::: "memory" );
@ -104,12 +103,11 @@
#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
/* In the absence of a priority mask register, these functions and macros
* globally enable and disable interrupts. */
globally enable and disable interrupts. */
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
#define portDISABLE_INTERRUPTS() \
__asm volatile ( "CPSID i \n" \
#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
"DSB \n" \
"ISB " ::: "memory" );
@ -118,7 +116,6 @@
volatile uint32_t ulCPSR;
__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
ulCPSR &= portINTERRUPT_ENABLE_BIT;
portDISABLE_INTERRUPTS();
return ulCPSR;
@ -130,8 +127,8 @@
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not required for this port but included in case common demo code that uses these
* macros is used. */
not required for this port but included in case common demo code that uses these
macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
@ -142,11 +139,11 @@
#endif
/* Prototype of the FreeRTOS tick handler. This must be installed as the
* handler for whichever peripheral is used to generate the RTOS tick. */
handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
* before any floating point instructions are executed. */
before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
@ -181,3 +178,4 @@
#endif /* PORTMACRO_H */

45
portable/GCC/ATMega323/port.c
View file

@ -26,12 +26,12 @@
*/
/*
*
* Changes from V2.6.0
*
Changes from V2.6.0
+ AVR port - Replaced the inb() and outb() functions with direct memory
+ access. This allows the port to be built with the 20050414 build of
+ WinAVR.
access. This allows the port to be built with the 20050414 build of
WinAVR.
*/
#include <stdlib.h>
@ -56,7 +56,7 @@
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
* any details of its type. */
any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
@ -182,14 +182,12 @@ static void prvSetupTimerInterrupt( void );
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint16_t usAddress;
/* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging. */
This is just useful for debugging. */
*pxTopOfStack = 0x11;
pxTopOfStack--;
@ -199,12 +197,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Simulate how the stack would look after a call to vPortYield() generated by
* the compiler. */
the compiler. */
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* The start of the task code will be popped off the stack last, so place
* it on first. */
it on first. */
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -214,9 +212,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
* portSAVE_CONTEXT places the flags on the stack immediately after r0
* to ensure the interrupts get disabled as soon as possible, and so ensuring
* the stack use is minimal should a context switch interrupt occur. */
portSAVE_CONTEXT places the flags on the stack immediately after r0
to ensure the interrupts get disabled as soon as possible, and so ensuring
the stack use is minimal should a context switch interrupt occur. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
@ -308,7 +306,7 @@ BaseType_t xPortStartScheduler( void )
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
* jump to the start of the task the context of which we have just restored. */
jump to the start of the task the context of which we have just restored. */
asm volatile ( "ret" );
/* Should not get here. */
@ -319,7 +317,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the AVR port will get stopped. If required simply
* disable the tick interrupt here. */
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@ -348,12 +346,10 @@ void vPortYieldFromTick( void ) __attribute__( ( naked ) );
void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
portRESTORE_CONTEXT();
asm volatile ( "ret" );
@ -369,7 +365,7 @@ static void prvSetupTimerInterrupt( void )
uint8_t ucHighByte, ucLowByte;
/* Using 16bit timer 1 to generate the tick. Correct fuses must be
* selected for the configCPU_CLOCK_HZ clock. */
selected for the configCPU_CLOCK_HZ clock. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
@ -380,7 +376,7 @@ static void prvSetupTimerInterrupt( void )
ulCompareMatch -= ( uint32_t ) 1;
/* Setup compare match value for compare match A. Interrupts are disabled
* before this is called so we need not worry here. */
before this is called so we need not worry here. */
ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
ulCompareMatch >>= 8;
ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
@ -392,7 +388,7 @@ static void prvSetupTimerInterrupt( void )
TCCR1B = ucLowByte;
/* Enable the interrupt - this is okay as interrupt are currently globally
* disabled. */
disabled. */
ucLowByte = TIMSK;
ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
TIMSK = ucLowByte;
@ -424,4 +420,7 @@ static void prvSetupTimerInterrupt( void )
{
xTaskIncrementTick();
}
#endif /* if configUSE_PREEMPTION == 1 */
#endif

13
portable/GCC/ATMega323/portmacro.h
View file

@ -26,10 +26,10 @@
*/
/*
* Changes from V1.2.3
*
Changes from V1.2.3
+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+ base 16.
base 16.
*/
#ifndef PORTMACRO_H
@ -72,13 +72,11 @@
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portENTER_CRITICAL() \
asm volatile ( "in __tmp_reg__, __SREG__"::); \
#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \
asm volatile ( "cli" :: ); \
asm volatile ( "push __tmp_reg__" :: )
#define portEXIT_CRITICAL() \
asm volatile ( "pop __tmp_reg__"::); \
#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \
asm volatile ( "out __SREG__, __tmp_reg__" :: )
#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: );
@ -106,3 +104,4 @@
#endif
#endif /* PORTMACRO_H */

77
portable/GCC/AVR32_UC3/port.c
View file

@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@ -106,11 +105,13 @@ void _init_startup( void )
INTC_init_interrupts();
#if configHEAP_INIT
/* Initialize the heap used by malloc. */
for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
{
*pxMem++ = 0xA5A5A5A5;
}
#endif
/* Give the used CPU clock frequency to Newlib, so it can work properly. */
@ -131,7 +132,7 @@ void _init_startup( void )
sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
usart_init( configDBG_USART_BAUDRATE );
}
#endif /* if configDBG */
#endif
}
/*-----------------------------------------------------------*/
@ -171,8 +172,7 @@ void __malloc_unlock( struct _reent * ptr )
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
void * pvPortRealloc( void * pv,
size_t xWantedSize )
void *pvPortRealloc( void *pv, size_t xWantedSize )
{
void *pvReturn;
@ -187,10 +187,9 @@ void * pvPortRealloc( void * pv,
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick. */
simply increment the system tick. */
/* The preemptive scheduler is defined as "naked" as the full context is saved
* on entry as part of the context switch. */
on entry as part of the context switch. */
__attribute__((__naked__)) static void vTick( void )
{
/* Save the context of the interrupted task. */
@ -200,14 +199,13 @@ __attribute__( ( __naked__ ) ) static void vTick( void )
/* Clear the interrupt flag. */
prvClearTcInt();
#else
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
* clock cycles from now. */
clock cycles from now. */
prvScheduleNextTick();
#endif
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
* calls in a critical section . */
calls in a critical section . */
portENTER_CRITICAL();
xTaskIncrementTick();
portEXIT_CRITICAL();
@ -227,17 +225,17 @@ __attribute__( ( __naked__ ) ) void SCALLYield( void )
/*-----------------------------------------------------------*/
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
different optimisation levels. The interrupt flags can therefore not always
be saved to the stack. Instead the critical section nesting level is stored
in a variable, which is then saved as part of the stack context. */
__attribute__((__noinline__)) void vPortEnterCritical( void )
{
/* Disable interrupts */
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -247,7 +245,6 @@ __attribute__( ( __noinline__ ) ) void vPortExitCritical( void )
if(ulCriticalNesting > portNO_CRITICAL_NESTING)
{
ulCriticalNesting--;
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable all interrupt/exception. */
@ -263,12 +260,10 @@ __attribute__( ( __noinline__ ) ) void vPortExitCritical( void )
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* When the task starts, it will expect to find the function parameter in R12. */
pxTopOfStack--;
@ -297,7 +292,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -311,12 +306,12 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the AVR32 port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
* clock cycles from now. */
clock cycles from now. */
#if( configTICK_USE_TC==0 )
static void prvScheduleFirstTick(void)
{
@ -324,14 +319,12 @@ void vPortEndScheduler( void )
lCycles = Get_system_register(AVR32_COUNT);
lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
// generation feature does not get disabled.
if(0 == lCycles)
{
lCycles++;
}
Set_system_register(AVR32_COMPARE, lCycles);
}
@ -341,38 +334,35 @@ void vPortEndScheduler( void )
lCycles = Get_system_register(AVR32_COMPARE);
lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
// generation feature does not get disabled.
if(0 == lCycles)
{
lCycles++;
}
lCount = Get_system_register(AVR32_COUNT);
if( lCycles < lCount )
{ /* We missed a tick, recover for the next. */
{ // We missed a tick, recover for the next.
lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
}
Set_system_register(AVR32_COMPARE, lCycles);
}
#else /* if ( configTICK_USE_TC == 0 ) */
#else
__attribute__((__noinline__)) static void prvClearTcInt(void)
{
AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
}
#endif /* if ( configTICK_USE_TC == 0 ) */
#endif
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt(void)
{
#if( configTICK_USE_TC==1 )
volatile avr32_tc_t *tc = &AVR32_TC;
/* Options for waveform genration. */
// Options for waveform genration.
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
@ -410,13 +400,14 @@ static void prvSetupTimerInterrupt( void )
.lovrs=0,
.covfs=0,
};
#endif /* if ( configTICK_USE_TC == 1 ) */
#endif
/* Disable all interrupt/exception. */
portDISABLE_INTERRUPTS();
/* Register the compare interrupt handler to the interrupt controller and
* enable the compare interrupt. */
enable the compare interrupt. */
#if( configTICK_USE_TC==1 )
{
@ -426,8 +417,8 @@ static void prvSetupTimerInterrupt( void )
tc_init_waveform(tc, &waveform_opt);
/* Set the compare triggers.
* Remember TC counter is 16-bits, so counting second is not possible!
* That's why we configure it to count ms. */
Remember TC counter is 16-bits, so counting second is not possible!
That's why we configure it to count ms. */
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
@ -435,10 +426,10 @@ static void prvSetupTimerInterrupt( void )
/* Start the timer/counter. */
tc_start(tc, configTICK_TC_CHANNEL);
}
#else /* if ( configTICK_USE_TC == 1 ) */
#else
{
INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
prvScheduleFirstTick();
}
#endif /* if ( configTICK_USE_TC == 1 ) */
#endif
}

50
portable/GCC/AVR32_UC3/portmacro.h
View file

@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@ -149,8 +148,7 @@
/* Added as there is no such function in FreeRTOS. */
extern void * pvPortRealloc( void * pv,
size_t xSize );
extern void *pvPortRealloc( void *pv, size_t xSize );
/*-----------------------------------------------------------*/
@ -207,25 +205,25 @@
* are not the same between INT0..3 exceptions and the scall exception.
*/
/* Task context stack layout: */
/* R8 (*) */
/* R9 (*) */
/* R10 (*) */
/* R11 (*) */
/* R12 (*) */
/* R14/LR (*) */
/* R15/PC (*) */
/* SR (*) */
/* R0 */
/* R1 */
/* R2 */
/* R3 */
/* R4 */
/* R5 */
/* R6 */
/* R7 */
/* ulCriticalNesting */
/* (*) automatically done for INT0..INT3, but not for SCALL */
// Task context stack layout:
// R8 (*)
// R9 (*)
// R10 (*)
// R11 (*)
// R12 (*)
// R14/LR (*)
// R15/PC (*)
// SR (*)
// R0
// R1
// R2
// R3
// R4
// R5
// R6
// R7
// ulCriticalNesting
// (*) automatically done for INT0..INT3, but not for SCALL
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
@ -260,7 +258,7 @@
); \
}
#else /* if configUSE_PREEMPTION == 0 */
#else
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
@ -374,7 +372,7 @@
); \
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
/*
@ -536,7 +534,7 @@
); \
}
#else /* if configUSE_PREEMPTION == 0 */
#else
/*
* ISR entry and exit macros. These are only required if a task switch
@ -653,7 +651,7 @@
); \
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
#define portYIELD() {__asm__ __volatile__ ("scall");}

38
portable/GCC/AVR_AVRDx/port.c
View file

@ -43,7 +43,7 @@
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
* any details of its type. */
typedef void RTOS_TCB_t;
extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
@ -171,23 +171,25 @@ static void prvSetupTimerInterrupt(void);
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint16_t usAddress;
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. Uncomment if needed. */
// *pxTopOfStack = 0x11;
// pxTopOfStack--;
// *pxTopOfStack = 0x22;
// pxTopOfStack--;
// *pxTopOfStack = 0x33;
// pxTopOfStack--;
* This is just useful for debugging. Uncomment if needed. */
/* *pxTopOfStack = 0x11; */
/* pxTopOfStack--; */
/* *pxTopOfStack = 0x22; */
/* pxTopOfStack--; */
/* *pxTopOfStack = 0x33; */
/* pxTopOfStack--; */
/* The start of the task code will be popped off the stack last, so place
it on first. */
* it on first. */
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -197,9 +199,9 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
portSAVE_CONTEXT places the flags on the stack immediately after r0
to ensure the interrupts get disabled as soon as possible, and so ensuring
the stack use is minimal should a context switch interrupt occur. */
* portSAVE_CONTEXT places the flags on the stack immediately after r0
* to ensure the interrupts get disabled as soon as possible, and so ensuring
* the stack use is minimal should a context switch interrupt occur. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
@ -239,7 +241,7 @@ BaseType_t xPortStartScheduler(void)
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
jump to the start of the task the context of which we have just restored. */
* jump to the start of the task the context of which we have just restored. */
asm volatile ( "ret" );
/* Should not get here. */
@ -291,7 +293,9 @@ void vPortYieldFromTick(void) __attribute__((naked));
void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
if (xTaskIncrementTick() != pdFALSE) {
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
@ -326,7 +330,7 @@ ISR(TICK_INT_vect, ISR_NAKED)
asm volatile ( "reti" );
}
#else
#else /* if configUSE_PREEMPTION == 1 */
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
@ -339,4 +343,4 @@ ISR(TICK_INT_vect)
INT_FLAGS = INT_MASK;
xTaskIncrementTick();
}
#endif
#endif /* if configUSE_PREEMPTION == 1 */

24
portable/GCC/AVR_AVRDx/porthardware.h
View file

@ -21,7 +21,8 @@
#define INT_FLAGS TCB0_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB0.INTCTRL = TCB_CAPT_bm; \
TCB0.CTRLA = TCB_ENABLE_bm; \
@ -33,7 +34,8 @@
#define INT_FLAGS TCB1_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB1.INTCTRL = TCB_CAPT_bm; \
TCB1.CTRLA = TCB_ENABLE_bm; \
@ -45,7 +47,8 @@
#define INT_FLAGS TCB2_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB2.INTCTRL = TCB_CAPT_bm; \
TCB2.CTRLA = TCB_ENABLE_bm; \
@ -57,7 +60,8 @@
#define INT_FLAGS TCB3_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB3.INTCTRL = TCB_CAPT_bm; \
TCB3.CTRLA = TCB_ENABLE_bm; \
@ -69,7 +73,8 @@
#define INT_FLAGS TCB4_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB4.INTCTRL = TCB_CAPT_bm; \
TCB4.CTRLA = TCB_ENABLE_bm; \
@ -83,20 +88,21 @@
/* Hertz to period for RTC setup */
#define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
#define TICK_init() { \
while (RTC.STATUS > 0); \
#define TICK_init() \
{ \
while( RTC.STATUS > 0 ) {; } \
RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
RTC.INTCTRL |= 1 << RTC_OVF_bp; \
}
#else
#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
#endif
#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/

4
portable/GCC/AVR_AVRDx/portmacro.h
View file

@ -28,9 +28,11 @@
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@ -99,8 +101,10 @@ extern void vPortYieldFromISR(void) __attribute__((naked));
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

38
portable/GCC/AVR_Mega0/port.c
View file

@ -43,7 +43,7 @@
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
* any details of its type. */
typedef void RTOS_TCB_t;
extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
@ -167,23 +167,25 @@ static void prvSetupTimerInterrupt(void);
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint16_t usAddress;
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. Uncomment if needed. */
// *pxTopOfStack = 0x11;
// pxTopOfStack--;
// *pxTopOfStack = 0x22;
// pxTopOfStack--;
// *pxTopOfStack = 0x33;
// pxTopOfStack--;
* This is just useful for debugging. Uncomment if needed. */
/* *pxTopOfStack = 0x11; */
/* pxTopOfStack--; */
/* *pxTopOfStack = 0x22; */
/* pxTopOfStack--; */
/* *pxTopOfStack = 0x33; */
/* pxTopOfStack--; */
/* The start of the task code will be popped off the stack last, so place
it on first. */
* it on first. */
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -193,9 +195,9 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
portSAVE_CONTEXT places the flags on the stack immediately after r0
to ensure the interrupts get disabled as soon as possible, and so ensuring
the stack use is minimal should a context switch interrupt occur. */
* portSAVE_CONTEXT places the flags on the stack immediately after r0
* to ensure the interrupts get disabled as soon as possible, and so ensuring
* the stack use is minimal should a context switch interrupt occur. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
@ -233,7 +235,7 @@ BaseType_t xPortStartScheduler(void)
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
jump to the start of the task the context of which we have just restored. */
* jump to the start of the task the context of which we have just restored. */
asm volatile ( "ret" );
/* Should not get here. */
@ -285,7 +287,9 @@ void vPortYieldFromTick(void) __attribute__((naked));
void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
if (xTaskIncrementTick() != pdFALSE) {
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
@ -320,7 +324,7 @@ ISR(TICK_INT_vect, ISR_NAKED)
asm volatile ( "reti" );
}
#else
#else /* if configUSE_PREEMPTION == 1 */
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
@ -333,4 +337,4 @@ ISR(TICK_INT_vect)
INT_FLAGS = INT_MASK;
xTaskIncrementTick();
}
#endif
#endif /* if configUSE_PREEMPTION == 1 */

21
portable/GCC/AVR_Mega0/porthardware.h
View file

@ -21,7 +21,8 @@
#define INT_FLAGS TCB0_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB0.INTCTRL = TCB_CAPT_bm; \
TCB0.CTRLA = TCB_ENABLE_bm; \
@ -33,7 +34,8 @@
#define INT_FLAGS TCB1_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB1.INTCTRL = TCB_CAPT_bm; \
TCB1.CTRLA = TCB_ENABLE_bm; \
@ -45,7 +47,8 @@
#define INT_FLAGS TCB2_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB2.INTCTRL = TCB_CAPT_bm; \
TCB2.CTRLA = TCB_ENABLE_bm; \
@ -57,7 +60,8 @@
#define INT_FLAGS TCB3_INTFLAGS
#define INT_MASK TCB_CAPT_bm
#define TICK_init() { \
#define TICK_init() \
{ \
TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
TCB3.INTCTRL = TCB_CAPT_bm; \
TCB3.CTRLA = TCB_ENABLE_bm; \
@ -71,20 +75,21 @@
/* Hertz to period for RTC setup */
#define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
#define TICK_init() { \
while (RTC.STATUS > 0); \
#define TICK_init() \
{ \
while( RTC.STATUS > 0 ) {; } \
RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
RTC.INTCTRL |= 1 << RTC_OVF_bp; \
}
#else
#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
#endif
#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/

4
portable/GCC/AVR_Mega0/portmacro.h
View file

@ -28,9 +28,11 @@
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@ -99,8 +101,10 @@ extern void vPortYieldFromISR(void) __attribute__((naked));
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

6
portable/GCC/CORTUS_APS3/port.c
View file

@ -48,12 +48,10 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Make space on the stack for the context - this leaves a couple of spaces
* empty. */
empty. */
pxTopOfStack -= 20;
/* Fill the registers with known values to assist debugging. */

18
portable/GCC/ColdFire_V2/port.c
View file

@ -35,14 +35,12 @@
#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
* will be set to 0 prior to the first task being started. */
will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack--;
@ -91,20 +89,19 @@ void vPortEnterCritical( void )
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
* critical section being entered. */
critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( MCF_INTC0_INTFRCL == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -112,7 +109,6 @@ void vPortEnterCritical( void )
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
@ -130,3 +126,9 @@ void vPortYieldHandler( void )
vTaskSwitchContext();
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}

4
portable/GCC/ColdFire_V2/portmacro.h
View file

@ -100,8 +100,7 @@
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
if( xSwitchRequired != pdFALSE ) \
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
{ \
portYIELD(); \
}
@ -112,3 +111,4 @@
#endif
#endif /* PORTMACRO_H */

26
portable/GCC/H8S2329/port.c
View file

@ -63,22 +63,19 @@ void vPortYield( void ) __attribute__( ( saveall, interrupt_handler ) );
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t ulValue;
/* This requires an even address. */
ulValue = ( uint32_t ) pxTopOfStack;
if( ulValue & 1UL )
{
pxTopOfStack = pxTopOfStack - 1;
}
/* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging. */
This is just useful for debugging. */
pxTopOfStack--;
*pxTopOfStack = 0xaa;
pxTopOfStack--;
@ -89,7 +86,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = 0xdd;
/* The initial stack mimics an interrupt stack. First there is the program
* counter (24 bits). */
counter (24 bits). */
ulValue = ( uint32_t ) pxCode;
pxTopOfStack--;
@ -106,8 +103,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = portINITIAL_CCR;
/* Next all the general purpose registers - with the parameters being passed
* in ER0. The parameter order must match that used by the compiler when the
* "saveall" function attribute is used. */
in ER0. The parameter order must match that used by the compiler when the
"saveall" function attribute is used. */
/* ER6 */
pxTopOfStack--;
@ -196,8 +193,8 @@ BaseType_t xPortStartScheduler( void )
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. This
* mirrors the function epilogue code generated by the compiler when the
* "saveall" function attribute is used. */
mirrors the function epilogue code generated by the compiler when the
"saveall" function attribute is used. */
asm volatile (
"MOV.L @_pxCurrentTCB, ER6 \n\t"
"MOV.L @ER6, ER7 \n\t"
@ -260,7 +257,7 @@ void vPortYield( void )
portRESTORE_STACK_POINTER();
}
#else /* if ( configUSE_PREEMPTION == 1 ) */
#else
/*
* The cooperative scheduler is being used so all we have to do is
@ -276,7 +273,7 @@ void vPortYield( void )
TSR1 &= ~0x01;
}
#endif /* if ( configUSE_PREEMPTION == 1 ) */
#endif
/*-----------------------------------------------------------*/
/*
@ -296,8 +293,11 @@ static void prvSetupTimerInterrupt( void )
TGR1A = ulCompareMatch;
/* Start the timer and enable the interrupt - we can do this here as
* interrupts are globally disabled when this function is called. */
interrupts are globally disabled when this function is called. */
TIER1 |= portTGRA_INTERRUPT_ENABLE;
TSTR |= portTIMER_CHANNEL;
}
/*-----------------------------------------------------------*/

14
portable/GCC/H8S2329/portmacro.h
View file

@ -78,8 +78,7 @@
#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" );
/* Push the CCR then disable interrupts. */
#define portENTER_CRITICAL() \
asm volatile ( "STC CCR, @-ER7" ); \
#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \
portDISABLE_INTERRUPTS();
/* Pop the CCR to set the interrupt masking back to its previous state. */
@ -89,9 +88,9 @@
/* Task utilities. */
/* Context switch macros. These macros are very simple as the context
* is saved simply by selecting the saveall attribute of the context switch
* interrupt service routines. These macros save and restore the stack
* pointer to the TCB. */
is saved simply by selecting the saveall attribute of the context switch
interrupt service routines. These macros save and restore the stack
pointer to the TCB. */
#define portSAVE_STACK_POINTER() \
extern void* pxCurrentTCB; \
@ -117,14 +116,14 @@
/* Macros to allow a context switch from within an application ISR. */
#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
#define portEXIT_SWITCHING_ISR( x ) \
if( x ) \
{ \
extern void vTaskSwitchContext( void ); \
vTaskSwitchContext(); \
} \
} \
portRESTORE_STACK_POINTER();
} portRESTORE_STACK_POINTER();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
@ -136,3 +135,4 @@
#endif
#endif /* PORTMACRO_H */

63
portable/GCC/HCS12/port.c
View file

@ -46,40 +46,40 @@
static void prvSetupTimerInterrupt( void );
/* NOTE: Interrupt service routines must be in non-banked memory - as does the
* scheduler startup function. */
scheduler startup function. */
#define ATTR_NEAR __attribute__((near))
/* Manual context switch function. This is the SWI ISR. */
/* __attribute__((interrupt)) */
// __attribute__((interrupt))
void ATTR_NEAR vPortYield( void );
/* Tick context switch function. This is the timer ISR. */
/* __attribute__((interrupt)) */
// __attribute__((interrupt))
void ATTR_NEAR vPortTickInterrupt( void );
/* Function in non-banked memory which actually switches to first task. */
BaseType_t ATTR_NEAR xStartSchedulerNear( void );
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
* critical section should not be left (i.e. interrupts should not be re-enabled)
* until the nesting depth reaches 0. This variable simply tracks the nesting
* depth. Each task maintains it's own critical nesting depth variable so
* uxCriticalNesting is saved and restored from the task stack during a context
* switch. */
volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. In this case the stack as
* expected by the HCS12 RTI instruction. */
expected by the portRESTORE_CONTEXT() macro. In this case the stack as
expected by the HCS12 RTI instruction. */
/* The address of the task function is placed in the stack byte at a time. */
@ -103,8 +103,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
/* CCR: Note that when the task starts interrupts will be enabled since
* "I" bit of CCR is cleared */
*--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
"I" bit of CCR is cleared */
*--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
/* tmp softregs used by GCC. Values right now don't matter. */
__asm("\n\
@ -118,11 +118,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
#ifdef BANKED_MODEL
/* The page of the task. */
*--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */
*--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
#endif
/* The critical nesting depth is initialised with 0 (meaning not in
* a critical section). */
a critical section). */
*--pxTopOfStack = ( StackType_t ) 0x00;
@ -140,21 +140,20 @@ static void prvSetupTimerInterrupt( void )
{
/* Enable hardware RTI timer */
/* Ignores configTICK_RATE_HZ */
RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
CRGINT |= 0x80; /* RTIE */
RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
CRGINT |= 0x80; // RTIE
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
/* xPortStartScheduler() does not start the scheduler directly because
* the header file containing the xPortStartScheduler() prototype is part
* of the common kernel code, and therefore cannot use the CODE_SEG pragma.
* Instead it simply calls the locally defined xNearStartScheduler() -
* which does use the CODE_SEG pragma. */
the header file containing the xPortStartScheduler() prototype is part
of the common kernel code, and therefore cannot use the CODE_SEG pragma.
Instead it simply calls the locally defined xNearStartScheduler() -
which does use the CODE_SEG pragma. */
int16_t register d;
__asm ("jmp xStartSchedulerNear ; will never return": "=d"(d));
return d;
}
@ -163,7 +162,7 @@ BaseType_t xPortStartScheduler( void )
BaseType_t xStartSchedulerNear( void )
{
/* Configure the timer that will generate the RTOS tick. Interrupts are
* disabled when this function is called. */
disabled when this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task. */
@ -187,10 +186,9 @@ BaseType_t xStartSchedulerNear( void )
void vPortYield( void )
{
portISR_HEAD();
/* NOTE: This is the trap routine (swi) although not defined as a trap.
* It will fill the stack the same way as an ISR in order to mix preemtion
* and cooperative yield. */
It will fill the stack the same way as an ISR in order to mix preemtion
and cooperative yield. */
portSAVE_CONTEXT();
vTaskSwitchContext();
@ -225,14 +223,15 @@ void vPortTickInterrupt( void )
}
/* Restore the context of a task - which may be a different task
* to that interrupted. */
to that interrupted. */
portRESTORE_CONTEXT();
}
#else /* if configUSE_PREEMPTION == 1 */
#else
{
xTaskIncrementTick();
}
#endif /* if configUSE_PREEMPTION == 1 */
#endif
portISR_TAIL();
}

6
portable/GCC/HCS12/portmacro.h
View file

@ -121,7 +121,6 @@
*/
#ifdef BANKED_MODEL
/*
* Load the stack pointer for the task, then pull the critical nesting
* count and PPAGE register from the stack. The remains of the
@ -159,7 +158,7 @@
sts 0,x ; Stack \n\
" ); \
}
#else /* ifdef BANKED_MODEL */
#else
/*
* These macros are as per the BANKED versions above, but without saving
@ -191,7 +190,7 @@
sts 0,x ; Stack \n\
" ); \
}
#endif /* ifdef BANKED_MODEL */
#endif
/*
* Utility macros to save/restore correct software registers for GCC. This is
@ -244,3 +243,4 @@
#endif
#endif /* PORTMACRO_H */

9
portable/GCC/IA32_flat/ISR_Support.h
View file

@ -36,7 +36,7 @@
pusha
/* If ulInterruptNesting is zero the rest of the task context will need
* saving and a stack switch might be required. */
saving and a stack switch might be required. */
movl ulInterruptNesting, %eax
test %eax, %eax
jne 2f
@ -45,7 +45,7 @@ jne 2f
.if configSUPPORT_FPU == 1
/* If the task has a buffer allocated to save the FPU context then
* save the FPU context now. */
save the FPU context now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f
@ -94,7 +94,8 @@ call vTaskSwitchContext
1:
/* Stack location is first item in the TCB. */
movl pxCurrentTCB, % eax movl( % eax ), % esp
movl pxCurrentTCB, %eax
movl (%eax), %esp
.if configSUPPORT_FPU == 1
@ -102,7 +103,7 @@ movl pxCurrentTCB, % eax movl( % eax ), % esp
pop pucPortTaskFPUContextBuffer
/* If the task has a buffer allocated in which its FPU context is saved,
* then restore it now. */
then restore it now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f

131
portable/GCC/IA32_flat/port.c
View file

@ -52,14 +52,14 @@
#endif
/* A critical section is exited when the critical section nesting count reaches
* this value. */
this value. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
* floating point context after they have been created. A variable is stored as
* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
* does not have an FPU context, or any other value if the task does have an FPU
* context. */
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Only the IF bit is set so tasks start with interrupts enabled. */
@ -76,7 +76,7 @@
#define portFPU_CONTEXT_SIZE_BYTES 108
/* The expected size of each entry in the IDT. Used to check structure packing
* is set correctly. */
is set correctly. */
#define portEXPECTED_IDT_ENTRY_SIZE 8
/* Default flags setting for entries in the IDT. */
@ -86,7 +86,7 @@
#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
/* If configASSERT() is defined then the system stack is filled with this value
* to allow for a crude stack overflow check. */
to allow for a crude stack overflow check. */
#define portSTACK_WORD ( 0xecececec )
/*-----------------------------------------------------------*/
@ -103,9 +103,7 @@ static void prvTaskExitError( void );
/*
* Complete one descriptor in the IDT.
*/
static void prvSetInterruptGate( uint8_t ucNumber,
ISR_Handler_t pxHandlerFunction,
uint8_t ucFlags );
static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
/*
* The default handler installed in each IDT position.
@ -136,13 +134,13 @@ static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
* variable must be initialised to a non zero value to ensure interrupts don't
* inadvertently become unmasked before the scheduler starts. It is set to zero
* before the first task starts executing. */
variable must be initialised to a non zero value to ensure interrupts don't
inadvertently become unmasked before the scheduler starts. It is set to zero
before the first task starts executing. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* A structure used to map the various fields of an IDT entry into separate
* structure members. */
structure members. */
struct IDTEntry
{
uint16_t usISRLow; /* Low 16 bits of handler address. */
@ -150,8 +148,7 @@ struct IDTEntry
uint8_t ucZero; /* Must be set to zero. */
uint8_t ucFlags; /* Flags for this entry. */
uint16_t usISRHigh; /* High 16 bits of handler address. */
}
__attribute__( ( packed ) );
} __attribute__( ( packed ) );
typedef struct IDTEntry IDTEntry_t;
@ -160,8 +157,7 @@ struct IDTPointer
{
uint16_t usTableLimit;
uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
}
__attribute__( ( __packed__ ) );
} __attribute__( ( __packed__ ) );
typedef struct IDTPointer IDTPointer_t;
/* The IDT itself. */
@ -170,8 +166,8 @@ static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
/* A table in which application defined interrupt handlers are stored. These
* are called by the central interrupt handler if a common interrupt entry
* point it used. */
are called by the central interrupt handler if a common interrupt entry
point it used. */
static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
@ -179,8 +175,8 @@ static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[
#if ( configSUPPORT_FPU == 1 )
/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
* then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
* not NULL then it points to a buffer into which the FPU context can be saved. */
then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
not NULL then it points to a buffer into which the FPU context can be saved. */
uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
#endif /* configSUPPORT_FPU */
@ -189,17 +185,17 @@ static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[
static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 };
/* Don't use the very top of the system stack so the return address
* appears as 0 if the debugger tries to unwind the stack. */
appears as 0 if the debugger tries to unwind the stack. */
volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
/* If a yield is requested from an interrupt or from a critical section then
* the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
* instead to indicate the yield should be performed at the end of the interrupt
* when the critical section is exited. */
the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
instead to indicate the yield should be performed at the end of the interrupt
when the critical section is exited. */
volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
/* Counts the interrupt nesting depth. Used to know when to switch to the
* interrupt/system stack and when to save/restore a complete context. */
interrupt/system stack and when to save/restore a complete context. */
volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
/*-----------------------------------------------------------*/
@ -207,9 +203,7 @@ volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t ulCodeSegment;
@ -225,7 +219,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* There is nothing to return to so assert if attempting to use the return
* address. */
address. */
*pxTopOfStack = ( StackType_t ) prvTaskExitError;
pxTopOfStack--;
@ -271,7 +265,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Buffer for FPU context, which is initialised to NULL as tasks are not
* created with an FPU context. */
created with an FPU context. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
}
#endif /* configSUPPORT_FPU */
@ -280,9 +274,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
}
/*-----------------------------------------------------------*/
static void prvSetInterruptGate( uint8_t ucNumber,
ISR_Handler_t pxHandlerFunction,
uint8_t ucFlags )
static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
{
uint16_t usCodeSegment;
uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
@ -328,17 +320,14 @@ void vPortSetupIDT( void )
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( ulCriticalNesting == ~0UL );
portDISABLE_INTERRUPTS();
for( ; ; )
{
}
for( ;; );
}
/*-----------------------------------------------------------*/
@ -385,12 +374,12 @@ BaseType_t xPortStartScheduler( void )
BaseType_t xWord;
/* Some versions of GCC require the -mno-ms-bitfields command line option
* for packing to work. */
for packing to work. */
configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
/* Fill part of the system stack with a known value to help detect stack
* overflow. A few zeros are left so GDB doesn't get confused unwinding
* the stack. */
overflow. A few zeros are left so GDB doesn't get confused unwinding
the stack. */
for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
{
ulSystemStack[ xWord ] = portSTACK_WORD;
@ -414,7 +403,7 @@ BaseType_t xPortStartScheduler( void )
portAPIC_TMRDIV = portAPIC_DIV_16;
/* Should not return from the following function as the scheduler will then
* be executing the tasks. */
be executing the tasks. */
vPortStartFirstTask();
return 0;
@ -424,7 +413,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -446,8 +435,8 @@ void vPortEnterCritical( void )
}
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -457,15 +446,15 @@ void vPortExitCritical( void )
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
* exited. */
exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
* priorities must be re-enabled. */
priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
* should be unmasked. */
should be unmasked. */
#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
{
__asm volatile( "sti" );
@ -477,7 +466,7 @@ void vPortExitCritical( void )
#endif
/* If a yield was pended from within the critical section then
* perform the yield now. */
perform the yield now. */
if( ulPortYieldPending != pdFALSE )
{
ulPortYieldPending = pdFALSE;
@ -496,7 +485,7 @@ uint32_t ulPortSetInterruptMask( void )
#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
{
/* Return whether interrupts were already enabled or not. Pop adjusts
* the stack first. */
the stack first. */
__asm volatile( "pushf \t\n"
"pop %0 \t\n"
"cli "
@ -511,7 +500,7 @@ uint32_t ulPortSetInterruptMask( void )
portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
}
#endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
#endif
return ulOriginalMask;
}
@ -531,7 +520,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
portAPIC_TASK_PRIORITY = ulNewMaskValue;
configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
}
#endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
#endif
}
/*-----------------------------------------------------------*/
@ -540,7 +529,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
void vPortTaskUsesFPU( void )
{
/* A task is registering the fact that it needs an FPU context. Allocate a
* buffer into which the context can be saved. */
buffer into which the context can be saved. */
pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
configASSERT( pucPortTaskFPUContextBuffer );
@ -588,8 +577,7 @@ void vPortAPICErrorHandler( void )
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
uint32_t ulVectorNumber )
BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
{
BaseType_t xReturn;
@ -598,8 +586,8 @@ void vPortAPICErrorHandler( void )
if( xReturn != pdFAIL )
{
/* Save the handler passed in by the application in the vector number
* passed in. The addresses are then called from the central interrupt
* handler. */
passed in. The addresses are then called from the central interrupt
handler. */
xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
}
@ -609,8 +597,7 @@ void vPortAPICErrorHandler( void )
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
/*-----------------------------------------------------------*/
BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
uint32_t ulVectorNumber )
BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
{
BaseType_t xReturn;
@ -683,3 +670,17 @@ void vGenerateYieldInterrupt( void )
{
__asm volatile( portYIELD_INTERRUPT );
}

110
portable/GCC/IA32_flat/portmacro.h
View file

@ -70,10 +70,10 @@
/* Task utilities. */
/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
* The quotient is rounded to the nearest integer with 1 being the lowest priority
* and 15 is the highest. Therefore the following two interrupts are at the lowest
* priority. *NOTE 1* If the yield vector is changed then it must also be changed
* in the portYIELD_INTERRUPT definition immediately below. */
The quotient is rounded to the nearest integer with 1 being the lowest priority
and 15 is the highest. Therefore the following two interrupts are at the lowest
priority. *NOTE 1* If the yield vector is changed then it must also be changed
in the portYIELD_INTERRUPT definition immediately below. */
#define portAPIC_TIMER_INT_VECTOR ( 0x21 )
#define portAPIC_YIELD_INT_VECTOR ( 0x20 )
@ -106,7 +106,7 @@
#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
/* Don't yield if inside a critical section - instead hold the yield pending
* so it is performed when the critical section is exited. */
so it is performed when the critical section is exited. */
#define portYIELD() \
{ \
extern volatile uint32_t ulCriticalNesting; \
@ -122,7 +122,7 @@
}
/* Called at the end of an ISR that can cause a context switch - pend a yield if
* xSwithcRequired is not false. */
xSwithcRequired is not false. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern volatile uint32_t ulPortYieldPending; \
@ -149,7 +149,7 @@
extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
/* These macros do not globally disable/enable interrupts. They do mask off
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
#define portDISABLE_INTERRUPTS() __asm volatile( "cli" )
@ -158,8 +158,8 @@
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not required for this port but included in case common demo code that uses these
* macros is used. */
not required for this port but included in case common demo code that uses these
macros is used. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
@ -187,7 +187,7 @@
typedef void ( *ISR_Handler_t ) ( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
* before any floating point instructions are executed. */
before any floating point instructions are executed. */
#ifndef configSUPPORT_FPU
#define configSUPPORT_FPU 0
#endif
@ -198,78 +198,71 @@
#endif
/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
* below. */
BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
uint32_t ulVectorNumber );
BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
uint32_t ulVectorNumber );
below. */
BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
#ifndef configAPIC_BASE
/* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can
* be overridden in FreeRTOSConfig.h should it not be constant. */
be overridden in FreeRTOSConfig.h should it not be constant. */
#define configAPIC_BASE 0xFEE00000UL
#endif
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
/* The FreeRTOS scheduling algorithm selects the task that will enter the
* Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
* that is done.
*
* If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
* enter the Running state is selected using a portable algorithm written in
* C. This is the slowest method, but the algorithm does not restrict the
* maximum number of unique RTOS task priorities that are available.
*
* If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
* enter the Running state is selected using a single assembly instruction.
* This is the fastest method, but restricts the maximum number of unique RTOS
* task priorities to 32 (the same task priority can be assigned to any number
* of RTOS tasks). */
Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
that is done.
If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
enter the Running state is selected using a portable algorithm written in
C. This is the slowest method, but the algorithm does not restrict the
maximum number of unique RTOS task priorities that are available.
If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
enter the Running state is selected using a single assembly instruction.
This is the fastest method, but restricts the maximum number of unique RTOS
task priorities to 32 (the same task priority can be assigned to any number
of RTOS tasks). */
#warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
/* There are two ways of implementing interrupt handlers:
*
* 1) As standard C functions -
*
* This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
* is set to 1. The C function is installed using
* xPortRegisterCInterruptHandler().
*
* This is the simplest of the two methods but incurs a slightly longer
* interrupt entry time.
*
* 2) By using an assembly stub that wraps the handler in the FreeRTOS
* portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
*
* This method can always be used. It is slightly more complex than
* method 1 but benefits from a faster interrupt entry time. */
1) As standard C functions -
This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
is set to 1. The C function is installed using
xPortRegisterCInterruptHandler().
This is the simplest of the two methods but incurs a slightly longer
interrupt entry time.
2) By using an assembly stub that wraps the handler in the FreeRTOS
portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
This method can always be used. It is slightly more complex than
method 1 but benefits from a faster interrupt entry time. */
#warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
#define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1
#endif
#ifndef configISR_STACK_SIZE
/* Interrupt entry code will switch the stack in use to a dedicated system
* stack.
*
* configISR_STACK_SIZE defines the number of 32-bit values that can be stored
* on the system stack, and must be large enough to hold a potentially nested
* interrupt stack frame. */
stack.
configISR_STACK_SIZE defines the number of 32-bit values that can be stored
on the system stack, and must be large enough to hold a potentially nested
interrupt stack frame. */
#error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
#endif
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
* be called from an interrupt that has a priority above that set by
* configMAX_API_CALL_INTERRUPT_PRIORITY. */
be called from an interrupt that has a priority above that set by
configMAX_API_CALL_INTERRUPT_PRIORITY. */
#warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
#define configMAX_API_CALL_INTERRUPT_PRIORITY 10
#endif
@ -280,13 +273,13 @@
#endif
/* The value written to the task priority register to raise the interrupt mask
* to the maximum from which FreeRTOS API calls can be made. */
to the maximum from which FreeRTOS API calls can be made. */
#define portAPIC_PRIORITY_SHIFT ( 4UL )
#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )
#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
/* Asserts if interrupt safe FreeRTOS functions are called from a priority
* above the max system call interrupt priority. */
above the max system call interrupt priority. */
#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
@ -295,3 +288,4 @@
#endif
#endif /* PORTMACRO_H */

108
portable/GCC/MCF5235/port.c
View file

@ -1,29 +1,29 @@
/*
* FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
* MCF5235 Port - Copyright (C) 2006 Christian Walter.
*
* This file is part of the FreeRTOS distribution.
*
* FreeRTOS is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License** as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* FreeRTOS is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with FreeRTOS; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* A special exception to the GPL can be applied should you wish to distribute
* a combined work that includes FreeRTOS, without being obliged to provide
* the source code for any proprietary components. See the licensing section
* of http://www.FreeRTOS.org for full details of how and when the exception
* can be applied.
*
FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
MCF5235 Port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
@ -37,18 +37,18 @@
* *
***************************************************************************
***************************************************************************
*
* Please ensure to read the configuration and relevant port sections of the
* online documentation.
*
* http://www.FreeRTOS.org - Documentation, latest information, license and
* contact details.
*
* http://www.SafeRTOS.com - A version that is certified for use in safety
* critical systems.
*
* http://www.OpenRTOS.com - Commercial support, development, porting,
* licensing and training services.
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include <stdlib.h>
@ -101,8 +101,8 @@ volatile uint32_t ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
/* ------------------------ Start implementation -------------------------- */
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
StackType_t *
pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode,
void *pvParameters )
{
/* Place the parameter on the stack in the expected location. */
@ -165,7 +165,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/*
* Called by portYIELD() or taskYIELD() to manually force a context switch.
*/
static void prvPortYield( void )
static void
prvPortYield( void )
{
asm volatile ( "move.w #0x2700, %sr\n\t" );
#if _GCC_USES_FP == 1
@ -182,12 +183,12 @@ static void prvPortYield( void )
}
#if configUSE_PREEMPTION == 0
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
static void prvPortPreemptiveTick( void )
static void
prvPortPreemptiveTick ( void )
{
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick.
@ -197,9 +198,10 @@ static void prvPortYield( void )
MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
}
#else /* if configUSE_PREEMPTION == 0 */
#else
static void prvPortPreemptiveTick( void )
static void
prvPortPreemptiveTick( void )
{
asm volatile ( "move.w #0x2700, %sr\n\t" );
#if _GCC_USES_FP == 1
@ -207,17 +209,16 @@ static void prvPortYield( void )
#endif
portSAVE_CONTEXT( );
MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext( );
}
portRESTORE_CONTEXT( );
}
#endif /* if configUSE_PREEMPTION == 0 */
#endif
void vPortEnterCritical()
void
vPortEnterCritical()
{
/* FIXME: We should store the old IPL here - How are we supposed to do
* this.
@ -230,7 +231,8 @@ void vPortEnterCritical()
ulCriticalNesting++;
}
void vPortExitCritical()
void
vPortExitCritical()
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
@ -238,7 +240,7 @@ void vPortExitCritical()
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
( void )portSET_IPL( 0 );
@ -246,7 +248,8 @@ void vPortExitCritical()
}
}
BaseType_t xPortStartScheduler( void )
BaseType_t
xPortStartScheduler( void )
{
extern void ( *portVECTOR_TABLE[ ] ) ( );
@ -276,6 +279,7 @@ BaseType_t xPortStartScheduler( void )
return pdTRUE;
}
void vPortEndScheduler( void )
void
vPortEndScheduler( void )
{
}

76
portable/GCC/MCF5235/portmacro.h
View file

@ -1,29 +1,29 @@
/*
* FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
* MCF5235 Port - Copyright (C) 2006 Christian Walter.
*
* This file is part of the FreeRTOS distribution.
*
* FreeRTOS is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License** as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* FreeRTOS is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with FreeRTOS; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* A special exception to the GPL can be applied should you wish to distribute
* a combined work that includes FreeRTOS, without being obliged to provide
* the source code for any proprietary components. See the licensing section
* of http://www.FreeRTOS.org for full details of how and when the exception
* can be applied.
*
FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
MCF5235 Port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
@ -37,18 +37,18 @@
* *
***************************************************************************
***************************************************************************
*
* Please ensure to read the configuration and relevant port sections of the
* online documentation.
*
* http://www.FreeRTOS.org - Documentation, latest information, license and
* contact details.
*
* http://www.SafeRTOS.com - A version that is certified for use in safety
* critical systems.
*
* http://www.OpenRTOS.com - Commercial support, development, porting,
* licensing and training services.
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
@ -151,6 +151,7 @@
/* Save the context of the interrupted task. */ \
portSAVE_CONTEXT( ); \
{
#define portEXIT_SWITCHING_ISR( SwitchRequired ) \
/* If a switch is required we call vTaskSwitchContext(). */ \
if( SwitchRequired ) \
@ -178,3 +179,4 @@
#endif /* PORTMACRO_H */

83
portable/GCC/MSP430F449/port.c
View file

@ -26,8 +26,8 @@
*/
/*
* Changes from V2.5.2
*
Changes from V2.5.2
+ usCriticalNesting now has a volatile qualifier.
*/
@ -44,28 +44,28 @@
*----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
* not the MCLK. */
not the MCLK. */
#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
* any details of its type. */
any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Most ports implement critical sections by placing the interrupt flags on
* the stack before disabling interrupts. Exiting the critical section is then
* simply a case of popping the flags from the stack. As mspgcc does not use
* a frame pointer this cannot be done as modifying the stack will clobber all
* the stack variables. Instead each task maintains a count of the critical
* section nesting depth. Each time a critical section is entered the count is
* incremented. Each time a critical section is left the count is decremented -
* with interrupts only being re-enabled if the count is zero.
*
* usCriticalNesting will get set to zero when the scheduler starts, but must
* not be initialised to zero as this will cause problems during the startup
* sequence. */
the stack before disabling interrupts. Exiting the critical section is then
simply a case of popping the flags from the stack. As mspgcc does not use
a frame pointer this cannot be done as modifying the stack will clobber all
the stack variables. Instead each task maintains a count of the critical
section nesting depth. Each time a critical section is entered the count is
incremented. Each time a critical section is left the count is decremented -
with interrupts only being re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as this will cause problems during the startup
sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@ -140,26 +140,24 @@ static void prvSetupTimerInterrupt( void );
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/*
* Place a few bytes of known values on the bottom of the stack.
* This is just useful for debugging and can be included if required.
*
Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging and can be included if required.
*pxTopOfStack = ( StackType_t ) 0x1111;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x2222;
* pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x3333;
* pxTopOfStack--;
pxTopOfStack--;
*/
/* The msp430 automatically pushes the PC then SR onto the stack before
* executing an ISR. We want the stack to look just as if this has happened
* so place a pointer to the start of the task on the stack first - followed
* by the flags we want the task to use when it starts up. */
executing an ISR. We want the stack to look just as if this has happened
so place a pointer to the start of the task on the stack first - followed
by the flags we want the task to use when it starts up. */
*pxTopOfStack = ( StackType_t ) pxCode;
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
@ -190,19 +188,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R15. */
R15. */
*pxTopOfStack = ( StackType_t ) pvParameters;
pxTopOfStack--;
/* The code generated by the mspgcc compiler does not maintain separate
* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
* use the stack as per other ports. Instead a variable is used to keep
* track of the critical section nesting. This variable has to be stored
* as part of the task context and is initially set to zero. */
stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
use the stack as per other ports. Instead a variable is used to keep
track of the critical section nesting. This variable has to be stored
as part of the task context and is initially set to zero. */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack we have generated so this can
* be stored in the task control block for the task. */
be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -210,7 +208,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. Interrupts are disabled when
* this function is called. */
this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. */
@ -224,7 +222,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the MSP430 port will get stopped. If required simply
* disable the tick interrupt here. */
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@ -237,9 +235,9 @@ void vPortYield( void ) __attribute__( ( naked ) );
void vPortYield( void )
{
/* We want the stack of the task being saved to look exactly as if the task
* was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
* msp430 places the status register onto the stack. As this is a function
* call and not an ISR we have to do this manually. */
was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
msp430 places the status register onto the stack. As this is a function
call and not an ISR we have to do this manually. */
asm volatile ( "push r2" );
_DINT();
@ -302,7 +300,7 @@ static void prvSetupTimerInterrupt( void )
portSAVE_CONTEXT();
/* Increment the tick count then switch to the highest priority task
* that is ready to run. */
that is ready to run. */
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
@ -312,7 +310,7 @@ static void prvSetupTimerInterrupt( void )
portRESTORE_CONTEXT();
}
#else /* if configUSE_PREEMPTION == 1 */
#else
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
@ -324,4 +322,7 @@ static void prvSetupTimerInterrupt( void )
{
xTaskIncrementTick();
}
#endif /* if configUSE_PREEMPTION == 1 */
#endif

1
portable/GCC/MSP430F449/portmacro.h
View file

@ -124,3 +124,4 @@
#endif
#endif /* PORTMACRO_H */

45
portable/GCC/MicroBlaze/port.c
View file

@ -50,24 +50,24 @@
#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
/* Tasks are started with a critical section nesting of 0 - however prior
* to the scheduler being commenced we don't want the critical nesting level
* to reach zero, so it is initialised to a high value. */
to the scheduler being commenced we don't want the critical nesting level
to reach zero, so it is initialised to a high value. */
#define portINITIAL_NESTING_VALUE ( 0xff )
/* Our hardware setup only uses one counter. */
#define portCOUNTER_0 0
/* The stack used by the ISR is filled with a known value to assist in
* debugging. */
debugging. */
#define portISR_STACK_FILL_VALUE 0x55555555
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains it's own count, so this variable is saved as part of the task
* context. */
maintains it's own count, so this variable is saved as part of the task
context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* To limit the amount of stack required by each task, this port uses a
* separate stack for interrupts. */
separate stack for interrupts. */
uint32_t *pulISRStack;
/*-----------------------------------------------------------*/
@ -85,18 +85,16 @@ static void prvSetupTimerInterrupt( void );
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
extern void *_SDA2_BASE_, *_SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
/* Place a few bytes of known values on the bottom of the stack.
* This is essential for the Microblaze port and these lines must
* not be omitted. The parameter value will overwrite the
* 0x22222222 value during the function prologue. */
This is essential for the Microblaze port and these lines must
not be omitted. The parameter value will overwrite the
0x22222222 value during the function prologue. */
*pxTopOfStack = ( StackType_t ) 0x11111111;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x22222222;
@ -105,7 +103,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* First stack an initial value for the critical section nesting. This
* is initialised to zero as tasks are started with interrupts enabled. */
is initialised to zero as tasks are started with interrupts enabled. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
/* Place an initial value for all the general purpose registers. */
@ -177,7 +175,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Return a pointer to the top of the stack we have generated so this can
* be stored in the task control block for the task. */
be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -196,7 +194,7 @@ BaseType_t xPortStartScheduler( void )
"shi r6, r0, 0x16 " );
/* Setup the hardware to generate the tick. Interrupts are disabled when
* this function is called. */
this function is called. */
prvSetupTimerInterrupt();
/* Allocate the stack to be used by the interrupt handler. */
@ -232,12 +230,11 @@ void vPortYield( void )
extern void VPortYieldASM( void );
/* Perform the context switch in a critical section to assure it is
* not interrupted by the tick ISR. It is not a problem to do this as
* each task maintains it's own interrupt status. */
not interrupted by the tick ISR. It is not a problem to do this as
each task maintains it's own interrupt status. */
portENTER_CRITICAL();
/* Jump directly to the yield function to ensure there is no
* compiler generated prologue code. */
compiler generated prologue code. */
asm volatile ( "bralid r14, VPortYieldASM \n\t" \
"or r0, r0, r0 \n\t" );
portEXIT_CRITICAL();
@ -254,14 +251,14 @@ static void prvSetupTimerInterrupt( void )
UBaseType_t uxMask;
/* The OPB timer1 is used to generate the tick. Use the provided library
* functions to enable the timer and set the tick frequency. */
functions to enable the timer and set the tick frequency. */
XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
/* Set the timer interrupt enable bit while maintaining the other bit
* states. */
states. */
uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
@ -297,7 +294,6 @@ void vTaskISRHandler( void )
pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
{
XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
@ -330,3 +326,8 @@ void vTickISR( void * pvBaseAddress )
XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
}
/*-----------------------------------------------------------*/

11
portable/GCC/MicroBlaze/portmacro.h
View file

@ -63,7 +63,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -78,15 +78,13 @@
/* Critical section macros. */
void vPortEnterCritical( void );
void vPortExitCritical( void );
#define portENTER_CRITICAL() \
{ \
#define portENTER_CRITICAL() { \
extern UBaseType_t uxCriticalNesting; \
microblaze_disable_interrupts(); \
uxCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
#define portEXIT_CRITICAL() { \
extern UBaseType_t uxCriticalNesting; \
/* Interrupts are disabled, so we can */ \
/* access the variable directly. */ \
@ -94,7 +92,7 @@
if( uxCriticalNesting == 0 ) \
{ \
/* The nesting has unwound and we \
* can enable interrupts again. */ \
can enable interrupts again. */ \
portENABLE_INTERRUPTS(); \
} \
}
@ -125,3 +123,4 @@
#endif
#endif /* PORTMACRO_H */

123
portable/GCC/MicroBlazeV8/port.c
View file

@ -43,19 +43,19 @@
#include <microblaze_exceptions_g.h>
/* Tasks are started with a critical section nesting of 0 - however, prior to
* the scheduler being commenced interrupts should not be enabled, so the critical
* nesting variable is initialised to a non-zero value. */
the scheduler being commenced interrupts should not be enabled, so the critical
nesting variable is initialised to a non-zero value. */
#define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts and
* exceptions respectively. */
exceptions respectively. */
#define portMSR_IE ( 0x02U )
#define portMSR_EE ( 0x100U )
/* If the floating point unit is included in the MicroBlaze build, then the
* FSR register is saved as part of the task context. portINITIAL_FSR is the value
* given to the FSR register when the initial context is set up for a task being
* created. */
FSR register is saved as part of the task context. portINITIAL_FSR is the value
given to the FSR register when the initial context is set up for a task being
created. */
#define portINITIAL_FSR ( 0U )
/*-----------------------------------------------------------*/
@ -72,27 +72,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
/*-----------------------------------------------------------*/
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains its own count, so this variable is saved as part of the task
* context. */
maintains its own count, so this variable is saved as part of the task
context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
* every task needing to be large enough to hold an entire interrupt stack on top
* of the task stack. */
every task needing to be large enough to hold an entire interrupt stack on top
of the task stack. */
uint32_t *pulISRStack;
/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
* get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
* handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
* will call vTaskSwitchContext() to ensure the task that runs immediately after
* the interrupt exists is the highest priority task that is able to run. This is
* an unusual mechanism, but is used for this port because a single interrupt can
* cause the servicing of multiple peripherals - and it is inefficient to call
* vTaskSwitchContext() multiple times as each peripheral is serviced. */
get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
will call vTaskSwitchContext() to ensure the task that runs immediately after
the interrupt exists is the highest priority task that is able to run. This is
an unusual mechanism, but is used for this port because a single interrupt can
cause the servicing of multiple peripherals - and it is inefficient to call
vTaskSwitchContext() multiple times as each peripheral is serviced. */
volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
* by the Xilinx library API functions. */
by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@ -103,17 +103,15 @@ static XIntc xInterruptControllerInstance;
*
* See the portable.h header file.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
extern void *_SDA2_BASE_, *_SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
/* Place a few bytes of known values on the bottom of the stack.
* This is essential for the Microblaze port and these lines must
* not be omitted. */
This is essential for the Microblaze port and these lines must
not be omitted. */
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
@ -128,8 +126,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
#endif
/* The MSR value placed in the initial task context should have interrupts
* disabled. Each task will enable interrupts automatically when it enters
* the running state for the first time. */
disabled. Each task will enable interrupts automatically when it enters
the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
@ -142,7 +140,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* First stack an initial value for the critical section nesting. This
* is initialised to zero. */
is initialised to zero. */
*pxTopOfStack = ( StackType_t ) 0x00;
/* R0 is always zero. */
@ -174,9 +172,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
pxTopOfStack--;
#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#else
pxTopOfStack-= 8;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#endif
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
pxTopOfStack--;
@ -224,12 +222,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
pxTopOfStack--;
#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#else
pxTopOfStack -= 13;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#endif
/* Return a pointer to the top of the stack that has been generated so this
* can be stored in the task control block for the task. */
can be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -240,25 +238,25 @@ BaseType_t xPortStartScheduler( void )
extern uint32_t _stack[];
/* Setup the hardware to generate the tick. Interrupts are disabled when
* this function is called.
*
* This port uses an application defined callback function to install the tick
* interrupt handler because the kernel will run on lots of different
* MicroBlaze and FPGA configurations - not all of which will have the same
* timer peripherals defined or available. An example definition of
* vApplicationSetupTimerInterrupt() is provided in the official demo
* application that accompanies this port. */
this function is called.
This port uses an application defined callback function to install the tick
interrupt handler because the kernel will run on lots of different
MicroBlaze and FPGA configurations - not all of which will have the same
timer peripherals defined or available. An example definition of
vApplicationSetupTimerInterrupt() is provided in the official demo
application that accompanies this port. */
vApplicationSetupTimerInterrupt();
/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
pulISRStack = ( uint32_t * ) _stack;
/* Ensure there is enough space for the functions called from the interrupt
* service routines to write back into the stack frame of the caller. */
service routines to write back into the stack frame of the caller. */
pulISRStack -= 2;
/* Restore the context of the first task that is going to run. From here
* on, the created tasks will be executing. */
on, the created tasks will be executing. */
vPortStartFirstTask();
/* Should not get here as the tasks are now running! */
@ -269,7 +267,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -282,12 +280,12 @@ void vPortYield( void )
extern void VPortYieldASM( void );
/* Perform the context switch in a critical section to assure it is
* not interrupted by the tick ISR. It is not a problem to do this as
* each task maintains its own interrupt status. */
not interrupted by the tick ISR. It is not a problem to do this as
each task maintains its own interrupt status. */
portENTER_CRITICAL();
{
/* Jump directly to the yield function to ensure there is no
* compiler generated prologue code. */
compiler generated prologue code. */
asm volatile ( "bralid r14, VPortYieldASM \n\t" \
"or r0, r0, r0 \n\t" );
}
@ -300,10 +298,9 @@ void vPortEnableInterrupt( uint8_t ucInterruptID )
int32_t lReturn;
/* An API function is provided to enable an interrupt in the interrupt
* controller because the interrupt controller instance variable is private
* to this file. */
controller because the interrupt controller instance variable is private
to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
{
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
@ -318,8 +315,8 @@ void vPortDisableInterrupt( uint8_t ucInterruptID )
int32_t lReturn;
/* An API function is provided to disable an interrupt in the interrupt
* controller because the interrupt controller instance variable is private
* to this file. */
controller because the interrupt controller instance variable is private
to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
@ -331,14 +328,12 @@ void vPortDisableInterrupt( uint8_t ucInterruptID )
}
/*-----------------------------------------------------------*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef )
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
int32_t lReturn;
/* An API function is provided to install an interrupt handler because the
* interrupt controller instance variable is private to this file. */
interrupt controller instance variable is private to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
@ -364,7 +359,7 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void )
int32_t lReturn;
/* Ensure the interrupt controller instance variable is initialised before
* it is used, and that the initialisation only happens once. */
it is used, and that the initialisation only happens once. */
if( lInterruptControllerInitialised != pdTRUE )
{
lReturn = prvInitialiseInterruptController();
@ -395,11 +390,11 @@ void vPortTickISR( void * pvUnused )
( void ) pvUnused;
/* This port uses an application defined callback function to clear the tick
* interrupt because the kernel will run on lots of different MicroBlaze and
* FPGA configurations - not all of which will have the same timer peripherals
* defined or available. An example definition of
* vApplicationClearTimerInterrupt() is provided in the official demo
* application that accompanies this port. */
interrupt because the kernel will run on lots of different MicroBlaze and
FPGA configurations - not all of which will have the same timer peripherals
defined or available. An example definition of
vApplicationClearTimerInterrupt() is provided in the official demo
application that accompanies this port. */
vApplicationClearTimerInterrupt();
/* Increment the RTOS tick - this might cause a task to unblock. */
@ -426,8 +421,8 @@ static int32_t prvInitialiseInterruptController( void )
XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
/* Install exception handlers if the MicroBlaze is configured to handle
* exceptions, and the application defined constant
* configINSTALL_EXCEPTION_HANDLERS is set to 1. */
exceptions, and the application defined constant
configINSTALL_EXCEPTION_HANDLERS is set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
{
vPortExceptionsInstallHandlers();
@ -435,7 +430,7 @@ static int32_t prvInitialiseInterruptController( void )
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
/* Start the interrupt controller. Interrupts are enabled when the
* scheduler starts. */
scheduler starts. */
lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
if( lStatus == XST_SUCCESS )
@ -453,3 +448,5 @@ static int32_t prvInitialiseInterruptController( void )
return lStatus;
}
/*-----------------------------------------------------------*/

63
portable/GCC/MicroBlazeV8/port_exceptions.c
View file

@ -34,8 +34,8 @@
#include <microblaze_exceptions_g.h>
/* The Xilinx library defined exception entry point stacks a number of
* registers. These definitions are offsets from the stack pointer to the various
* stacked register values. */
registers. These definitions are offsets from the stack pointer to the various
stacked register values. */
#define portexR3_STACK_OFFSET 4
#define portexR4_STACK_OFFSET 5
#define portexR5_STACK_OFFSET 6
@ -52,41 +52,41 @@
#define portexR19_STACK_OFFSET -1
/* This is defined to equal the size, in bytes, of the stack frame generated by
* the Xilinx standard library exception entry point. It is required to determine
* the stack pointer value prior to the exception being entered. */
the Xilinx standard library exception entry point. It is required to determine
the stack pointer value prior to the exception being entered. */
#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
/* The number of bytes a MicroBlaze instruction consumes. */
#define portexINSTRUCTION_SIZE 4
/* Exclude this entire file if the MicroBlaze is not configured to handle
* exceptions, or the application defined configuration constant
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
exceptions, or the application defined configuration constant
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
/* This variable is set in the exception entry code, before
* vPortExceptionHandler is called. */
vPortExceptionHandler is called. */
uint32_t *pulStackPointerOnFunctionEntry = NULL;
/* This is the structure that is filled with the MicroBlaze context as it
* existed immediately prior to the exception occurrence. A pointer to this
* structure is passed into the vApplicationExceptionRegisterDump() callback
* function, if one is defined. */
existed immediately prior to the exception occurrence. A pointer to this
structure is passed into the vApplicationExceptionRegisterDump() callback
function, if one is defined. */
static xPortRegisterDump xRegisterDump;
/* This is the FreeRTOS exception handler that is installed for all exception
* types. It is called from vPortExceptionHanlderEntry() - which is itself defined
* in portasm.S. */
types. It is called from vPortExceptionHanlderEntry() - which is itself defined
in portasm.S. */
void vPortExceptionHandler( void *pvExceptionID );
extern void vPortExceptionHandlerEntry( void *pvExceptionID );
/*-----------------------------------------------------------*/
/* vApplicationExceptionRegisterDump() is a callback function that the
* application can optionally define to receive a populated xPortRegisterDump
* structure. If the application chooses not to define a version of
* vApplicationExceptionRegisterDump() then this weekly defined default
* implementation will be called instead. */
application can optionally define to receive a populated xPortRegisterDump
structure. If the application chooses not to define a version of
vApplicationExceptionRegisterDump() then this weekly defined default
implementation will be called instead. */
extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
{
@ -104,17 +104,17 @@
extern void *pxCurrentTCB;
/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
* was immediately before the exception occurrence. */
was immediately before the exception occurrence. */
/* First fill in the name and handle of the task that was in the Running
* state when the exception occurred. */
state when the exception occurred. */
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
configASSERT( pulStackPointerOnFunctionEntry );
/* Obtain the values of registers that were stacked prior to this function
* being called, and may have changed since they were stacked. */
being called, and may have changed since they were stacked. */
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
@ -154,8 +154,8 @@
xRegisterDump.ulEDR = mfedr();
/* Move the saved program counter back to the instruction that was executed
* when the exception occurred. This is only valid for certain types of
* exception. */
when the exception occurred. This is only valid for certain types of
exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
@ -169,8 +169,8 @@
#endif
/* Also fill in a string that describes what type of exception this is.
* The string uses the same ID names as defined in the MicroBlaze standard
* library exception header files. */
The string uses the same ID names as defined in the MicroBlaze standard
library exception header files. */
switch( ( uint32_t ) pvExceptionID )
{
case XEXC_ID_FSL :
@ -202,17 +202,19 @@
break;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
case XEXC_ID_FPU :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
break;
#endif /* XPAR_MICROBLAZE_USE_FPU */
}
/* vApplicationExceptionRegisterDump() is a callback function that the
* application can optionally define to receive the populated xPortRegisterDump
* structure. If the application chooses not to define a version of
* vApplicationExceptionRegisterDump() then the weekly defined default
* implementation within this file will be called instead. */
application can optionally define to receive the populated xPortRegisterDump
structure. If the application chooses not to define a version of
vApplicationExceptionRegisterDump() then the weekly defined default
implementation within this file will be called instead. */
vApplicationExceptionRegisterDump( &xRegisterDump );
/* Must not attempt to leave this function! */
@ -272,6 +274,9 @@
}
/* Exclude the entire file if the MicroBlaze is not configured to handle
* exceptions, or the application defined configuration item
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
exceptions, or the application defined configuration item
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */

43
portable/GCC/MicroBlazeV8/portmacro.h
View file

@ -67,7 +67,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -82,15 +82,13 @@
/* Critical section macros. */
void vPortEnterCritical( void );
void vPortExitCritical( void );
#define portENTER_CRITICAL() \
{ \
#define portENTER_CRITICAL() { \
extern volatile UBaseType_t uxCriticalNesting; \
microblaze_disable_interrupts(); \
uxCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
#define portEXIT_CRITICAL() { \
extern volatile UBaseType_t uxCriticalNesting; \
/* Interrupts are disabled, so we can */ \
/* access the variable directly. */ \
@ -98,7 +96,7 @@
if( uxCriticalNesting == 0 ) \
{ \
/* The nesting has unwound and we \
* can enable interrupts again. */ \
can enable interrupts again. */ \
portENABLE_INTERRUPTS(); \
} \
}
@ -110,11 +108,11 @@
#define portYIELD() vPortYield()
/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
* sets a flag to say that a yield has been requested. The interrupt exit code
* then checks this flag, and calls vTaskSwitchContext() before restoring a task
* context, if the flag is not false. This is done to prevent multiple calls to
* vTaskSwitchContext() being made from a single interrupt, as a single interrupt
* can result in multiple peripherals being serviced. */
sets a flag to say that a yield has been requested. The interrupt exit code
then checks this flag, and calls vTaskSwitchContext() before restoring a task
context, if the flag is not false. This is done to prevent multiple calls to
vTaskSwitchContext() being made from a single interrupt, as a single interrupt
can result in multiple peripherals being serviced. */
extern volatile uint32_t ulTaskSwitchRequested;
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
@ -126,7 +124,6 @@
uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
return ucReturn;
}
@ -160,12 +157,12 @@
/*-----------------------------------------------------------*/
/* The following structure is used by the FreeRTOS exception handler. It is
* filled with the MicroBlaze context as it was at the time the exception occurred.
* This is done as an aid to debugging exception occurrences. */
filled with the MicroBlaze context as it was at the time the exception occurred.
This is done as an aid to debugging exception occurrences. */
typedef struct PORT_REGISTER_DUMP
{
/* The following structure members hold the values of the MicroBlaze
* registers at the time the exception was raised. */
registers at the time the exception was raised. */
uint32_t ulR1_SP;
uint32_t ulR2_small_data_area;
uint32_t ulR3;
@ -205,18 +202,19 @@
uint32_t ulEDR;
/* A human readable description of the exception cause. The strings used
* are the same as the #define constant names found in the
* microblaze_exceptions_i.h header file */
are the same as the #define constant names found in the
microblaze_exceptions_i.h header file */
int8_t *pcExceptionCause;
/* The human readable name of the task that was running at the time the
* exception occurred. This is the name that was given to the task when the
* task was created using the FreeRTOS xTaskCreate() API function. */
exception occurred. This is the name that was given to the task when the
task was created using the FreeRTOS xTaskCreate() API function. */
char *pcCurrentTaskName;
/* The handle of the task that was running a the time the exception
* occurred. */
occurred. */
void * xCurrentTaskHandle;
} xPortRegisterDump;
@ -255,9 +253,7 @@
* pdPASS is returned if the function executes successfully. Any other value
* being returned indicates that the function did not execute correctly.
*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
/*
@ -370,3 +366,4 @@
#endif
#endif /* PORTMACRO_H */

125
portable/GCC/MicroBlazeV9/port.c
View file

@ -43,19 +43,19 @@
#include <microblaze_exceptions_g.h>
/* Tasks are started with a critical section nesting of 0 - however, prior to
* the scheduler being commenced interrupts should not be enabled, so the critical
* nesting variable is initialised to a non-zero value. */
the scheduler being commenced interrupts should not be enabled, so the critical
nesting variable is initialised to a non-zero value. */
#define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts and
* exceptions respectively. */
exceptions respectively. */
#define portMSR_IE ( 0x02U )
#define portMSR_EE ( 0x100U )
/* If the floating point unit is included in the MicroBlaze build, then the
* FSR register is saved as part of the task context. portINITIAL_FSR is the value
* given to the FSR register when the initial context is set up for a task being
* created. */
FSR register is saved as part of the task context. portINITIAL_FSR is the value
given to the FSR register when the initial context is set up for a task being
created. */
#define portINITIAL_FSR ( 0U )
/*-----------------------------------------------------------*/
@ -73,27 +73,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
/*-----------------------------------------------------------*/
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains its own count, so this variable is saved as part of the task
* context. */
maintains its own count, so this variable is saved as part of the task
context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
* every task needing to be large enough to hold an entire interrupt stack on top
* of the task stack. */
every task needing to be large enough to hold an entire interrupt stack on top
of the task stack. */
uint32_t *pulISRStack;
/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
* get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
* handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
* will call vTaskSwitchContext() to ensure the task that runs immediately after
* the interrupt exists is the highest priority task that is able to run. This is
* an unusual mechanism, but is used for this port because a single interrupt can
* cause the servicing of multiple peripherals - and it is inefficient to call
* vTaskSwitchContext() multiple times as each peripheral is serviced. */
get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
will call vTaskSwitchContext() to ensure the task that runs immediately after
the interrupt exists is the highest priority task that is able to run. This is
an unusual mechanism, but is used for this port because a single interrupt can
cause the servicing of multiple peripherals - and it is inefficient to call
vTaskSwitchContext() multiple times as each peripheral is serviced. */
volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
* by the Xilinx library API functions. */
by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@ -104,9 +104,7 @@ static XIntc xInterruptControllerInstance;
*
* See the portable.h header file.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
extern void *_SDA2_BASE_, *_SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
@ -114,8 +112,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
extern void _start1( void );
/* Place a few bytes of known values on the bottom of the stack.
* This is essential for the Microblaze port and these lines must
* not be omitted. */
This is essential for the Microblaze port and these lines must
not be omitted. */
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
@ -130,8 +128,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
#endif
/* The MSR value placed in the initial task context should have interrupts
* disabled. Each task will enable interrupts automatically when it enters
* the running state for the first time. */
disabled. Each task will enable interrupts automatically when it enters
the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
@ -144,7 +142,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* First stack an initial value for the critical section nesting. This
* is initialised to zero. */
is initialised to zero. */
*pxTopOfStack = ( StackType_t ) 0x00;
/* R0 is always zero. */
@ -176,9 +174,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
pxTopOfStack--;
#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#else
pxTopOfStack-= 8;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#endif
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
pxTopOfStack--;
@ -226,12 +224,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
pxTopOfStack--;
#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#else
pxTopOfStack -= 13;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
#endif
/* Return a pointer to the top of the stack that has been generated so this
* can be stored in the task control block for the task. */
can be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -242,25 +240,25 @@ BaseType_t xPortStartScheduler( void )
extern uint32_t _stack[];
/* Setup the hardware to generate the tick. Interrupts are disabled when
* this function is called.
*
* This port uses an application defined callback function to install the tick
* interrupt handler because the kernel will run on lots of different
* MicroBlaze and FPGA configurations - not all of which will have the same
* timer peripherals defined or available. An example definition of
* vApplicationSetupTimerInterrupt() is provided in the official demo
* application that accompanies this port. */
this function is called.
This port uses an application defined callback function to install the tick
interrupt handler because the kernel will run on lots of different
MicroBlaze and FPGA configurations - not all of which will have the same
timer peripherals defined or available. An example definition of
vApplicationSetupTimerInterrupt() is provided in the official demo
application that accompanies this port. */
vApplicationSetupTimerInterrupt();
/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
pulISRStack = ( uint32_t * ) _stack;
/* Ensure there is enough space for the functions called from the interrupt
* service routines to write back into the stack frame of the caller. */
service routines to write back into the stack frame of the caller. */
pulISRStack -= 2;
/* Restore the context of the first task that is going to run. From here
* on, the created tasks will be executing. */
on, the created tasks will be executing. */
vPortStartFirstTask();
/* Should not get here as the tasks are now running! */
@ -271,7 +269,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@ -284,12 +282,12 @@ void vPortYield( void )
extern void VPortYieldASM( void );
/* Perform the context switch in a critical section to assure it is
* not interrupted by the tick ISR. It is not a problem to do this as
* each task maintains its own interrupt status. */
not interrupted by the tick ISR. It is not a problem to do this as
each task maintains its own interrupt status. */
portENTER_CRITICAL();
{
/* Jump directly to the yield function to ensure there is no
* compiler generated prologue code. */
compiler generated prologue code. */
asm volatile ( "bralid r14, VPortYieldASM \n\t" \
"or r0, r0, r0 \n\t" );
}
@ -302,14 +300,13 @@ void vPortEnableInterrupt( uint8_t ucInterruptID )
int32_t lReturn;
/* An API function is provided to enable an interrupt in the interrupt
* controller because the interrupt controller instance variable is private
* to this file. */
controller because the interrupt controller instance variable is private
to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
{
/* Critical section protects read/modify/writer operation inside
* XIntc_Enable(). */
XIntc_Enable(). */
portENTER_CRITICAL();
{
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
@ -326,8 +323,8 @@ void vPortDisableInterrupt( uint8_t ucInterruptID )
int32_t lReturn;
/* An API function is provided to disable an interrupt in the interrupt
* controller because the interrupt controller instance variable is private
* to this file. */
controller because the interrupt controller instance variable is private
to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
@ -339,14 +336,12 @@ void vPortDisableInterrupt( uint8_t ucInterruptID )
}
/*-----------------------------------------------------------*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef )
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
int32_t lReturn;
/* An API function is provided to install an interrupt handler because the
* interrupt controller instance variable is private to this file. */
interrupt controller instance variable is private to this file. */
lReturn = prvEnsureInterruptControllerIsInitialised();
@ -372,7 +367,7 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void )
int32_t lReturn;
/* Ensure the interrupt controller instance variable is initialised before
* it is used, and that the initialisation only happens once. */
it is used, and that the initialisation only happens once. */
if( lInterruptControllerInitialised != pdTRUE )
{
lReturn = prvInitialiseInterruptController();
@ -403,11 +398,11 @@ void vPortTickISR( void * pvUnused )
( void ) pvUnused;
/* This port uses an application defined callback function to clear the tick
* interrupt because the kernel will run on lots of different MicroBlaze and
* FPGA configurations - not all of which will have the same timer peripherals
* defined or available. An example definition of
* vApplicationClearTimerInterrupt() is provided in the official demo
* application that accompanies this port. */
interrupt because the kernel will run on lots of different MicroBlaze and
FPGA configurations - not all of which will have the same timer peripherals
defined or available. An example definition of
vApplicationClearTimerInterrupt() is provided in the official demo
application that accompanies this port. */
vApplicationClearTimerInterrupt();
/* Increment the RTOS tick - this might cause a task to unblock. */
@ -434,8 +429,8 @@ static int32_t prvInitialiseInterruptController( void )
XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
/* Install exception handlers if the MicroBlaze is configured to handle
* exceptions, and the application defined constant
* configINSTALL_EXCEPTION_HANDLERS is set to 1. */
exceptions, and the application defined constant
configINSTALL_EXCEPTION_HANDLERS is set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
{
vPortExceptionsInstallHandlers();
@ -443,7 +438,7 @@ static int32_t prvInitialiseInterruptController( void )
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
/* Start the interrupt controller. Interrupts are enabled when the
* scheduler starts. */
scheduler starts. */
lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
if( lStatus == XST_SUCCESS )
@ -461,3 +456,5 @@ static int32_t prvInitialiseInterruptController( void )
return lStatus;
}
/*-----------------------------------------------------------*/

63
portable/GCC/MicroBlazeV9/port_exceptions.c
View file

@ -34,8 +34,8 @@
#include <microblaze_exceptions_g.h>
/* The Xilinx library defined exception entry point stacks a number of
* registers. These definitions are offsets from the stack pointer to the various
* stacked register values. */
registers. These definitions are offsets from the stack pointer to the various
stacked register values. */
#define portexR3_STACK_OFFSET 4
#define portexR4_STACK_OFFSET 5
#define portexR5_STACK_OFFSET 6
@ -52,41 +52,41 @@
#define portexR19_STACK_OFFSET -1
/* This is defined to equal the size, in bytes, of the stack frame generated by
* the Xilinx standard library exception entry point. It is required to determine
* the stack pointer value prior to the exception being entered. */
the Xilinx standard library exception entry point. It is required to determine
the stack pointer value prior to the exception being entered. */
#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
/* The number of bytes a MicroBlaze instruction consumes. */
#define portexINSTRUCTION_SIZE 4
/* Exclude this entire file if the MicroBlaze is not configured to handle
* exceptions, or the application defined configuration constant
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
exceptions, or the application defined configuration constant
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
/* This variable is set in the exception entry code, before
* vPortExceptionHandler is called. */
vPortExceptionHandler is called. */
uint32_t *pulStackPointerOnFunctionEntry = NULL;
/* This is the structure that is filled with the MicroBlaze context as it
* existed immediately prior to the exception occurrence. A pointer to this
* structure is passed into the vApplicationExceptionRegisterDump() callback
* function, if one is defined. */
existed immediately prior to the exception occurrence. A pointer to this
structure is passed into the vApplicationExceptionRegisterDump() callback
function, if one is defined. */
static xPortRegisterDump xRegisterDump;
/* This is the FreeRTOS exception handler that is installed for all exception
* types. It is called from vPortExceptionHanlderEntry() - which is itself defined
* in portasm.S. */
types. It is called from vPortExceptionHanlderEntry() - which is itself defined
in portasm.S. */
void vPortExceptionHandler( void *pvExceptionID );
extern void vPortExceptionHandlerEntry( void *pvExceptionID );
/*-----------------------------------------------------------*/
/* vApplicationExceptionRegisterDump() is a callback function that the
* application can optionally define to receive a populated xPortRegisterDump
* structure. If the application chooses not to define a version of
* vApplicationExceptionRegisterDump() then this weekly defined default
* implementation will be called instead. */
application can optionally define to receive a populated xPortRegisterDump
structure. If the application chooses not to define a version of
vApplicationExceptionRegisterDump() then this weekly defined default
implementation will be called instead. */
extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
{
@ -104,17 +104,17 @@
extern void *pxCurrentTCB;
/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
* was immediately before the exception occurrence. */
was immediately before the exception occurrence. */
/* First fill in the name and handle of the task that was in the Running
* state when the exception occurred. */
state when the exception occurred. */
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
configASSERT( pulStackPointerOnFunctionEntry );
/* Obtain the values of registers that were stacked prior to this function
* being called, and may have changed since they were stacked. */
being called, and may have changed since they were stacked. */
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
@ -154,8 +154,8 @@
xRegisterDump.ulEDR = mfedr();
/* Move the saved program counter back to the instruction that was executed
* when the exception occurred. This is only valid for certain types of
* exception. */
when the exception occurred. This is only valid for certain types of
exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
@ -169,8 +169,8 @@
#endif
/* Also fill in a string that describes what type of exception this is.
* The string uses the same ID names as defined in the MicroBlaze standard
* library exception header files. */
The string uses the same ID names as defined in the MicroBlaze standard
library exception header files. */
switch( ( uint32_t ) pvExceptionID )
{
case XEXC_ID_FSL :
@ -202,17 +202,19 @@
break;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
case XEXC_ID_FPU :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
break;
#endif /* XPAR_MICROBLAZE_USE_FPU */
}
/* vApplicationExceptionRegisterDump() is a callback function that the
* application can optionally define to receive the populated xPortRegisterDump
* structure. If the application chooses not to define a version of
* vApplicationExceptionRegisterDump() then the weekly defined default
* implementation within this file will be called instead. */
application can optionally define to receive the populated xPortRegisterDump
structure. If the application chooses not to define a version of
vApplicationExceptionRegisterDump() then the weekly defined default
implementation within this file will be called instead. */
vApplicationExceptionRegisterDump( &xRegisterDump );
/* Must not attempt to leave this function! */
@ -272,6 +274,9 @@
}
/* Exclude the entire file if the MicroBlaze is not configured to handle
* exceptions, or the application defined configuration item
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
exceptions, or the application defined configuration item
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */

43
portable/GCC/MicroBlazeV9/portmacro.h
View file

@ -67,7 +67,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -82,15 +82,13 @@
/* Critical section macros. */
void vPortEnterCritical( void );
void vPortExitCritical( void );
#define portENTER_CRITICAL() \
{ \
#define portENTER_CRITICAL() { \
extern volatile UBaseType_t uxCriticalNesting; \
microblaze_disable_interrupts(); \
uxCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
#define portEXIT_CRITICAL() { \
extern volatile UBaseType_t uxCriticalNesting; \
/* Interrupts are disabled, so we can */ \
/* access the variable directly. */ \
@ -98,7 +96,7 @@
if( uxCriticalNesting == 0 ) \
{ \
/* The nesting has unwound and we \
* can enable interrupts again. */ \
can enable interrupts again. */ \
portENABLE_INTERRUPTS(); \
} \
}
@ -110,11 +108,11 @@
#define portYIELD() vPortYield()
/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
* sets a flag to say that a yield has been requested. The interrupt exit code
* then checks this flag, and calls vTaskSwitchContext() before restoring a task
* context, if the flag is not false. This is done to prevent multiple calls to
* vTaskSwitchContext() being made from a single interrupt, as a single interrupt
* can result in multiple peripherals being serviced. */
sets a flag to say that a yield has been requested. The interrupt exit code
then checks this flag, and calls vTaskSwitchContext() before restoring a task
context, if the flag is not false. This is done to prevent multiple calls to
vTaskSwitchContext() being made from a single interrupt, as a single interrupt
can result in multiple peripherals being serviced. */
extern volatile uint32_t ulTaskSwitchRequested;
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
@ -126,7 +124,6 @@
uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
return ucReturn;
}
@ -160,12 +157,12 @@
/*-----------------------------------------------------------*/
/* The following structure is used by the FreeRTOS exception handler. It is
* filled with the MicroBlaze context as it was at the time the exception occurred.
* This is done as an aid to debugging exception occurrences. */
filled with the MicroBlaze context as it was at the time the exception occurred.
This is done as an aid to debugging exception occurrences. */
typedef struct PORT_REGISTER_DUMP
{
/* The following structure members hold the values of the MicroBlaze
* registers at the time the exception was raised. */
registers at the time the exception was raised. */
uint32_t ulR1_SP;
uint32_t ulR2_small_data_area;
uint32_t ulR3;
@ -205,18 +202,19 @@
uint32_t ulEDR;
/* A human readable description of the exception cause. The strings used
* are the same as the #define constant names found in the
* microblaze_exceptions_i.h header file */
are the same as the #define constant names found in the
microblaze_exceptions_i.h header file */
int8_t *pcExceptionCause;
/* The human readable name of the task that was running at the time the
* exception occurred. This is the name that was given to the task when the
* task was created using the FreeRTOS xTaskCreate() API function. */
exception occurred. This is the name that was given to the task when the
task was created using the FreeRTOS xTaskCreate() API function. */
char *pcCurrentTaskName;
/* The handle of the task that was running a the time the exception
* occurred. */
occurred. */
void * xCurrentTaskHandle;
} xPortRegisterDump;
@ -255,9 +253,7 @@
* pdPASS is returned if the function executes successfully. Any other value
* being returned indicates that the function did not execute correctly.
*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
/*
@ -370,3 +366,4 @@
#endif
#endif /* PORTMACRO_H */

19
portable/GCC/NiosII/port.c
View file

@ -55,8 +55,7 @@ static void prvSetupTimerInterrupt( void );
/*
* Call back for the alarm function.
*/
void vPortSysTickHandler( void * context,
alt_u32 id );
void vPortSysTickHandler( void * context, alt_u32 id );
/*-----------------------------------------------------------*/
@ -69,9 +68,7 @@ static void prvReadGp( uint32_t * ulValue )
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxFramePointer = pxTopOfStack - 1;
StackType_t xGlobalPointer;
@ -113,7 +110,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -128,7 +125,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the NIOS2 port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -158,8 +155,7 @@ void prvSetupTimerInterrupt( void )
}
/*-----------------------------------------------------------*/
void vPortSysTickHandler( void * context,
alt_u32 id )
void vPortSysTickHandler( void * context, alt_u32 id )
{
/* Increment the kernel tick. */
if( xTaskIncrementTick() != pdFALSE )
@ -178,9 +174,7 @@ void vPortSysTickHandler( void * context,
* kernel has its scheduler started so that contexts are saved and switched
* correctly.
*/
int alt_irq_register( alt_u32 id,
void * context,
void ( * handler )( void *, alt_u32 ) )
int alt_irq_register( alt_u32 id, void* context, void (*handler)(void*, alt_u32) )
{
int rc = -EINVAL;
alt_irq_context status;
@ -206,3 +200,4 @@ int alt_irq_register( alt_u32 id,
return rc;
}
/*-----------------------------------------------------------*/

3
portable/GCC/NiosII/portmacro.h
View file

@ -65,7 +65,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -106,3 +106,4 @@
#endif
#endif /* PORTMACRO_H */

5
portable/GCC/PPC405_Xilinx/FPU_Macros.h
View file

@ -26,7 +26,7 @@
*/
/* When switching out a task, if the task tag contains a buffer address then
* save the flop context into the buffer. */
save the flop context into the buffer. */
#define traceTASK_SWITCHED_OUT() \
if( pxCurrentTCB->pxTaskTag != NULL ) \
{ \
@ -35,10 +35,11 @@
}
/* When switching in a task, if the task tag contains a buffer address then
* load the flop context from the buffer. */
load the flop context from the buffer. */
#define traceTASK_SWITCHED_IN() \
if( pxCurrentTCB->pxTaskTag != NULL ) \
{ \
extern void vPortRestoreFPURegisters( void * ); \
vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
}

26
portable/GCC/PPC405_Xilinx/port.c
View file

@ -96,9 +96,7 @@ static XIntc xInterruptController;
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Place a known value at the bottom of the stack for debugging. */
*pxTopOfStack = 0xDEADBEEF;
@ -121,7 +119,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* R1 is the stack pointer so is omitted. */
*pxTopOfStack = 0x10000001UL; /* R0. */
*pxTopOfStack = 0x10000001UL;; /* R0. */
pxTopOfStack--;
*pxTopOfStack = 0x00000000UL; /* USPRG0. */
pxTopOfStack--;
@ -159,9 +157,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented. */
for( ; ; )
{
}
for( ;; );
}
/*-----------------------------------------------------------*/
@ -197,7 +193,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
( void ) pvNullDoNotUse;
/* Get the configuration by using the device ID - in this case it is
* assumed that only one interrupt controller is being used. */
assumed that only one interrupt controller is being used. */
pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
/* Which interrupts are pending? */
@ -233,28 +229,26 @@ void vPortSetupInterruptController( void )
extern void vPortISRWrapper( void );
/* Perform all library calls necessary to initialise the exception table
* and interrupt controller. This assumes only one interrupt controller is in
* use. */
and interrupt controller. This assumes only one interrupt controller is in
use. */
XExc_mDisableExceptions( XEXC_NON_CRITICAL );
XExc_Init();
/* The library functions save the context - we then jump to a wrapper to
* save the stack into the TCB. The wrapper then calls the handler defined
* above. */
save the stack into the TCB. The wrapper then calls the handler defined
above. */
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
XIntc_Start( &xInterruptController, XIN_REAL_MODE );
}
/*-----------------------------------------------------------*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef )
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
BaseType_t xReturn = pdFAIL;
/* This function is defined here so the scope of xInterruptController can
* remain within this file. */
remain within this file. */
if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
{

7
portable/GCC/PPC405_Xilinx/portmacro.h
View file

@ -67,7 +67,7 @@
/*-----------------------------------------------------------*/
/* This port uses the critical nesting count from the TCB rather than
* maintaining a separate value and then saving this value in the task stack. */
maintaining a separate value and then saving this value in the task stack. */
#define portCRITICAL_NESTING_IN_TCB 1
/* Interrupt control macros. */
@ -108,12 +108,11 @@
/* Port specific interrupt handling functions. */
void vPortSetupInterruptController( void );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

5
portable/GCC/PPC440_Xilinx/FPU_Macros.h
View file

@ -26,7 +26,7 @@
*/
/* When switching out a task, if the task tag contains a buffer address then
* save the flop context into the buffer. */
save the flop context into the buffer. */
#define traceTASK_SWITCHED_OUT() \
if( pxCurrentTCB->pxTaskTag != NULL ) \
{ \
@ -35,10 +35,11 @@
}
/* When switching in a task, if the task tag contains a buffer address then
* load the flop context from the buffer. */
load the flop context from the buffer. */
#define traceTASK_SWITCHED_IN() \
if( pxCurrentTCB->pxTaskTag != NULL ) \
{ \
extern void vPortRestoreFPURegisters( void * ); \
vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
}

26
portable/GCC/PPC440_Xilinx/port.c
View file

@ -96,9 +96,7 @@ static XIntc xInterruptController;
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Place a known value at the bottom of the stack for debugging. */
*pxTopOfStack = 0xDEADBEEF;
@ -121,7 +119,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* R1 is the stack pointer so is omitted. */
*pxTopOfStack = 0x10000001UL; /* R0. */
*pxTopOfStack = 0x10000001UL;; /* R0. */
pxTopOfStack--;
*pxTopOfStack = 0x00000000UL; /* USPRG0. */
pxTopOfStack--;
@ -159,9 +157,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented. */
for( ; ; )
{
}
for( ;; );
}
/*-----------------------------------------------------------*/
@ -197,7 +193,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
( void ) pvNullDoNotUse;
/* Get the configuration by using the device ID - in this case it is
* assumed that only one interrupt controller is being used. */
assumed that only one interrupt controller is being used. */
pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
/* Which interrupts are pending? */
@ -233,28 +229,26 @@ void vPortSetupInterruptController( void )
extern void vPortISRWrapper( void );
/* Perform all library calls necessary to initialise the exception table
* and interrupt controller. This assumes only one interrupt controller is in
* use. */
and interrupt controller. This assumes only one interrupt controller is in
use. */
XExc_mDisableExceptions( XEXC_NON_CRITICAL );
XExc_Init();
/* The library functions save the context - we then jump to a wrapper to
* save the stack into the TCB. The wrapper then calls the handler defined
* above. */
save the stack into the TCB. The wrapper then calls the handler defined
above. */
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
XIntc_Start( &xInterruptController, XIN_REAL_MODE );
}
/*-----------------------------------------------------------*/
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef )
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
BaseType_t xReturn = pdFAIL;
/* This function is defined here so the scope of xInterruptController can
* remain within this file. */
remain within this file. */
if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
{

7
portable/GCC/PPC440_Xilinx/portmacro.h
View file

@ -67,7 +67,7 @@
/*-----------------------------------------------------------*/
/* This port uses the critical nesting count from the TCB rather than
* maintaining a separate value and then saving this value in the task stack. */
maintaining a separate value and then saving this value in the task stack. */
#define portCRITICAL_NESTING_IN_TCB 1
/* Interrupt control macros. */
@ -108,12 +108,11 @@
/* Port specific interrupt handling functions. */
void vPortSetupInterruptController( void );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
XInterruptHandler pxHandler,
void * pvCallBackRef );
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

4
portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
View file

@ -7,8 +7,8 @@
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and t
*
* o permit persons to whom the Software is furnished to do so,
o permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all

66
portable/GCC/RISC-V/port.c
View file

@ -38,20 +38,20 @@
#include "string.h"
#ifdef configCLINT_BASE_ADDRESS
#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIME_BASE_ADDRESS
#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIMECMP_BASE_ADDRESS
#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
@ -59,19 +59,19 @@
#endif
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
* to use a statically allocated array as the interrupt stack. Alternative leave
* configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
* linker variable names __freertos_irq_stack_top has the same value as the top
* of the stack used by main. Using the linker script method will repurpose the
* stack that was used by main before the scheduler was started for use as the
* interrupt stack after the scheduler has started. */
to use a statically allocated array as the interrupt stack. Alternative leave
configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
linker variable names __freertos_irq_stack_top has the same value as the top
of the stack used by main. Using the linker script method will repurpose the
stack that was used by main before the scheduler was started for use as the
interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS
static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
* the task stacks, and so will legitimately appear in many positions within
* the ISR stack. */
the task stacks, and so will legitimately appear in many positions within
the ISR stack. */
#define portISR_STACK_FILL_BYTE 0xee
#else
extern const uint32_t __freertos_irq_stack_top[];
@ -95,23 +95,21 @@ uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
* stack checking. A problem in the ISR stack will trigger an assert, not call the
* stack overflow hook function (because the stack overflow hook is specific to a
* task stack, not the ISR stack). */
stack checking. A problem in the ISR stack will trigger an assert, not call the
stack overflow hook function (because the stack overflow hook is specific to a
task stack, not the ISR stack). */
#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
#warning This path not tested, or even compiled yet.
static const uint8_t ucExpectedStackBytes[] =
{
static const uint8_t ucExpectedStackBytes[] = {
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
}; \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
#else
/* Define the function away. */
#define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@ -128,7 +126,6 @@ volatile uint64_t * pullMachineTimerCompareRegister = NULL;
volatile uint32_t ulHartId;
__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
do
@ -159,13 +156,13 @@ BaseType_t xPortStartScheduler( void )
volatile uint32_t mtvec = 0;
/* Check the least significant two bits of mtvec are 00 - indicating
* single vector mode. */
single vector mode. */
__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
configASSERT( ( mtvec & 0x03UL ) == 0 );
/* Check alignment of the interrupt stack - which is the same as the
* stack that was being used by main() prior to the scheduler being
* started. */
stack that was being used by main() prior to the scheduler being
started. */
configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
#ifdef configISR_STACK_SIZE_WORDS
@ -177,15 +174,15 @@ BaseType_t xPortStartScheduler( void )
#endif /* configASSERT_DEFINED */
/* If there is a CLINT then it is ok to use the default implementation
* in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
* configure whichever clock is to be used to generate the tick interrupt. */
in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
configure whichever clock is to be used to generate the tick interrupt. */
vPortSetupTimerInterrupt();
#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
{
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
* for external interrupt. _RB_ What happens here when mtime is not present as
* with pulpino? */
for external interrupt. _RB_ What happens here when mtime is not present as
with pulpino? */
__asm volatile( "csrs mie, %0" :: "r"(0x880) );
}
#else
@ -198,7 +195,7 @@ BaseType_t xPortStartScheduler( void )
xPortStartFirstTask();
/* Should not get here as after calling xPortStartFirstTask() only tasks
* should be executing. */
should be executing. */
return pdFAIL;
}
/*-----------------------------------------------------------*/
@ -206,7 +203,10 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented. */
for( ; ; )
{
}
for( ;; );
}

31
portable/GCC/RISC-V/portmacro.h
View file

@ -55,9 +55,9 @@
#define portBASE_TYPE int32_t
#define portUBASE_TYPE uint32_t
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#else /* if __riscv_xlen == 64 */
#else
#error Assembler did not define __riscv_xlen
#endif /* if __riscv_xlen == 64 */
#endif
typedef portSTACK_TYPE StackType_t;
@ -73,7 +73,7 @@
#define portSHORT short
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
@ -137,8 +137,8 @@
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
@ -157,26 +157,24 @@
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
* configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
* backward compatibility derive the newer definitions from the old if the old
* definition is found. */
configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
backward compatibility derive the newer definitions from the old if the old
definition is found. */
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
* there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
* addresses to 0. */
there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
addresses to 0. */
#define configMTIME_BASE_ADDRESS ( 0 )
#define configMTIMECMP_BASE_ADDRESS ( 0 )
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
* the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
* from the CLINT address. */
the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
from the CLINT address. */
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
@ -185,3 +183,4 @@
#endif
#endif /* PORTMACRO_H */

6
portable/GCC/RL78/isr_support.h
View file

@ -94,10 +94,9 @@ MOVW SP, AX
/* Restore usCriticalNesting value. */
POP AX
MOVW !_usCriticalNesting, AX
/* Restore the alternative register banks - only necessary in the GCC
* port. Register bank 3 is dedicated for interrupts use so is not saved or
* restored. */
port. Register bank 3 is dedicated for interrupts use so is not saved or
restored. */
SEL RB2
POP HL
POP DE
@ -124,3 +123,4 @@ POP HL
POP AX
.endm

41
portable/GCC/RL78/port.c
View file

@ -30,7 +30,7 @@
#include "task.h"
/* The critical nesting value is initialised to a non zero value to ensure
* interrupts don't accidentally become enabled before the scheduler is started. */
interrupts don't accidentally become enabled before the scheduler is started. */
#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
/* Initial PSW value allocated to a newly created task.
@ -47,13 +47,13 @@
#define portPSW ( 0xc6UL )
/* Each task maintains a count of the critical section nesting depth. Each time
* a critical section is entered the count is incremented. Each time a critical
* section is exited the count is decremented - with interrupts only being
* re-enabled if the count is zero.
*
* usCriticalNesting will get set to zero when the scheduler starts, but must
* not be initialised to zero as that could cause problems during the startup
* sequence. */
a critical section is entered the count is incremented. Each time a critical
section is exited the count is decremented - with interrupts only being
re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as that could cause problems during the startup
sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@ -77,16 +77,14 @@ extern void vPortStartFirstTask( void );
*
* See the header file portable.h.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t *pulLocal;
/* Stack type and pointers to the stack type are both 2 bytes. */
/* Parameters are passed in on the stack, and written using a 32bit value
* hence a space is left for the second two bytes. */
hence a space is left for the second two bytes. */
pxTopOfStack--;
/* Write in the parameter value. */
@ -95,14 +93,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The return address, leaving space for the first two bytes of the
* 32-bit value. */
32-bit value. */
pxTopOfStack--;
pulLocal = ( uint32_t * ) pxTopOfStack;
*pulLocal = ( uint32_t ) 0;
pxTopOfStack--;
/* The start address / PSW value is also written in as a 32bit value,
* so leave a space for the second two bytes. */
so leave a space for the second two bytes. */
pxTopOfStack--;
/* Task function start address combined with the PSW. */
@ -123,16 +121,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* The remaining general purpose registers bank 0 (DE and BC) and the other
* two register banks...register bank 3 is dedicated for use by interrupts so
* is not saved as part of the task context. */
two register banks...register bank 3 is dedicated for use by interrupts so
is not saved as part of the task context. */
pxTopOfStack -= 10;
/* Finally the critical section nesting count is set to zero when the task
* first starts. */
first starts. */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack that has beene generated so it
* can be stored in the task control block for the task. */
can be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@ -140,7 +138,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
portBASE_TYPE xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. Interrupts are disabled when
* this function is called. */
this function is called. */
vApplicationSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. */
@ -185,7 +183,7 @@ __attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void )
/* Enable INTIT interrupt. */
ITMK = ( unsigned char ) 0;
}
#endif /* ifdef RTCEN */
#endif
#ifdef TMKAEN
{
@ -207,6 +205,7 @@ __attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void )
/* Enable INTIT interrupt. */
TMKAMK = ( unsigned char ) 0;
}
#endif /* ifdef TMKAEN */
#endif
}
/*-----------------------------------------------------------*/

1
portable/GCC/RL78/portmacro.h
View file

@ -118,3 +118,4 @@ typedef unsigned short UBaseType_t;
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */

179
portable/GCC/RX100/port.c
View file

@ -45,11 +45,11 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
* PSW is set with U and I set, and PM and IPL clear. */
PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
/* The peripheral clock is divided by this value before being supplying the
* CMT. */
CMT. */
#if ( configUSE_TICKLESS_IDLE == 0 )
/* If tickless idle is not used then the divisor can be fixed. */
#define portCLOCK_DIVISOR 8UL
@ -64,15 +64,15 @@
#endif
/* These macros allow a critical section to be added around the call to
* xTaskIncrementTick(), which is only ever called from interrupts at the kernel
* priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */
xTaskIncrementTick(), which is only ever called from interrupts at the kernel
priority - ie a known priority. Therefore these local macros are a slight
optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
which would require the old IPL to be read first and stored in a local variable. */
#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/* Keys required to lock and unlock access to certain system registers
* respectively. */
respectively. */
#define portUNLOCK_KEY 0xA50B
#define portLOCK_KEY 0xA500
@ -104,9 +104,8 @@ void vPortTickISR( void ) __attribute__( ( interrupt ) );
*/
static void prvSetupTimerInterrupt( void );
#ifndef configSETUP_TICK_INTERRUPT
/* The user has not provided their own tick interrupt configuration so use
* the definition in this file (which uses the interval timer). */
the definition in this file (which uses the interval timer). */
#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
#endif /* configSETUP_TICK_INTERRUPT */
@ -130,34 +129,32 @@ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / p
#if configUSE_TICKLESS_IDLE == 1
/* Holds the maximum number of ticks that can be suppressed - which is
* basically how far into the future an interrupt can be generated. Set
* during initialisation. This is the maximum possible value that the
* compare match register can hold divided by ulMatchValueForOneTick. */
basically how far into the future an interrupt can be generated. Set
during initialisation. This is the maximum possible value that the
compare match register can hold divided by ulMatchValueForOneTick. */
static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
/* Flag set from the tick interrupt to allow the sleep processing to know if
* sleep mode was exited because of a tick interrupt, or an interrupt
* generated by something else. */
sleep mode was exited because of a tick interrupt, or an interrupt
generated by something else. */
static volatile uint32_t ulTickFlag = pdFALSE;
/* The CMT counter is stopped temporarily each time it is re-programmed.
* The following constant offsets the CMT counter match value by the number of
* CMT counts that would typically be missed while the counter was stopped to
* compensate for the lost time. The large difference between the divided CMT
* clock and the CPU clock means it is likely ulStoppedTimerCompensation will
* equal zero - and be optimised away. */
The following constant offsets the CMT counter match value by the number of
CMT counts that would typically be missed while the counter was stopped to
compensate for the lost time. The large difference between the divided CMT
clock and the CPU clock means it is likely ulStoppedTimerCompensation will
equal zero - and be optimised away. */
static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
#endif /* if configUSE_TICKLESS_IDLE == 1 */
#endif
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Offset to end up on 8 byte boundary. */
pxTopOfStack--;
@ -172,8 +169,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = ( StackType_t ) pxCode;
/* When debugging it can be useful if every register is set to a known
* value. Otherwise code space can be saved by just setting the registers
* that need to be set. */
value. Otherwise code space can be saved by just setting the registers
that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION
{
pxTopOfStack--;
@ -206,13 +203,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = 0x22222222;
pxTopOfStack--;
}
#else /* ifdef USE_FULL_REGISTER_INITIALISATION */
#else
{
/* Leave space for the registers that will get popped from the stack
* when the task first starts executing. */
when the task first starts executing. */
pxTopOfStack -= 15;
}
#endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
#endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
pxTopOfStack--;
@ -230,10 +227,10 @@ BaseType_t xPortStartScheduler( void )
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate
* the tick interrupt. This way the application can decide which
* peripheral to use. If tickless mode is used then the default
* implementation defined in this file (which uses CMT0) should not be
* overridden. */
the tick interrupt. This way the application can decide which
peripheral to use. If tickless mode is used then the default
implementation defined in this file (which uses CMT0) should not be
overridden. */
configSETUP_TICK_INTERRUPT();
/* Enable the software interrupt. */
@ -250,11 +247,11 @@ BaseType_t xPortStartScheduler( void )
}
/* Execution should not reach here as the tasks are now running!
* prvSetupTimerInterrupt() is called here to prevent the compiler outputting
* a warning about a statically declared function not being referenced in the
* case that the application writer has provided their own tick interrupt
* configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
* their own routine will be called in place of prvSetupTimerInterrupt()). */
prvSetupTimerInterrupt() is called here to prevent the compiler outputting
a warning about a statically declared function not being referenced in the
case that the application writer has provided their own tick interrupt
configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
their own routine will be called in place of prvSetupTimerInterrupt()). */
prvSetupTimerInterrupt();
/* Should not get here. */
@ -265,7 +262,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
@ -274,22 +271,19 @@ static void prvStartFirstTask( void )
{
__asm volatile
(
/* When starting the scheduler there is nothing that needs moving to the
* interrupt stack because the function is not called from an interrupt.
* Just ensure the current stack is the user stack. */
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
"SETPSW U \n" \
/* Obtain the location of the stack associated with which ever task
* pxCurrentTCB is currently pointing to. */
pxCurrentTCB is currently pointing to. */
"MOV.L #_pxCurrentTCB, R15 \n" \
"MOV.L [R15], R15 \n" \
"MOV.L [R15], R0 \n" \
/* Restore the registers from the stack of the task pointed to by
* pxCurrentTCB. */
pxCurrentTCB. */
"POP R15 \n" \
/* Accumulator low 32 bits. */
@ -317,11 +311,10 @@ void vPortSoftwareInterruptISR( void )
/* Re-enable interrupts. */
"SETPSW I \n" \
/* Move the data that was automatically pushed onto the interrupt stack when
* the interrupt occurred from the interrupt stack to the user stack.
*
* R15 is saved before it is clobbered. */
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
"PUSH.L R15 \n" \
/* Read the user stack pointer. */
@ -361,9 +354,8 @@ void vPortSoftwareInterruptISR( void )
"MOV.L [ R15 ], R15 \n" \
"MOV.L R0, [ R15 ] \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel
* structures are being accessed. */
structures are being accessed. */
"MVTIPL %0 \n" \
/* Select the next task to run. */
@ -372,16 +364,14 @@ void vPortSoftwareInterruptISR( void )
/* Reset the interrupt mask as no more data structure access is required. */
"MVTIPL %1 \n" \
/* Load the stack pointer of the task that is now selected as the Running
* state task from its TCB. */
state task from its TCB. */
"MOV.L #_pxCurrentTCB,R15 \n" \
"MOV.L [ R15 ], R15 \n" \
"MOV.L [ R15 ], R0 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and
* PC will be popped by the RTE instruction. */
PC will be popped by the RTE instruction. */
"POP R15 \n" \
"MVTACLO R15 \n" \
"POP R15 \n" \
@ -401,7 +391,7 @@ void vPortTickISR( void )
__asm volatile( "SETPSW I" );
/* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */
necessitates. Ensure IPL is at the max syscall value first. */
portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
{
if( xTaskIncrementTick() != pdFALSE )
@ -417,7 +407,7 @@ void vPortTickISR( void )
ulTickFlag = pdTRUE;
/* If this is the first tick since exiting tickless mode then the CMT
* compare match value needs resetting. */
compare match value needs resetting. */
CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
}
#endif
@ -488,11 +478,11 @@ static void prvSetupTimerInterrupt( void )
{
CMT0.CMCR.BIT.CKS = 0;
}
#else /* if portCLOCK_DIVISOR == 512 */
#else
{
#error Invalid portCLOCK_DIVISOR setting
}
#endif /* if portCLOCK_DIVISOR == 512 */
#endif
/* Enable the interrupt... */
_IEN( _CMT0_CMI0 ) = 1;
@ -513,8 +503,8 @@ static void prvSetupTimerInterrupt( void )
configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
* means the application defined code has already executed the WAIT
* instruction. */
means the application defined code has already executed the WAIT
instruction. */
if( xExpectedIdleTime > 0 )
{
__asm volatile( "WAIT" );
@ -543,41 +533,38 @@ static void prvSetupTimerInterrupt( void )
}
/* Calculate the reload value required to wait xExpectedIdleTime tick
* periods. */
periods. */
ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
if( ulMatchValue > ulStoppedTimerCompensation )
{
/* Compensate for the fact that the CMT is going to be stopped
* momentarily. */
momentarily. */
ulMatchValue -= ulStoppedTimerCompensation;
}
/* Stop the CMT momentarily. The time the CMT is stopped for is
* accounted for as best it can be, but using the tickless mode will
* inevitably result in some tiny drift of the time maintained by the
* kernel with respect to calendar time. */
accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
CMT.CMSTR0.BIT.STR0 = 0;
while( CMT.CMSTR0.BIT.STR0 == 1 )
{
/* Nothing to do here. */
}
/* Critical section using the global interrupt bit as the i bit is
* automatically reset by the WAIT instruction. */
automatically reset by the WAIT instruction. */
__asm volatile( "CLRPSW i" );
/* The tick flag is set to false before sleeping. If it is true when
* sleep mode is exited then sleep mode was probably exited because the
* tick was suppressed for the entire xExpectedIdleTime period. */
sleep mode is exited then sleep mode was probably exited because the
tick was suppressed for the entire xExpectedIdleTime period. */
ulTickFlag = pdFALSE;
/* If a context switch is pending then abandon the low power entry as
* the context switch might have been pended by an external interrupt that
* requires processing. */
the context switch might have been pended by an external interrupt that
requires processing. */
eSleepAction = eTaskConfirmSleepModeStatus();
if( eSleepAction == eAbortSleep )
{
/* Restart tick. */
@ -596,7 +583,7 @@ static void prvSetupTimerInterrupt( void )
SYSTEM.PRCR.WORD = portLOCK_KEY;
/* Sleep until something happens. Calling prvSleep() will
* automatically reset the i bit in the PSW. */
automatically reset the i bit in the PSW. */
prvSleep( xExpectedIdleTime );
/* Restart the CMT. */
@ -616,7 +603,7 @@ static void prvSetupTimerInterrupt( void )
SYSTEM.PRCR.WORD = portLOCK_KEY;
/* Adjust the match value to take into account that the current
* time slice is already partially complete. */
time slice is already partially complete. */
ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
@ -625,15 +612,14 @@ static void prvSetupTimerInterrupt( void )
CMT.CMSTR0.BIT.STR0 = 1;
/* Sleep until something happens. Calling prvSleep() will
* automatically reset the i bit in the PSW. */
automatically reset the i bit in the PSW. */
prvSleep( xExpectedIdleTime );
/* Stop CMT. Again, the time the SysTick is stopped for is
* accounted for as best it can be, but using the tickless mode will
* inevitably result in some tiny drift of the time maintained by the
* kernel with respect to calendar time. */
accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
CMT.CMSTR0.BIT.STR0 = 0;
while( CMT.CMSTR0.BIT.STR0 == 1 )
{
/* Nothing to do here. */
@ -644,44 +630,45 @@ static void prvSetupTimerInterrupt( void )
if( ulTickFlag != pdFALSE )
{
/* The tick interrupt has already executed, although because
* this function is called with the scheduler suspended the actual
* tick processing will not occur until after this function has
* exited. Reset the match value with whatever remains of this
* tick period. */
this function is called with the scheduler suspended the actual
tick processing will not occur until after this function has
exited. Reset the match value with whatever remains of this
tick period. */
ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
/* The tick interrupt handler will already have pended the tick
* processing in the kernel. As the pending tick will be
* processed as soon as this function exits, the tick value
* maintained by the tick is stepped forward by one less than the
* time spent sleeping. The actual stepping of the tick appears
* later in this function. */
processing in the kernel. As the pending tick will be
processed as soon as this function exits, the tick value
maintained by the tick is stepped forward by one less than the
time spent sleeping. The actual stepping of the tick appears
later in this function. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
/* Something other than the tick interrupt ended the sleep.
* How many complete tick periods passed while the processor was
* sleeping? */
How many complete tick periods passed while the processor was
sleeping? */
ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
/* The match value is set to whatever fraction of a single tick
* period remains. */
period remains. */
ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
CMT0.CMCOR = ( uint16_t ) ulMatchValue;
}
/* Restart the CMT so it runs up to the match value. The match value
* will get set to the value required to generate exactly one tick period
* the next time the CMT interrupt executes. */
will get set to the value required to generate exactly one tick period
the next time the CMT interrupt executes. */
CMT0.CMCNT = 0;
CMT.CMSTR0.BIT.STR0 = 1;
/* Wind the tick forward by the number of tick periods that the CPU
* remained in a low power state. */
remained in a low power state. */
vTaskStepTick( ulCompleteTickPeriods );
}
}
#endif /* configUSE_TICKLESS_IDLE */

25
portable/GCC/RX100/portmacro.h
View file

@ -44,7 +44,7 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */
portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
@ -65,7 +65,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -77,8 +77,8 @@
#define portNOP() __asm volatile( "NOP" )
/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
* back to ensure it is set before continuing, then restore the clobbered
* register. */
back to ensure it is set before continuing, then restore the clobbered
register. */
#define portYIELD() \
__asm volatile \
( \
@ -91,14 +91,14 @@
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
/* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */
taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
performed if configASSERT() is defined to ensure an assertion handler does not
inadvertently attempt to lower the IPL when the call to assert was triggered
because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
functions are those that end in FromISR. FreeRTOS maintains a separate
interrupt API to ensure API function and interrupt entry is as fast and as
simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
@ -141,3 +141,4 @@
#endif
#endif /* PORTMACRO_H */

57
portable/GCC/RX600/port.c
View file

@ -42,15 +42,15 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
* PSW is set with U and I set, and PM and IPL clear. */
PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to
* xTaskIncrementTick(), which is only ever called from interrupts at the kernel
* priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */
xTaskIncrementTick(), which is only ever called from interrupts at the kernel
priority - ie a known priority. Therefore these local macros are a slight
optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
which would require the old IPL to be read first and stored in a local variable. */
#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
@ -83,9 +83,7 @@ extern void * pxCurrentTCB;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* R0 is not included as it is the stack pointer. */
@ -96,8 +94,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = ( StackType_t ) pxCode;
/* When debugging it can be useful if every register is set to a known
* value. Otherwise code space can be saved by just setting the registers
* that need to be set. */
value. Otherwise code space can be saved by just setting the registers
that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION
{
pxTopOfStack--;
@ -130,11 +128,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = 0x22222222;
pxTopOfStack--;
}
#else /* ifdef USE_FULL_REGISTER_INITIALISATION */
#else
{
pxTopOfStack -= 15;
}
#endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
#endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
pxTopOfStack--;
@ -156,8 +154,8 @@ BaseType_t xPortStartScheduler( void )
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate the
* tick interrupt. This way the application can decide which peripheral to
* use. A demo application is provided to show a suitable example. */
tick interrupt. This way the application can decide which peripheral to
use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */
@ -181,7 +179,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
@ -190,22 +188,19 @@ static void prvStartFirstTask( void )
{
__asm volatile
(
/* When starting the scheduler there is nothing that needs moving to the
* interrupt stack because the function is not called from an interrupt.
* Just ensure the current stack is the user stack. */
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
"SETPSW U \n" \
/* Obtain the location of the stack associated with which ever task
* pxCurrentTCB is currently pointing to. */
pxCurrentTCB is currently pointing to. */
"MOV.L #_pxCurrentTCB, R15 \n" \
"MOV.L [R15], R15 \n" \
"MOV.L [R15], R0 \n" \
/* Restore the registers from the stack of the task pointed to by
* pxCurrentTCB. */
pxCurrentTCB. */
"POP R15 \n" \
/* Accumulator low 32 bits. */
@ -237,11 +232,10 @@ void vSoftwareInterruptISR( void )
/* Re-enable interrupts. */
"SETPSW I \n" \
/* Move the data that was automatically pushed onto the interrupt stack when
* the interrupt occurred from the interrupt stack to the user stack.
*
* R15 is saved before it is clobbered. */
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
"PUSH.L R15 \n" \
/* Read the user stack pointer. */
@ -283,9 +277,8 @@ void vSoftwareInterruptISR( void )
"MOV.L [ R15 ], R15 \n" \
"MOV.L R0, [ R15 ] \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel
* structures are being accessed. */
structures are being accessed. */
"MVTIPL %0 \n" \
/* Select the next task to run. */
@ -294,16 +287,14 @@ void vSoftwareInterruptISR( void )
/* Reset the interrupt mask as no more data structure access is required. */
"MVTIPL %1 \n" \
/* Load the stack pointer of the task that is now selected as the Running
* state task from its TCB. */
state task from its TCB. */
"MOV.L #_pxCurrentTCB,R15 \n" \
"MOV.L [ R15 ], R15 \n" \
"MOV.L [ R15 ], R0 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and
* PC will be popped by the RTE instruction. */
PC will be popped by the RTE instruction. */
"POP R15 \n" \
"MVTACLO R15 \n" \
"POP R15 \n" \
@ -325,7 +316,7 @@ void vTickISR( void )
__asm volatile( "SETPSW I" );
/* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */
necessitates. Ensure IPL is at the max syscall value first. */
portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
{
if( xTaskIncrementTick() != pdFALSE )

27
portable/GCC/RX600/portmacro.h
View file

@ -44,7 +44,7 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */
portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
@ -65,7 +65,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -77,9 +77,9 @@
#define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
* where portITU_SWINTR is the location of the software interrupt register
* (0x000872E0). Don't rely on the assembler to select a register, so instead
* save and restore clobbered registers manually. */
where portITU_SWINTR is the location of the software interrupt register
(0x000872E0). Don't rely on the assembler to select a register, so instead
save and restore clobbered registers manually. */
#define portYIELD() \
__asm volatile \
( \
@ -93,14 +93,14 @@
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */
taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
performed if configASSERT() is defined to ensure an assertion handler does not
inadvertently attempt to lower the IPL when the call to assert was triggered
because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
functions are those that end in FromISR. FreeRTOS maintains a separate
interrupt API to ensure API function and interrupt entry is as fast and as
simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
@ -135,3 +135,4 @@
#endif
#endif /* PORTMACRO_H */

57
portable/GCC/RX600v2/port.c
View file

@ -42,15 +42,15 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
* PSW is set with U and I set, and PM and IPL clear. */
PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to
* xTaskIncrementTick(), which is only ever called from interrupts at the kernel
* priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */
xTaskIncrementTick(), which is only ever called from interrupts at the kernel
priority - ie a known priority. Therefore these local macros are a slight
optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
which would require the old IPL to be read first and stored in a local variable. */
#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
@ -83,9 +83,7 @@ extern void * pxCurrentTCB;
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* R0 is not included as it is the stack pointer. */
@ -96,8 +94,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = ( StackType_t ) pxCode;
/* When debugging it can be useful if every register is set to a known
* value. Otherwise code space can be saved by just setting the registers
* that need to be set. */
value. Otherwise code space can be saved by just setting the registers
that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION
{
pxTopOfStack--;
@ -130,11 +128,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = 0x22222222;
pxTopOfStack--;
}
#else /* ifdef USE_FULL_REGISTER_INITIALISATION */
#else
{
pxTopOfStack -= 15;
}
#endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
#endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
pxTopOfStack--;
@ -164,8 +162,8 @@ BaseType_t xPortStartScheduler( void )
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate the
* tick interrupt. This way the application can decide which peripheral to
* use. A demo application is provided to show a suitable example. */
tick interrupt. This way the application can decide which peripheral to
use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */
@ -189,7 +187,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
Artificially force an assert. */
configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
@ -198,22 +196,19 @@ static void prvStartFirstTask( void )
{
__asm volatile
(
/* When starting the scheduler there is nothing that needs moving to the
* interrupt stack because the function is not called from an interrupt.
* Just ensure the current stack is the user stack. */
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
"SETPSW U \n" \
/* Obtain the location of the stack associated with which ever task
* pxCurrentTCB is currently pointing to. */
pxCurrentTCB is currently pointing to. */
"MOV.L #_pxCurrentTCB, R15 \n" \
"MOV.L [R15], R15 \n" \
"MOV.L [R15], R0 \n" \
/* Restore the registers from the stack of the task pointed to by
* pxCurrentTCB. */
pxCurrentTCB. */
"POP R15 \n" \
/* Accumulator low 32 bits. */
@ -261,11 +256,10 @@ void vSoftwareInterruptISR( void )
/* Re-enable interrupts. */
"SETPSW I \n" \
/* Move the data that was automatically pushed onto the interrupt stack when
* the interrupt occurred from the interrupt stack to the user stack.
*
* R15 is saved before it is clobbered. */
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
"PUSH.L R15 \n" \
/* Read the user stack pointer. */
@ -312,9 +306,8 @@ void vSoftwareInterruptISR( void )
"MOV.L [ R15 ], R15 \n" \
"MOV.L R0, [ R15 ] \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel
* structures are being accessed. */
structures are being accessed. */
"MVTIPL %0 \n" \
/* Select the next task to run. */
@ -323,16 +316,14 @@ void vSoftwareInterruptISR( void )
/* Reset the interrupt mask as no more data structure access is required. */
"MVTIPL %1 \n" \
/* Load the stack pointer of the task that is now selected as the Running
* state task from its TCB. */
state task from its TCB. */
"MOV.L #_pxCurrentTCB,R15 \n" \
"MOV.L [ R15 ], R15 \n" \
"MOV.L [ R15 ], R0 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and
* PC will be popped by the RTE instruction. */
PC will be popped by the RTE instruction. */
"POP R15 \n" \
/* Accumulator low 32 bits. */
@ -374,7 +365,7 @@ void vTickISR( void )
__asm volatile( "SETPSW I" );
/* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */
necessitates. Ensure IPL is at the max syscall value first. */
portMASK_INTERRUPTS_FROM_KERNEL_ISR();
{
if( xTaskIncrementTick() != pdFALSE )

27
portable/GCC/RX600v2/portmacro.h
View file

@ -44,7 +44,7 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */
portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
@ -65,7 +65,7 @@
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
@ -77,9 +77,9 @@
#define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
* where portITU_SWINTR is the location of the software interrupt register
* (0x000872E0). Don't rely on the assembler to select a register, so instead
* save and restore clobbered registers manually. */
where portITU_SWINTR is the location of the software interrupt register
(0x000872E0). Don't rely on the assembler to select a register, so instead
save and restore clobbered registers manually. */
#define portYIELD() \
__asm volatile \
( \
@ -93,14 +93,14 @@
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */
taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
performed if configASSERT() is defined to ensure an assertion handler does not
inadvertently attempt to lower the IPL when the call to assert was triggered
because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
functions are those that end in FromISR. FreeRTOS maintains a separate
interrupt API to ensure API function and interrupt entry is as fast and as
simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
@ -135,3 +135,4 @@
#endif
#endif /* PORTMACRO_H */

29
portable/GCC/STR75x/port.c
View file

@ -63,24 +63,22 @@ static void prvSetupTimerInterrupt( void );
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
* is not really required. */
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
* start of the task. The offset is added to make the return address appear
* as it would within an IRQ ISR. */
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
@ -114,7 +112,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
* R0. */
R0. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
@ -131,8 +129,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
* instead be stored in a variable, which is then saved as part of the
* tasks context. */
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
@ -144,7 +142,7 @@ BaseType_t xPortStartScheduler( void )
extern void vPortISRStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
@ -158,7 +156,7 @@ BaseType_t xPortStartScheduler( void )
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
* is nothing to return to. */
is nothing to return to. */
}
/*-----------------------------------------------------------*/
@ -190,3 +188,10 @@ static void prvSetupTimerInterrupt( void )
TB_Cmd(ENABLE);
}
/*-----------------------------------------------------------*/

15
portable/GCC/STR75x/portISR.c
View file

@ -56,7 +56,7 @@ void vPortISRStartFirstTask( void );
void vPortISRStartFirstTask( void )
{
/* Simply start the scheduler. This is included here as it can only be
* called from ARM mode. */
called from ARM mode. */
asm volatile ( \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
@ -89,7 +89,7 @@ void vPortISRStartFirstTask( void )
void vPortTickISR( void )
{
/* Increment the RTOS tick count, then look for the highest priority
* task that is ready to run. */
task that is ready to run. */
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
@ -148,8 +148,8 @@ void vPortEnterCritical( void )
"LDMIA SP!, {R0}" ); /* Pop R0. */
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@ -162,7 +162,7 @@ void vPortExitCritical( void )
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
* re-enabled. */
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
@ -175,3 +175,8 @@ void vPortExitCritical( void )
}
}
}

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