mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Style: Revert uncrustify for portable directories (#122)
* Style: revert uncrustify portable directories * Style: Uncrustify Some Portable files Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
This commit is contained in:
alfred gedeon
GitHub
parent
a6da1cd0ce
commit
86653e2a1f
273 changed files with 64802 additions and 65931 deletions
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@ -25,34 +25,34 @@
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* 1 tab == 4 spaces!
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*/
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/*
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* Changes between V1.2.4 and V1.2.5
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*
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+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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+ interrupt flag setting. Using the two bits defined within
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+ portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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+ before the test was performed.
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+
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+ Changes from V1.2.5
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+
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+ Set the interrupt vector address to 0x08. Previously it was at the
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+ incorrect address for compatibility mode of 0x18.
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+
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+ Changes from V2.1.1
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+
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+ PCLATU and PCLATH are now saved as part of the context. This allows
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+ function pointers to be used within tasks. Thanks to Javier Espeche
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+ for the enhancement.
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+
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+ Changes from V2.3.1
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+
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+ TABLAT is now saved as part of the task context.
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+
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+ Changes from V3.2.0
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+
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+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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+ value and does not write to the register.
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*/
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/*
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Changes between V1.2.4 and V1.2.5
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+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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interrupt flag setting. Using the two bits defined within
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portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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before the test was performed.
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Changes from V1.2.5
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+ Set the interrupt vector address to 0x08. Previously it was at the
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incorrect address for compatibility mode of 0x18.
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Changes from V2.1.1
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+ PCLATU and PCLATH are now saved as part of the context. This allows
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function pointers to be used within tasks. Thanks to Javier Espeche
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for the enhancement.
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Changes from V2.3.1
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+ TABLAT is now saved as part of the task context.
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Changes from V3.2.0
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+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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value and does not write to the register.
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*/
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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@ -62,37 +62,37 @@
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#include "timers.h"
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PIC port.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the PIC port.
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*----------------------------------------------------------*/
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/* Hardware setup for tick. */
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#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
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/* Initial interrupt enable state for newly created tasks. This value is
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* copied into INTCON when a task switches in for the first time. */
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#define portINITAL_INTERRUPT_STATE 0xc0
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copied into INTCON when a task switches in for the first time. */
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#define portINITAL_INTERRUPT_STATE 0xc0
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/* Just the bit within INTCON for the global interrupt flag. */
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#define portGLOBAL_INTERRUPT_FLAG 0x80
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#define portGLOBAL_INTERRUPT_FLAG 0x80
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/* Constant used for context switch macro when we require the interrupt
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* enable state to be unchanged when the interrupted task is switched back in. */
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#define portINTERRUPTS_UNCHANGED 0x00
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/* Constant used for context switch macro when we require the interrupt
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enable state to be unchanged when the interrupted task is switched back in. */
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#define portINTERRUPTS_UNCHANGED 0x00
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/* Some memory areas get saved as part of the task context. These memory
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* area's get used by the compiler for temporary storage, especially when
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* performing mathematical operations, or when using 32bit data types. This
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* constant defines the size of memory area which must be saved. */
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#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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area's get used by the compiler for temporary storage, especially when
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performing mathematical operations, or when using 32bit data types. This
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constant defines the size of memory area which must be saved. */
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#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
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/* We require the address of the pxCurrentTCB variable, but don't want to know
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* any details of its type. */
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any details of its type. */
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typedef void TCB_t;
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extern volatile TCB_t * volatile pxCurrentTCB;
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/* IO port constants. */
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#define portBIT_SET ( ( uint8_t ) 1 )
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#define portBIT_CLEAR ( ( uint8_t ) 0 )
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#define portBIT_SET ( ( uint8_t ) 1 )
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#define portBIT_CLEAR ( ( uint8_t ) 0 )
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/*
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* The serial port ISR's are defined in serial.c, but are called from portable
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@ -106,7 +106,7 @@ void vSerialRxISR( void );
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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/*
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* ISR to maintain the tick, and perform tick context switches if the
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* preemptive scheduler is being used.
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*/
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@ -118,13 +118,13 @@ static void prvTickISR( void );
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*/
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static void prvLowInterrupt( void );
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/*
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/*
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* Macro that pushes all the registers that make up the context of a task onto
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* the stack, then saves the new top of stack into the TCB.
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*
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* If this is called from an ISR then the interrupt enable bits must have been
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*
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* If this is called from an ISR then the interrupt enable bits must have been
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* set for the ISR to ever get called. Therefore we want to save the INTCON
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* register with the enable bits forced to be set - and ucForcedInterruptFlags
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* register with the enable bits forced to be set - and ucForcedInterruptFlags
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* must contain these bit settings. This means the interrupts will again be
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* enabled when the interrupted task is switched back in.
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*
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@ -137,362 +137,360 @@ static void prvLowInterrupt( void );
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* storage during math and other computations. This is especially true if
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* 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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* and MATH_DATA sections have to be stored in there entirety as part of a task
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* context. This macro stores from data address 0x00 to
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* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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* applications but you should check the map file for your project to ensure
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* this is sufficient for your needs. It is not clear whether this size is
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* context. This macro stores from data address 0x00 to
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* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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* applications but you should check the map file for your project to ensure
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* this is sufficient for your needs. It is not clear whether this size is
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* fixed for all compilations or has the potential to be program specific.
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*/
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#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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{ \
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_asm \
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/* Save the status and WREG registers first, as these will get modified \
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* by the operations below. */ \
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MOVFF WREG, PREINC1 \
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MOVFF STATUS, PREINC1 \
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/* Save the INTCON register with the appropriate bits forced if \
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* necessary - as described above. */ \
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MOVFF INTCON, WREG \
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IORLW ucForcedInterruptFlags \
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MOVFF WREG, PREINC1 \
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_endasm \
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\
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portDISABLE_INTERRUPTS(); \
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\
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_asm \
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/* Store the necessary registers to the stack. */ \
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MOVFF BSR, PREINC1 \
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MOVFF FSR2L, PREINC1 \
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MOVFF FSR2H, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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MOVFF TABLAT, PREINC1 \
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MOVFF TBLPTRU, PREINC1 \
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MOVFF TBLPTRH, PREINC1 \
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MOVFF TBLPTRL, PREINC1 \
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MOVFF PRODH, PREINC1 \
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MOVFF PRODL, PREINC1 \
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MOVFF PCLATU, PREINC1 \
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MOVFF PCLATH, PREINC1 \
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/* Store the .tempdata and MATH_DATA areas as described above. */ \
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CLRF FSR0L, 0 \
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CLRF FSR0H, 0 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF INDF0, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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/* Store the hardware stack pointer in a temp register before we \
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* modify it. */ \
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MOVFF STKPTR, FSR0L \
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_endasm \
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\
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/* Store each address from the hardware stack. */ \
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while( STKPTR > ( uint8_t ) 0 ) \
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{ \
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_asm \
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MOVFF TOSL, PREINC1 \
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MOVFF TOSH, PREINC1 \
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MOVFF TOSU, PREINC1 \
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POP \
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_endasm \
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} \
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\
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_asm \
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/* Store the number of addresses on the hardware stack (from the \
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* temporary register). */ \
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MOVFF FSR0L, PREINC1 \
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MOVF PREINC1, 1, 0 \
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_endasm \
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\
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/* Save the new top of the software stack in the TCB. */ \
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_asm \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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MOVFF FSR1L, POSTINC0 \
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MOVFF FSR1H, POSTINC0 \
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_endasm \
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}
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#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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{ \
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_asm \
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/* Save the status and WREG registers first, as these will get modified \
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by the operations below. */ \
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MOVFF WREG, PREINC1 \
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MOVFF STATUS, PREINC1 \
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/* Save the INTCON register with the appropriate bits forced if \
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necessary - as described above. */ \
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MOVFF INTCON, WREG \
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IORLW ucForcedInterruptFlags \
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MOVFF WREG, PREINC1 \
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_endasm \
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\
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portDISABLE_INTERRUPTS(); \
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\
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_asm \
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/* Store the necessary registers to the stack. */ \
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MOVFF BSR, PREINC1 \
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MOVFF FSR2L, PREINC1 \
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MOVFF FSR2H, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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MOVFF TABLAT, PREINC1 \
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MOVFF TBLPTRU, PREINC1 \
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MOVFF TBLPTRH, PREINC1 \
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MOVFF TBLPTRL, PREINC1 \
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MOVFF PRODH, PREINC1 \
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MOVFF PRODL, PREINC1 \
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MOVFF PCLATU, PREINC1 \
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MOVFF PCLATH, PREINC1 \
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/* Store the .tempdata and MATH_DATA areas as described above. */ \
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CLRF FSR0L, 0 \
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CLRF FSR0H, 0 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF INDF0, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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/* Store the hardware stack pointer in a temp register before we \
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modify it. */ \
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MOVFF STKPTR, FSR0L \
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_endasm \
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\
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/* Store each address from the hardware stack. */ \
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while( STKPTR > ( uint8_t ) 0 ) \
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{ \
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_asm \
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MOVFF TOSL, PREINC1 \
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MOVFF TOSH, PREINC1 \
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MOVFF TOSU, PREINC1 \
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POP \
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_endasm \
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} \
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\
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_asm \
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/* Store the number of addresses on the hardware stack (from the \
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temporary register). */ \
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MOVFF FSR0L, PREINC1 \
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MOVF PREINC1, 1, 0 \
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_endasm \
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\
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/* Save the new top of the software stack in the TCB. */ \
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_asm \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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MOVFF FSR1L, POSTINC0 \
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MOVFF FSR1H, POSTINC0 \
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_endasm \
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}
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/*-----------------------------------------------------------*/
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/*
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* This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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* details.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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_asm \
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/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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\
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/* De-reference FSR0 to set the address it holds into FSR1. \
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* (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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MOVFF POSTINC0, FSR1L \
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MOVFF POSTINC0, FSR1H \
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\
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/* How many return addresses are there on the hardware stack? Discard \
|
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* the first byte as we are pointing to the next free space. */ \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, FSR0L \
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_endasm \
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||||
\
|
||||
/* Fill the hardware stack from our software stack. */ \
|
||||
STKPTR = 0; \
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||||
\
|
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while( STKPTR < FSR0L ) \
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||||
{ \
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||||
_asm \
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||||
PUSH \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSU, 0 \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSH, 0 \
|
||||
MOVF POSTDEC1, 0, 0 \
|
||||
MOVWF TOSL, 0 \
|
||||
_endasm \
|
||||
} \
|
||||
\
|
||||
_asm \
|
||||
/* Restore the .tmpdata and MATH_DATA memory. */ \
|
||||
MOVFF POSTDEC1, FSR0H \
|
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MOVFF POSTDEC1, FSR0L \
|
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MOVFF POSTDEC1, POSTDEC0 \
|
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MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
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MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, INDF0 \
|
||||
/* Restore the other registers forming the tasks context. */ \
|
||||
MOVFF POSTDEC1, PCLATH \
|
||||
MOVFF POSTDEC1, PCLATU \
|
||||
MOVFF POSTDEC1, PRODL \
|
||||
MOVFF POSTDEC1, PRODH \
|
||||
MOVFF POSTDEC1, TBLPTRL \
|
||||
MOVFF POSTDEC1, TBLPTRH \
|
||||
MOVFF POSTDEC1, TBLPTRU \
|
||||
MOVFF POSTDEC1, TABLAT \
|
||||
MOVFF POSTDEC1, FSR0H \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
MOVFF POSTDEC1, FSR2H \
|
||||
MOVFF POSTDEC1, FSR2L \
|
||||
MOVFF POSTDEC1, BSR \
|
||||
/* The next byte is the INTCON register. Read this into WREG as some \
|
||||
* manipulation is required. */ \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
_endasm \
|
||||
\
|
||||
/* From the INTCON register, only the interrupt enable bits form part \
|
||||
* of the tasks context. It is perfectly legitimate for another task to \
|
||||
* have modified any other bits. We therefore only restore the top two bits. \
|
||||
*/ \
|
||||
if( WREG &portGLOBAL_INTERRUPT_FLAG ) \
|
||||
{ \
|
||||
_asm \
|
||||
MOVFF POSTDEC1, STATUS \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
/* Return enabling interrupts. */ \
|
||||
RETFIE 0 \
|
||||
_endasm \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
_asm \
|
||||
MOVFF POSTDEC1, STATUS \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
/* Return without effecting interrupts. The context may have \
|
||||
* been saved from a critical region. */ \
|
||||
RETURN 0 \
|
||||
_endasm \
|
||||
} \
|
||||
}
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
_asm \
|
||||
/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
|
||||
MOVFF pxCurrentTCB, FSR0L \
|
||||
MOVFF pxCurrentTCB + 1, FSR0H \
|
||||
\
|
||||
/* De-reference FSR0 to set the address it holds into FSR1. \
|
||||
(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
|
||||
MOVFF POSTINC0, FSR1L \
|
||||
MOVFF POSTINC0, FSR1H \
|
||||
\
|
||||
/* How many return addresses are there on the hardware stack? Discard \
|
||||
the first byte as we are pointing to the next free space. */ \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
_endasm \
|
||||
\
|
||||
/* Fill the hardware stack from our software stack. */ \
|
||||
STKPTR = 0; \
|
||||
\
|
||||
while( STKPTR < FSR0L ) \
|
||||
{ \
|
||||
_asm \
|
||||
PUSH \
|
||||
MOVF POSTDEC1, 0, 0 \
|
||||
MOVWF TOSU, 0 \
|
||||
MOVF POSTDEC1, 0, 0 \
|
||||
MOVWF TOSH, 0 \
|
||||
MOVF POSTDEC1, 0, 0 \
|
||||
MOVWF TOSL, 0 \
|
||||
_endasm \
|
||||
} \
|
||||
\
|
||||
_asm \
|
||||
/* Restore the .tmpdata and MATH_DATA memory. */ \
|
||||
MOVFF POSTDEC1, FSR0H \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, POSTDEC0 \
|
||||
MOVFF POSTDEC1, INDF0 \
|
||||
/* Restore the other registers forming the tasks context. */ \
|
||||
MOVFF POSTDEC1, PCLATH \
|
||||
MOVFF POSTDEC1, PCLATU \
|
||||
MOVFF POSTDEC1, PRODL \
|
||||
MOVFF POSTDEC1, PRODH \
|
||||
MOVFF POSTDEC1, TBLPTRL \
|
||||
MOVFF POSTDEC1, TBLPTRH \
|
||||
MOVFF POSTDEC1, TBLPTRU \
|
||||
MOVFF POSTDEC1, TABLAT \
|
||||
MOVFF POSTDEC1, FSR0H \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
MOVFF POSTDEC1, FSR2H \
|
||||
MOVFF POSTDEC1, FSR2L \
|
||||
MOVFF POSTDEC1, BSR \
|
||||
/* The next byte is the INTCON register. Read this into WREG as some \
|
||||
manipulation is required. */ \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
_endasm \
|
||||
\
|
||||
/* From the INTCON register, only the interrupt enable bits form part \
|
||||
of the tasks context. It is perfectly legitimate for another task to \
|
||||
have modified any other bits. We therefore only restore the top two bits. \
|
||||
*/ \
|
||||
if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
|
||||
{ \
|
||||
_asm \
|
||||
MOVFF POSTDEC1, STATUS \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
/* Return enabling interrupts. */ \
|
||||
RETFIE 0 \
|
||||
_endasm \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
_asm \
|
||||
MOVFF POSTDEC1, STATUS \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
/* Return without effecting interrupts. The context may have \
|
||||
been saved from a critical region. */ \
|
||||
RETURN 0 \
|
||||
_endasm \
|
||||
} \
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
uint32_t ulAddress;
|
||||
uint8_t ucBlock;
|
||||
uint32_t ulAddress;
|
||||
uint8_t ucBlock;
|
||||
|
||||
/* Place a few bytes of known values on the bottom of the stack.
|
||||
* This is just useful for debugging. */
|
||||
/* Place a few bytes of known values on the bottom of the stack.
|
||||
This is just useful for debugging. */
|
||||
|
||||
*pxTopOfStack = 0x11;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = 0x22;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = 0x33;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = 0x11;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = 0x22;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = 0x33;
|
||||
pxTopOfStack++;
|
||||
|
||||
|
||||
/* Simulate how the stack would look after a call to vPortYield() generated
|
||||
* by the compiler.
|
||||
*
|
||||
* First store the function parameters. This is where the task will expect to
|
||||
* find them when it starts running. */
|
||||
ulAddress = ( uint32_t ) pvParameters;
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
/* Simulate how the stack would look after a call to vPortYield() generated
|
||||
by the compiler.
|
||||
|
||||
ulAddress >>= 8;
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
First store the function parameters. This is where the task will expect to
|
||||
find them when it starts running. */
|
||||
ulAddress = ( uint32_t ) pvParameters;
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Next we just leave a space. When a context is saved the stack pointer
|
||||
* is incremented before it is used so as not to corrupt whatever the stack
|
||||
* pointer is actually pointing to. This is especially necessary during
|
||||
* function epilogue code generated by the compiler. */
|
||||
*pxTopOfStack = 0x44;
|
||||
pxTopOfStack++;
|
||||
ulAddress >>= 8;
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Next are all the registers that form part of the task context. */
|
||||
/* Next we just leave a space. When a context is saved the stack pointer
|
||||
is incremented before it is used so as not to corrupt whatever the stack
|
||||
pointer is actually pointing to. This is especially necessary during
|
||||
function epilogue code generated by the compiler. */
|
||||
*pxTopOfStack = 0x44;
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
|
||||
pxTopOfStack++;
|
||||
/* Next are all the registers that form part of the task context. */
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
|
||||
pxTopOfStack++;
|
||||
|
||||
/* INTCON is saved with interrupts enabled. */
|
||||
*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
|
||||
pxTopOfStack++;
|
||||
/* INTCON is saved with interrupts enabled. */
|
||||
*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Next the .tmpdata and MATH_DATA sections. */
|
||||
for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
|
||||
{
|
||||
*pxTopOfStack = ( StackType_t ) ucBlock;
|
||||
*pxTopOfStack++;
|
||||
}
|
||||
/* Next the .tmpdata and MATH_DATA sections. */
|
||||
for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
|
||||
{
|
||||
*pxTopOfStack = ( StackType_t ) ucBlock;
|
||||
*pxTopOfStack++;
|
||||
}
|
||||
|
||||
/* Store the top of the global data section. */
|
||||
*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
|
||||
pxTopOfStack++;
|
||||
/* Store the top of the global data section. */
|
||||
*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
|
||||
pxTopOfStack++;
|
||||
|
||||
/* The only function return address so far is the address of the
|
||||
* task. */
|
||||
ulAddress = ( uint32_t ) pxCode;
|
||||
/* The only function return address so far is the address of the
|
||||
task. */
|
||||
ulAddress = ( uint32_t ) pxCode;
|
||||
|
||||
/* TOS low. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
ulAddress >>= 8;
|
||||
/* TOS low. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
ulAddress >>= 8;
|
||||
|
||||
/* TOS high. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
ulAddress >>= 8;
|
||||
/* TOS high. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
ulAddress >>= 8;
|
||||
|
||||
/* TOS even higher. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
/* TOS even higher. */
|
||||
*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Store the number of return addresses on the hardware stack - so far only
|
||||
* the address of the task entry point. */
|
||||
*pxTopOfStack = ( StackType_t ) 1;
|
||||
pxTopOfStack++;
|
||||
/* Store the number of return addresses on the hardware stack - so far only
|
||||
the address of the task entry point. */
|
||||
*pxTopOfStack = ( StackType_t ) 1;
|
||||
pxTopOfStack++;
|
||||
|
||||
return pxTopOfStack;
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* Setup a timer for the tick ISR is using the preemptive scheduler. */
|
||||
prvSetupTimerInterrupt();
|
||||
/* Setup a timer for the tick ISR is using the preemptive scheduler. */
|
||||
prvSetupTimerInterrupt();
|
||||
|
||||
/* Restore the context of the first task to run. */
|
||||
portRESTORE_CONTEXT();
|
||||
/* Restore the context of the first task to run. */
|
||||
portRESTORE_CONTEXT();
|
||||
|
||||
/* Should not get here. Use the function name to stop compiler warnings. */
|
||||
( void ) prvLowInterrupt;
|
||||
( void ) prvTickISR;
|
||||
/* Should not get here. Use the function name to stop compiler warnings. */
|
||||
( void ) prvLowInterrupt;
|
||||
( void ) prvTickISR;
|
||||
|
||||
return pdTRUE;
|
||||
return pdTRUE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* It is unlikely that the scheduler for the PIC port will get stopped
|
||||
* once running. If required disable the tick interrupt here, then return
|
||||
* to xPortStartScheduler(). */
|
||||
/* It is unlikely that the scheduler for the PIC port will get stopped
|
||||
once running. If required disable the tick interrupt here, then return
|
||||
to xPortStartScheduler(). */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -503,15 +501,15 @@ void vPortEndScheduler( void )
|
|||
*/
|
||||
void vPortYield( void )
|
||||
{
|
||||
/* This can get called with interrupts either enabled or disabled. We
|
||||
* will save the INTCON register with the interrupt enable bits unmodified. */
|
||||
portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
|
||||
/* This can get called with interrupts either enabled or disabled. We
|
||||
will save the INTCON register with the interrupt enable bits unmodified. */
|
||||
portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
|
||||
|
||||
/* Switch to the highest priority task that is ready to run. */
|
||||
vTaskSwitchContext();
|
||||
/* Switch to the highest priority task that is ready to run. */
|
||||
vTaskSwitchContext();
|
||||
|
||||
/* Start executing the task we have just switched to. */
|
||||
portRESTORE_CONTEXT();
|
||||
/* Start executing the task we have just switched to. */
|
||||
portRESTORE_CONTEXT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -521,32 +519,32 @@ void vPortYield( void )
|
|||
#pragma code high_vector=0x08
|
||||
static void prvLowInterrupt( void )
|
||||
{
|
||||
/* Was the interrupt the tick? */
|
||||
if( PIR1bits.CCP1IF )
|
||||
{
|
||||
_asm
|
||||
goto prvTickISR
|
||||
_endasm
|
||||
}
|
||||
/* Was the interrupt the tick? */
|
||||
if( PIR1bits.CCP1IF )
|
||||
{
|
||||
_asm
|
||||
goto prvTickISR
|
||||
_endasm
|
||||
}
|
||||
|
||||
/* Was the interrupt a byte being received? */
|
||||
if( PIR1bits.RCIF )
|
||||
{
|
||||
_asm
|
||||
goto vSerialRxISR
|
||||
_endasm
|
||||
}
|
||||
/* Was the interrupt a byte being received? */
|
||||
if( PIR1bits.RCIF )
|
||||
{
|
||||
_asm
|
||||
goto vSerialRxISR
|
||||
_endasm
|
||||
}
|
||||
|
||||
/* Was the interrupt the Tx register becoming empty? */
|
||||
if( PIR1bits.TXIF )
|
||||
{
|
||||
if( PIE1bits.TXIE )
|
||||
{
|
||||
_asm
|
||||
goto vSerialTxISR
|
||||
_endasm
|
||||
}
|
||||
}
|
||||
/* Was the interrupt the Tx register becoming empty? */
|
||||
if( PIR1bits.TXIF )
|
||||
{
|
||||
if( PIE1bits.TXIE )
|
||||
{
|
||||
_asm
|
||||
goto vSerialTxISR
|
||||
_endasm
|
||||
}
|
||||
}
|
||||
}
|
||||
#pragma code
|
||||
|
||||
|
|
@ -554,25 +552,25 @@ static void prvLowInterrupt( void )
|
|||
|
||||
/*
|
||||
* ISR for the tick.
|
||||
* This increments the tick count and, if using the preemptive scheduler,
|
||||
* performs a context switch. This must be identical to the manual
|
||||
* context switch in how it stores the context of a task.
|
||||
* This increments the tick count and, if using the preemptive scheduler,
|
||||
* performs a context switch. This must be identical to the manual
|
||||
* context switch in how it stores the context of a task.
|
||||
*/
|
||||
static void prvTickISR( void )
|
||||
{
|
||||
/* Interrupts must have been enabled for the ISR to fire, so we have to
|
||||
* save the context with interrupts enabled. */
|
||||
portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
|
||||
PIR1bits.CCP1IF = 0;
|
||||
/* Interrupts must have been enabled for the ISR to fire, so we have to
|
||||
save the context with interrupts enabled. */
|
||||
portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
|
||||
PIR1bits.CCP1IF = 0;
|
||||
|
||||
/* Maintain the tick count. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Switch to the highest priority task that is ready to run. */
|
||||
vTaskSwitchContext();
|
||||
}
|
||||
/* Maintain the tick count. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Switch to the highest priority task that is ready to run. */
|
||||
vTaskSwitchContext();
|
||||
}
|
||||
|
||||
portRESTORE_CONTEXT();
|
||||
portRESTORE_CONTEXT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -581,36 +579,37 @@ static void prvTickISR( void )
|
|||
*/
|
||||
static void prvSetupTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
|
||||
uint32_t ulCompareValue;
|
||||
uint8_t ucByte;
|
||||
const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
|
||||
uint32_t ulCompareValue;
|
||||
uint8_t ucByte;
|
||||
|
||||
/* Interrupts are disabled when this function is called.
|
||||
*
|
||||
* Setup CCP1 to provide the tick interrupt using a compare match on timer
|
||||
* 1.
|
||||
*
|
||||
* Clear the time count then setup timer. */
|
||||
TMR1H = ( uint8_t ) 0x00;
|
||||
TMR1L = ( uint8_t ) 0x00;
|
||||
/* Interrupts are disabled when this function is called.
|
||||
|
||||
/* Set the compare match value. */
|
||||
ulCompareValue = ulConstCompareValue;
|
||||
CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||||
ulCompareValue >>= ( uint32_t ) 8;
|
||||
CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||||
Setup CCP1 to provide the tick interrupt using a compare match on timer
|
||||
1.
|
||||
|
||||
CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
|
||||
PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
|
||||
Clear the time count then setup timer. */
|
||||
TMR1H = ( uint8_t ) 0x00;
|
||||
TMR1L = ( uint8_t ) 0x00;
|
||||
|
||||
/* We are only going to use the global interrupt bit, so set the peripheral
|
||||
* bit to true. */
|
||||
INTCONbits.GIEL = portBIT_SET;
|
||||
/* Set the compare match value. */
|
||||
ulCompareValue = ulConstCompareValue;
|
||||
CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||||
ulCompareValue >>= ( uint32_t ) 8;
|
||||
CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
|
||||
|
||||
/* Provided library function for setting up the timer that will produce the
|
||||
* tick. */
|
||||
OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
|
||||
CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
|
||||
CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
|
||||
PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
|
||||
|
||||
/* We are only going to use the global interrupt bit, so set the peripheral
|
||||
bit to true. */
|
||||
INTCONbits.GIEL = portBIT_SET;
|
||||
|
||||
/* Provided library function for setting up the timer that will produce the
|
||||
tick. */
|
||||
OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -39,76 +39,74 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT int
|
||||
#define portSTACK_TYPE uint8_t
|
||||
#define portBASE_TYPE char
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT int
|
||||
#define portSTACK_TYPE uint8_t
|
||||
#define portBASE_TYPE char
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef signed char BaseType_t;
|
||||
typedef unsigned char UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef signed char BaseType_t;
|
||||
typedef unsigned char UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 1
|
||||
#define portGLOBAL_INT_ENABLE_BIT 0x80
|
||||
#define portSTACK_GROWTH 1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 1
|
||||
#define portGLOBAL_INT_ENABLE_BIT 0x80
|
||||
#define portSTACK_GROWTH 1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;
|
||||
#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
|
||||
#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;
|
||||
#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
|
||||
|
||||
/* Push the INTCON register onto the stack, then disable interrupts. */
|
||||
#define portENTER_CRITICAL() \
|
||||
POSTINC1 = INTCON; \
|
||||
INTCONbits.GIEH = 0;
|
||||
#define portENTER_CRITICAL() POSTINC1 = INTCON; \
|
||||
INTCONbits.GIEH = 0;
|
||||
|
||||
/* Retrieve the INTCON register from the stack, and enable interrupts
|
||||
* if they were saved as being enabled. Don't modify any other bits
|
||||
* within the INTCON register as these may have lagitimately have been
|
||||
* modified within the critical region. */
|
||||
#define portEXIT_CRITICAL() \
|
||||
_asm \
|
||||
MOVF POSTDEC1, 1, 0 \
|
||||
_endasm \
|
||||
if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
|
||||
{ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
}
|
||||
if they were saved as being enabled. Don't modify any other bits
|
||||
within the INTCON register as these may have lagitimately have been
|
||||
modified within the critical region. */
|
||||
#define portEXIT_CRITICAL() _asm \
|
||||
MOVF POSTDEC1, 1, 0 \
|
||||
_endasm \
|
||||
if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
|
||||
{ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
extern void vPortYield( void );
|
||||
#define portYIELD() vPortYield()
|
||||
#define portYIELD() vPortYield()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
|
||||
#define portNOP() \
|
||||
_asm \
|
||||
NOP \
|
||||
_endasm
|
||||
#define portNOP() _asm \
|
||||
NOP \
|
||||
_endasm
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -26,129 +26,129 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Changes from V4.2.1
|
||||
*
|
||||
+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
|
||||
*/
|
||||
Changes from V4.2.1
|
||||
|
||||
+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC24 port.
|
||||
*----------------------------------------------------------*/
|
||||
* Implementation of functions defined in portable.h for the PIC24 port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBIT_SET 1
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portINITIAL_SR 0
|
||||
#define portBIT_SET 1
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portINITIAL_SR 0
|
||||
|
||||
/* Defined for backward compatability with project created prior to
|
||||
* FreeRTOS.org V4.3.0. */
|
||||
FreeRTOS.org V4.3.0. */
|
||||
#ifndef configKERNEL_INTERRUPT_PRIORITY
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 1
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/* Use _T1Interrupt as the interrupt handler name if the application writer has
|
||||
* not provided their own. */
|
||||
not provided their own. */
|
||||
#ifndef configTICK_INTERRUPT_HANDLER
|
||||
#define configTICK_INTERRUPT_HANDLER _T1Interrupt
|
||||
#define configTICK_INTERRUPT_HANDLER _T1Interrupt
|
||||
#endif /* configTICK_INTERRUPT_HANDLER */
|
||||
|
||||
/* The program counter is only 23 bits. */
|
||||
#define portUNUSED_PR_BITS 0x7f
|
||||
#define portUNUSED_PR_BITS 0x7f
|
||||
|
||||
/* Records the nesting depth of calls to portENTER_CRITICAL(). */
|
||||
UBaseType_t uxCriticalNesting = 0xef;
|
||||
|
||||
#if configKERNEL_INTERRUPT_PRIORITY != 1
|
||||
#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
|
||||
#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
|
||||
#endif
|
||||
|
||||
#if defined( __PIC24E__ ) || defined( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
|
||||
#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
|
||||
|
||||
#ifdef __HAS_EDS__
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP DSWPAG \n" \
|
||||
"POP DSRPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR ");
|
||||
#else /* __HAS_EDS__ */
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR ");
|
||||
#endif /* __HAS_EDS__ */
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP DSWPAG \n" \
|
||||
"POP DSRPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR " );
|
||||
#else /* __HAS_EDS__ */
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR " );
|
||||
#endif /* __HAS_EDS__ */
|
||||
#endif /* MPLAB_PIC24_PORT */
|
||||
|
||||
#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
|
||||
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP DOENDH \n" \
|
||||
"POP DOENDL \n" \
|
||||
"POP DOSTARTH \n" \
|
||||
"POP DOSTARTL \n" \
|
||||
"POP DCOUNT \n" \
|
||||
"POP ACCBU \n" \
|
||||
"POP ACCBH \n" \
|
||||
"POP ACCBL \n" \
|
||||
"POP ACCAU \n" \
|
||||
"POP ACCAH \n" \
|
||||
"POP ACCAL \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR ");
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP DOENDH \n" \
|
||||
"POP DOENDL \n" \
|
||||
"POP DOSTARTH \n" \
|
||||
"POP DOSTARTL \n" \
|
||||
"POP DCOUNT \n" \
|
||||
"POP ACCBU \n" \
|
||||
"POP ACCBH \n" \
|
||||
"POP ACCBL \n" \
|
||||
"POP ACCAU \n" \
|
||||
"POP ACCAH \n" \
|
||||
"POP ACCAL \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
"POP.D W8 \n" \
|
||||
"POP.D W6 \n" \
|
||||
"POP.D W4 \n" \
|
||||
"POP.D W2 \n" \
|
||||
"POP.D W0 \n" \
|
||||
"POP SR " );
|
||||
|
||||
#endif /* MPLAB_DSPIC_PORT */
|
||||
|
||||
#ifndef portRESTORE_CONTEXT
|
||||
#error Unrecognised device selected
|
||||
#error Unrecognised device selected
|
||||
|
||||
/* Note: dsPIC parts with EDS are not supported as there is no easy way to
|
||||
* recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
|
||||
/* Note: dsPIC parts with EDS are not supported as there is no easy way to
|
||||
recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -159,177 +159,175 @@ void vApplicationSetupTickTimerInterrupt( void );
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
uint16_t usCode;
|
||||
UBaseType_t i;
|
||||
uint16_t usCode;
|
||||
UBaseType_t i;
|
||||
|
||||
const StackType_t xInitialStack[] =
|
||||
{
|
||||
0x1111, /* W1 */
|
||||
0x2222, /* W2 */
|
||||
0x3333, /* W3 */
|
||||
0x4444, /* W4 */
|
||||
0x5555, /* W5 */
|
||||
0x6666, /* W6 */
|
||||
0x7777, /* W7 */
|
||||
0x8888, /* W8 */
|
||||
0x9999, /* W9 */
|
||||
0xaaaa, /* W10 */
|
||||
0xbbbb, /* W11 */
|
||||
0xcccc, /* W12 */
|
||||
0xdddd, /* W13 */
|
||||
0xeeee, /* W14 */
|
||||
0xcdce, /* RCOUNT */
|
||||
0xabac, /* TBLPAG */
|
||||
const StackType_t xInitialStack[] =
|
||||
{
|
||||
0x1111, /* W1 */
|
||||
0x2222, /* W2 */
|
||||
0x3333, /* W3 */
|
||||
0x4444, /* W4 */
|
||||
0x5555, /* W5 */
|
||||
0x6666, /* W6 */
|
||||
0x7777, /* W7 */
|
||||
0x8888, /* W8 */
|
||||
0x9999, /* W9 */
|
||||
0xaaaa, /* W10 */
|
||||
0xbbbb, /* W11 */
|
||||
0xcccc, /* W12 */
|
||||
0xdddd, /* W13 */
|
||||
0xeeee, /* W14 */
|
||||
0xcdce, /* RCOUNT */
|
||||
0xabac, /* TBLPAG */
|
||||
|
||||
/* dsPIC specific registers. */
|
||||
#ifdef MPLAB_DSPIC_PORT
|
||||
0x0202, /* ACCAL */
|
||||
0x0303, /* ACCAH */
|
||||
0x0404, /* ACCAU */
|
||||
0x0505, /* ACCBL */
|
||||
0x0606, /* ACCBH */
|
||||
0x0707, /* ACCBU */
|
||||
0x0808, /* DCOUNT */
|
||||
0x090a, /* DOSTARTL */
|
||||
0x1010, /* DOSTARTH */
|
||||
0x1110, /* DOENDL */
|
||||
0x1212, /* DOENDH */
|
||||
#endif /* ifdef MPLAB_DSPIC_PORT */
|
||||
};
|
||||
/* dsPIC specific registers. */
|
||||
#ifdef MPLAB_DSPIC_PORT
|
||||
0x0202, /* ACCAL */
|
||||
0x0303, /* ACCAH */
|
||||
0x0404, /* ACCAU */
|
||||
0x0505, /* ACCBL */
|
||||
0x0606, /* ACCBH */
|
||||
0x0707, /* ACCBU */
|
||||
0x0808, /* DCOUNT */
|
||||
0x090a, /* DOSTARTL */
|
||||
0x1010, /* DOSTARTH */
|
||||
0x1110, /* DOENDL */
|
||||
0x1212, /* DOENDH */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Setup the stack as if a yield had occurred.
|
||||
*
|
||||
* Save the low bytes of the program counter. */
|
||||
usCode = ( uint16_t ) pxCode;
|
||||
*pxTopOfStack = ( StackType_t ) usCode;
|
||||
pxTopOfStack++;
|
||||
/* Setup the stack as if a yield had occurred.
|
||||
|
||||
/* Save the high byte of the program counter. This will always be zero
|
||||
* here as it is passed in a 16bit pointer. If the address is greater than
|
||||
* 16 bits then the pointer will point to a jump table. */
|
||||
*pxTopOfStack = ( StackType_t ) 0;
|
||||
pxTopOfStack++;
|
||||
Save the low bytes of the program counter. */
|
||||
usCode = ( uint16_t ) pxCode;
|
||||
*pxTopOfStack = ( StackType_t ) usCode;
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Status register with interrupts enabled. */
|
||||
*pxTopOfStack = portINITIAL_SR;
|
||||
pxTopOfStack++;
|
||||
/* Save the high byte of the program counter. This will always be zero
|
||||
here as it is passed in a 16bit pointer. If the address is greater than
|
||||
16 bits then the pointer will point to a jump table. */
|
||||
*pxTopOfStack = ( StackType_t ) 0;
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Parameters are passed in W0. */
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters;
|
||||
pxTopOfStack++;
|
||||
/* Status register with interrupts enabled. */
|
||||
*pxTopOfStack = portINITIAL_SR;
|
||||
pxTopOfStack++;
|
||||
|
||||
for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
|
||||
{
|
||||
*pxTopOfStack = xInitialStack[ i ];
|
||||
pxTopOfStack++;
|
||||
}
|
||||
/* Parameters are passed in W0. */
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters;
|
||||
pxTopOfStack++;
|
||||
|
||||
*pxTopOfStack = CORCON;
|
||||
pxTopOfStack++;
|
||||
for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
|
||||
{
|
||||
*pxTopOfStack = xInitialStack[ i ];
|
||||
pxTopOfStack++;
|
||||
}
|
||||
|
||||
#if defined( __HAS_EDS__ )
|
||||
*pxTopOfStack = DSRPAG;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = DSWPAG;
|
||||
pxTopOfStack++;
|
||||
#else /* __HAS_EDS__ */
|
||||
*pxTopOfStack = PSVPAG;
|
||||
pxTopOfStack++;
|
||||
#endif /* __HAS_EDS__ */
|
||||
*pxTopOfStack = CORCON;
|
||||
pxTopOfStack++;
|
||||
|
||||
/* Finally the critical nesting depth. */
|
||||
*pxTopOfStack = 0x00;
|
||||
pxTopOfStack++;
|
||||
#if defined(__HAS_EDS__)
|
||||
*pxTopOfStack = DSRPAG;
|
||||
pxTopOfStack++;
|
||||
*pxTopOfStack = DSWPAG;
|
||||
pxTopOfStack++;
|
||||
#else /* __HAS_EDS__ */
|
||||
*pxTopOfStack = PSVPAG;
|
||||
pxTopOfStack++;
|
||||
#endif /* __HAS_EDS__ */
|
||||
|
||||
return pxTopOfStack;
|
||||
/* Finally the critical nesting depth. */
|
||||
*pxTopOfStack = 0x00;
|
||||
pxTopOfStack++;
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
/* Setup a timer for the tick ISR. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
/* Setup a timer for the tick ISR. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Restore the context of the first task to run. */
|
||||
portRESTORE_CONTEXT();
|
||||
/* Restore the context of the first task to run. */
|
||||
portRESTORE_CONTEXT();
|
||||
|
||||
/* Simulate the end of the yield function. */
|
||||
asm volatile ( "return" );
|
||||
/* Simulate the end of the yield function. */
|
||||
asm volatile ( "return" );
|
||||
|
||||
/* Should not reach here. */
|
||||
return pdTRUE;
|
||||
/* Should not reach here. */
|
||||
return pdTRUE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxCriticalNesting == 1000UL );
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxCriticalNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Setup a timer for a regular tick.
|
||||
*/
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
|
||||
const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
|
||||
|
||||
/* Prescale of 8. */
|
||||
T1CON = 0;
|
||||
TMR1 = 0;
|
||||
/* Prescale of 8. */
|
||||
T1CON = 0;
|
||||
TMR1 = 0;
|
||||
|
||||
PR1 = ( uint16_t ) ulCompareMatch;
|
||||
PR1 = ( uint16_t ) ulCompareMatch;
|
||||
|
||||
/* Setup timer 1 interrupt priority. */
|
||||
IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
/* Setup timer 1 interrupt priority. */
|
||||
IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
|
||||
/* Setup the prescale value. */
|
||||
T1CONbits.TCKPS0 = 1;
|
||||
T1CONbits.TCKPS1 = 0;
|
||||
/* Setup the prescale value. */
|
||||
T1CONbits.TCKPS0 = 1;
|
||||
T1CONbits.TCKPS1 = 0;
|
||||
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
portDISABLE_INTERRUPTS();
|
||||
uxCriticalNesting++;
|
||||
portDISABLE_INTERRUPTS();
|
||||
uxCriticalNesting++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
configASSERT( uxCriticalNesting );
|
||||
uxCriticalNesting--;
|
||||
|
||||
if( uxCriticalNesting == 0 )
|
||||
{
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
configASSERT( uxCriticalNesting );
|
||||
uxCriticalNesting--;
|
||||
if( uxCriticalNesting == 0 )
|
||||
{
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__( ( __interrupt__, auto_psv ) ) configTICK_INTERRUPT_HANDLER( void )
|
||||
void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
|
||||
{
|
||||
/* Clear the timer interrupt. */
|
||||
IFS0bits.T1IF = 0;
|
||||
/* Clear the timer interrupt. */
|
||||
IFS0bits.T1IF = 0;
|
||||
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
portYIELD();
|
||||
}
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
portYIELD();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,11 +26,11 @@
|
|||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -43,66 +43,66 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint16_t
|
||||
#define portBASE_TYPE short
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint16_t
|
||||
#define portBASE_TYPE short
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef short BaseType_t;
|
||||
typedef unsigned short UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef short BaseType_t;
|
||||
typedef unsigned short UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 2
|
||||
#define portSTACK_GROWTH 1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 2
|
||||
#define portSTACK_GROWTH 1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
|
||||
#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 )
|
||||
#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
|
||||
#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 )
|
||||
|
||||
/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
|
||||
* what their value was prior to entering the critical section. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
what their value was prior to entering the critical section. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
extern void vPortYield( void );
|
||||
#define portYIELD() \
|
||||
asm volatile ( "CALL _vPortYield \n"\
|
||||
"NOP ");
|
||||
extern void vPortYield( void );
|
||||
#define portYIELD() asm volatile ( "CALL _vPortYield \n" \
|
||||
"NOP " );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -27,187 +27,188 @@
|
|||
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
#define portCONTEXT_SIZE 132
|
||||
#define portEPC_STACK_LOCATION 124
|
||||
#define portSTATUS_STACK_LOCATION 128
|
||||
#define portCONTEXT_SIZE 132
|
||||
#define portEPC_STACK_LOCATION 124
|
||||
#define portSTATUS_STACK_LOCATION 128
|
||||
|
||||
#ifdef __LANGUAGE_ASSEMBLY__
|
||||
|
||||
/******************************************************************/
|
||||
.macro portSAVE_CONTEXT
|
||||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
* maintain the values of these registers across the ISR. */
|
||||
sw s6, 44 ( sp )
|
||||
sw s5, 40 ( sp )
|
||||
sw k1, portSTATUS_STACK_LOCATION( sp )
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Prepare to enable interrupts above the current priority.
|
||||
* k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
|
||||
srl k0, k0, 0xa
|
||||
/* Prepare to enable interrupts above the current priority.
|
||||
k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
|
||||
srl k0, k0, 0xa
|
||||
|
||||
/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
|
||||
ins k1, k0, 10, 7
|
||||
/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
|
||||
ins k1, k0, 10, 7
|
||||
|
||||
/* Sets CP0.Status.IPL = CP0.Cause.RIPL
|
||||
* Copy the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
srl k0, k0, 0x7
|
||||
/* Sets CP0.Status.IPL = CP0.Cause.RIPL
|
||||
Copy the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
srl k0, k0, 0x7
|
||||
|
||||
/* MSB of IPL is bit[18] of CP0.Status */
|
||||
ins k1, k0, 18, 1
|
||||
/* MSB of IPL is bit[18] of CP0.Status */
|
||||
ins k1, k0, 18, 1
|
||||
|
||||
/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
|
||||
* b[3]=Rsvd, b[2]=ERL, b[1]=EXL
|
||||
* Setting EXL=0 allows higher priority interrupts
|
||||
* to preempt this handler */
|
||||
ins k1, zero, 1, 4
|
||||
/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
|
||||
b[3]=Rsvd, b[2]=ERL, b[1]=EXL
|
||||
Setting EXL=0 allows higher priority interrupts
|
||||
to preempt this handler */
|
||||
ins k1, zero, 1, 4
|
||||
|
||||
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, ( k0 )
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, (k0)
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, ( sp )
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, (sp)
|
||||
|
||||
/* Increment and save the nesting count. */
|
||||
1 : addiu s6, s6, 1
|
||||
sw s6, 0 ( k0 )
|
||||
/* Increment and save the nesting count. */
|
||||
1: addiu s6, s6, 1
|
||||
sw s6, 0(k0)
|
||||
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
sw ra, 120 ( s5 ) /* Return address (RA=R31) */
|
||||
sw s8, 116 ( s5 ) /* Frame Pointer (FP=R30) */
|
||||
sw t9, 112 ( s5 )
|
||||
sw t8, 108 ( s5 )
|
||||
sw t7, 104 ( s5 )
|
||||
sw t6, 100 ( s5 )
|
||||
sw t5, 96 ( s5 )
|
||||
sw t4, 92 ( s5 )
|
||||
sw t3, 88 ( s5 )
|
||||
sw t2, 84 ( s5 )
|
||||
sw t1, 80 ( s5 )
|
||||
sw t0, 76 ( s5 )
|
||||
sw a3, 72 ( s5 )
|
||||
sw a2, 68 ( s5 )
|
||||
sw a1, 64 ( s5 )
|
||||
sw a0, 60 ( s5 )
|
||||
sw v1, 56 ( s5 )
|
||||
sw v0, 52 ( s5 )
|
||||
sw s6, portEPC_STACK_LOCATION( s5 )
|
||||
sw $1, 16 ( s5 )
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5) /* Return address (RA=R31) */
|
||||
sw s8, 116(s5) /* Frame Pointer (FP=R30) */
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* MEC14xx does not have DSP, removed 7 words */
|
||||
mfhi s6
|
||||
sw s6, 12 ( s5 )
|
||||
mflo s6
|
||||
sw s6, 8 ( s5 )
|
||||
/* MEC14xx does not have DSP, removed 7 words */
|
||||
mfhi s6
|
||||
sw s6, 12(s5)
|
||||
mflo s6
|
||||
sw s6, 8(s5)
|
||||
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, ( s6 )
|
||||
1 :
|
||||
.endm
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, (s6)
|
||||
1:
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portRESTORE_CONTEXT
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, ( s6 )
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, (s6)
|
||||
|
||||
/* Restore the context.
|
||||
* MCHP MEC14xx does not include DSP */
|
||||
1 :
|
||||
lw s6, 8 ( s5 )
|
||||
mtlo s6
|
||||
lw s6, 12 ( s5 )
|
||||
mthi s6
|
||||
lw $1, 16 ( s5 )
|
||||
/* Restore the context.
|
||||
MCHP MEC14xx does not include DSP */
|
||||
1:
|
||||
lw s6, 8(s5)
|
||||
mtlo s6
|
||||
lw s6, 12(s5)
|
||||
mthi s6
|
||||
lw $1, 16(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
lw s6, 44 ( s5 )
|
||||
lw v0, 52 ( s5 )
|
||||
lw v1, 56 ( s5 )
|
||||
lw a0, 60 ( s5 )
|
||||
lw a1, 64 ( s5 )
|
||||
lw a2, 68 ( s5 )
|
||||
lw a3, 72 ( s5 )
|
||||
lw t0, 76 ( s5 )
|
||||
lw t1, 80 ( s5 )
|
||||
lw t2, 84 ( s5 )
|
||||
lw t3, 88 ( s5 )
|
||||
lw t4, 92 ( s5 )
|
||||
lw t5, 96 ( s5 )
|
||||
lw t6, 100 ( s5 )
|
||||
lw t7, 104 ( s5 )
|
||||
lw t8, 108 ( s5 )
|
||||
lw t9, 112 ( s5 )
|
||||
lw s8, 116 ( s5 )
|
||||
lw ra, 120 ( s5 )
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
as part of the interrupt context. */
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, ( k0 )
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0 ( k0 )
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, (k0)
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0(k0)
|
||||
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.endm
|
||||
.endm
|
||||
|
||||
#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@
|
|||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
|
||||
*----------------------------------------------------------*/
|
||||
* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
|
|
@ -37,96 +37,94 @@
|
|||
#include <xc.h>
|
||||
#include <cp0defs.h>
|
||||
|
||||
#if !defined( __MEC__ )
|
||||
#error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
|
||||
#if !defined(__MEC__)
|
||||
#error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
|
||||
#endif
|
||||
|
||||
#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#endif
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
the first task is being restored. MEC14xx does not have DSP HW. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/* MEC14xx RTOS Timer MMCR's. */
|
||||
#define portMMCR_RTMR_PRELOAD *( ( volatile uint32_t * ) ( 0xA0007404ul ) )
|
||||
#define portMMCR_RTMR_CONTROL *( ( volatile uint32_t * ) ( 0xA0007408ul ) )
|
||||
#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
|
||||
#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
|
||||
|
||||
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
|
||||
* peripheral space. */
|
||||
#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
|
||||
#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SRC *( ( volatile uint32_t * ) ( 0xBFFFC0F0ul ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC0F4ul ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC3F0ul ) )
|
||||
peripheral space. */
|
||||
#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
|
||||
#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
|
||||
#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
|
||||
|
||||
/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_SRC *( ( volatile uint32_t * ) ( 0xBFFFC100ul ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC104ul ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC400ul ) )
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
|
||||
#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
|
||||
#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
|
||||
#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
* can override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
* behaviour for the specified interrupt vector.
|
||||
* 3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
* handler.
|
||||
*/
|
||||
By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
can override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
behaviour for the specified interrupt vector.
|
||||
3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
handler.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
* in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
|
||||
|
|
@ -140,7 +138,7 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
|
|
@ -150,7 +148,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
|
|||
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. */
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -158,62 +156,56 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) ulPortGetCP0Cause();
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
return pxTopOfStack;
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static __inline uint32_t prvDisableInterrupt( void )
|
||||
{
|
||||
uint32_t prev_state;
|
||||
uint32_t prev_state;
|
||||
|
||||
__asm volatile ( "di %0; ehb" : "=r" ( prev_state )::"memory" );
|
||||
|
||||
return prev_state;
|
||||
__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
|
||||
return prev_state;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -225,124 +217,129 @@ static void prvTaskExitError( void )
|
|||
* ensure the RTOS provided tick interrupt handler is installed on the correct
|
||||
* vector number.
|
||||
*/
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
/* MEC14xx RTOS Timer whose input clock is 32KHz. */
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
|
||||
configASSERT( ulPreload != 0UL );
|
||||
configASSERT( ulPreload != 0UL );
|
||||
|
||||
/* Configure the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0ul;
|
||||
portMMCR_RTMR_PRELOAD = ulPreload;
|
||||
/* Configure the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0ul;
|
||||
portMMCR_RTMR_PRELOAD = ulPreload;
|
||||
|
||||
/* Configure interrupts from the RTOS timer. */
|
||||
portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
/* Configure interrupts from the RTOS timer. */
|
||||
portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
|
||||
portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
|
||||
|
||||
/* Enable the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0x0Fu;
|
||||
/* Enable the RTOS timer. */
|
||||
portMMCR_RTMR_CONTROL = 0x0Fu;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void * pxCurrentTCB;
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
portMMCR_JTVIC_GIRQ24_SRC = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
/* Clear the software interrupt flag. */
|
||||
portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
|
||||
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
* priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~( 0xF0ul );
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
/* Enable software interrupt. */
|
||||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
* by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
* location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
ulCause = ulPortGetCP0Cause();
|
||||
ulCause |= ( 1ul << 8UL );
|
||||
vPortSetCP0Cause( ulCause );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
ulCause = ulPortGetCP0Cause();
|
||||
ulCause |= ( 1ul << 8UL );
|
||||
vPortSetCP0Cause( ulCause );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
prvDisableInterrupt();
|
||||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
prvDisableInterrupt();
|
||||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
return uxSavedStatusRegister;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
||||
{
|
||||
vPortSetCP0Status( uxSavedStatusRegister );
|
||||
vPortSetCP0Status( uxSavedStatusRegister );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -26,11 +26,11 @@
|
|||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -43,211 +43,210 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
* never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* Interrupt priority conversion */
|
||||
#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
|
||||
#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
|
||||
#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
|
||||
#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Status( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
static inline uint32_t ulPortGetCP0Status( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile (
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv )::);
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Status( uint32_t new_status )
|
||||
{
|
||||
( void ) new_status;
|
||||
static inline void vPortSetCP0Status( uint32_t new_status)
|
||||
{
|
||||
( void ) new_status;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
: "r" ( new_status ) : );
|
||||
}
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_status ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Cause( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
static inline uint32_t ulPortGetCP0Cause( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile (
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv )::);
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
|
||||
return rv;
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Cause( uint32_t new_cause )
|
||||
{
|
||||
( void ) new_cause;
|
||||
static inline void vPortSetCP0Cause( uint32_t new_cause )
|
||||
{
|
||||
( void ) new_cause;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
: "r" ( new_cause ) : );
|
||||
}
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_cause ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
|
||||
if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -27,165 +27,165 @@
|
|||
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
#define portCONTEXT_SIZE 132
|
||||
#define portEPC_STACK_LOCATION 124
|
||||
#define portSTATUS_STACK_LOCATION 128
|
||||
#define portCONTEXT_SIZE 132
|
||||
#define portEPC_STACK_LOCATION 124
|
||||
#define portSTATUS_STACK_LOCATION 128
|
||||
|
||||
/******************************************************************/
|
||||
.macro portSAVE_CONTEXT
|
||||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
* maintain the values of these registers across the ISR. */
|
||||
sw s6, 44 ( sp )
|
||||
sw s5, 40 ( sp )
|
||||
sw k1, portSTATUS_STACK_LOCATION( sp )
|
||||
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
|
||||
maintain the values of these registers across the ISR. */
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Prepare to enable interrupts above the current priority. */
|
||||
srl k0, k0, 0xa
|
||||
ins k1, k0, 10, 6
|
||||
ins k1, zero, 1, 4
|
||||
/* Prepare to enable interrupts above the current priority. */
|
||||
srl k0, k0, 0xa
|
||||
ins k1, k0, 10, 6
|
||||
ins k1, zero, 1, 4
|
||||
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, ( k0 )
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, (k0)
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, ( sp )
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, (sp)
|
||||
|
||||
/* Increment and save the nesting count. */
|
||||
1 : addiu s6, s6, 1
|
||||
sw s6, 0 ( k0 )
|
||||
/* Increment and save the nesting count. */
|
||||
1: addiu s6, s6, 1
|
||||
sw s6, 0(k0)
|
||||
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
sw ra, 120 ( s5 )
|
||||
sw s8, 116 ( s5 )
|
||||
sw t9, 112 ( s5 )
|
||||
sw t8, 108 ( s5 )
|
||||
sw t7, 104 ( s5 )
|
||||
sw t6, 100 ( s5 )
|
||||
sw t5, 96 ( s5 )
|
||||
sw t4, 92 ( s5 )
|
||||
sw t3, 88 ( s5 )
|
||||
sw t2, 84 ( s5 )
|
||||
sw t1, 80 ( s5 )
|
||||
sw t0, 76 ( s5 )
|
||||
sw a3, 72 ( s5 )
|
||||
sw a2, 68 ( s5 )
|
||||
sw a1, 64 ( s5 )
|
||||
sw a0, 60 ( s5 )
|
||||
sw v1, 56 ( s5 )
|
||||
sw v0, 52 ( s5 )
|
||||
sw s6, portEPC_STACK_LOCATION( s5 )
|
||||
sw $1, 16 ( s5 )
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* s6 is used as a scratch register. */
|
||||
mfhi s6
|
||||
sw s6, 12 ( s5 )
|
||||
mflo s6
|
||||
sw s6, 8 ( s5 )
|
||||
/* s6 is used as a scratch register. */
|
||||
mfhi s6
|
||||
sw s6, 12(s5)
|
||||
mflo s6
|
||||
sw s6, 8(s5)
|
||||
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, ( s6 )
|
||||
1 :
|
||||
.endm
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, (s6)
|
||||
1:
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portRESTORE_CONTEXT
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, ( s6 )
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, (s6)
|
||||
|
||||
/* Restore the context. */
|
||||
1 : lw s6, 8 ( s5 )
|
||||
mtlo s6
|
||||
lw s6, 12 ( s5 )
|
||||
mthi s6
|
||||
lw $1, 16 ( s5 )
|
||||
/* Restore the context. */
|
||||
1: lw s6, 8(s5)
|
||||
mtlo s6
|
||||
lw s6, 12(s5)
|
||||
mthi s6
|
||||
lw $1, 16(s5)
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
as part of the interrupt context. */
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
lw s6, 44 ( s5 )
|
||||
lw v0, 52 ( s5 )
|
||||
lw v1, 56 ( s5 )
|
||||
lw a0, 60 ( s5 )
|
||||
lw a1, 64 ( s5 )
|
||||
lw a2, 68 ( s5 )
|
||||
lw a3, 72 ( s5 )
|
||||
lw t0, 76 ( s5 )
|
||||
lw t1, 80 ( s5 )
|
||||
lw t2, 84 ( s5 )
|
||||
lw t3, 88 ( s5 )
|
||||
lw t4, 92 ( s5 )
|
||||
lw t5, 96 ( s5 )
|
||||
lw t6, 100 ( s5 )
|
||||
lw t7, 104 ( s5 )
|
||||
lw t8, 108 ( s5 )
|
||||
lw t9, 112 ( s5 )
|
||||
lw s8, 116 ( s5 )
|
||||
lw ra, 120 ( s5 )
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, (k0)
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0(k0)
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, ( k0 )
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0 ( k0 )
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
.endm
|
||||
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@
|
|||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MX port.
|
||||
*----------------------------------------------------------*/
|
||||
* Implementation of functions defined in portable.h for the PIC32MX port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#ifndef __XC
|
||||
#error This port is designed to work with XC32. Please update your C compiler version.
|
||||
|
|
@ -38,80 +38,78 @@
|
|||
#include "task.h"
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
|
||||
/* Bits within the CAUSE register. */
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
the first task is being restored. */
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
* override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
* to generate the tick interrupt. For example, when timer 1 is used then
|
||||
* configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
* configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
* 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
* timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
* used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
* IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
to generate the tick interrupt. For example, when timer 1 is used then
|
||||
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
* debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -123,7 +121,7 @@
|
|||
* following line of code has no effect. The interrupt priority is set by the
|
||||
* call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
|
||||
*/
|
||||
extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT_VECTOR ) ) ) vPortTickInterruptHandler( void );
|
||||
extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
|
||||
|
||||
/*
|
||||
* The software interrupt handler that performs the yield. Note that, because
|
||||
|
|
@ -131,7 +129,7 @@ extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT
|
|||
* code has no effect. The interrupt priority is set by the call to
|
||||
* mConfigIntCoreSW0() in xPortStartScheduler().
|
||||
*/
|
||||
void __attribute__( ( interrupt( IPL1AUTO ), vector( _CORE_SOFTWARE_0_VECTOR ) ) ) vPortYieldISR( void );
|
||||
void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
|
||||
|
||||
/*
|
||||
* Used to catch tasks that attempt to return from their implementing function.
|
||||
|
|
@ -141,17 +139,17 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
UBaseType_t uxSavedTaskStackPointer = 0;
|
||||
|
||||
/* The stack used by interrupt service routines that cause a context switch. */
|
||||
__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. */
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -159,52 +157,47 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
return pxTopOfStack;
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -217,119 +210,123 @@ static void prvTaskExitError( void )
|
|||
* vector number. When Timer 1 is used the vector number is defined as
|
||||
* _TIMER_1_VECTOR.
|
||||
*/
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
|
||||
const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
|
||||
|
||||
T1CON = 0x0000;
|
||||
T1CONbits.TCKPS = portPRESCALE_BITS;
|
||||
PR1 = ulCompareMatch;
|
||||
IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
T1CON = 0x0000;
|
||||
T1CONbits.TCKPS = portPRESCALE_BITS;
|
||||
PR1 = ulCompareMatch;
|
||||
IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void * pxCurrentTCB;
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
IFS0CLR = _IFS0_CS0IF_MASK;
|
||||
/* Clear the software interrupt flag. */
|
||||
IFS0CLR = _IFS0_CS0IF_MASK;
|
||||
|
||||
/* Set software timer priority. */
|
||||
IPC0CLR = _IPC0_CS0IP_MASK;
|
||||
IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
|
||||
/* Set software timer priority. */
|
||||
IPC0CLR = _IPC0_CS0IP_MASK;
|
||||
IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
IEC0CLR = _IEC0_CS0IE_MASK;
|
||||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
/* Enable software interrupt. */
|
||||
IEC0CLR = _IEC0_CS0IE_MASK;
|
||||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
* disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
* Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
UBaseType_t uxSavedStatus;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
_CP0_BIS_CAUSE( portCORE_SW_0 );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
_CP0_BIS_CAUSE( portCORE_SW_0 );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
return uxSavedStatusRegister;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
||||
{
|
||||
_CP0_SET_STATUS( uxSavedStatusRegister );
|
||||
_CP0_SET_STATUS( uxSavedStatusRegister );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -26,14 +26,14 @@
|
|||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
/* System include files */
|
||||
#include <xc.h>
|
||||
#include <xc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -46,159 +46,159 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
|
||||
if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -27,406 +27,406 @@
|
|||
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
#define portCONTEXT_SIZE 160
|
||||
#define portEPC_STACK_LOCATION 152
|
||||
#define portSTATUS_STACK_LOCATION 156
|
||||
#define portFPCSR_STACK_LOCATION 0
|
||||
#define portTASK_HAS_FPU_STACK_LOCATION 0
|
||||
#define portFPU_CONTEXT_SIZE 264
|
||||
#define portCONTEXT_SIZE 160
|
||||
#define portEPC_STACK_LOCATION 152
|
||||
#define portSTATUS_STACK_LOCATION 156
|
||||
#define portFPCSR_STACK_LOCATION 0
|
||||
#define portTASK_HAS_FPU_STACK_LOCATION 0
|
||||
#define portFPU_CONTEXT_SIZE 264
|
||||
|
||||
/******************************************************************/
|
||||
.macro portSAVE_FPU_REGS offset, base
|
||||
.macro portSAVE_FPU_REGS offset, base
|
||||
/* Macro to assist with saving just the FPU registers to the
|
||||
* specified address and base offset,
|
||||
* offset is a constant, base is the base pointer register */
|
||||
|
||||
/* Macro to assist with saving just the FPU registers to the
|
||||
* specified address and base offset,
|
||||
* offset is a constant, base is the base pointer register */
|
||||
sdc1 $f31, \offset + 248(\base)
|
||||
sdc1 $f30, \offset + 240(\base)
|
||||
sdc1 $f29, \offset + 232(\base)
|
||||
sdc1 $f28, \offset + 224(\base)
|
||||
sdc1 $f27, \offset + 216(\base)
|
||||
sdc1 $f26, \offset + 208(\base)
|
||||
sdc1 $f25, \offset + 200(\base)
|
||||
sdc1 $f24, \offset + 192(\base)
|
||||
sdc1 $f23, \offset + 184(\base)
|
||||
sdc1 $f22, \offset + 176(\base)
|
||||
sdc1 $f21, \offset + 168(\base)
|
||||
sdc1 $f20, \offset + 160(\base)
|
||||
sdc1 $f19, \offset + 152(\base)
|
||||
sdc1 $f18, \offset + 144(\base)
|
||||
sdc1 $f17, \offset + 136(\base)
|
||||
sdc1 $f16, \offset + 128(\base)
|
||||
sdc1 $f15, \offset + 120(\base)
|
||||
sdc1 $f14, \offset + 112(\base)
|
||||
sdc1 $f13, \offset + 104(\base)
|
||||
sdc1 $f12, \offset + 96(\base)
|
||||
sdc1 $f11, \offset + 88(\base)
|
||||
sdc1 $f10, \offset + 80(\base)
|
||||
sdc1 $f9, \offset + 72(\base)
|
||||
sdc1 $f8, \offset + 64(\base)
|
||||
sdc1 $f7, \offset + 56(\base)
|
||||
sdc1 $f6, \offset + 48(\base)
|
||||
sdc1 $f5, \offset + 40(\base)
|
||||
sdc1 $f4, \offset + 32(\base)
|
||||
sdc1 $f3, \offset + 24(\base)
|
||||
sdc1 $f2, \offset + 16(\base)
|
||||
sdc1 $f1, \offset + 8(\base)
|
||||
sdc1 $f0, \offset + 0(\base)
|
||||
|
||||
sdc1 $f31, \ offset + 248 ( \ base )
|
||||
sdc1 $f30, \ offset + 240 ( \ base )
|
||||
sdc1 $f29, \ offset + 232 ( \ base )
|
||||
sdc1 $f28, \ offset + 224 ( \ base )
|
||||
sdc1 $f27, \ offset + 216 ( \ base )
|
||||
sdc1 $f26, \ offset + 208 ( \ base )
|
||||
sdc1 $f25, \ offset + 200 ( \ base )
|
||||
sdc1 $f24, \ offset + 192 ( \ base )
|
||||
sdc1 $f23, \ offset + 184 ( \ base )
|
||||
sdc1 $f22, \ offset + 176 ( \ base )
|
||||
sdc1 $f21, \ offset + 168 ( \ base )
|
||||
sdc1 $f20, \ offset + 160 ( \ base )
|
||||
sdc1 $f19, \ offset + 152 ( \ base )
|
||||
sdc1 $f18, \ offset + 144 ( \ base )
|
||||
sdc1 $f17, \ offset + 136 ( \ base )
|
||||
sdc1 $f16, \ offset + 128 ( \ base )
|
||||
sdc1 $f15, \ offset + 120 ( \ base )
|
||||
sdc1 $f14, \ offset + 112 ( \ base )
|
||||
sdc1 $f13, \ offset + 104 ( \ base )
|
||||
sdc1 $f12, \ offset + 96 ( \ base )
|
||||
sdc1 $f11, \ offset + 88 ( \ base )
|
||||
sdc1 $f10, \ offset + 80 ( \ base )
|
||||
sdc1 $f9, \ offset + 72 ( \ base )
|
||||
sdc1 $f8, \ offset + 64 ( \ base )
|
||||
sdc1 $f7, \ offset + 56 ( \ base )
|
||||
sdc1 $f6, \ offset + 48 ( \ base )
|
||||
sdc1 $f5, \ offset + 40 ( \ base )
|
||||
sdc1 $f4, \ offset + 32 ( \ base )
|
||||
sdc1 $f3, \ offset + 24 ( \ base )
|
||||
sdc1 $f2, \ offset + 16 ( \ base )
|
||||
sdc1 $f1, \ offset + 8 ( \ base )
|
||||
sdc1 $f0, \ offset + 0 ( \ base )
|
||||
|
||||
.endm
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portLOAD_FPU_REGS offset, base
|
||||
.macro portLOAD_FPU_REGS offset, base
|
||||
/* Macro to assist with loading just the FPU registers from the
|
||||
* specified address and base offset, offset is a constant,
|
||||
* base is the base pointer register */
|
||||
|
||||
/* Macro to assist with loading just the FPU registers from the
|
||||
* specified address and base offset, offset is a constant,
|
||||
* base is the base pointer register */
|
||||
ldc1 $f0, \offset + 0(\base)
|
||||
ldc1 $f1, \offset + 8(\base)
|
||||
ldc1 $f2, \offset + 16(\base)
|
||||
ldc1 $f3, \offset + 24(\base)
|
||||
ldc1 $f4, \offset + 32(\base)
|
||||
ldc1 $f5, \offset + 40(\base)
|
||||
ldc1 $f6, \offset + 48(\base)
|
||||
ldc1 $f7, \offset + 56(\base)
|
||||
ldc1 $f8, \offset + 64(\base)
|
||||
ldc1 $f9, \offset + 72(\base)
|
||||
ldc1 $f10, \offset + 80(\base)
|
||||
ldc1 $f11, \offset + 88(\base)
|
||||
ldc1 $f12, \offset + 96(\base)
|
||||
ldc1 $f13, \offset + 104(\base)
|
||||
ldc1 $f14, \offset + 112(\base)
|
||||
ldc1 $f15, \offset + 120(\base)
|
||||
ldc1 $f16, \offset + 128(\base)
|
||||
ldc1 $f17, \offset + 136(\base)
|
||||
ldc1 $f18, \offset + 144(\base)
|
||||
ldc1 $f19, \offset + 152(\base)
|
||||
ldc1 $f20, \offset + 160(\base)
|
||||
ldc1 $f21, \offset + 168(\base)
|
||||
ldc1 $f22, \offset + 176(\base)
|
||||
ldc1 $f23, \offset + 184(\base)
|
||||
ldc1 $f24, \offset + 192(\base)
|
||||
ldc1 $f25, \offset + 200(\base)
|
||||
ldc1 $f26, \offset + 208(\base)
|
||||
ldc1 $f27, \offset + 216(\base)
|
||||
ldc1 $f28, \offset + 224(\base)
|
||||
ldc1 $f29, \offset + 232(\base)
|
||||
ldc1 $f30, \offset + 240(\base)
|
||||
ldc1 $f31, \offset + 248(\base)
|
||||
|
||||
ldc1 $f0, \ offset + 0 ( \ base )
|
||||
ldc1 $f1, \ offset + 8 ( \ base )
|
||||
ldc1 $f2, \ offset + 16 ( \ base )
|
||||
ldc1 $f3, \ offset + 24 ( \ base )
|
||||
ldc1 $f4, \ offset + 32 ( \ base )
|
||||
ldc1 $f5, \ offset + 40 ( \ base )
|
||||
ldc1 $f6, \ offset + 48 ( \ base )
|
||||
ldc1 $f7, \ offset + 56 ( \ base )
|
||||
ldc1 $f8, \ offset + 64 ( \ base )
|
||||
ldc1 $f9, \ offset + 72 ( \ base )
|
||||
ldc1 $f10, \ offset + 80 ( \ base )
|
||||
ldc1 $f11, \ offset + 88 ( \ base )
|
||||
ldc1 $f12, \ offset + 96 ( \ base )
|
||||
ldc1 $f13, \ offset + 104 ( \ base )
|
||||
ldc1 $f14, \ offset + 112 ( \ base )
|
||||
ldc1 $f15, \ offset + 120 ( \ base )
|
||||
ldc1 $f16, \ offset + 128 ( \ base )
|
||||
ldc1 $f17, \ offset + 136 ( \ base )
|
||||
ldc1 $f18, \ offset + 144 ( \ base )
|
||||
ldc1 $f19, \ offset + 152 ( \ base )
|
||||
ldc1 $f20, \ offset + 160 ( \ base )
|
||||
ldc1 $f21, \ offset + 168 ( \ base )
|
||||
ldc1 $f22, \ offset + 176 ( \ base )
|
||||
ldc1 $f23, \ offset + 184 ( \ base )
|
||||
ldc1 $f24, \ offset + 192 ( \ base )
|
||||
ldc1 $f25, \ offset + 200 ( \ base )
|
||||
ldc1 $f26, \ offset + 208 ( \ base )
|
||||
ldc1 $f27, \ offset + 216 ( \ base )
|
||||
ldc1 $f28, \ offset + 224 ( \ base )
|
||||
ldc1 $f29, \ offset + 232 ( \ base )
|
||||
ldc1 $f30, \ offset + 240 ( \ base )
|
||||
ldc1 $f31, \ offset + 248 ( \ base )
|
||||
|
||||
.endm
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portSAVE_CONTEXT
|
||||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
* manipulated, and the cause and EPC registers so their original values are
|
||||
* captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
/* Make room for the context. First save the current status so it can be
|
||||
manipulated, and the cause and EPC registers so their original values are
|
||||
captured. */
|
||||
mfc0 k0, _CP0_CAUSE
|
||||
addiu sp, sp, -portCONTEXT_SIZE
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* Test if we are already using the system stack. Only tasks may use the
|
||||
FPU so if we are already in a nested interrupt then the FPU context does
|
||||
not require saving. */
|
||||
la k1, uxInterruptNesting
|
||||
lw k1, 0(k1)
|
||||
bne k1, zero, 2f
|
||||
nop
|
||||
|
||||
/* Test if we are already using the system stack. Only tasks may use the
|
||||
* FPU so if we are already in a nested interrupt then the FPU context does
|
||||
* not require saving. */
|
||||
la k1, uxInterruptNesting
|
||||
lw k1, 0 ( k1 )
|
||||
bne k1, zero, 2f
|
||||
nop
|
||||
/* Test if the current task needs the FPU context saving. */
|
||||
la k1, ulTaskHasFPUContext
|
||||
lw k1, 0(k1)
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* Test if the current task needs the FPU context saving. */
|
||||
la k1, ulTaskHasFPUContext
|
||||
lw k1, 0 ( k1 )
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
/* Adjust the stack to account for the additional FPU context.*/
|
||||
addiu sp, sp, -portFPU_CONTEXT_SIZE
|
||||
|
||||
/* Adjust the stack to account for the additional FPU context.*/
|
||||
addiu sp, sp, -portFPU_CONTEXT_SIZE
|
||||
1:
|
||||
/* Save the ulTaskHasFPUContext flag. */
|
||||
sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
|
||||
|
||||
1 :
|
||||
/* Save the ulTaskHasFPUContext flag. */
|
||||
sw k1, portTASK_HAS_FPU_STACK_LOCATION( sp )
|
||||
2:
|
||||
#endif
|
||||
|
||||
2 :
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
mfc0 k1, _CP0_STATUS
|
||||
|
||||
mfc0 k1, _CP0_STATUS
|
||||
/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
|
||||
should maintain the values of these registers across the ISR. */
|
||||
sw s7, 48(sp)
|
||||
sw s6, 44(sp)
|
||||
sw s5, 40(sp)
|
||||
sw k1, portSTATUS_STACK_LOCATION(sp)
|
||||
|
||||
/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
|
||||
* should maintain the values of these registers across the ISR. */
|
||||
sw s7, 48 ( sp )
|
||||
sw s6, 44 ( sp )
|
||||
sw s5, 40 ( sp )
|
||||
sw k1, portSTATUS_STACK_LOCATION( sp )
|
||||
/* Prepare to enable interrupts above the current priority. */
|
||||
srl k0, k0, 0xa
|
||||
ins k1, k0, 10, 7
|
||||
srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
ins k1, k0, 18, 1
|
||||
ins k1, zero, 1, 4
|
||||
|
||||
/* Prepare to enable interrupts above the current priority. */
|
||||
srl k0, k0, 0xa
|
||||
ins k1, k0, 10, 7
|
||||
srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
|
||||
ins k1, k0, 18, 1
|
||||
ins k1, zero, 1, 4
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
|
||||
/* s5 is used as the frame pointer. */
|
||||
add s5, zero, sp
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, (k0)
|
||||
|
||||
/* Check the nesting count value. */
|
||||
la k0, uxInterruptNesting
|
||||
lw s6, ( k0 )
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* If the nesting count is 0 then swap to the the system stack, otherwise
|
||||
* the system stack is already being used. */
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, (sp)
|
||||
|
||||
/* Swap to the system stack. */
|
||||
la sp, xISRStackTop
|
||||
lw sp, ( sp )
|
||||
/* Increment and save the nesting count. */
|
||||
1: addiu s6, s6, 1
|
||||
sw s6, 0(k0)
|
||||
|
||||
/* Increment and save the nesting count. */
|
||||
1 : addiu s6, s6, 1
|
||||
sw s6, 0 ( k0 )
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. No other s registers need be
|
||||
saved. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
* here as it now contains the EPC value. No other s registers need be
|
||||
* saved. */
|
||||
sw ra, 120 ( s5 )
|
||||
sw s8, 116 ( s5 )
|
||||
sw t9, 112 ( s5 )
|
||||
sw t8, 108 ( s5 )
|
||||
sw t7, 104 ( s5 )
|
||||
sw t6, 100 ( s5 )
|
||||
sw t5, 96 ( s5 )
|
||||
sw t4, 92 ( s5 )
|
||||
sw t3, 88 ( s5 )
|
||||
sw t2, 84 ( s5 )
|
||||
sw t1, 80 ( s5 )
|
||||
sw t0, 76 ( s5 )
|
||||
sw a3, 72 ( s5 )
|
||||
sw a2, 68 ( s5 )
|
||||
sw a1, 64 ( s5 )
|
||||
sw a0, 60 ( s5 )
|
||||
sw v1, 56 ( s5 )
|
||||
sw v0, 52 ( s5 )
|
||||
sw s6, portEPC_STACK_LOCATION( s5 )
|
||||
sw $1, 16 ( s5 )
|
||||
/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
|
||||
scratch register. */
|
||||
mfhi s6, $ac1
|
||||
sw s6, 128(s5)
|
||||
mflo s6, $ac1
|
||||
sw s6, 124(s5)
|
||||
|
||||
/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
|
||||
* scratch register. */
|
||||
mfhi s6, $ac1
|
||||
sw s6, 128 ( s5 )
|
||||
mflo s6, $ac1
|
||||
sw s6, 124 ( s5 )
|
||||
mfhi s6, $ac2
|
||||
sw s6, 136(s5)
|
||||
mflo s6, $ac2
|
||||
sw s6, 132(s5)
|
||||
|
||||
mfhi s6, $ac2
|
||||
sw s6, 136 ( s5 )
|
||||
mflo s6, $ac2
|
||||
sw s6, 132 ( s5 )
|
||||
mfhi s6, $ac3
|
||||
sw s6, 144(s5)
|
||||
mflo s6, $ac3
|
||||
sw s6, 140(s5)
|
||||
|
||||
mfhi s6, $ac3
|
||||
sw s6, 144 ( s5 )
|
||||
mflo s6, $ac3
|
||||
sw s6, 140 ( s5 )
|
||||
/* Save the DSP Control register */
|
||||
rddsp s6
|
||||
sw s6, 148(s5)
|
||||
|
||||
/* Save the DSP Control register */
|
||||
rddsp s6
|
||||
sw s6, 148 ( s5 )
|
||||
/* ac0 is done separately to match the MX port. */
|
||||
mfhi s6, $ac0
|
||||
sw s6, 12(s5)
|
||||
mflo s6, $ac0
|
||||
sw s6, 8(s5)
|
||||
|
||||
/* ac0 is done separately to match the MX port. */
|
||||
mfhi s6, $ac0
|
||||
sw s6, 12 ( s5 )
|
||||
mflo s6, $ac0
|
||||
sw s6, 8 ( s5 )
|
||||
/* Save the FPU context if the nesting count was zero. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, 0(s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the FPU context if the nesting count was zero. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, 0 ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Test if the current task needs the FPU context saving. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Test if the current task needs the FPU context saving. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
/* Save the FPU registers. */
|
||||
portSAVE_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
|
||||
/* Save the FPU registers. */
|
||||
portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
/* Save the FPU status register */
|
||||
cfc1 s6, $f31
|
||||
sw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
|
||||
/* Save the FPU status register */
|
||||
cfc1 s6, $f31
|
||||
sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
|
||||
|
||||
1 :
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
1:
|
||||
#endif
|
||||
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
/* Update the task stack pointer value if nesting is zero. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, ( s6 )
|
||||
1 :
|
||||
.endm
|
||||
/* Save the stack pointer. */
|
||||
la s6, uxSavedTaskStackPointer
|
||||
sw s5, (s6)
|
||||
1:
|
||||
.endm
|
||||
|
||||
/******************************************************************/
|
||||
.macro portRESTORE_CONTEXT
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
* nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, ( s6 )
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, ( s6 )
|
||||
/* Restore the stack pointer from the TCB. This is only done if the
|
||||
nesting count is 1. */
|
||||
la s6, uxInterruptNesting
|
||||
lw s6, (s6)
|
||||
addiu s6, s6, -1
|
||||
bne s6, zero, 1f
|
||||
nop
|
||||
la s6, uxSavedTaskStackPointer
|
||||
lw s5, (s6)
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* Restore the FPU context if required. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
/* Restore the FPU registers. */
|
||||
portLOAD_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* Restore the FPU context if required. */
|
||||
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
|
||||
beq s6, zero, 1f
|
||||
nop
|
||||
|
||||
/* Restore the FPU status register. */
|
||||
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
|
||||
ctc1 s6, $f31
|
||||
#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
/* Restore the FPU registers. */
|
||||
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
|
||||
|
||||
1 :
|
||||
/* Restore the FPU status register. */
|
||||
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
|
||||
ctc1 s6, $f31
|
||||
#endif
|
||||
|
||||
/* Restore the context. */
|
||||
lw s6, 128 ( s5 )
|
||||
mthi s6, $ac1
|
||||
lw s6, 124 ( s5 )
|
||||
mtlo s6, $ac1
|
||||
1:
|
||||
|
||||
lw s6, 136 ( s5 )
|
||||
mthi s6, $ac2
|
||||
lw s6, 132 ( s5 )
|
||||
mtlo s6, $ac2
|
||||
/* Restore the context. */
|
||||
lw s6, 128(s5)
|
||||
mthi s6, $ac1
|
||||
lw s6, 124(s5)
|
||||
mtlo s6, $ac1
|
||||
|
||||
lw s6, 144 ( s5 )
|
||||
mthi s6, $ac3
|
||||
lw s6, 140 ( s5 )
|
||||
mtlo s6, $ac3
|
||||
lw s6, 136(s5)
|
||||
mthi s6, $ac2
|
||||
lw s6, 132(s5)
|
||||
mtlo s6, $ac2
|
||||
|
||||
/* Restore DSPControl. */
|
||||
lw s6, 148 ( s5 )
|
||||
wrdsp s6
|
||||
lw s6, 144(s5)
|
||||
mthi s6, $ac3
|
||||
lw s6, 140(s5)
|
||||
mtlo s6, $ac3
|
||||
|
||||
lw s6, 8 ( s5 )
|
||||
mtlo s6, $ac0
|
||||
lw s6, 12 ( s5 )
|
||||
mthi s6, $ac0
|
||||
lw $1, 16 ( s5 )
|
||||
/* Restore DSPControl. */
|
||||
lw s6, 148(s5)
|
||||
wrdsp s6
|
||||
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
* as part of the interrupt context. */
|
||||
lw s7, 48 ( s5 )
|
||||
lw s6, 44 ( s5 )
|
||||
lw v0, 52 ( s5 )
|
||||
lw v1, 56 ( s5 )
|
||||
lw a0, 60 ( s5 )
|
||||
lw a1, 64 ( s5 )
|
||||
lw a2, 68 ( s5 )
|
||||
lw a3, 72 ( s5 )
|
||||
lw t0, 76 ( s5 )
|
||||
lw t1, 80 ( s5 )
|
||||
lw t2, 84 ( s5 )
|
||||
lw t3, 88 ( s5 )
|
||||
lw t4, 92 ( s5 )
|
||||
lw t5, 96 ( s5 )
|
||||
lw t6, 100 ( s5 )
|
||||
lw t7, 104 ( s5 )
|
||||
lw t8, 108 ( s5 )
|
||||
lw t9, 112 ( s5 )
|
||||
lw s8, 116 ( s5 )
|
||||
lw ra, 120 ( s5 )
|
||||
lw s6, 8(s5)
|
||||
mtlo s6, $ac0
|
||||
lw s6, 12(s5)
|
||||
mthi s6, $ac0
|
||||
lw $1, 16(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
/* s6 is loaded as it was used as a scratch register and therefore saved
|
||||
as part of the interrupt context. */
|
||||
lw s7, 48(s5)
|
||||
lw s6, 44(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, ( k0 )
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0 ( k0 )
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
ehb
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* If the nesting count is now zero then the FPU context may be restored. */
|
||||
bne k1, zero, 1f
|
||||
nop
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, (k0)
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0(k0)
|
||||
|
||||
/* Restore the value of ulTaskHasFPUContext */
|
||||
la k0, ulTaskHasFPUContext
|
||||
lw k1, 0 ( s5 )
|
||||
sw k1, 0 ( k0 )
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
/* If the nesting count is now zero then the FPU context may be restored. */
|
||||
bne k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* If the task does not have an FPU context then adjust the stack normally. */
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
/* Restore the value of ulTaskHasFPUContext */
|
||||
la k0, ulTaskHasFPUContext
|
||||
lw k1, 0(s5)
|
||||
sw k1, 0(k0)
|
||||
|
||||
/* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
/* If the task does not have an FPU context then adjust the stack normally. */
|
||||
beq k1, zero, 1f
|
||||
nop
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
/* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
/* Adjust the stack pointer to remove the FPU context */
|
||||
addiu sp, sp, portFPU_CONTEXT_SIZE
|
||||
beq zero, zero, 2f
|
||||
nop
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
1 : /* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
/* Adjust the stack pointer to remove the FPU context */
|
||||
addiu sp, sp, portFPU_CONTEXT_SIZE
|
||||
beq zero, zero, 2f
|
||||
nop
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
1: /* Restore the STATUS and EPC registers */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
2 : /* Adjust the stack pointer */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
||||
2: /* Adjust the stack pointer */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
/* Restore the frame when there is no hardware FP support. */
|
||||
lw k0, portSTATUS_STACK_LOCATION( s5 )
|
||||
lw k1, portEPC_STACK_LOCATION( s5 )
|
||||
#else
|
||||
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
* restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40 ( sp )
|
||||
/* Restore the frame when there is no hardware FP support. */
|
||||
lw k0, portSTATUS_STACK_LOCATION(s5)
|
||||
lw k1, portEPC_STACK_LOCATION(s5)
|
||||
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
/* Leave the stack in its original state. First load sp from s5, then
|
||||
restore s5 from the stack. */
|
||||
add sp, zero, s5
|
||||
lw s5, 40(sp)
|
||||
|
||||
#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
mtc0 k0, _CP0_STATUS
|
||||
mtc0 k1, _CP0_EPC
|
||||
ehb
|
||||
eret
|
||||
nop
|
||||
|
||||
.endm
|
||||
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@
|
|||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Implementation of functions defined in portable.h for the PIC32MZ port.
|
||||
*----------------------------------------------------------*/
|
||||
* Implementation of functions defined in portable.h for the PIC32MZ port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Microchip specific headers. */
|
||||
#include <xc.h>
|
||||
|
|
@ -39,101 +39,99 @@
|
|||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#if !defined( __PIC32MZ__ )
|
||||
#if !defined(__PIC32MZ__)
|
||||
#error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings.
|
||||
#endif
|
||||
|
||||
#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
|
||||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
|
||||
#endif
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
#define portTIMER_PRESCALE 8
|
||||
#define portPRESCALE_BITS 1
|
||||
|
||||
/* Bits within various registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
|
||||
#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
|
||||
#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
|
||||
#define portIE_BIT ( 0x00000001 )
|
||||
#define portEXL_BIT ( 0x00000002 )
|
||||
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
|
||||
#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
|
||||
#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
|
||||
|
||||
/* Bits within the CAUSE register. */
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
#define portCORE_SW_0 ( 0x00000100 )
|
||||
#define portCORE_SW_1 ( 0x00000200 )
|
||||
|
||||
/* The EXL bit is set to ensure interrupts do not occur while the context of
|
||||
* the first task is being restored. */
|
||||
the first task is being restored. */
|
||||
#if ( __mips_hard_float == 1 )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
|
||||
#else
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
|
||||
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
|
||||
#endif
|
||||
|
||||
/* The initial value to store into the FPU status and control register. This is
|
||||
* only used on parts that support a hardware FPU. */
|
||||
#define portINITIAL_FPSCR ( 0x1000000 ) /* High perf on denormal ops */
|
||||
only used on parts that support a hardware FPU. */
|
||||
#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
|
||||
|
||||
|
||||
/*
|
||||
* By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
* override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
* to generate the tick interrupt. For example, when timer 1 is used then
|
||||
* configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
* configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
* 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
* timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
* used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
* IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
By default port.c generates its tick interrupt from TIMER1. The user can
|
||||
override this behaviour by:
|
||||
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
which is the function that configures the timer. The function is defined
|
||||
as a weak symbol in this file so if the same function name is used in the
|
||||
application code then the version in the application code will be linked
|
||||
into the application in preference to the version defined in this file.
|
||||
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
|
||||
to generate the tick interrupt. For example, when timer 1 is used then
|
||||
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
|
||||
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
|
||||
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
|
||||
timer used to generate the tick interrupt. For example, when timer 1 is
|
||||
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
|
||||
IFS0CLR = _IFS0_T1IF_MASK.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
* debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -146,25 +144,25 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
* decremented to 0 when the first task starts. */
|
||||
decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
UBaseType_t uxSavedTaskStackPointer = 0;
|
||||
|
||||
/* The stack used by interrupt service routines that cause a context switch. */
|
||||
__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
* the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
* is required to allow double word floating point stack pushes generated by the
|
||||
* compiler. */
|
||||
the callers stack, as some functions seem to want to do this. 8 byte alignment
|
||||
is required to allow double word floating point stack pushes generated by the
|
||||
compiler. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
|
||||
|
||||
/* Saved as part of the task context. Set to pdFALSE if the task does not
|
||||
* require an FPU context. */
|
||||
require an FPU context. */
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
uint32_t ulTaskHasFPUContext = 0;
|
||||
uint32_t ulTaskHasFPUContext = 0;
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -172,58 +170,53 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Ensure 8 byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
pxTopOfStack--;
|
||||
/* Ensure 8 byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) 0x00000000; /* DSPControl */
|
||||
pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
|
||||
*pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
|
||||
pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = ( StackType_t ) pdFALSE; /*by default disable FPU context save on parts with FPU */
|
||||
*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
|
||||
|
||||
return pxTopOfStack;
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -236,141 +229,144 @@ static void prvTaskExitError( void )
|
|||
* vector number. When Timer 1 is used the vector number is defined as
|
||||
* _TIMER_1_VECTOR.
|
||||
*/
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1UL;
|
||||
const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
|
||||
|
||||
T1CON = 0x0000;
|
||||
T1CONbits.TCKPS = portPRESCALE_BITS;
|
||||
PR1 = ulCompareMatch;
|
||||
IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
T1CON = 0x0000;
|
||||
T1CONbits.TCKPS = portPRESCALE_BITS;
|
||||
PR1 = ulCompareMatch;
|
||||
IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
|
||||
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
/* Clear the interrupt as a starting condition. */
|
||||
IFS0bits.T1IF = 0;
|
||||
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
/* Enable the interrupt. */
|
||||
IEC0bits.T1IE = 1;
|
||||
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
/* Start the timer. */
|
||||
T1CONbits.TON = 1;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
void vPortEndScheduler(void)
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void * pxCurrentTCB;
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
/* Fill the ISR stack to make it easy to asses how much is being used. */
|
||||
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||
}
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
IFS0CLR = _IFS0_CS0IF_MASK;
|
||||
/* Clear the software interrupt flag. */
|
||||
IFS0CLR = _IFS0_CS0IF_MASK;
|
||||
|
||||
/* Set software timer priority. */
|
||||
IPC0CLR = _IPC0_CS0IP_MASK;
|
||||
IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
|
||||
/* Set software timer priority. */
|
||||
IPC0CLR = _IPC0_CS0IP_MASK;
|
||||
IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
IEC0CLR = _IEC0_CS0IE_MASK;
|
||||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
/* Enable software interrupt. */
|
||||
IEC0CLR = _IEC0_CS0IE_MASK;
|
||||
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
* disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
/* Setup the timer to generate the tick. Interrupts will have been
|
||||
disabled by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
* Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
/* Kick off the highest priority task that has been created so far.
|
||||
Its stack location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
UBaseType_t uxSavedStatus;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
_CP0_BIS_CAUSE( portCORE_SW_0 );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Pend a context switch. */
|
||||
_CP0_BIS_CAUSE( portCORE_SW_0 );
|
||||
}
|
||||
}
|
||||
vPortClearInterruptMaskFromISR( uxSavedStatus );
|
||||
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
/* Look for the ISR stack getting near or past its limit. */
|
||||
portCHECK_ISR_STACK();
|
||||
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
/* Clear timer interrupt. */
|
||||
configCLEAR_TICK_TIMER_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
__builtin_disable_interrupts();
|
||||
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
return uxSavedStatusRegister;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
|
||||
{
|
||||
_CP0_SET_STATUS( uxSavedStatusRegister );
|
||||
_CP0_SET_STATUS( uxSavedStatusRegister );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
|
||||
void vPortTaskUsesFPU( void )
|
||||
{
|
||||
extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
|
||||
void vPortTaskUsesFPU(void)
|
||||
{
|
||||
extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
|
||||
|
||||
portENTER_CRITICAL();
|
||||
portENTER_CRITICAL();
|
||||
|
||||
/* Initialise the floating point status register. */
|
||||
vPortInitialiseFPSCR( portINITIAL_FPSCR );
|
||||
/* Initialise the floating point status register. */
|
||||
vPortInitialiseFPSCR(portINITIAL_FPSCR);
|
||||
|
||||
/* A task is registering the fact that it needs a FPU context. Set the
|
||||
* FPU flag (saved as part of the task context). */
|
||||
ulTaskHasFPUContext = pdTRUE;
|
||||
/* A task is registering the fact that it needs a FPU context. Set the
|
||||
FPU flag (saved as part of the task context). */
|
||||
ulTaskHasFPUContext = pdTRUE;
|
||||
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
|
||||
#endif /* __mips_hard_float == 1 */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -26,14 +26,14 @@
|
|||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
/* System include files */
|
||||
#include <xc.h>
|
||||
#include <xc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -46,171 +46,170 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
* never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
\
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
\
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = _CP0_GET_STATUS(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
_CP0_SET_STATUS( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
#error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
|
||||
#endif
|
||||
#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
#error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
|
||||
#endif
|
||||
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
void vPortTaskUsesFPU( void );
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
#endif
|
||||
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
|
||||
void vPortTaskUsesFPU( void );
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
#endif
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
\
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = _CP0_GET_CAUSE(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
_CP0_SET_CAUSE( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
|
||||
if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
|
||||
{ \
|
||||
portYIELD(); \
|
||||
}
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
#ifdef __DEBUG
|
||||
#define portREMOVE_STATIC_QUALIFIER
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue