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Style: Revert uncrustify for portable directories (#122)
* Style: revert uncrustify portable directories * Style: Uncrustify Some Portable files Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
This commit is contained in:
alfred gedeon
GitHub
parent
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commit
86653e2a1f
273 changed files with 64802 additions and 65931 deletions
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@ -360,14 +360,14 @@ static void prvRestoreContextOfFirstTask( void )
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" str r3, [r2] \n"/* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" \n"
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#if ( portTOTAL_NUM_REGIONS == 16 )
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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#endif /* portTOTAL_NUM_REGIONS == 16. */
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" \n"
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" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
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@ -584,14 +584,14 @@ void xPortPendSVHandler( void )
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" str r3, [r2] \n"/* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" \n"
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#if ( portTOTAL_NUM_REGIONS == 16 )
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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#endif /* portTOTAL_NUM_REGIONS == 16. */
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" \n"
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" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
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@ -941,10 +941,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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* be set to a value equal to or numerically *higher* than
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* configMAX_SYSCALL_INTERRUPT_PRIORITY.
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*
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* Interrupts that use the FreeRTOS API must not be left at their
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* default priority of zero as that is the highest possible priority,
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* Interrupts that use the FreeRTOS API must not be left at their
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* default priority of zero as that is the highest possible priority,
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* which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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* and therefore also guaranteed to be invalid.
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* and therefore also guaranteed to be invalid.
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*
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* FreeRTOS maintains separate thread and ISR API functions to ensure
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* interrupt entry is as fast and simple as possible.
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@ -27,11 +27,14 @@
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/*-----------------------------------------------------------
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* Port specific definitions.
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@ -44,169 +47,170 @@
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if ( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#if ( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#endif
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#define portTICK_TYPE_IS_ATOMIC 1
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#endif
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/*-----------------------------------------------------------*/
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/* MPU specific constants. */
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#define portUSING_MPU_WRAPPERS 1
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#define portUSING_MPU_WRAPPERS 1
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
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#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
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/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
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* Register (RASR). */
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#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
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#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
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#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
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#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
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* Register (RASR). */
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#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
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#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
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/*
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* The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
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* memory type, and where necessary the cacheable and shareable properties
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* of the memory region.
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*
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* The TEX, C, and B bits together indicate the memory type of the region,
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* and:
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* - For Normal memory, the cacheable properties of the region.
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* - For Device memory, whether the region is shareable.
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*
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* For Normal memory regions, the S bit indicates whether the region is
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* shareable. For Strongly-ordered and Device memory, the S bit is ignored.
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*
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* See the following two tables for setting TEX, S, C and B bits for
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* unprivileged flash, privileged flash and privileged RAM regions.
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*
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 1 | Device | Shared device | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 0 | Device | Non-shared device | Not shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 1 | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 011 | X | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
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| | | | | outer cacheability rules that must be exported on the | |
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| | | | | bus. See the table below for the cacheability policy | |
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| | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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+-----------------------------------------+----------------------------------------+
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| AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
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+-----------------------------------------+----------------------------------------+
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| 00 | Non-cacheable |
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+-----------------------------------------+----------------------------------------+
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| 01 | Write-back, write and read allocate |
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+-----------------------------------------+----------------------------------------+
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| 10 | Write-through, no write allocate |
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+-----------------------------------------+----------------------------------------+
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| 11 | Write-back, no write allocate |
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+-----------------------------------------+----------------------------------------+
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*/
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/*
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* The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
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* memory type, and where necessary the cacheable and shareable properties
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* of the memory region.
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*
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* The TEX, C, and B bits together indicate the memory type of the region,
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* and:
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* - For Normal memory, the cacheable properties of the region.
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* - For Device memory, whether the region is shareable.
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*
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* For Normal memory regions, the S bit indicates whether the region is
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* shareable. For Strongly-ordered and Device memory, the S bit is ignored.
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*
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* See the following two tables for setting TEX, S, C and B bits for
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* unprivileged flash, privileged flash and privileged RAM regions.
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*
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 1 | Device | Shared device | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 0 | Device | Non-shared device | Not shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 1 | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 011 | X | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
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| | | | | outer cacheability rules that must be exported on the | |
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| | | | | bus. See the table below for the cacheability policy | |
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| | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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|
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+-----------------------------------------+----------------------------------------+
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| AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
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+-----------------------------------------+----------------------------------------+
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| 00 | Non-cacheable |
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+-----------------------------------------+----------------------------------------+
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| 01 | Write-back, write and read allocate |
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+-----------------------------------------+----------------------------------------+
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| 10 | Write-through, no write allocate |
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+-----------------------------------------+----------------------------------------+
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| 11 | Write-back, no write allocate |
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+-----------------------------------------+----------------------------------------+
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*/
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
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* region. */
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#ifndef configTEX_S_C_B_FLASH
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_FLASH ( 0x07UL )
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#endif
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
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* region. */
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#ifndef configTEX_S_C_B_FLASH
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_FLASH ( 0x07UL )
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#endif
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
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* region. */
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#ifndef configTEX_S_C_B_SRAM
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_SRAM ( 0x07UL )
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#endif
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
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* region. */
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#ifndef configTEX_S_C_B_SRAM
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_SRAM ( 0x07UL )
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#endif
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#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
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#define portPRIVILEGED_FLASH_REGION ( 1UL )
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#define portPRIVILEGED_RAM_REGION ( 2UL )
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#define portGENERAL_PERIPHERALS_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
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#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
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#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
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#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
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#define portPRIVILEGED_FLASH_REGION ( 1UL )
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#define portPRIVILEGED_RAM_REGION ( 2UL )
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#define portGENERAL_PERIPHERALS_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
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#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
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#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
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#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
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#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
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typedef struct MPU_REGION_REGISTERS
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{
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uint32_t ulRegionBaseAddress;
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uint32_t ulRegionAttribute;
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} xMPU_REGION_REGISTERS;
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typedef struct MPU_REGION_REGISTERS
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{
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uint32_t ulRegionBaseAddress;
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uint32_t ulRegionAttribute;
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} xMPU_REGION_REGISTERS;
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/* Plus 1 to create space for the stack region. */
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typedef struct MPU_SETTINGS
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||||
{
|
||||
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
|
||||
} xMPU_SETTINGS;
|
||||
typedef struct MPU_SETTINGS
|
||||
{
|
||||
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
|
||||
} xMPU_SETTINGS;
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* SVC numbers for various services. */
|
||||
#define portSVC_START_SCHEDULER 0
|
||||
#define portSVC_YIELD 1
|
||||
#define portSVC_RAISE_PRIVILEGE 2
|
||||
#define portSVC_START_SCHEDULER 0
|
||||
#define portSVC_YIELD 1
|
||||
#define portSVC_RAISE_PRIVILEGE 2
|
||||
|
||||
/* Scheduler utilities. */
|
||||
|
||||
#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
|
||||
#define portYIELD_WITHIN_API() \
|
||||
#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
|
||||
#define portYIELD_WITHIN_API() \
|
||||
{ \
|
||||
/* Set a PendSV to request a context switch. */ \
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
|
|
@ -217,178 +221,181 @@
|
|||
__asm volatile ( "isb" ); \
|
||||
}
|
||||
|
||||
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
|
||||
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
|
||||
#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
|
||||
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
|
||||
#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
* not necessary for to use this port. They are defined so the common demo files
|
||||
* (which build with all the ports) will build. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Generic helper function. */
|
||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint8_t ucReturn;
|
||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint8_t ucReturn;
|
||||
|
||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
||||
|
||||
return ucReturn;
|
||||
}
|
||||
return ucReturn;
|
||||
}
|
||||
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef configASSERT
|
||||
void vPortValidateInterruptPriority( void );
|
||||
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
|
||||
#endif
|
||||
#ifdef configASSERT
|
||||
void vPortValidateInterruptPriority( void );
|
||||
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
|
||||
#endif
|
||||
|
||||
/* portNOP() is not required by this port. */
|
||||
#define portNOP()
|
||||
#define portNOP()
|
||||
|
||||
#define portINLINE __inline
|
||||
#define portINLINE __inline
|
||||
|
||||
#ifndef portFORCE_INLINE
|
||||
#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
|
||||
#endif
|
||||
#ifndef portFORCE_INLINE
|
||||
#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
extern BaseType_t xIsPrivileged( void );
|
||||
extern void vResetPrivilege( void );
|
||||
extern BaseType_t xIsPrivileged( void );
|
||||
extern void vResetPrivilege( void );
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the processor is privileged.
|
||||
*
|
||||
* @return 1 if the processor is already privileged, 0 otherwise.
|
||||
*/
|
||||
#define portIS_PRIVILEGED() xIsPrivileged()
|
||||
#define portIS_PRIVILEGED() xIsPrivileged()
|
||||
|
||||
/**
|
||||
* @brief Raise an SVC request to raise privilege.
|
||||
*/
|
||||
#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
|
||||
#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
|
||||
|
||||
/**
|
||||
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
|
||||
* register.
|
||||
*/
|
||||
#define portRESET_PRIVILEGE() vResetPrivilege()
|
||||
#define portRESET_PRIVILEGE() vResetPrivilege()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
|
||||
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. */
|
||||
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
||||
|
||||
if( ulCurrentInterrupt == 0 )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. */
|
||||
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
||||
|
||||
if( ulCurrentInterrupt == 0 )
|
||||
{
|
||||
xReturn = pdFALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdTRUE;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
xReturn = pdFALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdTRUE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulNewBASEPRI;
|
||||
|
||||
__asm volatile
|
||||
(
|
||||
" mov %0, %1 \n"\
|
||||
" msr basepri, %0 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
}
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
||||
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulNewBASEPRI;
|
||||
|
||||
__asm volatile
|
||||
(
|
||||
" mrs %0, basepri \n"\
|
||||
" mov %1, %2 \n"\
|
||||
" msr basepri, %1 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
__asm volatile
|
||||
(
|
||||
" mov %0, %1 \n"\
|
||||
" msr basepri, %0 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
}
|
||||
|
||||
/* This return will not be reached but is necessary to prevent compiler
|
||||
* warnings. */
|
||||
return ulOriginalBASEPRI;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
|
||||
);
|
||||
}
|
||||
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
||||
{
|
||||
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
||||
|
||||
__asm volatile
|
||||
(
|
||||
" mrs %0, basepri \n"\
|
||||
" mov %1, %2 \n"\
|
||||
" msr basepri, %1 \n"\
|
||||
" isb \n"\
|
||||
" dsb \n"\
|
||||
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||||
);
|
||||
|
||||
/* This return will not be reached but is necessary to prevent compiler
|
||||
* warnings. */
|
||||
return ulOriginalBASEPRI;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
|
||||
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
|
||||
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
|
||||
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
|
||||
#endif
|
||||
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
|
||||
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
|
||||
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
|
||||
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/* *INDENT-ON* */
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue