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Style: Revert uncrustify for portable directories (#122)
* Style: revert uncrustify portable directories * Style: Uncrustify Some Portable files Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
This commit is contained in:
alfred gedeon
GitHub
parent
a6da1cd0ce
commit
86653e2a1f
273 changed files with 64802 additions and 65931 deletions
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@ -27,12 +27,12 @@
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM7 port.
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*
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in this file. The ISR routines, which can only be compiled
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* to ARM mode are contained in portISR.c.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the ARM7 port.
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*
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in this file. The ISR routines, which can only be compiled
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* to ARM mode are contained in portISR.c.
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*----------------------------------------------------------*/
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/* Standard includes. */
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@ -43,136 +43,134 @@
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#include "task.h"
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/* Constants required to setup the task context. */
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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/* Constants required to setup the tick ISR. */
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#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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#define portPRESCALE_VALUE 0x00
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#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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#define portPRESCALE_VALUE 0x00
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#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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/* Constants required to setup the VIC for the tick ISR. */
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#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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/*-----------------------------------------------------------*/
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/*
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* The scheduler can only be started from ARM mode, so
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* vPortISRStartFirstSTask() is defined in portISR.c.
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/*
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* The scheduler can only be started from ARM mode, so
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* vPortISRStartFirstSTask() is defined in portISR.c.
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*/
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extern void vPortISRStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been called.
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*
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* See header file for description.
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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StackType_t * pxOriginalTOS;
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StackType_t *pxOriginalTOS;
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pxOriginalTOS = pxTopOfStack;
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pxOriginalTOS = pxTopOfStack;
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/* To ensure asserts in tasks.c don't fail, although in this case the assert
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is not really required. */
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pxTopOfStack--;
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/* To ensure asserts in tasks.c don't fail, although in this case the assert
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* is not really required. */
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pxTopOfStack--;
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/* Setup the initial stack of the task. The stack is set exactly as
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expected by the portRESTORE_CONTEXT() macro. */
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. */
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/* First on the stack is the return address - which in this case is the
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start of the task. The offset is added to make the return address appear
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as it would within an IRQ ISR. */
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*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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/* First on the stack is the return address - which in this case is the
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* start of the task. The offset is added to make the return address appear
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* as it would within an IRQ ISR. */
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*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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/* When the task starts is will expect to find the function parameter in
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R0. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* When the task starts is will expect to find the function parameter in
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* R0. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* The last thing onto the stack is the status register, which is set for
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system mode, with interrupts enabled. */
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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/* The last thing onto the stack is the status register, which is set for
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* system mode, with interrupts enabled. */
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
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{
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/* We want the task to start in thumb mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
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{
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/* We want the task to start in thumb mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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pxTopOfStack--;
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pxTopOfStack--;
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/* Some optimisation levels use the stack differently to others. This
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means the interrupt flags cannot always be stored on the stack and will
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instead be stored in a variable, which is then saved as part of the
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tasks context. */
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*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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/* Some optimisation levels use the stack differently to others. This
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* means the interrupt flags cannot always be stored on the stack and will
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* instead be stored in a variable, which is then saved as part of the
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* tasks context. */
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*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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return pxTopOfStack;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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* here already. */
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prvSetupTimerInterrupt();
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Start the first task. */
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vPortISRStartFirstTask();
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/* Start the first task. */
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vPortISRStartFirstTask();
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/* Should not get here! */
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return 0;
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the ARM port will require this function as there
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* is nothing to return to. */
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/* It is unlikely that the ARM port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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@ -181,52 +179,55 @@ void vPortEndScheduler( void )
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*/
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static void prvSetupTimerInterrupt( void )
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{
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uint32_t ulCompareMatch;
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uint32_t ulCompareMatch;
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PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 );
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T0TCR = 2; /* Stop and reset the timer */
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T0CTCR = 0; /* Timer mode */
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PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
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T0TCR = 2; /* Stop and reset the timer */
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T0CTCR = 0; /* Timer mode */
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/* A 1ms tick does not require the use of the timer prescale. This is
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defaulted to zero but can be used if necessary. */
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T0PR = portPRESCALE_VALUE;
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/* A 1ms tick does not require the use of the timer prescale. This is
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* defaulted to zero but can be used if necessary. */
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T0PR = portPRESCALE_VALUE;
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/* Calculate the match value required for our wanted tick rate. */
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ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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/* Calculate the match value required for our wanted tick rate. */
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ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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/* Protect against divide by zero. Using an if() statement still results
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in a warning - hence the #if. */
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#if portPRESCALE_VALUE != 0
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{
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ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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}
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#endif
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T0MR1 = ulCompareMatch;
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/* Protect against divide by zero. Using an if() statement still results
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* in a warning - hence the #if. */
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#if portPRESCALE_VALUE != 0
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{
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ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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}
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#endif
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T0MR1 = ulCompareMatch;
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/* Generate tick with timer 0 compare match. */
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T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */
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/* Generate tick with timer 0 compare match. */
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T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */
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/* Setup the VIC for the timer. */
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VICIntEnable = 0x00000010;
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/* The ISR installed depends on whether the preemptive or cooperative
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scheduler is being used. */
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#if configUSE_PREEMPTION == 1
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{
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extern void ( vPreemptiveTick )( void );
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VICVectAddr4 = ( int32_t ) vPreemptiveTick;
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}
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#else
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{
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extern void ( vNonPreemptiveTick )( void );
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VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
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}
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#endif
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/* Setup the VIC for the timer. */
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VICIntEnable = 0x00000010;
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VICVectCntl4 = 1;
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/* The ISR installed depends on whether the preemptive or cooperative
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* scheduler is being used. */
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#if configUSE_PREEMPTION == 1
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{
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extern void( vPreemptiveTick )( void );
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VICVectAddr4 = ( int32_t ) vPreemptiveTick;
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}
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#else
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{
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extern void( vNonPreemptiveTick )( void );
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VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
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}
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#endif
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VICVectCntl4 = 1;
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/* Start the timer - interrupts are disabled when this function is called
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* so it is okay to do this here. */
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T0TCR = portENABLE_TIMER;
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/* Start the timer - interrupts are disabled when this function is called
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so it is okay to do this here. */
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T0TCR = portENABLE_TIMER;
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}
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/*-----------------------------------------------------------*/
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@ -27,29 +27,29 @@
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/*-----------------------------------------------------------
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to handle interrupts. */
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#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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volatile uint32_t ulCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/* ISR to handle manual context switches (from a call to taskYIELD()). */
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void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
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void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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/*
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/*
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* The scheduler can only be started from ARM mode, hence the inclusion of this
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* function here.
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*/
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@ -58,39 +58,39 @@ void vPortISRStartFirstTask( void );
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void vPortISRStartFirstTask( void )
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{
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/* Simply start the scheduler. This is included here as it can only be
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* called from ARM mode. */
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portRESTORE_CONTEXT();
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/* Simply start the scheduler. This is included here as it can only be
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called from ARM mode. */
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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* Called by portYIELD() or taskYIELD() to manually force a context switch.
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*
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* When a context switch is performed from the task level the saved task
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* When a context switch is performed from the task level the saved task
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* context is made to look as if it occurred from within the tick ISR. This
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* way the same restore context function can be used when restoring the context
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* saved from the ISR or that saved from a call to vPortYieldProcessor.
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*/
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void vPortYieldProcessor( void )
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{
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/* Within an IRQ ISR the link register has an offset from the true return
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* address, but an SWI ISR does not. Add the offset manually so the same
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* ISR return code can be used in both cases. */
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__asm volatile ( "ADD LR, LR, #4");
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/* Within an IRQ ISR the link register has an offset from the true return
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address, but an SWI ISR does not. Add the offset manually so the same
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ISR return code can be used in both cases. */
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__asm volatile ( "ADD LR, LR, #4" );
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/* Perform the context switch. First save the context of the current task. */
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portSAVE_CONTEXT();
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/* Perform the context switch. First save the context of the current task. */
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portSAVE_CONTEXT();
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/* Find the highest priority task that is ready to run. */
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__asm volatile ( "bl vTaskSwitchContext");
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/* Find the highest priority task that is ready to run. */
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__asm volatile( "bl vTaskSwitchContext" );
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/* Restore the context of the new task. */
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portRESTORE_CONTEXT();
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/* Restore the context of the new task. */
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portRESTORE_CONTEXT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
/*
|
||||
* The ISR used for the scheduler tick depends on whether the cooperative or
|
||||
* the preemptive scheduler is being used.
|
||||
*/
|
||||
|
|
@ -98,46 +98,46 @@ void vPortYieldProcessor( void )
|
|||
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
||||
/* The cooperative scheduler requires a normal IRQ service routine to
|
||||
* simply increment the system tick. */
|
||||
void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
|
||||
void vNonPreemptiveTick( void )
|
||||
{
|
||||
xTaskIncrementTick();
|
||||
T0IR = 2;
|
||||
VICVectAddr = portCLEAR_VIC_INTERRUPT;
|
||||
}
|
||||
/* The cooperative scheduler requires a normal IRQ service routine to
|
||||
simply increment the system tick. */
|
||||
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
|
||||
void vNonPreemptiveTick( void )
|
||||
{
|
||||
xTaskIncrementTick();
|
||||
T0IR = 2;
|
||||
VICVectAddr = portCLEAR_VIC_INTERRUPT;
|
||||
}
|
||||
|
||||
#else /* if configUSE_PREEMPTION == 0 */
|
||||
#else
|
||||
|
||||
/* The preemptive scheduler is defined as "naked" as the full context is
|
||||
* saved on entry as part of the context switch. */
|
||||
void vPreemptiveTick( void ) __attribute__( ( naked ) );
|
||||
void vPreemptiveTick( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT();
|
||||
/* The preemptive scheduler is defined as "naked" as the full context is
|
||||
saved on entry as part of the context switch. */
|
||||
void vPreemptiveTick( void ) __attribute__((naked));
|
||||
void vPreemptiveTick( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT();
|
||||
|
||||
/* Increment the RTOS tick count, then look for the highest priority
|
||||
* task that is ready to run. */
|
||||
__asm volatile
|
||||
(
|
||||
" bl xTaskIncrementTick \t\n"\
|
||||
" cmp r0, #0 \t\n"\
|
||||
" beq SkipContextSwitch \t\n"\
|
||||
" bl vTaskSwitchContext \t\n"\
|
||||
"SkipContextSwitch: \t\n"
|
||||
);
|
||||
/* Increment the RTOS tick count, then look for the highest priority
|
||||
task that is ready to run. */
|
||||
__asm volatile
|
||||
(
|
||||
" bl xTaskIncrementTick \t\n" \
|
||||
" cmp r0, #0 \t\n" \
|
||||
" beq SkipContextSwitch \t\n" \
|
||||
" bl vTaskSwitchContext \t\n" \
|
||||
"SkipContextSwitch: \t\n"
|
||||
);
|
||||
|
||||
/* Ready for the next interrupt. */
|
||||
T0IR = 2;
|
||||
VICVectAddr = portCLEAR_VIC_INTERRUPT;
|
||||
/* Ready for the next interrupt. */
|
||||
T0IR = 2;
|
||||
VICVectAddr = portCLEAR_VIC_INTERRUPT;
|
||||
|
||||
/* Restore the context of the new task. */
|
||||
portRESTORE_CONTEXT();
|
||||
}
|
||||
|
||||
/* Restore the context of the new task. */
|
||||
portRESTORE_CONTEXT();
|
||||
}
|
||||
|
||||
#endif /* if configUSE_PREEMPTION == 0 */
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
|
|
@ -148,71 +148,71 @@ void vPortYieldProcessor( void )
|
|||
*/
|
||||
#ifdef THUMB_INTERWORK
|
||||
|
||||
void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
|
||||
void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
|
||||
void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
|
||||
void vPortDisableInterruptsFromThumb( void )
|
||||
{
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */
|
||||
"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */
|
||||
"LDMIA SP!, {R0} \n\t"/* Pop R0. */
|
||||
"BX R14"); /* Return back to thumb. */
|
||||
}
|
||||
|
||||
void vPortEnableInterruptsFromThumb( void )
|
||||
{
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */
|
||||
"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */
|
||||
"LDMIA SP!, {R0} \n\t"/* Pop R0. */
|
||||
"BX R14"); /* Return back to thumb. */
|
||||
}
|
||||
void vPortDisableInterruptsFromThumb( void )
|
||||
{
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
||||
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
||||
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
|
||||
"BX R14" ); /* Return back to thumb. */
|
||||
}
|
||||
|
||||
void vPortEnableInterruptsFromThumb( void )
|
||||
{
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
||||
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
||||
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
|
||||
"BX R14" ); /* Return back to thumb. */
|
||||
}
|
||||
|
||||
#endif /* THUMB_INTERWORK */
|
||||
|
||||
/* The code generated by the GCC compiler uses the stack in different ways at
|
||||
* different optimisation levels. The interrupt flags can therefore not always
|
||||
* be saved to the stack. Instead the critical section nesting level is stored
|
||||
* in a variable, which is then saved as part of the stack context. */
|
||||
different optimisation levels. The interrupt flags can therefore not always
|
||||
be saved to the stack. Instead the critical section nesting level is stored
|
||||
in a variable, which is then saved as part of the stack context. */
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */
|
||||
"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */
|
||||
"LDMIA SP!, {R0}"); /* Pop R0. */
|
||||
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
||||
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
||||
"LDMIA SP!, {R0}" ); /* Pop R0. */
|
||||
|
||||
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
||||
* directly. Increment ulCriticalNesting to keep a count of how many times
|
||||
* portENTER_CRITICAL() has been called. */
|
||||
ulCriticalNesting++;
|
||||
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
||||
directly. Increment ulCriticalNesting to keep a count of how many times
|
||||
portENTER_CRITICAL() has been called. */
|
||||
ulCriticalNesting++;
|
||||
}
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Decrement the nesting count as we are leaving a critical section. */
|
||||
ulCriticalNesting--;
|
||||
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Decrement the nesting count as we are leaving a critical section. */
|
||||
ulCriticalNesting--;
|
||||
|
||||
/* If the nesting level has reached zero then interrupts should be
|
||||
* re-enabled. */
|
||||
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Enable interrupts as per portEXIT_CRITICAL(). */
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */
|
||||
"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */
|
||||
"LDMIA SP!, {R0}"); /* Pop R0. */
|
||||
}
|
||||
}
|
||||
/* If the nesting level has reached zero then interrupts should be
|
||||
re-enabled. */
|
||||
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Enable interrupts as per portEXIT_CRITICAL(). */
|
||||
__asm volatile (
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
||||
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
||||
"LDMIA SP!, {R0}" ); /* Pop R0. */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,34 +26,34 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Changes from V3.2.3
|
||||
*
|
||||
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
|
||||
+
|
||||
+ Changes from V3.2.4
|
||||
+
|
||||
+ Removed the use of the %0 parameter within the assembler macros and
|
||||
+ replaced them with hard coded registers. This will ensure the
|
||||
+ assembler does not select the link register as the temp register as
|
||||
+ was occasionally happening previously.
|
||||
+
|
||||
+ The assembler statements are now included in a single asm block rather
|
||||
+ than each line having its own asm block.
|
||||
+
|
||||
+ Changes from V4.5.0
|
||||
+
|
||||
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
|
||||
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
|
||||
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
|
||||
+ macros as per the V4.5.1 demo code.
|
||||
*/
|
||||
Changes from V3.2.3
|
||||
|
||||
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
|
||||
|
||||
Changes from V3.2.4
|
||||
|
||||
+ Removed the use of the %0 parameter within the assembler macros and
|
||||
replaced them with hard coded registers. This will ensure the
|
||||
assembler does not select the link register as the temp register as
|
||||
was occasionally happening previously.
|
||||
|
||||
+ The assembler statements are now included in a single asm block rather
|
||||
than each line having its own asm block.
|
||||
|
||||
Changes from V4.5.0
|
||||
|
||||
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
|
||||
and replaced them with portYIELD_FROM_ISR() macro. Application code
|
||||
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
|
||||
macros as per the V4.5.1 demo code.
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -66,32 +66,32 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE portLONG
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE portLONG
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portNOP() __asm volatile ( "NOP" );
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portNOP() __asm volatile ( "NOP" );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
|
@ -104,92 +104,92 @@
|
|||
* THUMB mode code will result in a compile time error.
|
||||
*/
|
||||
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile void * volatile pxCurrentTCB; \
|
||||
extern volatile uint32_t ulCriticalNesting; \
|
||||
\
|
||||
/* Set the LR to the task stack. */ \
|
||||
__asm volatile ( \
|
||||
"LDR R0, =pxCurrentTCB \n\t"\
|
||||
"LDR R0, [R0] \n\t"\
|
||||
"LDR LR, [R0] \n\t"\
|
||||
\
|
||||
/* The critical nesting depth is the first item on the stack. */ \
|
||||
/* Load it into the ulCriticalNesting variable. */ \
|
||||
"LDR R0, =ulCriticalNesting \n\t"\
|
||||
"LDMFD LR!, {R1} \n\t"\
|
||||
"STR R1, [R0] \n\t"\
|
||||
\
|
||||
/* Get the SPSR from the stack. */ \
|
||||
"LDMFD LR!, {R0} \n\t"\
|
||||
"MSR SPSR, R0 \n\t"\
|
||||
\
|
||||
/* Restore all system mode registers for the task. */ \
|
||||
"LDMFD LR, {R0-R14}^ \n\t"\
|
||||
"NOP \n\t"\
|
||||
\
|
||||
/* Restore the return address. */ \
|
||||
"LDR LR, [LR, #+60] \n\t"\
|
||||
\
|
||||
/* And return - correcting the offset in the LR to obtain the */ \
|
||||
/* correct address. */ \
|
||||
"SUBS PC, LR, #4 \n\t"\
|
||||
); \
|
||||
( void ) ulCriticalNesting; \
|
||||
( void ) pxCurrentTCB; \
|
||||
}
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile void * volatile pxCurrentTCB; \
|
||||
extern volatile uint32_t ulCriticalNesting; \
|
||||
\
|
||||
/* Set the LR to the task stack. */ \
|
||||
__asm volatile ( \
|
||||
"LDR R0, =pxCurrentTCB \n\t" \
|
||||
"LDR R0, [R0] \n\t" \
|
||||
"LDR LR, [R0] \n\t" \
|
||||
\
|
||||
/* The critical nesting depth is the first item on the stack. */ \
|
||||
/* Load it into the ulCriticalNesting variable. */ \
|
||||
"LDR R0, =ulCriticalNesting \n\t" \
|
||||
"LDMFD LR!, {R1} \n\t" \
|
||||
"STR R1, [R0] \n\t" \
|
||||
\
|
||||
/* Get the SPSR from the stack. */ \
|
||||
"LDMFD LR!, {R0} \n\t" \
|
||||
"MSR SPSR, R0 \n\t" \
|
||||
\
|
||||
/* Restore all system mode registers for the task. */ \
|
||||
"LDMFD LR, {R0-R14}^ \n\t" \
|
||||
"NOP \n\t" \
|
||||
\
|
||||
/* Restore the return address. */ \
|
||||
"LDR LR, [LR, #+60] \n\t" \
|
||||
\
|
||||
/* And return - correcting the offset in the LR to obtain the */ \
|
||||
/* correct address. */ \
|
||||
"SUBS PC, LR, #4 \n\t" \
|
||||
); \
|
||||
( void ) ulCriticalNesting; \
|
||||
( void ) pxCurrentTCB; \
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile void * volatile pxCurrentTCB; \
|
||||
extern volatile uint32_t ulCriticalNesting; \
|
||||
\
|
||||
/* Push R0 as we are going to use the register. */ \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t"\
|
||||
\
|
||||
/* Set R0 to point to the task stack pointer. */ \
|
||||
"STMDB SP,{SP}^ \n\t"\
|
||||
"NOP \n\t"\
|
||||
"SUB SP, SP, #4 \n\t"\
|
||||
"LDMIA SP!,{R0} \n\t"\
|
||||
\
|
||||
/* Push the return address onto the stack. */ \
|
||||
"STMDB R0!, {LR} \n\t"\
|
||||
\
|
||||
/* Now we have saved LR we can use it instead of R0. */ \
|
||||
"MOV LR, R0 \n\t"\
|
||||
\
|
||||
/* Pop R0 so we can save it onto the system mode stack. */ \
|
||||
"LDMIA SP!, {R0} \n\t"\
|
||||
\
|
||||
/* Push all the system mode registers onto the task stack. */ \
|
||||
"STMDB LR,{R0-LR}^ \n\t"\
|
||||
"NOP \n\t"\
|
||||
"SUB LR, LR, #60 \n\t"\
|
||||
\
|
||||
/* Push the SPSR onto the task stack. */ \
|
||||
"MRS R0, SPSR \n\t"\
|
||||
"STMDB LR!, {R0} \n\t"\
|
||||
\
|
||||
"LDR R0, =ulCriticalNesting \n\t"\
|
||||
"LDR R0, [R0] \n\t"\
|
||||
"STMDB LR!, {R0} \n\t"\
|
||||
\
|
||||
/* Store the new top of stack for the task. */ \
|
||||
"LDR R0, =pxCurrentTCB \n\t"\
|
||||
"LDR R0, [R0] \n\t"\
|
||||
"STR LR, [R0] \n\t"\
|
||||
); \
|
||||
( void ) ulCriticalNesting; \
|
||||
( void ) pxCurrentTCB; \
|
||||
}
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile void * volatile pxCurrentTCB; \
|
||||
extern volatile uint32_t ulCriticalNesting; \
|
||||
\
|
||||
/* Push R0 as we are going to use the register. */ \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" \
|
||||
\
|
||||
/* Set R0 to point to the task stack pointer. */ \
|
||||
"STMDB SP,{SP}^ \n\t" \
|
||||
"NOP \n\t" \
|
||||
"SUB SP, SP, #4 \n\t" \
|
||||
"LDMIA SP!,{R0} \n\t" \
|
||||
\
|
||||
/* Push the return address onto the stack. */ \
|
||||
"STMDB R0!, {LR} \n\t" \
|
||||
\
|
||||
/* Now we have saved LR we can use it instead of R0. */ \
|
||||
"MOV LR, R0 \n\t" \
|
||||
\
|
||||
/* Pop R0 so we can save it onto the system mode stack. */ \
|
||||
"LDMIA SP!, {R0} \n\t" \
|
||||
\
|
||||
/* Push all the system mode registers onto the task stack. */ \
|
||||
"STMDB LR,{R0-LR}^ \n\t" \
|
||||
"NOP \n\t" \
|
||||
"SUB LR, LR, #60 \n\t" \
|
||||
\
|
||||
/* Push the SPSR onto the task stack. */ \
|
||||
"MRS R0, SPSR \n\t" \
|
||||
"STMDB LR!, {R0} \n\t" \
|
||||
\
|
||||
"LDR R0, =ulCriticalNesting \n\t" \
|
||||
"LDR R0, [R0] \n\t" \
|
||||
"STMDB LR!, {R0} \n\t" \
|
||||
\
|
||||
/* Store the new top of stack for the task. */ \
|
||||
"LDR R0, =pxCurrentTCB \n\t" \
|
||||
"LDR R0, [R0] \n\t" \
|
||||
"STR LR, [R0] \n\t" \
|
||||
); \
|
||||
( void ) ulCriticalNesting; \
|
||||
( void ) pxCurrentTCB; \
|
||||
}
|
||||
|
||||
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
#define portYIELD() __asm volatile ( "SWI 0" )
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
#define portYIELD() __asm volatile ( "SWI 0" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
|
@ -202,47 +202,48 @@
|
|||
* defined then the utilities are defined as macros here - as per other ports.
|
||||
*/
|
||||
|
||||
#ifdef THUMB_INTERWORK
|
||||
#ifdef THUMB_INTERWORK
|
||||
|
||||
extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
|
||||
extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
|
||||
extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
|
||||
#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
|
||||
#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
|
||||
#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
|
||||
#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
|
||||
|
||||
#else
|
||||
#else
|
||||
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */\
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */\
|
||||
"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */\
|
||||
"LDMIA SP!, {R0} ") /* Pop R0. */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
|
||||
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
|
||||
"LDMIA SP!, {R0} " ) /* Pop R0. */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */\
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */\
|
||||
"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */\
|
||||
"LDMIA SP!, {R0} ") /* Pop R0. */
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
|
||||
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
|
||||
"LDMIA SP!, {R0} " ) /* Pop R0. */
|
||||
|
||||
#endif /* THUMB_INTERWORK */
|
||||
#endif /* THUMB_INTERWORK */
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue