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+ New feature added: Task notifications.

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+ Optimise Cortex-M4F ports by inlining some critical section macros.
+ Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h.
+ Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked.
+ Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos.
+ Update trace recorder code, and some demos to use the new version (more to do).
+ Introduce uxTaskPriorityGetFromISR().
+ Minor typo corrections.
+ Update MingW simulator demo to match the MSVC simulator demo.
This commit is contained in:
Richard Barry 2014-12-15 14:13:03 +00:00
parent ca22607d14
commit 85fb1cc024
65 changed files with 5524 additions and 4527 deletions
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58
FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
View file

@ -110,11 +110,10 @@ typedef unsigned long UBaseType_t;
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
extern void vPortYield( void );
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portYIELD() vPortYield()
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@ -145,15 +144,13 @@ extern void vPortYield( void );
/* Critical section management. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
extern uint32_t ulPortSetInterruptMask( void );
extern void vPortClearInterruptMask( uint32_t ulNewMask );
#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
#define portDISABLE_INTERRUPTS() ulPortRaiseBASEPRI()
#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
@ -179,6 +176,51 @@ not necessary for to use this port. They are defined so the common demo files
/* portNOP() is not required by this port. */
#define portNOP()
#ifndef portFORCE_INLINE
#define portFORCE_INLINE _Pragma("inline=forced")
#endif
portFORCE_INLINE static void vPortYield( void )
{
/* Set a PendSV to request a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
/* Barriers are normally not required but do ensure the code is completely
within the specified behaviour for the architecture. */
__DSB();
__ISB();
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI;
__asm volatile
(
" mrs %0, basepri \n" \
" mov r1, %1 \n" \
" msr basepri, r1 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulOriginalBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r1"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue )
);
}
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
the source code because to do so would cause other compilers to generate
warnings. */